A level shifting circuit based on current compensation

Abstract

The application provides a level shift circuit based on current compensation, a low-voltage pulse signal is connected to a first level input end and a second level output end respectively, so that the two low-voltage pulse signals are converted into two high-voltage pulse signals, and the high-voltage pulse signals are output to a current compensation circuit and a common mode noise elimination circuit through a first level output end and a second level output end; the output of the current compensation circuit and the common mode noise elimination circuit jointly influences the signal state of R end and S end in a latch, and the latch is used for restoring the high-voltage pulse signal into a floating square wave signal with the same phase as the input signal. The application not only can resist high common mode noise, but also has a good inhibitory effect on differential mode noise, and effectively improves the stability and reliability of the level shift circuit.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a level shifting circuit based on current compensation. Background Technology

[0002] In power integrated circuits, gate driver chips are used to receive control signals from external digital chips such as CPUs or MCUs, and to provide the gate signals required to control and drive power MOSFET or IGBT devices. They are widely used in motor control, servo systems, 5G communication, wireless transmission, fast charging, and other fields. Typically, a gate driver chip consists of two parts: a high-voltage domain and a low-voltage domain. The level shifting circuit acts as a transmission bridge between the different voltage domains, shifting the potential of the control logic from the low-voltage domain to the high-voltage domain or vice versa.

[0003] However, this high-low voltage conversion circuit requires the integration of high-voltage LDMOS transistors. Due to the large parasitic capacitance of LDMOS transistors, when dv / dt occurs, their parasitic capacitance will generate charging or discharging current, forming dv / dt noise, which interferes with the normal operation of the level converter and causes errors in the high-voltage domain logic signal of the driver.

[0004] like Figure 1 The circuit structure shown includes a level shifting circuit and a gate driver chip. When the high-side power transistor is turned on, V HS The voltage will rise rapidly to VPVDD, dV HS The change in / dt is coupled to a level shifter via a bootstrap capacitor, V HB With V HS Change, dV HB / dt is approximately equal to dV HS / dt; Because the input MOS devices MH1 (MH2) of the level converter are high-voltage LDMOS transistors, there is a large parasitic capacitance C1 (C2) at point A (B), V HB The rapid change in voltage generates a large current in C1 (C2), pulling down the voltage at point A (B). The noise amplitude generated at point A (B) is (=R×C×dV). HS / dt, where R is R1 or R2, C is C1 or C2) is greater than V BOOT -V th Time (where V) BOOT equals V HB -V HS The subsequent circuits may be affected by noise signals, leading to drive logic errors. Especially in high-voltage applications, the dv / dt noise of the level shift circuit seriously threatens the reliability of the gate driver.

[0005] To suppress the interference of dv / dt noise signals on the circuit, a common approach is to add a common-mode noise cancellation circuit with a cross-coupling structure to the level shifting circuit. For example... Figure 2 As shown, the commonly used level shifting circuit works by having an input pulse signal trigger high-voltage transistors MH1 and MH2, which then copy the control signal to the latch input via a current mirror. The latch then restores the pulse signal to its original square wave signal. MP2 to MP6 and MN1 to MN4 form a cross-coupling structure. Theoretically, when dv / dt occurs, the noise current generated by the parasitic capacitance of high-voltage transistors MH1 and MH2 will be canceled out in the cross-coupling structure. The dv / dt noise is essentially input common-mode noise for the latch, thus providing excellent suppression of common-mode noise.

[0006] However, during the wafer fabrication process, due to process limitations, the parasitic capacitances of high-voltage transistors MH1 and MH2 are not entirely identical, which introduces differential-mode noise into the circuit. Furthermore, differential-mode noise may also be introduced during the layout and routing process. Level shifting circuits with added cross-coupling structures cannot cancel the noise current caused by differential-mode noise. Therefore, there is an urgent need to provide a new level shifting circuit to handle differential-mode noise. Summary of the Invention

[0007] To address the shortcomings of existing technologies, this invention provides a current-compensated level shifting circuit, which solves the problem that existing level shifting circuits with added cross-coupling structures cannot handle differential-mode noise, making them prone to signal distortion or circuit instability.

[0008] According to an embodiment of the present invention, a level shifting circuit based on current compensation includes:

[0009] The level shifting circuit includes a first level input terminal and a second level input terminal for receiving low-voltage pulse signals, and also includes a first level output terminal and a second level output terminal for outputting high-voltage pulse signals.

[0010] The common-mode noise cancellation circuit includes a first mirror input terminal connected to the first level output terminal, a second mirror input terminal connected to the second level output terminal, a first current output terminal that outputs a first current, a second current output terminal that outputs a second current, a third current output terminal that outputs a third current, and a fourth current output terminal that outputs a fourth current.

[0011] The current compensation circuit includes a third mirror input terminal connected to the first level output terminal, a fourth mirror input terminal connected to the second level output terminal, a first compensation output terminal that outputs a first compensation current, and a second compensation output terminal that outputs a second compensation current.

[0012] A latch, including an R terminal, a S terminal, and a latch output terminal;

[0013] When differential-mode +dv / dt noise exists, the R terminal is 1 and the S terminal is 0. A mismatch occurs in the level shifting circuit, causing the first current and the second current to be less than the third current and the fourth current. Then, the first compensation output terminal, the first current output terminal, and the third current output terminal generate a first latch signal, which is input to the R terminal. In the first latch signal, the sum of the first current and the first compensation current is greater than or equal to the third current. The second compensation output terminal, the fourth current output terminal, and the second current output terminal generate a second latch signal, which is input to the S terminal. In the second latch signal, the fourth current minus the second compensation current is less than or equal to the second current.

[0014] A driver, connected to the output of the latch, is used to enhance the square wave signal output from the latch and output a logic control signal with driving capability.

[0015] Optionally, the first level input terminal and the second level input terminal are connected to a low-voltage pulse signal through a cascaded circuit including a high-voltage LDMOS and a low-voltage MOS.

[0016] Optionally, the level shifting circuit includes a first NMOS transistor, a second NMOS transistor, a first LDMOS transistor, a second LDMOS transistor, a first PMOS transistor, a second PMOS transistor, a first Zener diode, and a second Zener diode;

[0017] The first level input terminal is the gate of the first NMOS transistor, used to acquire the rising edge pulse signal in the low voltage pulse signal; the second level input terminal is the gate of the second NMOS transistor, used to acquire the falling edge pulse signal in the low voltage pulse signal.

[0018] The sources of the first and second NMOS transistors are grounded. The drain of the first NMOS transistor is connected to the source of the first LDMOS transistor, and the drain of the second NMOS transistor is connected to the source of the second LDMOS transistor. The gates of both the first and second LDMOS transistors are connected to an internal 5V bias voltage. The drain of the first LDMOS transistor is connected to the drain of the first PMOS transistor, and the drain of the second PMOS transistor is connected to the drain of the first LDMOS transistor. The gate of the first PMOS transistor is connected to its drain, and the gate of the second PMOS transistor is connected to its drain. The sources of both the first and second PMOS transistors are connected to a floating power supply. The positive terminal of the first Zener diode is connected to the drain of the first PMOS transistor, and the positive terminal of the second Zener diode is connected to its drain. The negative terminals of both the first and second Zener diodes are connected to a floating power supply.

[0019] The first level output terminal is the gate of the first PMOS transistor; the second level output terminal is the gate of the second PMOS transistor.

[0020] Optionally, the current compensation circuit further includes a first switch, a second switch, and a third switch; the first switch and the second switch are connected to the S terminal, and the third switch is connected to the R terminal;

[0021] When differential-mode +dv / dt noise is present, if the R terminal is 0 and the S terminal is 1, the current compensation circuit is turned off by the first switch, the second switch and the third switch.

[0022] Optionally, the current compensation circuit includes a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor;

[0023] The seventh NMOS transistor is the first switch, the eighth NMOS transistor is the second switch, and the eighth PMOS transistor is the third switch; the gate of the third PMOS transistor is the third mirror input terminal, receiving the high-voltage pulse signal output from the first level output terminal, and the gate of the fourth PMOS transistor is the fourth mirror input terminal, receiving the high-voltage pulse signal output from the second level output terminal.

[0024] The source of the fourth PMOS transistor and the source of the third PMOS transistor are both connected to a floating power supply. The drain of the fourth PMOS transistor is connected to the drain of the third NMOS transistor, and the drain of the third PMOS transistor is connected to the drain of the fourth NMOS transistor. The gate and drain of the third NMOS transistor are connected to the gate of the fourth NMOS transistor to form a current mirror. The source of the third NMOS transistor and the source of the fourth NMOS transistor are both connected to a floating ground.

[0025] The gates of the fifth PMOS transistor, the sixth PMOS transistor, and the seventh PMOS transistor are connected to the drain of the fifth PMOS transistor to form a current mirror, which is then connected to the drain of the fourth NMOS transistor. The sources of the fifth PMOS transistor, the sixth PMOS transistor, and the seventh PMOS transistor are all connected to a floating power supply.

[0026] The gate and drain of the fifth NMOS transistor are connected to the gate of the sixth NMOS transistor to form a current mirror, and are connected to the drain of the sixth PMOS transistor. The sources of the fifth and sixth NMOS transistors are both connected to a floating ground. The drain of the seventh PMOS transistor is connected to the R terminal, and the drain of the sixth NMOS transistor is connected to the S terminal. The gate of the eighth PMOS transistor is connected to the R terminal, and the drain of the eighth PMOS transistor is connected to the gate of the seventh PMOS transistor. The sources of the eighth and seventh PMOS transistors are both connected to a floating power supply. The drain of the seventh NMOS transistor is connected to the drain of the fourth NMOS transistor, and the drain of the eighth NMOS transistor is connected to the gate of the sixth NMOS transistor. The gates of the seventh and eighth NMOS transistors are both connected to the S terminal, and the sources of the seventh and eighth NMOS transistors are both connected to a floating ground.

[0027] Optionally, the common-mode noise cancellation circuit includes a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, and a twelfth NMOS transistor;

[0028] The gates of the eleventh PMOS transistor and the twelfth PMOS transistor are both connected to the gate of the second PMOS transistor in the level shift circuit. The sources of the eleventh PMOS transistor and the twelfth PMOS transistor are both connected to a floating power supply. The drain of the eleventh PMOS transistor is connected to the drain of the tenth NMOS transistor, and the drain of the twelfth PMOS transistor is connected to the drain of the twelfth NMOS transistor. The gates of the ninth PMOS transistor and the tenth PMOS transistor are both connected to the gate of the first PMOS transistor in the level shift circuit. The sources of the ninth PMOS transistor and the tenth PMOS transistor are both connected to a floating power supply. The drain of the ninth PMOS transistor is connected to the gate of the first PMOS transistor in the level shift circuit. The drain of the ninth NMOS transistor is connected, and the drain of the tenth PMOS transistor is connected to the drain of the eleventh NMOS transistor; the gate and drain of the tenth NMOS transistor are connected to the gate of the ninth NMOS transistor, and the source and source of the tenth NMOS transistor are both connected to floating ground; the gate and drain of the eleventh NMOS transistor are connected to the gate of the twelfth NMOS transistor, and the source of the eleventh NMOS transistor and source of the twelfth NMOS transistor are both connected to floating ground; the drain of the ninth PMOS transistor is connected to the R terminal, and the drain of the twelfth PMOS transistor is connected to the S terminal of the latch.

[0029] Optionally, the latch further includes a first inverter and a second inverter;

[0030] The first inverter and the second inverter are connected in series to form a loop. The R terminal is the input terminal of the first inverter and the output terminal of the second inverter. The S terminal is the output terminal of the first inverter and the input terminal of the second inverter.

[0031] The latch output includes a first latch output and a second latch output.

[0032] The first latch output terminal is the input terminal of the first inverter and the output terminal of the second inverter, and the second latch output terminal is the output terminal of the first inverter and the input terminal of the second inverter.

[0033] Optionally, the driver includes a first driving circuit connected to the first latch output terminal and a second driving circuit connected to the second latch output terminal.

[0034] The present invention has the following beneficial effects: The level shifting circuit receives a low-voltage pulse signal through the first level input terminal and the second level output terminal, thereby converting the two low-voltage pulse signals into two high-voltage pulse signals. These signals are then output to the current compensation circuit and the common-mode noise cancellation circuit through the first and second level output terminals. The outputs of the current compensation circuit and the common-mode noise cancellation circuit jointly affect the signal states of the R and S terminals in the latch. The latch is used to restore the high-voltage pulse signal into a floating square wave signal in phase with the input signal. Therefore, in the presence of differential-mode noise, especially when there is noise affecting the latch output, the present invention is effective. When differential-mode noise plus dv / dt occurs, the first compensation current of the common-mode noise cancellation circuit is compensated by the first compensation current of the current compensation circuit, and the fourth compensation current of the common-mode noise cancellation circuit is compensated by the second compensation current of the current compensation circuit. This ensures that the R and S terminals of the latch maintain the correct signal state, preventing differential-mode noise from affecting the latch output state and causing signal distortion or circuit instability. Simultaneously, the common-mode noise cancellation circuit eliminates common-mode noise in the circuit, the latch restores the high-voltage pulse signal to a floating square wave signal in phase with the input signal, and the output stage drive circuit enhances the driving capability of the logic control signal. Therefore, this invention not only resists high common-mode noise but also effectively suppresses differential-mode noise, significantly improving the stability and reliability of the level shifting circuit. Attached Figure Description

[0035] Figure 1 This is a circuit structure diagram including a level shifting circuit and a gate driver chip;

[0036] Figure 2 This is a circuit structure diagram of a commonly used level shifting circuit;

[0037] Figure 3 A circuit structure diagram of a current-compensated level shifting circuit provided in an embodiment of the present invention;

[0038] Figure 4 A detailed circuit structure diagram of a current-compensated level shifting circuit provided in an embodiment of the present invention;

[0039] Figure 5 This is a simulation waveform of common-mode noise interference before the current compensation circuit is added in an embodiment of the present invention.

[0040] Figure 6 The simulation waveform of common-mode noise interference after adding a current compensation circuit in an embodiment of the present invention is shown.

[0041] Figure 7 This is a simulation waveform of differential-mode noise interference before the current compensation circuit is added in an embodiment of the present invention.

[0042] Figure 8 The simulation waveform of differential-mode noise interference after adding a current compensation circuit in an embodiment of the present invention is shown.

[0043] Figure descriptions: 1. Level shifting circuit; 2. Common-mode noise cancellation circuit; 3. Current compensation circuit; 4. Latch; 5. Driver. Detailed Implementation

[0044] The technical solutions of the present invention will be further described below with reference to the accompanying drawings and embodiments.

[0045] like Figure 3As shown, this embodiment of the invention proposes a level shifting circuit based on current compensation, including a level shifting circuit, a common-mode noise cancellation circuit, a current compensation circuit, a latch, and a driver. The detailed working process of this embodiment is as follows: the level shifting circuit receives a low-voltage pulse signal through the first level input terminal and the second level output terminal, thereby converting the two low-voltage pulse signals into two high-voltage pulse signals. These signals are then output to the current compensation circuit and the common-mode noise cancellation circuit through the first and second level output terminals. The outputs of the current compensation circuit and the common-mode noise cancellation circuit jointly affect the signal states of the R and S terminals in the latch. The latch is used to restore the high-voltage pulse signal into a floating square wave signal in phase with the input signal. Therefore, in the presence of differential-mode noise, this embodiment compensates the first current of the common-mode noise cancellation circuit with the first compensation current of the current compensation circuit, and compensates the fourth current of the common-mode noise cancellation circuit with the second compensation current of the current compensation circuit, so that the R and S terminals of the latch maintain the correct signal states and avoid differential-mode noise affecting the output state of the latch, thereby causing signal distortion or circuit instability. At the same time, the common-mode noise cancellation circuit is used to eliminate common-mode noise in the circuit, the latch is used to restore the high-voltage pulse signal into a floating square wave signal in phase with the input signal, and the output stage drive circuit is used to enhance the driving capability of the logic control signal. Therefore, this invention not only resists high common-mode noise, but also has a good suppression effect on differential-mode noise, effectively improving the stability and reliability of the level shifting circuit.

[0046] like Figure 3 As shown in the figure, the connection relationship of each part and the signal input and output relationship of the current-compensated level shifting circuit provided in this embodiment of the invention are as follows:

[0047] The level shifting circuit 1 includes a first level input terminal INN and a second level input terminal INP for receiving two low-voltage pulse signals, and also includes a first level output terminal W1 and a second level output terminal W2 for outputting high-voltage pulse signals.

[0048] The common-mode noise cancellation circuit 2 includes a first mirror input terminal J1 connected to the first level output terminal W1, a second mirror input terminal J2 connected to the second level output terminal W2, a first current output terminal A1 that outputs the first current I1, a second current output terminal A2 that outputs the second current I2, a third current output terminal A3 that outputs the third current I3, and a fourth current output terminal A4 that outputs the fourth current I4.

[0049] The current compensation circuit 3 includes a third mirror input terminal J3 connected to the first level output terminal W1, and a fourth mirror input terminal J4 connected to the second level output terminal W2, outputting a first compensation current I. B1 The first compensation output terminal B1 and the output second compensation current I B2 The second compensation output terminal B2.

[0050] Latch 4, including R terminal, S terminal and latch output terminal C, is used to restore the high voltage pulse signal into a floating square wave signal in phase with the input signal.

[0051] In practical applications, differential-mode noise can be categorized into two types: rising (+dv / dt) and falling (-dv / dt). Differential-mode -dv / dt noise has no effect on the R and S terminals. When differential-mode +dv / dt noise occurs, the high-voltage transistor in the circuit mismatches, causing changes in the current in the two switching paths of the level shifting circuit. This may result in unequal values ​​for the first, second, third, and fourth currents in the common-mode noise cancellation circuit; alternatively, it may not have any effect, and the first, second, third, and fourth currents may remain equal. However, if these currents are unequal, it will affect the latch logic output.

[0052] Therefore, the current-compensated level shifting circuit provided in this embodiment of the invention, when differential-mode +dv / dt noise exists, has R terminal 1 and S terminal 0, and a mismatch occurs in the level shifting circuit such that the first current I1 and the second current I2 are less than the third current I3 and the fourth current I4, then current compensation is performed. The relevant circuit structure is as follows: the first compensation output terminal B1, the first current output terminal A1, and the third current output terminal A3 generate a first latch signal input to the R terminal, and in the first latch signal, the sum of the first current I1 and the first compensation current is greater than or equal to the third current I3, thereby enhancing the pull-up capability of the R terminal and keeping the R terminal state 1; the second compensation output terminal B2, the fourth current output terminal A4, and the second current output terminal A2 generate a second latch signal input to the S terminal, and in the second latch signal, the fourth current I4 minus the second compensation current is less than or equal to the second current I2, thereby enhancing the pull-down capability of the S terminal and keeping the S terminal state 0.

[0053] Driver 5, connected to the output of the latch, is used to enhance the square wave signal output from the latch and output a logic control signal with driving capability.

[0054] In one embodiment, the circuit structure of the first level input terminal INN and the second level output terminal W2 is optimized. The first level input terminal INN and the second level input terminal INP are connected to the low-voltage pulse signal through a cascaded circuit including a high-voltage LDMOS and a low-voltage MOS, thereby isolating the high-voltage domain from the low-voltage domain and accelerating the signal transmission speed.

[0055] like Figure 4 As shown in the figure, the embodiment of the present invention also illustrates a detailed circuit structure of a level shifting circuit, which is... Figure 3 One implementation of a mid-level shift circuit. Please refer to [link / reference]. Figure 4The level shifting circuit includes a first NMOS transistor MN1, a second NMOS transistor MN2, a first LDMOS transistor MH1, a second LDMOS transistor MH2, a first PMOS transistor MP1, a second PMOS transistor MP2, a first Zener diode D1, and a second Zener diode D2. The first level input terminal INN is the gate INN of the first NMOS transistor MN1, and the second level input terminal INP is the gate INP of the second NMOS transistor MN2. The first level input terminal INN is used to acquire the rising edge pulse signal in the low-voltage pulse signal, and the second level input terminal INP is used to acquire the falling edge pulse signal in the low-voltage pulse signal. The source of the first NMOS transistor MN1 and the source of the second NMOS transistor MN2 are grounded. The drain of the first NMOS transistor MN1 is connected to the source of the first LDMOS transistor MH1, and the drain of the second NMOS transistor MN2 is connected to the source of the second LDMOS transistor MH2. The gates of both the first LDMOS transistor MH1 and the second LDMOS transistor MH2 are connected to an internal 5V bias voltage. The drain of the first LDMOS transistor MH1 is connected to the drain of the first PMOS transistor MP1, and the drain of the second PMOS transistor MP2 is connected to the drain of the first LDMOS transistor MH1. The gate of the first PMOS transistor MP1 is connected to its drain, and the gate of the second PMOS transistor MP2 is connected to its drain. The sources of both the first PMOS transistor MP1 and the second PMOS transistor MP2 are connected to a floating power supply V. HB The positive terminal of the first Zener diode D1 is connected to the drain of the first PMOS transistor MP1, and the positive terminal of the second Zener diode D2 is connected to the drain of the second PMOS transistor MP2. The negative terminals of both the first Zener diode D1 and the second Zener diode D2 are connected to the floating power supply V. HB It should be noted that, in combination Figure 3 and Figure 4 The first level output terminal W1 is the gate of the first PMOS transistor MP1; the second level output terminal W2 is the gate of the second PMOS transistor MP2.

[0056] In practical applications, when differential-mode -dv / dt noise is generated, the R terminal is 0 and the S terminal is 1. At this time, no current compensation circuit is needed for compensation. However, in this case, the current compensation circuit may still participate in the circuit operation.

[0057] Therefore, in one embodiment, the current compensation circuit further includes a first switch, a second switch, and a third switch; the first and second switches are connected to the S terminal, and the third switch is connected to the R terminal; when differential-mode -dv / dt noise exists, the current compensation circuit is turned off through the first, second, and third switches.

[0058] like Figure 4 As shown in the figure, the embodiment of the present invention also illustrates a detailed circuit structure of a current compensation circuit, which is... Figure 3 One implementation method for a medium current compensation circuit. Please refer to [link / reference]. Figure 4 The current compensation circuit includes a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, and an eighth NMOS transistor MN8. Among these, the seventh NMOS transistor MN7 is the first switch, the eighth NMOS transistor MN8 is the second switch, and the eighth PMOS transistor MP8 is the third switch.

[0059] The gate of the third PMOS transistor MP3 is the third mirror input terminal J3, receiving the high-voltage pulse signal output from the first-level output terminal W1. The gate of the fourth PMOS transistor MP4 is the fourth mirror input terminal J4, receiving the high-voltage pulse signal output from the second-level output terminal W2. The sources of both the fourth PMOS transistor MP4 and the third PMOS transistor MP3 are connected to a floating power supply V. HB The drain of the fourth PMOS transistor MP4 is connected to the drain of the third NMOS transistor MN3, and the drain of the third PMOS transistor MP3 is connected to the drain of the fourth NMOS transistor MN4. The gate and drain of the third NMOS transistor MN3 are connected to the gate of the fourth NMOS transistor MN4 to form a current mirror. The sources of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are both connected to a floating ground VHS. The gates of the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, and the seventh PMOS transistor MP7 are connected to the drain of the fifth PMOS transistor MP5 to form a current mirror, and are connected to the drain of the fourth NMOS transistor MN4. The sources of the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, and the seventh PMOS transistor MP7 are all connected to a floating power supply VHS. HB The gate and drain of the fifth NMOS transistor MN5 are connected together and connected to the gate of the sixth NMOS transistor MN6 to form a current mirror, which is then connected to the drain of the sixth PMOS transistor MP6. The sources of both the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are connected to a floating ground VHS. The drain of the seventh PMOS transistor MP7 is connected to the R terminal, and the drain of the sixth NMOS transistor MN6 is connected to the S terminal. The gate of the eighth PMOS transistor MP8 is connected to the R terminal, and the drain of the eighth PMOS transistor MP8 is connected to the gate of the seventh PMOS transistor MP7. The sources of both the eighth PMOS transistor MP8 and the seventh PMOS transistor MP7 are connected to a floating power supply VHS. HBThe drain of the seventh NMOS transistor MN7 is connected to the drain of the fourth NMOS transistor MN4, and the drain of the eighth NMOS transistor MN8 is connected to the gate of the sixth NMOS transistor MN6. The gates of the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 are both connected to the source (S) terminal, and the sources of the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 are both connected to the floating ground VHS. When the source (R) terminal is 0 and the source (S) terminal is 1, the seventh NMOS transistor MN7, the eighth NMOS transistor MN8, and the eighth PMOS transistor MP8 are turned on, and the current compensation circuit is turned off.

[0060] The embodiments of the present invention are combined with Figure 4 The output of the current compensation circuit and the common-mode noise cancellation circuit are used to control the signal states of the R and S terminals in the latch. First, differential-mode -dv / dt noise has no effect on the R and S terminals. Only when differential-mode +dv / dt noise occurs, potentially causing I1, I2 and I3, I4 to be unequal, will the signal states of the R and S terminals be affected. Currently, R is 1 and S is 0. Figure 4 When differential-mode +dv / dt noise occurs, MH1 and MH2 mismatch, and IA > IB, then there will be no impact; that is, I1, I2 and I3, I4 will not be unequal. However, when differential-mode +dv / dt noise occurs, MH1 and MH2 mismatch, and IA < IB, then there will be an impact; that is, I1, I2 and I3, I4 will be unequal, and the current flowing through MN9 and MN11 will be less than the current flowing through MN10 and MN12. In this case, the logic signals may be affected by the noise, with R abruptly changing to 0 and S abruptly changing to 1, leading to driving logic errors. However, the current compensation circuit added in this embodiment of the invention works as follows in the above state: Since IA < IB, the noise current is mirrored into I5 and I6 through MP3 and MP4, I5 = I6 + I7, and I7 is mirrored into pull-up current I8 through MP7, and I7 is mirrored into pull-down current I9 through MP6, MN5 and MN6; at this time, I8 is used to compensate I1, so that I1 + I8 ≥ I3, enhancing the pull-up capability of R terminal and keeping the R terminal state 1; I9 is ​​used to compensate I4, so that I4 - I9 ≤ I2, enhancing the pull-down capability of S terminal and keeping the S terminal state 0.

[0061] In addition, when differential-mode -dv / dt noise is present, MP8, MN7, and MN8 are turned on, shutting down the current compensation circuit.

[0062] like Figure 4 As shown in the figure, the embodiment of the present invention also illustrates a detailed circuit structure of a common-mode noise cancellation circuit, which is... Figure 3 One implementation of a common-mode noise cancellation circuit. Please refer to [link / reference]. Figure 4The common-mode noise cancellation circuit includes the ninth PMOS transistor MP9, the tenth PMOS transistor MP10, the eleventh PMOS transistor MP11, the twelfth PMOS transistor MP12, the ninth NMOS transistor MN9, the tenth NMOS transistor MN10, the eleventh NMOS transistor MN11, and the twelfth NMOS transistor MN12.

[0063] The gates of the eleventh PMOS transistor MP11 and the twelfth PMOS transistor MP12 are both connected to the gate of the second PMOS transistor MP2 in the level shifting circuit. The sources of the eleventh PMOS transistor MP11 and the twelfth PMOS transistor MP12 are both connected to the floating power supply V. HB The drain of the eleventh PMOS transistor MP11 is connected to the drain of the tenth NMOS transistor MN10, and the drain of the twelfth PMOS transistor MP12 is connected to the drain of the twelfth NMOS transistor MN12. The gates of the ninth PMOS transistor MP9 and the tenth PMOS transistor MP10 are both connected to the gate of the first PMOS transistor MP1 in the level shifting circuit, and the sources of the ninth PMOS transistor MP9 and the tenth PMOS transistor MP10 are both connected to the floating power supply V. HB The drain of the ninth PMOS transistor MP9 is connected to the drain of the ninth NMOS transistor MN9, and the drain of the tenth PMOS transistor MP10 is connected to the drain of the eleventh NMOS transistor MN11. The gate and drain of the tenth NMOS transistor MN10 are connected to the gate of the ninth NMOS transistor MN9, and the source and source of the tenth NMOS transistor MN10 are both connected to a floating ground V. HS The gate and drain of the eleventh NMOS transistor MN11 are connected to the gate of the twelfth NMOS transistor MN12, and the source of both the eleventh NMOS transistor MN11 and the source of the twelfth NMOS transistor MN12 are connected to a floating ground V. HS The drain of the ninth PMOS transistor MP9 is connected to the R terminal, and the drain of the twelfth PMOS transistor MP12 is connected to the S terminal of the latch.

[0064] like Figure 4 As shown in the figure, the embodiment of the present invention also illustrates a detailed circuit structure of a latch, which is... Figure 3 One implementation of a latch. Please refer to [link / reference]. Figure 4 The latch includes a first inverter and a second inverter.

[0065] The first inverter and the second inverter are connected in series to form a loop. The R terminal is the input terminal of the first inverter and the output terminal of the second inverter. The S terminal is the output terminal of the first inverter and the input terminal of the second inverter.

[0066] The latch output includes a first latch output and a second latch output;

[0067] The first latch output terminal is the input terminal of the first inverter and the output terminal of the second inverter, and the second latch output terminal is the output terminal of the first inverter and the input terminal of the second inverter.

[0068] like Figure 4 As shown in the figure, the embodiment of the present invention also illustrates a detailed circuit structure of a driver, for Figure 3 One implementation of the driver. Please refer to [link / reference]. Figure 4 The driver includes a first driving circuit connected to a first latch output terminal and a second driving circuit connected to a second latch output terminal. For example, since the square wave signal output from the latch terminal has weak driving capability, this embodiment of the invention uses a buffer as the driving circuit to progressively enhance the signal's power driving capability through the buffer, outputting a logic control signal with driving capability.

[0069] like Figures 5 to 8 As shown in the figure, the embodiments of the present invention illustrate the simulation results obtained by simulating the current-compensated level shift circuit described above, in order to explain its ability to resist common-mode noise interference and differential-mode noise interference.

[0070] in, Figure 5 The simulation waveform of common-mode noise interference before the current compensation circuit is added. Figure 6 The simulation waveforms for common-mode noise interference after adding the current compensation circuit are shown. The simulation conditions are the same for both simulations: INN and INP are 5V pulse signal inputs with a frequency of 50kHz, the gate bias of the high-voltage transistor is connected to a 5V bias voltage, and V is set... HS A square wave ranging from 0 to 100V, with the same frequency as the input signal, but with a delay of 100ns compared to the input signal. HB It is more than V HS A synchronous square wave signal with a high voltage of 5V was simulated; V HS The waveform output is scanned from 2ns to 1ns in rise time, with a step size of 0.2ns. Please refer to [link / reference]. Figure 5 and Figure 6 , Figure 5 It shows V without the addition of a current compensation circuit. HS RV HS and OUT1-V HS The output waveform diagram shows that when dv / dt is about 83V / ns, common-mode noise causes abrupt changes in the signal, which may lead to errors in the output logic. Figure 6 After adding a current compensation circuit, V HS RV HS and OUT1-V HSThe output waveform diagram shows that when dv / dt is approximately 100V / ns, common-mode noise causes abrupt signal changes, posing a risk of output logic errors. (Comparison) Figure 5 and Figure 6 The simulation results show that the current-compensated level shifting circuit provided in this embodiment of the invention has excellent common-mode noise immunity.

[0071] in, Figure 7 The simulation waveform of differential-mode noise interference before the current compensation circuit is added. Figure 7 The simulation waveforms for differential-mode noise interference after adding a current compensation circuit are shown. The simulation conditions for both simulations are the same, and the above... Figure 5 and Figure 6 The simulation conditions are the same, so they will not be repeated here. Furthermore, when dv / dt is selected to be approximately 71V / ns, a wide mismatch ratio is set for MH1 and MH2 to simulate process errors and artificially introduce differential-mode noise. Please refer to [link to relevant documentation]. Figure 7 and Figure 8 , Figure 7 It shows V without the addition of a current compensation circuit. HS RV HS and OUT1-V HS The output waveform diagram shows that when the mismatch tolerance (1-MH1 / MH2) of MH1 and MH2 is about 10%, differential mode noise causes abrupt changes in the signal, and there is a risk of errors in the output logic. Figure 8 This shows V after adding a current compensation circuit. HS RV HS and OUT1-V HS The output waveform diagram shows that when the mismatch tolerance between MH1 and MH2 is greater than 30%, RV HS and OUT1-V HS The sudden change in the output waveform indicates that the current compensation circuit has a good suppression effect on differential mode noise and can effectively improve the stability and reliability of the level shifting circuit.

[0072] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0073] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A current compensation based level shifting combinatorial circuit, characterized by, include: The level shifting circuit includes a first level input terminal and a second level input terminal for receiving low-voltage pulse signals, and also includes a first level output terminal and a second level output terminal for outputting high-voltage pulse signals. The common-mode noise cancellation circuit includes a first mirror input terminal connected to the first level output terminal, a second mirror input terminal connected to the second level output terminal, a first current output terminal that outputs a first current, a second current output terminal that outputs a second current, a third current output terminal that outputs a third current, and a fourth current output terminal that outputs a fourth current. The current compensation circuit includes a third mirror input terminal connected to the first level output terminal, a fourth mirror input terminal connected to the second level output terminal, a first compensation output terminal that outputs a first compensation current, and a second compensation output terminal that outputs a second compensation current. A latch, including an R terminal, a S terminal, and a latch output terminal; When differential-mode +dv / dt noise is present, the R terminal is 1 and the S terminal is 0. A mismatch occurs in the level shifting circuit, causing the first current and the second current to be less than the third current and the fourth current. Then, the first compensation output terminal, the first current output terminal, and the third current output terminal generate a first latch signal, which is input to the R terminal. In the first latch signal, the sum of the first current and the first compensation current is greater than or equal to the third current. The second compensation output terminal, the fourth current output terminal, and the second current output terminal generate a second latch signal, which is input to the S terminal. In the second latch signal, the fourth current minus the second compensation current is less than or equal to the second current. A driver, connected to the output of the latch, is used to enhance the square wave signal output from the latch and output a logic control signal with driving capability.

2. A current compensation based level shifting combinatorial circuit as claimed in claim 1, wherein, The first level input terminal and the second level input terminal are connected to the low-voltage pulse signal through a cascaded circuit including a high-voltage LDMOS and a low-voltage MOS.

3. A current-compensated level-shifting combination circuit according to claim 1 or 2, characterized in that The level shifting circuit includes a first NMOS transistor, a second NMOS transistor, a first LDMOS transistor, a second LDMOS transistor, a first PMOS transistor, a second PMOS transistor, a first Zener diode, and a second Zener diode; The first level input terminal is the gate of the first NMOS transistor, used to acquire the rising edge pulse signal in the low voltage pulse signal; the second level input terminal is the gate of the second NMOS transistor, used to acquire the falling edge pulse signal in the low voltage pulse signal. The source of the first NMOS tube and the source of the second NMOS tube are grounded, the drain of the first NMOS tube is connected with the source of the first LDMOS tube, and the drain of the second NMOS tube is connected with the source of the second LDMOS tube; the gates of the first LDMOS tube and the second LDMOS tube are connected with a bias voltage of 5V, the drain of the first LDMOS tube is connected with the drain of the first PMOS tube, and the drain of the second PMOS tube is connected with the drain of the first PMOS tube; the gate of the first PMOS tube is connected with the drain of the first PMOS tube, the gate of the second PMOS tube is connected with the drain of the second PMOS tube, the source of the first PMOS tube and the source of the second PMOS tube are connected with a floating power supply; the positive terminal of the first Zener diode is connected with the drain of the first PMOS tube, the positive terminal of the second Zener diode is connected with the drain of the second PMOS tube, and the negative terminal of the first Zener diode and the negative terminal of the second Zener diode are connected with the floating power supply; The first level output end is the gate of the first PMOS tube; and the second level output end is the gate of the second PMOS tube.

4. A current-compensated level-shifting combination circuit according to claim 1, wherein The current compensation circuit further comprises a first switch, a second switch and a third switch; the first switch and the second switch are connected with the S end, and the third switch is connected with the R end; When there is a differential mode-dv / dt noise, the current compensation circuit is closed through the first switch, the second switch and the third switch.

5. A current-compensated level-shifting combination circuit according to claim 4, wherein The current compensation circuit comprises a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube and an eighth NMOS tube; The seventh NMOS tube is the first switch, the eighth NMOS tube is the second switch, and the eighth PMOS tube is the third switch; the gate of the third PMOS tube is the third mirror input end and receives a high-voltage pulse signal output by the first level output end, and the gate of the fourth PMOS tube is the fourth mirror input end and receives a high-voltage pulse signal output by the second level output end; The source of the fourth PMOS tube and the source of the third PMOS tube are connected with a floating power supply, the drain of the fourth PMOS tube is connected with the drain of the third NMOS tube, and the drain of the third PMOS tube is connected with the drain of the fourth NMOS tube; the gate of the third NMOS tube is connected with the drain of the third NMOS tube and the gate of the fourth NMOS tube to form a current mirror, and the source of the third NMOS tube and the source of the fourth NMOS tube are connected with a floating ground; The gates of the fifth PMOS tube, the sixth PMOS tube and the seventh PMOS tube are connected with the drain of the fifth PMOS tube to form a current mirror, and the drain of the fifth PMOS tube is connected with the drain of the fourth NMOS tube; the source of the fifth PMOS tube, the source of the sixth PMOS tube and the source of the seventh PMOS tube are connected with a floating power supply; The gate and the drain of the fifth NMOS tube are connected and connected to the gate of the sixth NMOS tube to form a current mirror, and connected to the drain of the sixth PMOS tube, the source of the fifth NMOS tube and the source of the sixth NMOS tube are both connected to the floating ground; the drain of the seventh PMOS tube is connected with the R terminal, the drain of the sixth NMOS tube is connected with the S terminal; the gate of the eighth PMOS tube is connected with the R terminal, the drain of the eighth PMOS tube is connected with the gate of the seventh PMOS tube, the source of the eighth PMOS tube and the source of the seventh PMOS tube are both connected to the floating power supply; the drain of the seventh NMOS tube is connected with the drain of the fourth NMOS tube, the drain of the eighth NMOS tube is connected with the gate of the sixth NMOS tube, the gate of the seventh NMOS tube and the gate of the eighth NMOS tube are both connected to the S terminal, the source of the seventh NMOS tube and the source of the eighth NMOS tube are both connected to the floating ground.

6. A current-compensated level-shifting combination circuit according to claim 5, wherein The common mode noise elimination circuit comprises a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube and a twelfth NMOS tube; The gate of the eleventh PMOS tube and the gate of the twelfth PMOS tube are both connected to the gate of the second PMOS tube in the level shift circuit, the source of the eleventh PMOS tube and the source of the twelfth PMOS tube are both connected to the floating power supply, the drain of the eleventh PMOS tube is connected with the drain of the tenth NMOS tube, and the drain of the twelfth PMOS tube is connected with the drain of the twelfth NMOS tube; the gate of the ninth PMOS tube and the gate of the tenth PMOS tube are both connected to the gate of the first PMOS tube in the level shift circuit, the source of the ninth PMOS tube and the source of the tenth PMOS tube are both connected to the floating power supply, the drain of the ninth PMOS tube is connected with the drain of the ninth NMOS tube, and the drain of the tenth PMOS tube is connected with the drain of the eleventh NMOS tube; the gate of the tenth NMOS tube and the drain of the tenth NMOS tube are connected with the gate of the ninth NMOS tube, and the source of the tenth NMOS tube and the source of the eleventh NMOS tube are both connected to the floating ground; the gate of the eleventh NMOS tube and the drain of the eleventh NMOS tube are connected with the gate of the twelfth NMOS tube, and the source of the eleventh NMOS tube and the source of the twelfth NMOS tube are both connected to the floating ground; the drain of the ninth PMOS tube is connected to the R terminal, and the drain of the twelfth PMOS tube is connected to the S terminal of the latch.

7. A current-compensated level-shifting combination circuit according to claim 1, wherein The latch further comprises a first inverter and a second inverter; The first inverter and the second inverter are connected in series and form a loop, the R terminal is the input terminal of the first inverter and the output terminal of the second inverter, and the S terminal is the output terminal of the first inverter and the input terminal of the second inverter; The latch output terminal comprises a first latch output terminal and a second latch output terminal; The latch output terminal comprises a first latch output terminal and a second latch output terminal; The first latch output is an input of a first inverter and an output of a second inverter, and the second latch output is an output of the first inverter and an input of the second inverter.

8. A current-compensated level-shifting combination circuit according to claim 7, wherein, The driver includes a first driving circuit connected with the first latch output, and a second driving circuit connected with the second latch output.

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