Circuit structure system applied to PD fast charging to realize Type-C cable interface control

Abstract

The invention relates to a circuit structure system applied to PD fast charging to realize Type-C cable interface control, which comprises an upper driving NMOS transistor NM0, a lower driving NMOS transistor NM1, a voltage modulation module, a rising edge slope control module, a falling edge slope control module and a falling edge slope control capacitor C0, and is characterized in that a grid electrode of the upper driving NMOS transistor NM0 is connected with the rising edge slope control module, and a grid electrode of the lower driving NMOS transistor NM1 is connected with the falling edge slope control capacitor C0; the drain electrode of the upper driving NMOS tube NM0 is connected with the voltage modulation module, and the source electrode of the upper driving NMOS tube NM0 is connected with the drain electrode of the lower driving NMOS tube NM1. By adopting the circuit structure system applied to PD fast charging to realize Type-C cable interface control, the participation of an MCU is not needed, additional power consumption is not needed, a simple circuit is used, relatively stable communication signals of rising edge and falling edge time can be output under the application condition of different CC cables, and the reliability of the Type-C cable interface control is improved. Therefore, the PD authentication test standard of the USB-IF association is met.

Description

Technical Field

[0001] The present invention relates to the field of USB Type-C interface, and in particular to the field of PD fast charging, and specifically refers to a circuit structure system applied to PD fast charging to realize Type-C cable interface control. Background Art

[0002] In recent years, the USB Type-C interface has been more widely used in various electronic devices due to its advantages such as small size, full functions and high reliability.

[0003] Compared with traditional interfaces, the USB Type-C interface can be configured with the PD protocol, and the latest PD protocol can configure the charging power to 100W.

[0004] However, the PD protocol also has stricter requirements on the voltage value and rising and falling edges of the interface communication signal. The protocol requires the voltage value range to be: 1.04V ~ 1.2V, and the rising and falling edge time to be: 300nS ~ 500nS. Among them, whether the rising and falling edges of the communication signal meet the standards, especially whether they can meet the standards when using different cables, often becomes the key to whether the USB-IF Association's PD certification test can be passed.

[0005] Figure 1 This is the USB-IF Association's PD certification requirement for communication signal eye diagrams.

[0006] In order to meet the eye diagram requirements in different cable applications, that is, with different equivalent capacitances, the communication interface circuit is relatively complex. Some use MCU to monitor the interface voltage in real time and then make real-time dynamic adjustments, but this will greatly increase the chip's responsibility and product cost; others increase the internal current consumption to reduce the impact of different load capacitance values ​​of different cables on the rise and fall slopes.

[0007] Figure 2 It is a common Type-C interface circuit. It first uses the voltage modulation module to generate a voltage that meets the PD certification requirements, and then uses the current source and switches S1 and S2 internally to generate a communication signal Vinner that is independent of the load capacitance. Then, the op amp OP and resistor R0 are used to convert Vinner into a current signal, and finally the current signal is restored to a voltage signal through resistor R1 and output from the CC line. In order to make the signal independent of the equivalent capacitance Cload of the CC line, the current value flowing through PM4 and R1 will be designed to be very large, about 30mA or even larger. This undoubtedly increases the power consumption of the chip and also brings interference. Summary of the invention

[0008] The purpose of the present invention is to overcome the shortcomings of the above-mentioned prior art and provide a circuit structure system for PD fast charging to realize Type-C cable interface control, which meets the requirements of high power consumption, low interference and a wide range of applications.

[0009] In order to achieve the above objectives, the circuit structure system of the present invention applied to PD fast charging to realize Type-C cable interface control is as follows:

[0010] The circuit structure system applied to PD fast charging to realize Type-C cable interface control has the following main features: the system includes an upper driving NMOS tube NM0, a lower driving NMOS tube NM1, a voltage modulation module, a rising edge slope control module, a falling edge slope control module and a falling edge slope control capacitor C0; the gate of the upper driving NMOS tube NM0 is connected to the rising edge slope control module, the drain of the upper driving NMOS tube NM0 is connected to the voltage modulation module, the source of the upper driving NMOS tube NM0 is connected to the drain of the lower driving NMOS tube NM1, the gate of the lower driving NMOS tube NM1 is connected to the falling edge slope control module, the source of the lower driving NMOS tube NM1 is grounded, the two ends of the falling edge slope control capacitor C0 are connected between the gate and the drain of the lower driving NMOS tube NM1, the drain of the lower driving NMOS tube NM1 is connected to the CC line, and the CC line has a grounded equivalent load capacitor.

[0011] Preferably, the voltage modulation module is used to generate a voltage source Vreg, the rising edge slope control module is used to generate a ramp voltage Vg_rise when the logic control signal jumps from 0 to 1, and maintain it at a high voltage until the logic control signal becomes 0, the upper drive NMOS tube NM0 is used to control the rising edge and high level of the CC line, the lower drive NMOS tube NM1 is responsible for the falling edge and low level of the CC line, the falling edge slope control capacitor C0 equivalently amplifies the capacitance of the gate and the drain of the lower drive NMOS tube NM1, and the falling edge slope control module enables the CC line to obtain a basically constant falling time under different Cload conditions.

[0012] Preferably, the rising edge slope control module includes a first current source Ichg, an NMOS tube NM2, a first capacitor C1, a first charging switch S1, a second discharging switch S2 and a voltage clamping circuit, the gate of the NMOS tube NM2 is connected to the drain, the source of the NMOS tube NM2 is connected to one end of the first capacitor C1, the other end of the first capacitor C1 is grounded, one end of the first charging switch S1 is connected to the drain of the NMOS tube NM2, the other end of the first charging switch S1 is connected to the first current source Ichg, the second discharging switch S2 is connected to both ends of the first capacitor C1, and the voltage clamping circuit is connected to the gate of the upper driving NMOS tube NM0.

[0013] Preferably, when the logic control signal of the rising edge slope control module is 0, that is, when the CC line outputs a low level, the gate of the upper driving NMOS tube NM0 is biased at a voltage value lower than the threshold voltage Vtn; when the logic control signal jumps from 0 to 1, the first charging switch S1 is closed, the second discharging switch S2 is opened, the first current source Ichg charges the first capacitor C1, and the voltage Vc1 on the first capacitor C1 rises linearly from zero; the upper driving NMOS tube NM0 works in a voltage follower state to obtain the CC line voltage; the ramp voltage Vg_rise continues to rise, and after rising to the sum of the voltage source Vreg and the threshold voltage Vtn, the upper driving NMOS tube NM0 enters the linear region, and the CC line voltage reaches its high level.

[0014] Preferably, the voltage clamping circuit includes a current source Iclmp, a third switch S3, a fourth switch S4 and a first resistor R1, one end of the current source Iclmp is connected to the gate of the upper driving NMOS tube NM0, the other end of the current source Iclmp is connected to the third switch S3, the third switch S3 is connected to the fourth switch S4, one end of the first resistor R1 is connected to the fourth switch S4, and the other end is grounded.

[0015] Preferably, the value of the current source Iclmp is linearly related to the threshold voltage Vtn; by adjusting the resistance values ​​of R0 and the first resistor R1, the gate voltage of NM0 is pre-biased to a voltage value near the threshold voltage Vtn.

[0016] Preferably, the falling edge slope control module includes a second current source Ichg2, a lower edge slope control capacitor C0, a fifth charging switch S5, a sixth discharging switch S6 and a second voltage clamping circuit, one end of the fifth charging switch S5 is connected to the second current source Ichg2, the other end of the fifth charging switch S5 is connected to the gate of the lower driving NMOS tube NM1, one end of the sixth discharging switch S6 is connected to the gate of the lower driving NMOS tube NM1, and the other end is grounded, the second voltage clamping circuit is connected to the gate of the lower driving NMOS tube NM1, one end of the lower edge slope control capacitor C0 is connected to the gate of the lower driving NMOS tube NM1, and the other end is connected to the drain of the lower driving NMOS tube NM1.

[0017] Preferably, when the logic control signal of the falling edge slope control module is 1, the fifth charging switch S5 is closed, and the second current source Ichg2 drives the gate Vg_fall of the NMOS tube NM1 downward to inject current, and combines with the falling edge slope control capacitor C0 to control the falling edge of the CC line; the gate Vg_fall of the lower-driven NMOS tube NM1 continues to rise, and the lower-driven NMOS tube NM1 enters the linear region, that is, it works in the switching state, and the CC line voltage is pulled down to 0V; when the logic control signal jumps from 1 to 0, a pulse signal Tpu_rise is generated and the sixth discharge switch S6 is controlled to be closed, and the voltage of the gate Vg_fall of the lower-driven NMOS tube NM1 is instantly dropped to a low level, and the lower-driven NMOS tube NM1 is quickly closed.

[0018] Preferably, the system further comprises a gate-source parasitic capacitor Cgs and a gate-drain parasitic capacitor Cgd of the lower driving NMOS tube NM1, wherein both ends of the gate-source parasitic capacitor Cgs are connected between the gate and the source of the lower driving NMOS tube NM1, and both ends of the gate-drain parasitic capacitor Cgd are connected between the gate and the drain of the lower driving NMOS tube NM1.

[0019] The circuit structure system of the present invention for PD fast charging to realize Type-C cable interface control does not require MCU participation and does not require additional power consumption. It uses a simple circuit and can output relatively stable rising and falling edge time communication signals under different CC cable application conditions, thereby meeting the PD certification test standards of the USB-IF Association. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is a diagram showing the requirements for the communication signal eye diagram of the USB-IF Association's PD certification.

[0021] Figure 2 This is a schematic diagram of the common Type-C interface circuit structure.

[0022] Figure 3 This is a circuit schematic diagram of the circuit structure system of the present invention applied to PD fast charging to realize Type-C cable interface control.

[0023] Figure 4 The present invention is a rising edge slope control circuit diagram of a circuit structure system for controlling a Type-C cable interface for PD fast charging.

[0024] Figure 5 The present invention is a circuit diagram of a rising edge slope control circuit with a voltage clamping circuit for a circuit structure system for controlling a Type-C cable interface applied to PD fast charging.

[0025] Figure 6 This is a falling edge slope control circuit diagram of a circuit structure system for controlling a Type-C cable interface for PD fast charging according to the present invention.

[0026] Figure 7 This is a principle analysis diagram of the falling edge slope control circuit of the circuit structure system of the present invention applied to PD fast charging to realize Type-C cable interface control.

[0027] Figure 8 This is a schematic diagram of the signal waveform of the Type-C cable interface control circuit of the circuit structure system for implementing Type-C cable interface control for PD fast charging of the present invention. DETAILED DESCRIPTION

[0028] In order to more clearly describe the technical content of the present invention, further description is given below in conjunction with specific embodiments.

[0029] The circuit structure system of the present invention applied to PD fast charging to realize Type-C cable interface control includes an upper driving NMOS tube NM0, a lower driving NMOS tube NM1, a voltage modulation module, a rising edge slope control module, a falling edge slope control module and a falling edge slope control capacitor C0, the gate of the upper driving NMOS tube NM0 is connected to the rising edge slope control module, the drain of the upper driving NMOS tube NM0 is connected to the voltage modulation module, the source of the upper driving NMOS tube NM0 is connected to the drain of the lower driving NMOS tube NM1, the gate of the lower driving NMOS tube NM1 is connected to the falling edge slope control module, the source of the lower driving NMOS tube NM1 is grounded, the two ends of the falling edge slope control capacitor C0 are connected between the gate and the drain of the lower driving NMOS tube NM1, the drain of the lower driving NMOS tube NM1 is connected to the CC line, and the CC line has a grounded equivalent load capacitor.

[0030] As a preferred embodiment of the present invention, the voltage modulation module is used to generate a voltage source Vreg, the rising edge slope control module is used to generate a ramp voltage Vg_rise when the logic control signal jumps from 0 to 1, and maintain it at a high voltage until the logic control signal becomes 0, the upper drive NMOS tube NM0 is used to control the rising edge and high level of the CC line, the lower drive NMOS tube NM1 is responsible for the falling edge and low level of the CC line, the falling edge slope control capacitor C0 equivalently amplifies the capacitance of the gate and the drain of the lower drive NMOS tube NM1, and the falling edge slope control module enables the CC line to obtain a basically constant falling time under different Cload conditions.

[0031] As a preferred embodiment of the present invention, the rising edge slope control module includes a first current source Ichg, an NMOS tube NM2, a first capacitor C1, a first charging switch S1, a second discharging switch S2 and a voltage clamping circuit, the gate of the NMOS tube NM2 is connected to the drain, the source of the NMOS tube NM2 is connected to one end of the first capacitor C1, the other end of the first capacitor C1 is grounded, one end of the first charging switch S1 is connected to the drain of the NMOS tube NM2, the other end of the first charging switch S1 is connected to the first current source Ichg, the second discharging switch S2 is connected to both ends of the first capacitor C1, and the voltage clamping circuit is connected to the gate of the upper driving NMOS tube NM0.

[0032] As a preferred embodiment of the present invention, when the logic control signal of the rising edge slope control module is 0, that is, when the CC line outputs a low level, the gate of the upper driving NMOS tube NM0 is biased at a voltage value lower than the threshold voltage Vtn; when the logic control signal jumps from 0 to 1, the first charging switch S1 is closed, the second discharging switch S2 is opened, the first current source Ichg charges the first capacitor C1, and the voltage Vc1 on the first capacitor C1 rises linearly from zero; the upper driving NMOS tube NM0 works in a voltage follower state to obtain the CC line voltage; the ramp voltage Vg_rise continues to rise, and after rising to the sum of the voltage source Vreg and the threshold voltage Vtn, the upper driving NMOS tube NM0 enters the linear region, and the CC line voltage reaches its high level.

[0033] As a preferred embodiment of the present invention, the voltage clamping circuit includes a current source Iclmp, a third switch S3, a fourth switch S4 and a first resistor R1, one end of the current source Iclmp is connected to the gate of the upper driving NMOS tube NM0, the other end of the current source Iclmp is connected to the third switch S3, the third switch S3 is connected to the fourth switch S4, one end of the first resistor R1 is connected to the fourth switch S4, and the other end is grounded.

[0034] As a preferred embodiment of the present invention, the value of the current source Iclmp is linearly related to the threshold voltage Vtn; by adjusting the resistance values ​​of R0 and the first resistor R1, the gate voltage of NM0 is pre-biased at a voltage value near the threshold voltage Vtn.

[0035] As a preferred embodiment of the present invention, the falling edge slope control module includes a second current source Ichg2, a lower edge slope control capacitor C0, a fifth charging switch S5, a sixth discharging switch S6 and a second voltage clamping circuit, one end of the fifth charging switch S5 is connected to the second current source Ichg2, the other end of the fifth charging switch S5 is connected to the gate of the lower driving NMOS tube NM1, one end of the sixth discharging switch S6 is connected to the gate of the lower driving NMOS tube NM1, and the other end is grounded, the second voltage clamping circuit is connected to the gate of the lower driving NMOS tube NM1, one end of the lower edge slope control capacitor C0 is connected to the gate of the lower driving NMOS tube NM1, and the other end is connected to the drain of the lower driving NMOS tube NM1.

[0036] As a preferred embodiment of the present invention, when the logic control signal of the falling edge slope control module is 1, the fifth charging switch S5 is closed, and the second current source Ichg2 drives the gate Vg_fall of the NMOS tube NM1 downward to inject current, and combines with the falling edge slope control capacitor C0 to control the falling edge of the CC line; the gate Vg_fall of the lower-driven NMOS tube NM1 continues to rise, and the lower-driven NMOS tube NM1 enters the linear region, that is, it works in the switching state, and the CC line voltage is pulled down to 0V; when the logic control signal jumps from 1 to 0, a pulse signal Tpu_rise is generated and the sixth discharge switch S6 is controlled to be closed, and the voltage of the gate Vg_fall of the lower-driven NMOS tube NM1 is instantly dropped to a low level, and the lower-driven NMOS tube NM1 is quickly closed.

[0037] As a preferred embodiment of the present invention, the system further includes a gate-source parasitic capacitor Cgs and a gate-drain parasitic capacitor Cgd of the lower driving NMOS tube NM1, wherein both ends of the gate-source parasitic capacitor Cgs are connected between the gate and the source of the lower driving NMOS tube NM1, and both ends of the gate-drain parasitic capacitor Cgd are connected between the gate and the drain of the lower driving NMOS tube NM1.

[0038] In a specific embodiment of the present invention, Figure 3 This is the schematic diagram of the Type-C cable interface control circuit proposed in the patent of this invention. It includes an upper driving NMOS tube NM0, a lower driving NMOS tube NM1, a voltage modulation module, a rising edge slope control module, a falling edge slope control module and a falling edge slope control capacitor C0.

[0039] The voltage modulation module generates a voltage source Vreg that meets the PD certification requirements. This voltage is the high-level voltage during CC line communication.

[0040] The rising edge slope control module generates a ramp voltage Vg_rise when the logic control signal jumps from 0 to 1, and then maintains it at a high voltage until the logic control signal becomes 0.

[0041] The upper drive NMOS tube NM0 controls the rising edge and high level of the CC line. When the logic control signal jumps from 0 to 1, Vg_rise is a ramp-up voltage. At this time, NM0 works in the saturation region and is a voltage follower; when Vg_rise continues to rise, NM0 enters the linear region and is a switch. At this time, the CC line voltage is equal to the Vreg voltage.

[0042] The lower driving NMOS tube NM1 is responsible for the falling edge and low level of the CC line.

[0043] The falling edge slope controls the capacitor C0, which is equivalent to amplifying the GD terminal capacitance of the NMOS tube NM1.

[0044] The falling edge slope control module, combined with the falling edge slope control capacitor C0 and the lower driving NMOS tube NM1, can achieve a substantially constant falling time of the CC line under different Cload conditions.

[0045] Figure 4 The rising slope control circuit diagram proposed by the present invention is composed of a current source Ichg, an NMOS tube NM2, a capacitor C1, a charging switch S1, a discharging switch S2 and a voltage clamping circuit.

[0046] When the upper driving NMOS tube NM0 works in the voltage follower stage, the CC line voltage has a voltage drop of a threshold value Vtn relative to the gate voltage Vg_rise of NM0, and thus a diode-connected NM2 is introduced to compensate for the Vtn voltage drop.

[0047] After the logic control signal changes from 0 to 1, the charging switch S1 is closed and the discharging switch S2 is opened. At this time, the current source Ichg charges the capacitor C1, and the voltage Vc1 on C1 rises linearly from zero.

[0048] Vc1(t)=(Ichg×t) / C1;

[0049] Due to the existence of NM2, Vg_rise is higher than Vc1 by a threshold voltage Vtn.

[0050] Vg_rise(t)=Vc1(t)+Vtn=(Ichg×t) / C1+Vtn;

[0051] At this time, the upper driving NMOS tube NM0 works in a voltage follower state, and the CC line voltage can be obtained.

[0052] Vcc(t)=Vg_rise(t)-Vtn=((Ichg×t) / C1+Vtn)-Vtn=(Ichg×t) / C1;

[0053] The Vg_rise voltage continues to rise, and when it rises to Vreg+Vtn, the upper driving NMOS tube NM0 enters the linear region, and NM0 can be regarded as a switch. At this time, the CC line voltage reaches its high level, and the voltage value is the output voltage of the voltage modulation module:

[0054] Vcc(hgh)=Vreg;

[0055] Since the size of the upper driving NMOS tube NM0 is relatively large, the gate will have a relatively large parasitic capacitance. In order to reduce the delay time of jumping from 0 to 1, the present invention introduces a voltage clamping module at the gate of NM0. When the logic control signal is 0, that is, the CC line outputs a low level, the gate of NM0 is first biased at a voltage value slightly lower than Vtn, so that once the logic control signal jumps to 1, the upper driving NMOS tube NM0 can be quickly turned on, thereby reducing the delay time.

[0056] Figure 5 The rising edge slope control circuit diagram with a voltage clamping circuit proposed by the present invention includes a current source Iclmp, switches S3 and S4, and a resistor R1.

[0057] The value of the current source Iclmp is designed to be linearly related to the threshold Vtn of the NMOS. A reference resistor R0 can be introduced through a simple circuit, which is designed as follows:

[0058] Iclmp=Vtn / R0;

[0059] This circuit is easy to implement for those skilled in the art, so it will not be described in detail here.

[0060] When the logic control signal is 0, switches S3 and S4 are both closed, and the gate voltage of NM0 can be obtained at this time.

[0061] Vg_rise(0)=Iclmp×R1=Vtn×R1 / R0;

[0062] As long as the resistance values ​​of R0 and R1 are set reasonably, the gate voltage of NM0 can be pre-biased to a voltage value near Vtn.

[0063] Figure 6The circuit diagram of the falling edge slope control proposed by the present invention is composed of a current source Ichg2, a lower edge slope control capacitor C0, a charging switch S5, a discharging switch S6 and a voltage clamping circuit 2.

[0064] When the logic control signal is 1, the switch S5 is closed, and the current source Ichg2 drives the gate Vg_fall of the NMOS tube NM1 downward to inject current. Combined with the falling edge slope control capacitor C0, the falling edge of the CC line is controlled.

[0065] After that, the gate voltage Vg_fall of the lower driving NMOS tube NM1 will continue to rise. At this time, NM1 enters the linear region, that is, it works in the switching state, and the CC line voltage is pulled down to 0V.

[0066] When the logic control signal jumps from 1 to 0, a pulse signal Tpu_rise is generated, which controls the switch S6 to close, and the voltage of the gate Vg_fall of the lower driving NMOS tube NM1 is instantly lowered to a low level, so that NM1 is quickly turned off.

[0067] In order to reduce the delay time from 1 to 0, similar to the rising slope control circuit, a voltage clamping module is also introduced at the gate of NM1. When the logic control signal is 1, that is, the CC line outputs a high level, the gate of NM1 is first biased at a voltage slightly lower than Vtn, so that once the logic control signal jumps to 0, the lower driving NMOS tube NM1 can be turned on quickly, thereby reducing the delay time.

[0068] Figure 7 This is a schematic diagram of the principle of the falling slope control circuit proposed by the present invention, where Cgs and Cgd are the gate-source parasitic capacitance and gate-drain parasitic capacitance of the lower driving NMOS tube NM1, respectively. Ichg2 is the current injected by the current source into the gate Vg_fall of NM1, Igs is the current charged to the gate-source parasitic capacitance Cgs, Igd is the sum of the currents charged to the gate-drain parasitic capacitance Cgd and the falling slope control capacitor C0, Id is the drain current of the lower driving NMOS tube NM1, and Icc is the current flowing out of the CC cable, that is, the discharge current of Cload.

[0069] When the logic control signal jumps to 0, Ichg2 starts to charge Vg_fall. Initially, NM1 is not turned on yet, Id and Igd are both 0, and Igs = Ichg2.

[0070] Since the gate Vg_fall of NM1 has been biased near Vtn before the logic control signal jumps to 0, Vg_fall will quickly reach the turn-on threshold Vtn of NM1.

[0071] Id = Gm × (Vg_fall - Vtn);

[0072] Where Gm is the transconductance of NM1.

[0073] The existence of Id is equivalent to discharging the parasitic capacitance Cload of the CC line, thereby causing the Vcc voltage to decrease.

[0074] The reduction of Vcc voltage is equivalent to discharging the C0 and Cgd capacitors, so that the Igd current is not zero, that is, part of Ichg2 flows to Cgs, and the other part flows to C0 and Cds. At this time:

[0075] Ichg2=Igd+Igs;

[0076] At this time, Ichg2 charges Cgs a little bit, that is, Vg_fall increases by △Vg_fall, so Id will increase by △Id. So Vcc will speed up the decline, which is equivalent to the voltage across the capacitors C0 and Cgd dropping by △Vgd more in △t time, so the Igd current will increase

[0077] △Igd=(C0+Cgd)×△Vgd / △t;

[0078] That is, Igd increases, resulting in Igs decrease. This negative feedback can automatically balance the ratio of Igs and Igd, so that the gate voltage Vg_fall of the lower driving NMOS tube NM1 is maintained at a platform voltage.

[0079] By setting reasonable values ​​for Ichg2 and C0, the falling slope of the CC line Vcc can be controlled.

[0080] Figure 8 This is a schematic diagram of the signal waveform of the Type-C cable interface control circuit proposed in the present invention.

[0081] The present invention is not necessarily or only limited to be applied to Type-C cable interfaces, but can also be applied to general communication interfaces.

[0082] The specific implementation scheme of this embodiment can refer to the relevant description in the above embodiment, which will not be repeated here.

[0083] It can be understood that the same or similar parts of the above embodiments can be referenced to each other, and the contents not described in detail in some embodiments can refer to the same or similar contents in other embodiments.

[0084] It should be noted that, in the description of the present invention, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, the meaning of "plurality" refers to at least two.

[0085] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present invention includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present invention belong.

[0086] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution device. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0087] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the corresponding program may be stored in a computer-readable storage medium, which, when executed, includes one of the steps of the method embodiment or a combination thereof.

[0088] In addition, each functional unit in each embodiment of the present invention may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0089] The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0090] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0091] The circuit structure system of the present invention for PD fast charging to realize Type-C cable interface control does not require MCU participation and does not require additional power consumption. It uses a simple circuit and can output relatively stable rising and falling edge time communication signals under different CC cable application conditions, thereby meeting the PD certification test standards of the USB-IF Association.

[0092] In this specification, the present invention has been described with reference to specific embodiments thereof. However, it is apparent that various modifications and variations may be made without departing from the spirit and scope of the present invention. Therefore, the specification and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A circuit structure system for PD fast charging to realize Type-C cable interface control, characterized in that: The system comprises an upper driving NMOS tube NM0, a lower driving NMOS tube NM1, a voltage modulation module, a rising edge slope control module, a falling edge slope control module and a falling edge slope control capacitor C0, wherein the gate of the upper driving NMOS tube NM0 is connected to the rising edge slope control module, the drain of the upper driving NMOS tube NM0 is connected to the voltage modulation module, the source of the upper driving NMOS tube NM0 is connected to the drain of the lower driving NMOS tube NM1, the gate of the lower driving NMOS tube NM1 is connected to the falling edge slope control module, the source of the lower driving NMOS tube NM1 is grounded, the two ends of the falling edge slope control capacitor C0 are connected between the gate and the drain of the lower driving NMOS tube NM1, the drain of the lower driving NMOS tube NM1 is connected to the CC line, and the CC line has a grounded equivalent load capacitor.

2. The circuit structure system for controlling the Type-C cable interface for PD fast charging according to claim 1 is characterized in that: The voltage modulation module is used to generate a voltage source Vreg, the rising edge slope control module is used to generate a ramp voltage Vg_rise when the logic control signal jumps from 0 to 1, and maintain it at a high voltage until the logic control signal becomes 0, the upper drive NMOS tube NM0 is used to control the rising edge and high level of the CC line, the lower drive NMOS tube NM1 is responsible for the falling edge and low level of the CC line, the falling edge slope control capacitor C0 equivalently amplifies the capacitance of the gate and the drain of the lower drive NMOS tube NM1, and the falling edge slope control module enables the CC line to obtain a basically constant falling time under different Cload conditions.

3. The circuit structure system for controlling the Type-C cable interface for PD fast charging according to claim 1 is characterized in that: The rising slope control module includes a first current source Ichg, an NMOS tube NM2, a first capacitor C1, a first charging switch S1, a second discharging switch S2 and a voltage clamping circuit, wherein the gate of the NMOS tube NM2 is connected to the drain, the source of the NMOS tube NM2 is connected to one end of the first capacitor C1, the other end of the first capacitor C1 is grounded, one end of the first charging switch S1 is connected to the drain of the NMOS tube NM2, the other end of the first charging switch S1 is connected to the first current source Ichg, the second discharging switch S2 is connected to both ends of the first capacitor C1, and the voltage clamping circuit is connected to the gate of the upper driving NMOS tube NM0.

4. The circuit structure system for controlling the Type-C cable interface for PD fast charging according to claim 1, characterized in that: In the rising edge slope control module, when the logic control signal is 0, that is, when the CC line outputs a low level, the gate of the upper driving NMOS tube NM0 is biased at a voltage value lower than the threshold voltage Vtn; when the logic control signal jumps from 0 to 1, the first charging switch S1 is closed, the second discharging switch S2 is opened, the first current source Ichg charges the first capacitor C1, and the voltage Vc1 on the first capacitor C1 rises linearly from zero; the upper driving NMOS tube NM0 works in a voltage follower state to obtain the CC line voltage; the ramp voltage Vg_rise continues to rise, and after rising to the sum of the voltage source Vreg and the threshold voltage Vtn, the upper driving NMOS tube NM0 enters the linear region, and the CC line voltage reaches its high level.

5. The circuit structure system for controlling the Type-C cable interface for PD fast charging according to claim 3 is characterized in that: The voltage clamping circuit includes a current source Iclmp, a third switch S3, a fourth switch S4 and a first resistor R1, one end of the current source Iclmp is connected to the gate of the upper driving NMOS tube NM0, the other end of the current source Iclmp is connected to the third switch S3, the third switch S3 is connected to the fourth switch S4, one end of the first resistor R1 is connected to the fourth switch S4, and the other end is grounded.

6. The circuit structure system for controlling the Type-C cable interface for PD fast charging according to claim 5, characterized in that: The value of the current source Iclmp is linearly related to the threshold voltage Vtn; by adjusting the resistance values ​​of R0 and the first resistor R1, the gate voltage of NM0 is pre-biased to a voltage value near the threshold voltage Vtn.

7. The circuit structure system for controlling the Type-C cable interface for PD fast charging according to claim 1, characterized in that: The falling edge slope control module includes a second current source Ichg2, a lower edge slope control capacitor C0, a fifth charging switch S5, a sixth discharging switch S6 and a second voltage clamping circuit, one end of the fifth charging switch S5 is connected to the second current source Ichg2, the other end of the fifth charging switch S5 is connected to the gate of the lower driving NMOS tube NM1, one end of the sixth discharging switch S6 is connected to the gate of the lower driving NMOS tube NM1, and the other end is grounded, the second voltage clamping circuit is connected to the gate of the lower driving NMOS tube NM1, one end of the lower edge slope control capacitor C0 is connected to the gate of the lower driving NMOS tube NM1, and the other end is connected to the drain of the lower driving NMOS tube NM1.

8. The circuit structure system for controlling the Type-C cable interface for PD fast charging according to claim 7, characterized in that: When the logic control signal of the falling edge slope control module is 1, the fifth charging switch S5 is closed, and the second current source Ichg2 drives the gate Vg_fall of the NMOS tube NM1 downward to inject current, and combines with the falling edge slope control capacitor C0 to control the falling edge of the CC line; the gate Vg_fall of the lower-driven NMOS tube NM1 continues to rise, and the lower-driven NMOS tube NM1 enters the linear region, that is, it works in the switching state, and the CC line voltage is pulled down to 0V; when the logic control signal jumps from 1 to 0, a pulse signal Tpu_rise is generated and the sixth discharge switch S6 is controlled to be closed, and the voltage of the gate Vg_fall of the lower-driven NMOS tube NM1 is instantly dropped to a low level, and the lower-driven NMOS tube NM1 is quickly closed.

9. The circuit structure system for controlling the Type-C cable interface for PD fast charging according to claim 1, characterized in that: The system also includes a gate-source parasitic capacitor Cgs and a gate-drain parasitic capacitor Cgd of the lower driving NMOS tube NM1, wherein both ends of the gate-source parasitic capacitor Cgs are connected between the gate and the source of the lower driving NMOS tube NM1, and both ends of the gate-drain parasitic capacitor Cgd are connected between the gate and the drain of the lower driving NMOS tube NM1.

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