Redundancy calibration method and device and terminal equipment

Abstract

The invention relates to the technical field of integrated circuits, in particular to a redundancy calibration method and device and terminal equipment, the method is applied to a lower polar plate sampling SAR ADC circuit, the lower polar plate sampling SAR ADC circuit comprises a single-ended SAR ADC circuit and a differential SAR ADC circuit, and the method comprises the following steps: sampling a binary capacitor array based on a lower polar plate of a plurality of sampling capacitors; after the sampling operation is completed, performing digital-to-analog conversion on the binary capacitor array according to a preset order from a high order to a low order to obtain a redundant bit comparison result of the redundant capacitor and a non-redundant bit comparison result of each sampling capacitor; and superposing the redundant bit comparison result on the plurality of non-redundant bit comparison results to calibrate the output binary code of the comparator. The redundancy calibration method is applied to the SAR ADC circuit, and the calibration accuracy of the output structure of the SAR ADC circuit is effectively improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a redundant calibration method, apparatus and terminal device. Background Art

[0002] With the rapid development of integrated circuit technology, the integration of chips is getting higher and higher, and various interface circuits are also increasing. Among them, the analog-to-digital converter (ADC) is an interface circuit used in the analog domain and the digital domain to convert analog signals into digital signals. The successive approximation register analog-to-digital converter (SAR ADC) has been widely used due to its simple structure and good matching with the process. At the same time, users have put forward higher requirements for the redundant calibration of SAR ADC circuits.

[0003] The redundant calibration method of the SAR ADC circuit proposed in recent years has a great defect. When the misjudgment occurs in the previous bit immediately adjacent to the redundant bit, although the error range is within the redundant range, it still cannot be calibrated back, which leads to errors in the output results of the SAR ADC circuit. Therefore, there are certain limitations in the application process. In other words, the existing redundant calibration method has the technical problem of poor calibration accuracy when applied to SAR ADC. Summary of the invention

[0004] The main purpose of the present application is to provide a redundant calibration method, apparatus and terminal device, aiming to improve the accuracy of redundant calibration for SAR ADC.

[0005] To achieve the above-mentioned object, the present application provides a redundant calibration method, which is applied to a SAR ADC circuit for lower plate sampling, wherein the SAR ADC circuit for lower plate sampling includes: a single-ended SAR ADC circuit, wherein the single-ended SAR ADC circuit includes: a binary capacitor array, wherein redundant capacitors in the binary capacitor array are added after a target capacitor, wherein the number of the target capacitors is at least one, and the target capacitor refers to any sampling capacitor in the binary capacitor array; The redundant capacitor includes a first capacitor and a second capacitor, wherein the accumulated data between the capacitance data of the first capacitor and the capacitance data of the second capacitor is equal to the capacitance data of the target capacitor; The redundant calibration method comprises: Performing a sampling operation on the binary capacitor array based on the lower plates of the plurality of sampling capacitors; After completing the sampling operation, performing digital-to-analog conversion on the binary capacitor array in a preset high-bit to low-bit order to obtain a redundant bit comparison result of the redundant capacitor and a non-redundant bit comparison result of each of the sampling capacitors; The redundant bit comparison result is superimposed on a plurality of the non-redundant bit comparison results to calibrate the output binary code of the comparator.

[0006] In addition, to achieve the above purpose, the present application also provides a redundant calibration device, and the redundant calibration device of the present application includes: A sampling module, used for performing a sampling operation on the binary capacitor array based on the lower plates of the plurality of sampling capacitors; A conversion module, configured to perform digital-to-analog conversion on the binary capacitor array in a preset high-to-low order after completing the sampling operation, to obtain a redundant bit comparison result of the redundant capacitor and a non-redundant bit comparison result of each of the sampling capacitors; The calibration module is used to superimpose the redundant bit comparison result on the plurality of non-redundant bit comparison results to calibrate the output binary code of the comparator.

[0007] Each functional module of the redundant calibration device of the present application implements the steps of the redundant calibration method of the present application as described above during operation.

[0008] In addition, to achieve the above-mentioned purpose, the present application also provides a terminal device, which includes a memory, a processor, and a redundant calibration program stored in the memory and executable on the processor, and the redundant calibration program implements the steps of the above-mentioned redundant calibration method when executed by the processor.

[0009] The redundant calibration method of the present application is applied to a single-ended SAR ADC circuit, and the single-ended SAR ADC circuit includes: a binary capacitor array, and the redundant capacitors in the binary capacitor array are added after the target capacitor, wherein the number of the target capacitors is at least one, and the target capacitor refers to any sampling capacitor in the binary capacitor array. In the present application, a sampling operation is first performed on the binary capacitor array based on the lower plates of multiple sampling capacitors. After completing the sampling operation, the binary capacitor array is converted in a preset high-to-low order in the comparator of the single-ended SAR ADC circuit to obtain a redundant bit comparison result of the redundant capacitor and a non-redundant bit comparison result of each sampling capacitor; then the redundant bit comparison result is superimposed on multiple non-redundant bit comparison results to calibrate the output binary code of the comparator.

[0010] Different from the traditional redundant calibration method, the present application performs sampling operation on the binary capacitor array based on the lower plates of multiple sampling capacitors, that is, the redundant capacitors in the present application do not participate in the sampling, and thus there is no need to additionally design a circuit module for reducing the input signal gain, thereby reducing the complexity of the single-ended SAR ADC circuit. In addition, after completing the sampling operation, the binary capacitor array is converted according to a preset high-to-low order, so that the redundant bit comparison results of the redundant capacitors and the non-redundant bit comparison results of each sampling capacitor can be obtained more simply and quickly, and then the redundant bit comparison results are superimposed on multiple non-redundant bit comparison results, so that the output binary code of the comparator can be accurately obtained, and then the output binary code is calibrated to improve the accuracy of redundant calibration of the single-ended structure SAR ADC. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a flowchart of the first embodiment of the redundant calibration method of the present application; Figure 2 This is a circuit diagram of a single-ended SAR ADC in which the redundant calibration method of the present application is applied; Figure 3 It is a schematic diagram of a 4-bit embodiment of a redundant calibration method of the present application applied to a single-ended SAR ADC circuit; Figure 4 This is an operation flow chart of an embodiment 4bit of the redundant calibration method of the present application applied to a single-ended SAR ADC circuit; Figure 5 It is a schematic diagram of a DEC logic module involved in a 4-bit embodiment of a redundant calibration method of the present application applied to a single-ended SAR ADC circuit; Figure 6 It is a conversion process diagram of a 4-bit embodiment of a single-ended SAR ADC circuit without redundancy; Figure 7 It is a conversion process diagram of a 4-bit embodiment of a single-ended SAR ADC circuit of the present application; Figure 8 This is a circuit structure diagram of a differential SAR ADC in which the redundant calibration method of the present application is applied; Fig. 9 This is an operation flow chart of an embodiment 5bit of the redundant calibration method of the present application applied to a differential SAR ADC circuit; Fig.10 It is a schematic diagram of the structure of a redundant calibration device involved in an embodiment of the present application; Fig.11 This is a schematic diagram of the structure of the terminal device involved in the embodiment of the present application.

[0012] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0013] The present application embodiment provides a redundant calibration method, referring to Figure 1 As shown, Figure 1 It is a flowchart of the first embodiment of the redundant calibration method of the present application.

[0014] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0015] In this embodiment, the redundant calibration method of the present application is applied to a single-ended SAR ADC circuit. In other words, the redundant calibration method is executed by a terminal device including the single-ended SAR ADC circuit, specifically by a control center of the terminal device.

[0016] Further, in some feasible embodiments, the single-ended SAR ADC circuit includes: a binary capacitor array, wherein redundant capacitors in the binary capacitor array are added after the target capacitor, wherein the number of the target capacitor is at least one, and the target capacitor refers to any sampling capacitor in the binary capacitor array.

[0017] In this embodiment, refer to Figure 2 , Figure 2 The redundant calibration method of the present application is applied to the circuit structure diagram of a single-ended SAR ADC. The single-ended SAR ADC circuit includes a binary capacitor array, a comparator, a SAR logic module and a DEC logic module connected in sequence, wherein the binary capacitor array is connected to the negative input terminal of the comparator, and the positive input terminal of the comparator can be connected to the upper plate of the capacitor, such as Figure 2 As shown, C+ (the capacitor can be a device that can realize the capacitor function, such as a MOS capacitor, a MOM capacitor or a MIM capacitor, and the capacitor type can be different from the negative input terminal), the lower plate of the capacitor is connected to the ground level GND, that is, the lower plate of the capacitor is connected to the ground terminal. In addition, the output terminal of the comparator, the SAR logic module and the DEC logic module are connected in sequence.

[0018] It should be noted that, refer to Figure 2In the sampling phase, the positive input of the comparator is connected to the Vcm0 voltage through a switch; after the sampling is completed, the switch connected to the Vcm0 voltage is disconnected, and the positive input of the comparator is in a high impedance state, and is maintained at the Vcm0 voltage by the C+ capacitor. In addition, the positive input of the comparator can also be connected to the Vcm0 voltage without a capacitor in both the sampling phase and the conversion phase, and this application does not impose any restrictions on this.

[0019] In addition, it should be noted that the positive input terminal and the negative input terminal of the comparator can be interchanged. It is only necessary to add an inverter to the output of the comparator. This application does not impose any restrictions on this.

[0020] The redundant capacitor includes a first capacitor and a second capacitor, wherein the accumulated data between the capacitance data of the first capacitor and the capacitance data of the second capacitor is equal to the capacitance data of the target capacitor.

[0021] In this embodiment, the redundant capacitor includes a first capacitor and a second capacitor. When the capacitance data of the first capacitor and the capacitance data of the second capacitor are equal, the capacitance data of the first capacitor is half of the capacitance data of the target capacitor. Figure 2 , the redundant capacitor can be represented by CiR, and each redundant capacitor in the binary capacitor array will be split into two capacitors, namely the first capacitor CiRN and the second capacitor CiRP, and CiRN=CiRP=Ci / 2, where Ci is the target capacitor, also known as the sampling capacitor, and i refers to the position of the sampling capacitor. During the step of performing the sampling operation on the binary capacitor array based on the lower plates of the plurality of sampling capacitors (i.e., in the sampling phase), the first capacitor CiRN is connected to GND, and the second capacitor CiRP is connected to VREF.

[0022] It should be noted that VREF is the reference voltage value provided by the reference voltage terminal; Vi is the input signal, which acts on multiple sampling capacitors in the binary capacitor array, and can also be understood as the analog quantity to be converted sent to the comparator, that is, the voltage value of the input signal; GND is the ground level; Vcm is the initial value of the redundant voltage, and its value is VREF / 2; Vcm0 is the common-mode voltage in the sampling stage of the comparator, that is, the common-mode input voltage of the op amp.

[0023] In addition, it should be noted that when CiRN=CiRP=Ci / 2, a bidirectional and symmetrical redundant calibration effect can be achieved. This application recommends using CiRN=CiRP=Ci / 2. However, if you want to achieve an asymmetric calibration effect, you only need to make the value of Vcm deviate from VREF / 2, that is, CiRN is not equal to CiRP, and at this time, to output the corresponding code, you need to replace 0.5 in (br-0.5) with the coefficient obtained by CiRP / (CiRN+CiRP). In other words, CiRN+CiRP=Ci in this application, but the values ​​of CiRN and CiRP can be different, and even one of them can be 0. These situations are within the protection scope of this application, and the value range of Vcm in this application is 0 to VREF.

[0024] During the sampling phase, the input of the comparator is connected to the Vcm0 voltage through a switch, wherein the applicable voltage value range of Vcm0 is also 0 to VREF, and VREF / 2 is recommended; VREF / 2 is only used as a recommended value, and the protection range of Vcm0 in this application is still 0 to VREF.

[0025] The redundant calibration method of this application includes: Step S10: performing a sampling operation on the binary capacitor array based on the lower plates of the plurality of sampling capacitors.

[0026] In this embodiment, refer to Figure 2 After the input terminals (i.e., the positive input terminal and the negative input terminal) of the comparator are connected to the op amp common-mode input voltage Vcm0, the input signal Vi is connected from the lower plates of the multiple sampling capacitors to sample the multiple sampling capacitors according to the responses of the upper plates of the multiple sampling capacitors to the op amp common-mode input voltage.

[0027] It should be noted that, refer to Figure 2 As shown, in the sampling phase, the lower plate of the first capacitor CiRN (ie, the redundant capacitor CiRN) is reset to GND, the lower plate of the second capacitor CiRP (ie, the redundant capacitor CiRP) is reset to VREF, and the first capacitor CiRN and the second capacitor CiRP are in the same redundant position.

[0028] In a specific embodiment, refer to Figure 3 , Figure 3This is a schematic diagram of an embodiment of the redundant calibration method of the present application applied to a 4-bit single-ended SAR ADC circuit. The binary capacitor array is a 4-bit binary structure, and the arrangement order of multiple sampling capacitors from high to low is C4, C3, C2, C1 and C0; the corresponding capacitance values ​​are 8C, 4C, 2C, 1C, 1C. The redundant capacitor C3R is split into two capacitors, namely C3RN and C3RP, which are added after C3, C3RN=C3RP=C3 / 2, and the capacitance values ​​of C3RN and C3RP are both 2C. In the sampling stage, after the Vcm0 voltage is connected to the input end of the comparator, that is, the upper plates of the multiple sampling capacitors and the upper plates of the redundant capacitors in the binary capacitor array are connected to the Vcm0 voltage through the switch, according to the response of the upper plates of the multiple sampling capacitors to the common-mode input voltage of the operational amplifier, the input signal Vi is connected from the lower plates of the sampling capacitors (C4, C3, C2, C1 and C0) to sample the multiple sampling capacitors. At this time, the lower plate of the redundant position capacitor C3RN is reset to GND, and the lower plate of the redundant position capacitor C3RP is reset to VREF, that is, the redundant capacitors do not participate in sampling.

[0029] In this embodiment, the sampling operation of the binary capacitor array is performed based on the lower plates of multiple sampling capacitors, which effectively avoids the phenomenon that the traditional redundant calibration method needs to add a circuit module for reducing the gain of the input signal Vi due to the participation of redundant capacitors in sampling, thereby causing complex circuit design. In other words, the input signal Vi of the traditional redundant calibration method can only be applied to the ADC (Analog-to-Digital Converter) after passing through the circuit module for reducing the gain of the input signal Vi, while the input signal Vi of the present application can directly act on the ADC, thereby effectively reducing the circuit complexity.

[0030] Step S20: after completing the sampling operation, performing digital-to-analog conversion on the binary capacitor array in a preset high-to-low order to obtain redundant bit comparison results of the redundant capacitors and non-redundant bit comparison results of each sampling capacitor.

[0031] In this embodiment, after the sampling operation is completed, the switch connected to the comparator input terminal is disconnected, that is, the switch connected to the Vcm0 voltage is disconnected, and the lower plates of the plurality of sampling capacitors Ci are switched from Vi to GND, and the lower plates of the redundant capacitors are still maintained at the initial value Vcm. Figure 3(a), the lower plate of the sampling capacitors (C4, C3, C2, C1 and C0) is switched from Vi to GND, while the lower plate of the redundant capacitor C3R still maintains the initial value Vcm during the sampling phase. At this time, the multiple sampling capacitors and redundant capacitors in the binary capacitor array are converted into digital analogs according to the preset high-to-low order, and the redundant bit comparison results of the redundant capacitors and the non-redundant bit comparison results of each sampling capacitor are obtained.

[0032] It should be noted that when there are multiple redundant capacitors, there are also multiple redundant bit comparison results, and each redundant capacitor corresponds to a redundant bit comparison result.

[0033] In yet another embodiment, referring to Figure 3 (b), the redundant capacitor C3R is split into the redundant position capacitor C3RN and the redundant position capacitor C3RP. After the sampling operation is completed, the switch connected to the Vcm0 voltage is disconnected. At this time, the lower plate of the sampling capacitor (C4, C3, C2, C1 and C0) is switched from Vi to GND, while the lower plate of the redundant position capacitor C3RN is connected to GND, and the lower plate of the redundant position capacitor C3RP is connected to VREF.

[0034] Step S30: superimposing the redundant bit comparison result on a plurality of the non-redundant bit comparison results to calibrate the output binary code of the comparator.

[0035] In this embodiment, after the SAR logic module receives the redundant bit comparison result and multiple non-redundant bit comparison results sent by the comparator, the redundant bit comparison result and the multiple non-redundant bit comparison results are summed up, and the calculated output binary code of the comparator is calibrated.

[0036] In summary, the redundant calibration method of the present application is applied to a single-ended SAR ADC circuit, and the single-ended SAR ADC circuit includes: a binary capacitor array, the redundant capacitors in the binary capacitor array are added after the target capacitor, wherein the number of target capacitors is at least one, and the target capacitor refers to any sampling capacitor in the binary capacitor array; the redundant capacitors include a first capacitor and a second capacitor, wherein the capacitance data of the first capacitor and the capacitance data of the second capacitor are equal, and the capacitance data of the first capacitor is half of the capacitance data of the target capacitor. In the present application, firstly, a sampling operation is performed on the binary capacitor array based on the lower plates of multiple sampling capacitors, and after completing the sampling operation, the binary capacitor array is converted according to a preset high-to-low order to obtain a redundant bit comparison result of the redundant capacitor and a non-redundant bit comparison result of each sampling capacitor; then the redundant bit comparison result is superimposed on multiple non-redundant bit comparison results to calibrate the output binary code of the comparator.

[0037] Different from the traditional redundant calibration method, the present application performs sampling operation on the binary capacitor array based on the lower plates of multiple sampling capacitors, that is, the redundant capacitors in the present application do not participate in the sampling, and thus there is no need to additionally design a circuit module for reducing the input signal gain, thereby reducing the complexity of the single-ended SAR ADC circuit. In addition, after completing the sampling operation, the binary capacitor array is converted according to a preset high-to-low order, so that the redundant bit comparison results of the redundant capacitors and the non-redundant bit comparison results of each sampling capacitor can be obtained more simply and quickly, and then the redundant bit comparison results are superimposed on multiple non-redundant bit comparison results, so that the output binary code of the comparator can be accurately obtained, and then the output binary code is calibrated to improve the accuracy of redundant calibration of the single-ended structure SAR ADC.

[0038] Furthermore, based on the first embodiment of the redundant calibration method of the present application, a second embodiment of the redundant calibration method of the present application is proposed.

[0039] Furthermore, in some feasible embodiments, the above step S20: performing digital-to-analog conversion on the binary capacitor array according to a preset high-order to low-order sequence, may also include the following implementation steps: Step S201: sorting the binary capacitor array in a preset high-order to low-order order to obtain a sorted binary capacitor array; In this embodiment, the binary capacitor array is first sorted in a preset high-to-low order to obtain a sorted binary capacitor array. After the sorted binary capacitor array is determined, the sorted binary capacitor array can also be stored in a storage list in a memory in the terminal device.

[0040] Step S202: determining the highest-order capacitor corresponding to the sorted binary capacitor array, and performing a "guess 1" operation on the highest-order capacitor, wherein the highest-order capacitor refers to the capacitor with the largest capacitance data among the plurality of sampling capacitors; In this embodiment, a sampling capacitor with the largest capacitance data is found from the sorted binary capacitor array, and the sampling capacitor with the largest capacitance data is used as the highest-order capacitor, and then a "guess 1" operation is performed on the highest-order capacitor, wherein the highest-order capacitor refers to the capacitor with the largest capacitance data among the multiple sampling capacitors.

[0041] It should be noted that the "guess 1" operation can be understood as switching the voltage value of the lower plate of the highest capacitor from GND to VREF. It can also be understood as switching the voltage value of the lower plate of the highest capacitor from Vi to VREF; switching the lower plates of other sampling capacitors except the highest capacitor from Vi to GND, and the lower plate of the redundant capacitor CiR still maintains the initial value Vcm.

[0042] In a specific embodiment, refer to Figure 3 As shown, C4 is the highest-order capacitor, that is, the highest-order capacitor C4 of the binary capacitor array is "guessed 1", in other words, the lower plate of the highest-order capacitor C4 is switched from GND to VREF. The lower plate of the highest-order capacitor C4 of the binary capacitor array can also be switched from Vi to VREF; the lower plates of other sampling capacitors (C3, C2, C1 and C0) except the highest-order capacitor C4 are switched from Vi to GND; the lower plate of the redundant capacitor C3R still maintains the initial value during the sampling stage, that is, the lower plate of the redundant capacitor C3RN is connected to GND, and the lower plate of the redundant capacitor C3RP is connected to VREF.

[0043] Step S203: If the comparison result of the non-redundant bit pointed to by the highest-order capacitor is 1, maintaining the operation of connecting the lower plate of the highest-order capacitor to the reference voltage terminal; In this embodiment, if the comparison result of the non-redundant bit pointed to by the highest capacitor is 1, the lower plate of the highest capacitor is connected to the reference voltage terminal, that is, the lower plate of the highest capacitor maintains VREF unchanged.

[0044] Step S204: if the comparison result of the non-redundant bit pointed to by the highest-order capacitor is 0, connecting the lower plate of the highest-order capacitor from the reference voltage terminal to the ground terminal; In this embodiment, if the comparison result of the non-redundant bit pointed to by the highest capacitor is 0, the lower plate of the highest capacitor is connected from the reference voltage terminal to the ground terminal, that is, the voltage value connected to the lower plate of the highest capacitor is switched from VREF to GND.

[0045] Step S205: taking the sampling capacitor adjacent to the highest-order capacitor as the next highest-order capacitor, and returning to the step of performing the “guess 1” operation on the highest-order capacitor.

[0046] In this embodiment, after the voltage value connected to the lower plate of the highest capacitor is switched from VREF to GND, the sampling capacitor adjacent to the capacitance of the highest capacitor is used as the next highest capacitor, and the step of performing the "guess 1" operation on the highest capacitor is returned.

[0047] It should be noted that the sampling capacitor adjacent to the highest capacitor may be referred to as an adjacent capacitor, and the capacitance of the adjacent capacitor is less than or equal to the capacitance of the highest capacitor.

[0048] Further, in some other feasible embodiments, after the above step S202: determining the highest-order capacitor corresponding to the sorted binary capacitor array and performing a "guess 1" operation on the highest-order capacitor, the redundant calibration method includes: Step A10: Detect whether the highest-order capacitor is the target capacitor; Step A20: if not, return to the step of using the sampling capacitor adjacent to the highest capacitor as the next highest capacitor; In this embodiment, if the highest-order capacitor is not the target capacitor, the process returns to the step of using a sampling capacitor with a capacitance value adjacent to the highest-order capacitor as the next highest-order capacitor.

[0049] Step A30: If yes, perform a “guess 1” operation on the first capacitor; In this embodiment, if the highest-order capacitor is the target capacitor, a “guess 1” operation is performed on the first capacitor, that is, the lower plate of the first capacitor CiRN is switched from GND to VREF.

[0050] Step A40: When the redundant bit comparison result of the redundant capacitor is 1, maintaining the connection between the lower plate of the first capacitor and the lower plate of the second capacitor at the reference voltage end; In this embodiment, when the redundant bit comparison result of the redundant capacitor is 1, the lower plate of the first capacitor CiRN and the lower plate of the second capacitor are connected to the reference voltage terminal. Figure 4 When the comparator receives the analog value V3R generated after D / A conversion, it compares it with the analog value Vi to be converted sent to the comparator. If V3R≤Vi, the redundant bit comparison result b3R of the comparator output C3R is 1. At this time, the lower plates of C3RN and C3RP are connected to VREF unchanged.

[0051] Step A50: When the redundant bit comparison result of the redundant capacitor is 0, the lower plate of the first capacitor and the lower plate of the second capacitor are connected from the reference voltage terminal to the ground terminal respectively, and the step of using the sampling capacitor adjacent to the highest-bit capacitor as the next highest-bit capacitor is returned to be executed.

[0052] In this embodiment, when the redundant bit comparison result of the redundant capacitor is 0, the lower plate of the first capacitor and the lower plate of the second capacitor CiRP are connected from the reference voltage terminal to the ground terminal, that is, the access voltage of the lower plate of the first capacitor and the lower plate of the second capacitor CiRP is switched from VREF to GND, and the step of using the sampling capacitor adjacent to the highest-order capacitor capacitance as the next highest-order capacitor is returned to be executed.

[0053] In a specific embodiment, when the comparator receives the analog quantity V3R generated after D / A conversion, it compares it with the analog quantity Vi to be converted sent to the comparator. If V3R>Vi, the redundant bit comparison result b3R of the comparator output C3R is 0, and the lower plates of C3RN and C3RP are switched from VREF to GND. After determining that the access voltage of the lower plate of the first capacitor and the lower plate of the second capacitor CiRP is switched from VREF to GND, return to the step of using the sampling capacitor adjacent to the highest capacitor as the next highest capacitor.

[0054] Further, in another embodiment, referring to Figure 3 and Figure 4 , Figure 3 The order of the multiple sampling capacitors from high to low is C4, C3, C2, C1 and C0; the corresponding capacitance values ​​are 8C, 4C, 2C, 1C, 1C, and the redundant capacitor C3R is added after C3. Figure 4 The flowchart in Figure 3 The multiple sampling capacitors and redundant capacitors in the system are used for digital-to-analog conversion. The relevant operations are as follows: First, the "guess 1" operation is performed on the highest-order capacitor C4 of the binary capacitor array, that is, the lower plate of the highest-order capacitor C4 is switched from GND to VREF. When the comparator receives the analog value V4 generated after D / A conversion, it is compared with the analog value Vi to be converted sent to the comparator. If V4≤Vi, the non-redundant bit comparison result b4 of the comparator output C4 is 1. At this time, the lower plate of the highest-order capacitor C4 remains connected to VREF; if V4>Vi, the non-redundant bit comparison result b4 of the comparator output C4 is 0, that is, the lower plate of the highest-order capacitor C4 is switched from VREF to GND.

[0055] Secondly, the "guess 1" operation is performed on C3, that is, the lower plate of the second highest capacitor C3 is switched from GND to VREF. When the comparator receives the analog value V3 generated after D / A conversion, it is compared with the analog value Vi to be converted sent to the comparator. If V3≤Vi, the comparator outputs the non-redundant bit comparison result b3 of C4 as 1, and the lower plate of C3 remains connected to VREF unchanged; if V3>Vi, the comparator outputs the non-redundant bit comparison result b3 of C3 as 0, that is, the lower plate of C3 is switched from VREF to GND.

[0056] Next, the redundant bit capacitor C3R is subjected to a "guess 1" operation, that is, the lower plate of the redundant bit capacitor C3R is switched from Vcm to VREF. When the comparator receives the analog quantity V3R generated after D / A conversion, it is compared with the analog quantity Vi to be converted sent to the comparator. If V3R≤Vi, the redundant bit comparison result b3R of the comparator output C3R is 1. At this time, the lower plate of C3R remains connected to VREF; if V3R>Vi, the redundant bit comparison result b3R of the comparator output C3R is 0, that is, the lower plate of C3R is switched from VREF to GND.

[0057] Then, a "guess 1" operation is performed on C2, that is, the lower electrode plate of C2 is switched from GND to VREF. When the comparator receives the analog value V2 generated after D / A conversion, it is compared with the analog value Vi to be converted sent to the comparator. If V2≤Vi, the comparator outputs the non-redundant bit comparison result b2 of C2 as 1, and the lower electrode plate of C2 remains connected to VREF unchanged; if V2>Vi, the comparator outputs the non-redundant bit comparison result b2 of C2 as 0, that is, the lower electrode plate of C2 is switched from VREF to GND.

[0058] Finally, a "guess 1" operation is performed on C1, that is, the lower electrode plate of C1 is switched from GND to VREF. When the comparator receives the analog value V1 generated after D / A conversion, it is compared with the analog value Vi to be converted sent to the comparator. If V1≤Vi, the comparator outputs the non-redundant bit comparison result b1 of C1 as 1, and the lower electrode plate of C1 remains connected to VREF unchanged; if V1>Vi, the comparator outputs the non-redundant bit comparison result b1 of C1 as 0, that is, the lower electrode plate of C1 is switched from VREF to GND.

[0059] Furthermore, in some other feasible embodiments, the above step S10: performing a sampling operation on the binary capacitor array based on the lower plates of the plurality of sampling capacitors may further include the following implementation steps: Step S101: after the input terminal of the comparator is connected to the common-mode input voltage of the operational amplifier, input signals are connected from the lower plates of the plurality of sampling capacitors to sample the plurality of sampling capacitors according to the responses of the upper plates of the plurality of sampling capacitors to the common-mode input voltage of the operational amplifier.

[0060] In this embodiment, refer to Figure 2 After the input terminals (i.e., the positive input terminal and the negative input terminal) of the comparator are connected to the op amp common-mode input voltage Vcm0, based on the responses of the upper plates of the multiple sampling capacitors to the op amp common-mode input voltage (i.e., the upper plates of the multiple sampling capacitors are connected to the Vcm0 voltage through the switches), at this time, the input signals are connected from the lower plates of the multiple sampling capacitors to sample the multiple sampling capacitors.

[0061] Further, in some feasible embodiments, the single-ended SAR ADC circuit further includes: a SAR logic module, the above step S30: superimposing the redundant bit comparison result on the plurality of non-redundant bit comparison results to calibrate the output binary code of the comparator, may also include the following implementation steps: Step S301: After the SAR logic module receives the redundant bit comparison result and the multiple non-redundant bit comparison results sent by the comparator, the redundant bit comparison result and the multiple non-redundant bit comparison results are summed up, and the calculated output binary code of the comparator is calibrated.

[0062] In this embodiment, the comparator sends the redundant bit comparison result of the redundant capacitor and the non-redundant bit comparison result corresponding to each sampling capacitor to the SAR logic module. At this time, the SAR logic module sums the received redundant bit comparison result and multiple non-redundant bit comparison results, and calibrates the calculated output binary code of the comparator.

[0063] Further, in some other feasible embodiments, in the above step S301: after the SAR logic module receives the redundant bit comparison result and the multiple non-redundant bit comparison results sent by the comparator, the redundant bit comparison result and the multiple non-redundant bit comparison results are summed up, the following implementation steps may also be included: Step S3011: After the SAR logic module receives the redundant bit comparison result and the multiple non-redundant bit comparison results sent by the comparator, the redundant bit comparison result and the multiple non-redundant bit comparison results are summed according to a preset summing algorithm, wherein the summing algorithm is: in, refers to the non-redundant bit comparison result of each of the sampling capacitors, The value is 1 or 0. refers to the non-redundant bit weight corresponding to each of the sampling capacitors, The value of is a power of 2; refers to the redundant bit comparison result of the redundant capacitor, The value is 1 or 0. is a constant value, and 0≤ a ≤1, refers to the redundant bit weight corresponding to the redundant capacitor, The value of is a power of 2, refers to the output binary code of the comparator.

[0064] In a specific embodiment, refer to Figure 3 and Figure 4,when When the value of is 0.5, a bidirectional and symmetrical calibration effect can be achieved. After the SAR logic module receives the redundant bit comparison result and the multiple non-redundant bit comparison results sent by the comparator, the entire digital-to-analog conversion process is completed. The decimal code represented by the output binary code of the comparator (i.e., the output code of the SAR logic) is as follows: Figure 3 As shown, specifically: Among them, b4, b3, b2, and b1 represent the non-redundant bit comparison results corresponding to each sampling capacitor involved in the operation, and b3R represents the redundant bit comparison result corresponding to the redundant capacitor.

[0065] Furthermore, in some feasible embodiments, the single-ended SAR ADC circuit further includes: a DEC logic module, and the above step S301: calibrating the calculated output binary code of the comparator, further includes the following implementation steps: Step S3012: after the DEC logic module receives the output binary code sent by the comparator, obtaining an error compensation value corresponding to the output binary code; In this embodiment, the SAR logic module transmits the output binary code of the comparator to the DEC logic module. At this time, after receiving the output binary code of the comparator, the DEC logic module obtains the error compensation value corresponding to the output binary code.

[0066] In a specific embodiment, the output code of the SAR logic is passed through a digital error correction (DEC) logic circuit to perform error compensation. The simplified formula is: That is, -2 in the above formula is used as the error compensation value.

[0067] Step S3013: calibrating the output binary code according to the error compensation value, and using the calibrated output binary code as the standard binary code of the comparator.

[0068] In this embodiment, the error compensation value is converted into a complement code, and according to the complement code and the above The simplified formula of is added to obtain the calibrated output binary code, and the calibrated output binary code is converted into the standard binary output code d4, d3, d2 and d1. The specific operation principle is shown in Figure 5 , Figure 5 It is a schematic diagram of a 4-bit DEC logic module involved in an embodiment of the redundant calibration method of the present application applied to a single-ended SAR ADC circuit.

[0069] Further, in yet another embodiment, referring to Figure 6 , Figure 6 This is a conversion process diagram of a 4-bit embodiment of a single-ended SAR ADC circuit without redundancy. The reference voltage VREF = 16, and VREF is not marked in the figure. Vi is the input analog signal amplitude, and the vertical axis represents the total input range of Vi. The number at the top of the bar chart in the figure represents VDAC, that is, the amplitude of the DAC in the conversion stage. And Vcmp = Vi – VDAC, Vcmp is the input voltage amplitude of the comparator, if Vcmp is less than 0, the comparator output result bi = 0; if Vcmp is greater than or equal to 0, the comparator output result bi = 1. The horizontal axis represents the conversion process from high to low, where bi is the output code of the comparator, and weight is the weight corresponding to each bit. Do is the decimal code converted from the output binary code of the comparator.

[0070] Figure 6 The capacitor array represented is a binary non-redundant structure, where (a) and (b) are the conversion process with and without misjudgment when Vi=3. From (b), it can be seen that misjudgment of 0 as 1 will result in a larger output code. (c) and (d) are the conversion process with and without misjudgment when Vi=4. From (d), it can be seen that misjudgment of 1 as 0 will result in a smaller output code. It can be seen from this that in a non-redundant structure, once a bit is misjudged, since the weight of the following bits is not greater than the misjudged bit, it cannot be corrected by the operation of the remaining bits, and the final output code is an incorrect output code.

[0071] The specific operation process is Figure 6 Take (a) and (b) as examples. For (a), when Vi = 3, Vi will be stored after being sampled by the capacitor array. In the conversion stage, C4 is first guessed to be 1. At this time, Vi-VREF / 2 is compared, that is, 3–8<0, so b4 = 0, and C4 is connected to GND; then C3 is guessed to be 1. At this time, Vi–VREF / 4 is compared, that is, 3–4<0, so b3 = 0, and C3 is connected to GND; then C2 is guessed to be 1. At this time, Vi–VREF / 8 is compared, that is, 3–2>0, so b2 = 1, and C3 is connected to VREF; finally, C1 is guessed to be 1. At this time, Vi–VREF* (3 / 16) is compared, that is, 3–3 = 0, so b1 = 1. Therefore, the final output code is 0011, which is 3. The input and output correspond to each other, and it can be seen that the output result is correct.

[0072] For (b), when Vi=3, Vi is sampled by the capacitor array and stored. In the conversion stage, C4 is first guessed as 1. At this time, Vi–VREF / 2 is compared, that is, 3–8<0, so b4 = 0, and C4 is connected to GND; then C3 is guessed as 1. At this time, Vi–VREF / 4 is compared, that is, 3–4 was originally less than 0, but this step was misjudged, and 3-4 was misjudged as greater than 0, so b3 = 1, and C3 is connected to VREF; then C2 is guessed as 1. At this time, Vi–VREF* (3 / 8) is compared, that is, 3–6<0, so b2 = 0, and C2 is connected to GND; finally, C1 is guessed as 1. At this time, Vi–VREF* (5 / 16) is compared, that is, 3–5<0, so b1 = 0. Therefore, the final output code is 0100, which is 4. The output is not equal to the input, and it can be seen that the output result is wrong.

[0073] Further, in yet another embodiment, referring to Figure 7 , Figure 7 It is a conversion process diagram of a 4-bit embodiment of a single-ended SAR ADC circuit of the present application. Figure 7 This is a conversion process diagram of a 4-bit embodiment of a redundant single-ended SAR ADC circuit of the present application, wherein the reference voltage VREF=16, and VREF is not labeled in the figure. Vi is the input analog signal amplitude, and the ordinate represents the total input range of Vi. The number at the top of the bar graph in the figure represents VDAC, that is, the amplitude of the DAC in the conversion phase. And Vcmp = Vi–VDAC, Vcmp is the input voltage amplitude of the comparator, if Vcmp is less than 0, the comparator output result bi = 0; if Vcmp is greater than or equal to 0, the comparator output result bi = 1. The horizontal axis represents the conversion process from high to low, wherein bi is the output code of the comparator, and weight is the weight corresponding to each bit. Do is the decimal code represented by the output binary code of the comparator (that is, the output code of the SAR logic).

[0074] Figure 5 The capacitor array structure of binary compensation is redundant. (a) and (b) are the conversion processes with and without misjudgment when Vi=3. From (b), it can be seen that 0 misjudged as 1 can be corrected in the end. (c) and (d) are the conversion processes with and without misjudgment when Vi=4. From (d), it can be seen that 1 misjudged as 0 can be corrected in the end. It can be seen that the structure of the present application adds redundant bits. Once a bit is misjudged, since the sum of the weights of the following bits is greater than the misjudged bit, and the split capacitors C3RN and C3RP of the redundant bits can be regarded as a whole C3R, since the split capacitor C3RN is initially connected to GND and C3RP is initially connected to VREF, the initial value of C3R can be regarded as starting from the middle level, which can realize both addition and subtraction operations. Therefore, it can be corrected by the operation of the remaining bits, and the correct output code is finally obtained.

[0075] Specific operation combination Figure 4 The operation flow chart is as follows: Figure 7 Take (a) and (b) as examples. For (a), when Vi = 3, Vi is sampled by the capacitor array and stored. In the conversion phase, C4 is first guessed to be 1. At this time, Vi–VREF / 2 is compared, that is, 3–8<0, so b4 = 0, and C4 is connected to GND; then C3 is guessed to be 1. At this time, Vi–VREF / 4 is compared, that is, 3–4<0, so b3 = 0, and C3 is connected to GND; then C3RN is guessed to be 1, and the voltage of C3RN is switched from GND to VREF. At this time, Vi–VREF / 8 is compared, that is, 3–2>0, so b3R = 1, and C3RN and C3RP are both connected to VREF unchanged; then C2 is guessed to be 1. At this time, Vi–VREF / 4 is compared, that is, 3–4<0, so b2 = 0, and C3 is connected to GND; finally, C1 is guessed to be 1. At this time, Vi–VREF*(3 / 16) is compared, that is, 3–3 = 0, so b1 = 1. Therefore, the final output code is 00101, which is 8*0+4*0+4*(1-0.5)+2*0+1*1=3. The input and output correspond to each other, and it can be seen that the output result is correct.

[0076] For (b), when Vi=3, Vi is sampled by the capacitor array and stored. In the conversion phase, C4 is first guessed as 1. At this time, Vi–VREF / 2 is compared, that is, 3–8<0, so b4 = 0, and C4 is connected to GND; then C3 guesses 1. At this time, Vi–VREF / 4 is compared, that is, 3–4 was originally less than 0, but this step was misjudged, and 3-4 was mistakenly judged to be greater than 0, so b3 = 1, and C3 is connected to VREF; then C3RN guesses 1, and the voltage of C3RN switches from GND to VREF. At this time, Vi–VREF* (3 / 8) is compared, that is, 3–6<0, so b3R= 0, and C3RN and C3RP are both changed from VREF to GND; then C2 guesses 1. At this time, Vi–VREF / 4 is compared, that is, 3–4<0, so b2 = 0, and C2 is connected to GND; finally, C1 guesses 1. At this time, Vi–VREF* (3 / 16) is compared, that is, 3–3 = 0, so b1 = 1. Therefore, the final output code is 01001, which is 8*0+4*1+4*(0-0.5)+2*0+1*1=3. The input and output correspond to each other, and it can be seen that the output result is correct.

[0077] In summary, a redundant calibration method provided by the present application is applied to a single-ended SAR ADC circuit. Compared with the traditional binary compensation redundant method, since the redundant capacitor of the present application does not participate in sampling, the input signal can be input at full swing and does not need to be reduced; in addition, the present application can not only realize the calibration processing of the output result of the single-ended SAR ADC circuit through the capacitor splitting technology, but also realize the calibration processing of the output result of the single-ended SAR ADC circuit by introducing an additional voltage Vcm. And when the capacitor splitting technology is adopted, it is not necessary to introduce an additional voltage Vcm, only VREF and GND are used, that is, the split capacitor is regarded as a whole, and the initial voltage value of the whole can be regarded as starting from the middle level, which can realize both addition and subtraction operations. Therefore, when a misjudgment occurs, as long as the misjudgment occurs before the redundant bit and is within the redundant error range, it can be corrected by the operation of the remaining bits behind, and the correct output code is finally obtained, so bidirectional symmetrical calibration can be realized, and there is no limitation in the application process.

[0078] Furthermore, based on the first embodiment or the second embodiment of the redundant calibration method of the present application, a third embodiment of the redundant calibration method of the present application is proposed.

[0079] The SAR ADC circuit based on lower plate sampling in the present application also includes: a differential SAR ADC circuit, wherein the differential SAR ADC circuit includes a first capacitor array and a second capacitor array that are symmetrical and equal, wherein the first capacitor array is connected to the positive input terminal of the comparator, and the second capacitor array is connected to the negative input terminal of the comparator; the first capacitor array includes a first redundant bit capacitor, and the first redundant bit capacitor is a mirror capacitor of the second redundant bit capacitor in the second capacitor array.

[0080] In this embodiment, refer to Figure 8 , Figure 8 The redundant calibration method of the present application is applied to the circuit structure diagram of the differential SAR ADC. The differential SAR ADC circuit includes a first capacitor array, a second capacitor array, a comparator, a SAR logic module and a DEC logic module, wherein the first capacitor array is connected to the positive input terminal of the comparator, the second capacitor array is connected to the negative input terminal of the comparator, and the output terminal of the comparator, the SAR logic module and the DEC logic module are connected in sequence.

[0081] It should be noted that the first capacitor array and the second capacitor array are respectively equal to the binary capacitor array in the single-ended SAR ADC circuit. Figure 8(b), the first capacitor array includes capacitor C0_P, capacitor C1_P, capacitor C2_P, capacitor C3R_P, capacitor C3_P, and capacitor C4_P, wherein capacitor C0_P, capacitor C1_P, capacitor C2_P, capacitor C3_P, and capacitor C4_P are first non-redundant capacitors in the first capacitor array, and these first non-redundant capacitors are equivalent to sampling capacitors in the binary capacitor array; capacitor C3R_P is the first redundant bit capacitor of the first capacitor array, and this first redundant bit capacitor is equivalent to the redundant capacitor in the binary capacitor array.

[0082] The second capacitor array includes capacitor C0_N, capacitor C1_N, capacitor C2_N, capacitor C3R_N, capacitor C3_N, and capacitor C4_N. Among them, capacitor C0_N, capacitor C1_N, capacitor C2_N, capacitor C3_N, and capacitor C4_N are second non-redundant capacitors, which are also equivalent to sampling capacitors in the binary capacitor array; capacitor C3R_N is a second redundant bit capacitor in the second capacitor array, which is equivalent to a redundant capacitor in the binary capacitor array.

[0083] In addition, it should be noted that, referring to Figure 8 (b), capacitor C0_N is a mirror capacitor of capacitor C0_P, capacitor C1_N is a mirror capacitor of capacitor C1_P, capacitor C2_N is a mirror capacitor of capacitor C2_P, capacitor C3R_N is a mirror capacitor of capacitor C3R_P, capacitor C3_N is a mirror capacitor of capacitor C3_P, and capacitor C4_N is a mirror capacitor of capacitor C4_P.

[0084] In another embodiment, referring to Figure 8 (b), in the sampling stage, when the upper plates of all first non-redundant capacitors and the upper plates of the first redundant capacitors in the first capacitor array are connected to the voltage Vcm0, the upper plates of all second non-redundant capacitors and the upper plates of the second redundant capacitors in the second capacitor array are also connected to the voltage Vcm0. At this time, the lower plates of all first non-redundant capacitors are connected to the voltage VIN terminal, the lower plates of all second non-redundant capacitors are connected to the voltage VIP terminal, and the lower plates of the first redundant capacitors and the second redundant capacitors are both connected to the voltage Vcm terminal.

[0085] It should be noted that the voltage Vcm outputted from the Vcm terminal is an average voltage value between the voltage VREFN and the voltage VREFP.

[0086] Furthermore, in some feasible embodiments, the redundant calibration method further includes the following implementation steps: Step E10: according to the voltage Vcm0 inputted by the positive input terminal of the first capacitor array, triggering the lower plate of the first non-redundant capacitor to access the voltage VIN to charge the first capacitor array, and determining that the charging input signal of the first capacitor array is the voltage VIN; In this embodiment, based on the response of the first capacitor array to the voltage Vcm0 input to the positive input terminal of the comparator, the switch between the first non-redundant capacitor and the voltage VIN terminal is automatically closed, so that the lower plate of the first non-redundant capacitor is connected to the voltage VIN to charge the first capacitor array, so as to determine that the charging input signal of the first capacitor array is the voltage VIN.

[0087] Step E20: according to the voltage Vcm0 inputted by the negative input terminal of the second capacitor array, triggering the lower plate of the second non-redundant capacitor to access the voltage VIP to charge the second capacitor array, and determining that the charging input signal of the second capacitor array is the voltage VIP; In this embodiment, based on the response of the second capacitor array to the voltage Vcm0 input to the negative input terminal of the comparator, the switch between the second non-redundant capacitor and the voltage VIP terminal is automatically closed, so that the lower plate of the second non-redundant capacitor is connected to the voltage VIP to charge the second capacitor array, so as to determine that the charging input signal of the second capacitor array is the voltage VIP.

[0088] Step E30: When the comparator is connected to the charging input signal of the first capacitor array and the charging input signal of the second capacitor array, the voltage VIN and the voltage VIP are compared to obtain a comparison output result of the differential SAR ADC circuit, and binary code calibration is performed on the differential SAR ADC circuit according to the comparison output result.

[0089] In this embodiment, refer to Figure 8 When the switch connecting the upper plates of the first capacitor array and the second capacitor array to the voltage Vcm0 end is in an open state, the sampling phase ends, and the switch between the lower plates of the first capacitor array and the second capacitor array and the voltage VCM end is automatically closed. At this time, the lower plates of the first capacitor array and the second capacitor array are both connected to the voltage VCM, which represents the beginning of the conversion phase. At this time, the charging input signal of the first capacitor array and the charging input signal of the second capacitor array are compared by a comparator to obtain the comparison output result of the differential SAR ADC circuit, and then the differential SAR ADC circuit is calibrated with binary code according to these comparison output results.

[0090] In a specific embodiment, the charging input signal connected to the lower plate of the first non-redundant capacitor and the charging input signal connected to the second non-redundant capacitor symmetrical to the first non-redundant capacitor in the second capacitor array are compared in sequence according to a preset high-to-low order to obtain a non-redundant comparison result, and the charging input signal connected to the lower plate of the first redundant capacitor and the charging input signal connected to the second redundant capacitor symmetrical to the first redundant capacitor in the second redundant capacitor are compared in sequence according to a preset high-to-low order to obtain a redundant comparison result, and the non-redundant comparison result and the redundant comparison result are summed according to a preset differential summation algorithm to obtain a comparison output result of the differential SARADC circuit.

[0091] It should be noted that the expression of the preset difference summation algorithm is: In another embodiment, after the comparator receives the charging input signal of the first capacitor array and the charging input signal of the second capacitor array, the comparator compares the size of the charging input signal of the first capacitor array and the charging input signal of the second capacitor array in a preset high-to-low order.

[0092] Specifically, refer to Fig. 9 , Fig. 9 This is an operation flow chart of an embodiment 5bit of the redundant calibration method of the present application applied to a differential SAR ADC circuit. Fig. 9 The flowchart in Figure 8 (b) is compared with the differential capacitor array Fig. 9 For example, the outputs of b4, b3, b3R, b2, b1, and b0 are 1, 1, 1, 0, 1, 1. The specific operations are as follows: When the sampling phase is over, the lower plates of the first capacitor and the second capacitor array are connected to VCM, which means the conversion phase begins. At this point, ideally, the voltage at the positive input of the comparator is: VCM0+[(C4_P+C3_P+C2_P+C1_P+C0_P) / (C4_P+C3_P+C3R_P+C2_P+C1_P+C0_P)] *(VCM-VIN); The voltage value of the negative terminal of the comparator is: VCM0+[(C4_N+C3_N+C2_N+C1_N+C0_N) / (C4_N+C3_N+C3R_N+C2_N+C1_N+C0_N)] *(VCM-VIP); By comparing the positive terminal voltage value of the comparator with the negative terminal voltage value (i.e., comparing the voltage values ​​of the upper plate of the first capacitor array and the upper plate of the second capacitor array), the output voltage value is (16 / 20)* (VIP-VIN). When VIP>VIN, that is, VI>0 (VI=VIP-VIN), the output digital code b4=1 of the first comparison. Then, according to the connection between the comparator and the SAR logic module, the digital code b4=1 is the highest bit of the output digital code, which is stored in the SAR logic module and waits for the full digital code to be obtained as the final output (i.e., the comparison output result). At this time, according to the response of the SAR logic module to the digital code b4=1, the switch connected to the lower plate of the capacitor C4_P is switched from the voltage Vcm terminal to the voltage VREFN terminal, so that the voltage at the positive input terminal of the comparator decreases, and the amplitude of the change is: [C4_P / (C4_P+C3_P+C3R_P+C2_P+C1_P+C0_P)]*(VREFN-VCM), that is, [(8 / 20)*(VREFN-VCM)].

[0093] The switch connected to the lower plate of capacitor C4_N is also switched from the voltage Vcm terminal to the voltage VREFP terminal, so that the voltage at the negative input terminal of the comparator increases, and the amplitude of the change is: [C4_N / (C4_N+C3_N+C3R_N+C2_N+C1_N+C0_N)]*(VREFP-VCM), that is, [(8 / 20)*(VREFP-VCM)].

[0094] After the above switch switching is completed, the voltage difference between the positive input and the negative input of the comparator is the voltage difference at the previous moment plus the change value at this moment, which is: (16 / 20)* (VIP-VIN)+ (8 / 20)* (VREFN-VREFP), that is (16 / 20)* (VI-VREF / 2) Among them, VI=VIP-VIN; VREF=VREFP-VREFN.

[0095] At this time, the voltage value of the positive input terminal of the comparator is compared with the voltage value of the negative input terminal for the second time, and the comparison result is (16 / 20)* (VI-VREF / 2); if the value is greater than 0, that is, VI>VREF / 2, the digital code b3=1 is output; then according to the connection between the comparator and the SAR logic module, the digital code b3=1 is stored in the SAR logic module. At this time, according to the response of the SAR logic module to the digital code b3=1, the switch connected to the lower plate of the capacitor C3_P is switched from the voltage Vcm terminal to the voltage VREFN terminal, so that the voltage of the positive input terminal of the comparator decreases, and the amplitude of the change is: [C3_P / (C4_P+C3_P+C3R_P+C2_P+C1_P+C0_P)]*(VREFN-VCM), that is, [(4 / 20)*(VREFN-VCM)].

[0096] The switch connected to the lower plate of capacitor C3_N is also switched from the voltage Vcm terminal to the voltage VREFP terminal, so that the voltage at the negative input terminal of the comparator increases, and the amplitude of the change is: [C3_N / (C4_N+C3_N+C3R_N+C2_N+C1_N+C0_N)]*(VREFP-VCM), that is, [(4 / 20)*(VREFP-VCM)].

[0097] After the switch switching of the lower plate connection of capacitor C3_P and the switch switching of the lower plate connection of capacitor C3_N are completed, the voltage difference between the positive input terminal and the negative input terminal of the comparator is the voltage difference at the previous moment plus the change value at this moment, which is (16 / 20)* (VI-VREF / 2)-(4 / 20)*VREF. At this time, the voltage value of the positive input terminal of the comparator is compared with the voltage value of the negative input terminal for the third time, and the comparison result is (16 / 20)* (VI-(3 / 4) *VREF); if the value is greater than 0, that is, VI>[(3 / 4) *VREF], the digital code b3R = 1 is output; then according to the connection between the comparator and the SAR logic module, the digital code b3R = 1 is stored in the SAR logic module. At this time, according to the response of the SAR logic module to the digital code b3R = 1, the switch connected to the lower plate of capacitor C3R _P is switched from the voltage Vcm terminal to the voltage VREFN terminal, so that the voltage of the positive input terminal of the comparator decreases, and the amplitude of the change is: [C3R_P / (C4_P+C3_P+C3R_P+C2_P+C1_P+C0_P)]*(VREFN-VCM), that is, [(4 / 20)*(VREFN-VCM)].

[0098] The switch connected to the lower plate of capacitor C3R_N is also switched from the voltage Vcm terminal to the voltage VREFP terminal, so that the voltage at the negative input terminal of the comparator increases, and the amplitude of the change is: [C3R_N / (C4_N+C3_N+C3R_N+C2_N+C1_N+C0_N)]*(VREFP-VCM), that is, [(4 / 20)*(VREFP-VCM)].

[0099] After completing the switching of the switch connected to the lower plate of capacitor C3R_P and the switching of the switch connected to the lower plate of capacitor C3R_N, the voltage difference between the positive input terminal and the negative input terminal of the comparator is the voltage difference at the previous moment plus the change value at this moment, and this value is (16 / 20)*(VI - (3 / 4)*VREF) - (4 / 20)*VREF. At this time, the voltage value of the positive input terminal and the voltage value of the negative input terminal of the comparator are compared for the fourth time, and the comparison result is (16 / 20)*(VI - VREF); if this value is less than 0, that is, VI < VREF, then the output digital code b2 = 0; then according to the connection between the comparator and the SAR logic module, the digital code b2 = 0 is stored in the SAR logic module. At this time, according to the response of the SAR logic module to the digital code b2 = 0, the switch connected to the lower plate of capacitor C2_P is switched from the Vcm terminal to the VREFP terminal, increasing the voltage at the positive input terminal of the comparator, and the amplitude of the change is: [C2_P / (C4_P + C3_P + C3R_P + C2_P + C1_P + C0_P)]*(VREFP - VCM), that is, [(2 / 20)*(VREFP - VCM)].

[0100] The switch connected to the lower plate of capacitor C2_N is also switched from the Vcm terminal to the VREFN terminal, decreasing the voltage at the negative input terminal of the comparator, and the amplitude of the change is: [C2_N / (C4_N + C3_N + C3R_N + C2_N + C1_N + C0_N)]*(VREFN - VCM)), that is, [(2 / 20)*(VREFN - VCM)].

[0101] After completing the switching of the switch connected to the lower plate of capacitor C2_P and the switching of the switch connected to the lower plate of capacitor C2_N, the voltage difference between the positive input terminal and the negative input terminal of the comparator is the voltage difference at the previous moment plus the change value at this moment, and this value is (16 / 20)*(VI - VREF) + (2 / 20)*VREF. At this time, the voltage value of the positive input terminal and the voltage value of the negative input terminal of the comparator are compared for the fifth time, and the comparison result is (16 / 20)*(VI - (7 / 8)*VREF); if this value is greater than 0, that is, VI > [(7 / 8)*VREF], then the output digital code b1 = 1; then according to the connection between the comparator and the SAR logic module, the digital code b1 = 1 is stored in the SAR logic module. At this time, according to the response of the SAR logic module to the digital code b1 = 1, the switch connected to the lower plate of capacitor C1_P is switched from the Vcm terminal to the VREFN terminal, decreasing the voltage at the positive input terminal of the comparator, and the amplitude of the change is: [C1_P / (C4_P+C3_P+C3R_P+C2_P+C1_P+C0_P)]*(VREFN-VCM), that is, [(1 / 20)*(VREFN-VCM)].

[0102] The switch connected to the lower plate of capacitor C1_N is also switched from the voltage Vcm terminal to the voltage VREFP terminal, so that the voltage at the negative input terminal of the comparator increases, and the amplitude of the change is: [C1_N / (C4_N+C3_N+C3R_N+C2_N+C1_N+C0_N)]*(VREFP-VCM), that is, [(1 / 20)*(VREFP-VCM)].

[0103] After completing the switch switching of the lower plate connection of capacitor C1_P and the switch switching of the lower plate connection of capacitor C1_N, the voltage difference between the positive input terminal and the negative input terminal of the comparator is the voltage difference at the previous moment plus the change value at this moment, which is (16 / 20)* (VI- (7 / 8) *VREF)- (1 / 20)*VREF. At this time, the voltage value of the positive input terminal of the comparator is compared with the voltage value of the negative input terminal for the sixth time, and the comparison result is (16 / 20)* (VI- (15 / 16) *VREF); if the value is greater than 0, that is, VI>[(15 / 16) *VREF], the digital code b0=1 is output, and then according to the connection between the comparator and the SAR logic module, the digital code b0=1 is stored in the SAR logic module. At this time, the SAR logic module substitutes the digital codes output by b4, b3, b3R, b2, b1 and b0 into the preset differential summation algorithm for summation calculation, and obtains the comparison output result of the differential SAR ADC circuit. That is, according to the operating steps in the above embodiment, it can be known that the voltage value of VI is between (15 / 16)*VREF and VREF. Then, according to the SAR logic module and the DEC logic module, the comparison output result is sent to the DEC logic module. After the DEC logic module receives the comparison output result, the target compensation value specified by the comparison output result is determined, and then the comparison output result is calibrated according to the target compensation value to obtain the calibrated comparison output result, which is expressed as follows: Among them, -4 in the above expression refers to the target compensation value specified by the comparison output result; the comparison output result after calibration is 31, and its corresponding VI=(31 / 32)*VREF, which is consistent with the result obtained in the operation steps.

[0104] In addition, this application also provides a redundant calibration device, please refer to Fig.10 , Fig.10 It is a schematic diagram of the structure of the redundant calibration device involved in the embodiment of the present application.

[0105] The redundant calibration device of this application includes: A sampling module H01, used for performing a sampling operation on the binary capacitor array based on the lower plates of the plurality of sampling capacitors; The conversion module H02 is used to perform digital-to-analog conversion on the binary capacitor array according to a preset high-to-low order after completing the sampling operation, so as to obtain a redundant bit comparison result of the redundant capacitor and a non-redundant bit comparison result of each sampling capacitor; The calibration module H03 is used to superimpose the redundant bit comparison result on the plurality of non-redundant bit comparison results to calibrate the output binary code of the comparator.

[0106] Each functional module of the redundant calibration device of the present application implements the steps of the redundant calibration method of the present application as described above during operation.

[0107] In addition, this application also provides a terminal device. Fig.11 , Fig.11 The terminal device of the embodiment of the present application is a schematic diagram of the structure of the terminal device involved in the embodiment of the present application. The terminal device of the embodiment of the present application can be a device for local redundant calibration.

[0108] like Fig.11 As shown, the terminal device of the embodiment of the present application may include: a processor 1001, such as a CPU, a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. Among them, the communication bus 1002 is used to realize the connection and communication between these components. The user interface 1003 may include a display screen (Display), an input unit such as a keyboard (Keyboard), and the optional user interface 1003 may also include a standard wired interface and a wireless interface. The network interface 1004 may optionally include a standard wired interface and a wireless interface (such as a Wi-Fi interface).

[0109] The memory 1005 is arranged on the terminal device body, and a program is stored on the memory 1005, and the program implements the corresponding operation when it is executed by the processor 1001. The memory 1005 is also used to store parameters for use by the terminal device. The memory 1005 can be a high-speed RAM memory, or a stable memory (non-volatile memory), such as a disk memory. The memory 1005 can also be a storage device independent of the aforementioned processor 1001.

[0110] Those skilled in the art will understand that Fig.11 The terminal device structure shown in the figure does not constitute a limitation on the terminal device, and may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0111] like Fig.11 As shown, the memory 1005 as a storage medium may include an operating system, a network communication module, a user interface module, and a redundant calibration program of a terminal device.

[0112] exist Fig.11 In the terminal device shown, the processor 1001 can be used to call the redundant calibration program of the terminal device stored in the memory 1005 and execute the steps of the above redundant calibration method.

[0113] In addition, the present application also provides a computer storage medium. Fig.10 , Fig.10 The structure diagram of the storage medium involved in the embodiment of the present application is shown in FIG. A redundant calibration program is stored on the computer storage medium, and when the redundant calibration program is executed by the processor, the steps of any of the redundant calibration methods described above are implemented.

[0114] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or system including the element.

[0115] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0116] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a computer storage medium (such as ROM / RAM, disk, optical disk) as described above, and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0117] The above are only preferred embodiments of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A redundant calibration method, characterized in that: The redundant calibration method is applied to a SAR ADC circuit for lower plate sampling, wherein the SAR ADC circuit for lower plate sampling comprises: a single-ended SAR ADC circuit, wherein the single-ended SAR ADC circuit comprises: a binary capacitor array and a comparator, wherein the binary capacitor array is connected to a negative input terminal of the comparator, and redundant capacitors in the binary capacitor array are added after a target capacitor, wherein the number of the target capacitors is at least one, and the target capacitor refers to any sampling capacitor in the binary capacitor array; The redundant capacitor includes a first capacitor and a second capacitor, wherein the accumulated data between the capacitance data of the first capacitor and the capacitance data of the second capacitor is equal to the capacitance data of the target capacitor; The redundant calibration method comprises: Performing a sampling operation on the binary capacitor array based on the lower plates of the plurality of sampling capacitors; After completing the sampling operation, performing digital-to-analog conversion on the binary capacitor array in a preset high-bit to low-bit order to obtain a redundant bit comparison result of the redundant capacitor and a non-redundant bit comparison result of each of the sampling capacitors; The redundant bit comparison result is superimposed on a plurality of the non-redundant bit comparison results to calibrate the output binary code of the comparator.

2. The redundant calibration method according to claim 1, characterized in that: The step of performing digital-to-analog conversion on the binary capacitor array according to a preset high-to-low order includes: Sorting the binary capacitor array according to a preset high-order to low-order sequence to obtain a sorted binary capacitor array; Determine the highest-order capacitor corresponding to the sorted binary capacitor array, and perform a "guess 1" operation on the highest-order capacitor, wherein the highest-order capacitor refers to the capacitor with the largest capacitance data among the plurality of sampling capacitors; If the comparison result of the non-redundant bit pointed to by the highest-order capacitor is 1, the lower plate of the highest-order capacitor is maintained to be connected to the reference voltage terminal; If the comparison result of the non-redundant bit pointed to by the highest-order capacitor is 0, connecting the lower plate of the highest-order capacitor from the reference voltage terminal to the ground terminal; The sampling capacitor adjacent to the highest-order capacitor is used as the next highest-order capacitor, and the step of performing the "guess 1" operation on the highest-order capacitor is returned to be executed.

3. The redundant calibration method according to claim 2, characterized in that: After the step of determining the highest-order capacitance corresponding to the sorted binary capacitance array and performing a "guess 1" operation on the highest-order capacitance, the method further includes: Detecting whether the highest-order capacitor is the target capacitor; If not, returning to the step of using the sampling capacitor adjacent to the highest-order capacitor as the next highest-order capacitor; If yes, then perform a "guess 1" operation on the first capacitor; When the redundant bit comparison result of the redundant capacitor is 1, maintaining the operation of connecting the lower plate of the first capacitor and the lower plate of the second capacitor at the reference voltage end; When the redundant bit comparison result of the redundant capacitor is 0, the lower plate of the first capacitor and the lower plate of the second capacitor are connected from the reference voltage terminal to the ground terminal respectively, and the step of using the sampling capacitor adjacent to the highest-bit capacitor as the next highest-bit capacitor is returned to be executed.

4. The redundant calibration method according to claim 1, characterized in that: The step of performing a sampling operation on the binary capacitor array based on the lower plates of the plurality of sampling capacitors comprises: After the op amp common mode input voltage is connected to the input end of the comparator, input signals are connected from the lower plates of the plurality of sampling capacitors to sample the plurality of sampling capacitors according to responses of the upper plates of the plurality of sampling capacitors to the op amp common mode input voltage.

5. The redundant calibration method according to claim 1, characterized in that: The single-ended SAR ADC circuit further includes: a SAR logic module, and the step of superimposing the redundant bit comparison result on the plurality of non-redundant bit comparison results to calibrate the output binary code of the comparator includes: After the SAR logic module receives the redundant bit comparison result and the multiple non-redundant bit comparison results sent by the comparator, the redundant bit comparison result and the multiple non-redundant bit comparison results are summed up, and the calculated output binary code of the comparator is calibrated.

6. The redundant calibration method according to claim 5, characterized in that: After the SAR logic module receives the redundant bit comparison result and the multiple non-redundant bit comparison results sent by the comparator, the step of summing the redundant bit comparison result and the multiple non-redundant bit comparison results comprises: After the SAR logic module receives the redundant bit comparison result and the multiple non-redundant bit comparison results sent by the comparator, the redundant bit comparison result and the multiple non-redundant bit comparison results are summed according to a preset summing algorithm, wherein the summing algorithm is: in, refers to the non-redundant bit comparison result of each of the sampling capacitors, The value is 1 or 0. refers to the non-redundant bit weight corresponding to each of the sampling capacitors, The value of is a power of 2; refers to the redundant bit comparison result of the redundant capacitor, The value is 1 or 0. is a constant value, and 0≤ a ≤1, refers to the redundant bit weight corresponding to the redundant capacitor, The value of is a power of 2, refers to the output binary code of the comparator.

7. The redundant calibration method according to claim 5, characterized in that: The single-ended SAR ADC circuit further includes: a DEC logic module, and the step of calibrating the calculated output binary code of the comparator includes: After the DEC logic module receives the output binary code of the comparator forwarded by the SAR logic module, acquiring an error compensation value corresponding to the output binary code; The output binary code is calibrated according to the error compensation value, and the calibrated output binary code is used as the standard binary code of the comparator.

8. The redundant calibration method according to claim 1, characterized in that: The SAR ADC circuit for lower plate sampling further includes: a differential SAR ADC circuit, wherein the differential SAR ADC circuit includes a first capacitor array and a second capacitor array that are symmetrical and equal, wherein the first capacitor array is connected to the positive input terminal of the comparator, and the second capacitor array is connected to the negative input terminal of the comparator; The first capacitor array includes a first non-redundant capacitor, and the first non-redundant capacitor is a mirror capacitor of a second non-redundant capacitor in the second capacitor array; The redundant calibration method further comprises: According to the voltage Vcm0 inputted by the positive input terminal of the first capacitor array, the lower plate of the first non-redundant capacitor is triggered to access the voltage VIN to charge the first capacitor array, and the charging input signal of the first capacitor array is determined to be the voltage VIN; According to the voltage Vcm0 inputted by the negative input terminal of the second capacitor array, the lower plate of the second non-redundant capacitor is triggered to access the voltage VIP to charge the second capacitor array, and the charging input signal of the second capacitor array is determined to be the voltage VIP; When the comparator is connected to the charging input signal of the first capacitor array and the charging input signal of the second capacitor array, the voltage VIN is compared with the voltage VIP to obtain a comparison output result of the differential SAR ADC circuit, and binary code calibration is performed on the differential SAR ADC circuit according to the comparison output result.

9. A redundant calibration device, characterized in that: The redundant calibration device comprises: A sampling module, used for performing a sampling operation on a binary capacitor array based on the lower plates of a plurality of sampling capacitors; A conversion module, configured to perform digital-to-analog conversion on the binary capacitor array in a preset high-to-low order after completing the sampling operation, to obtain a redundant bit comparison result of the redundant capacitor and a non-redundant bit comparison result of each of the sampling capacitors; The calibration module is used to superimpose the redundant bit comparison result on the plurality of non-redundant bit comparison results to calibrate the output binary code of the comparator.

10. A terminal device, characterized in that: The terminal device includes a memory, a processor, and a redundant calibration program stored in the memory and executable on the processor. When the processor executes the redundant calibration program, the steps of the redundant calibration method according to any one of claims 1 to 8 are implemented.

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