Semiconductor structure and method of manufacturing the same, storage system

Abstract

This application provides a semiconductor structure, a method for manufacturing the same, and a memory system. The method for manufacturing the semiconductor structure includes: forming a first sacrificial structure penetrating a stacked structure and a gate line slot penetrating the stacked structure and extending along a first direction, wherein the first direction is perpendicular to the stacking direction of the stacked structure; removing the first sacrificial structure to form a memory via; and forming a gate line slot structure and a memory structure in the gate line slot and the memory via, respectively.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to semiconductor structures, methods for manufacturing semiconductor structures, and memory systems. Background Technology

[0002] With the rise and development of artificial intelligence, big data, the Internet of Things, mobile communications, mobile devices, and cloud storage, the requirements for storage density in semiconductor structures such as three-dimensional semiconductor memory devices are becoming increasingly stringent. However, as the number of stacked layers in semiconductor structures increases and the storage density per unit area improves, the fabrication process of three-dimensional semiconductor structures becomes complex and lengthy. Therefore, simplifying the fabrication process of semiconductor structures while ensuring their reliability and overall performance is one of the urgent problems to be solved. Summary of the Invention

[0003] The embodiments proposed in this application can solve or partially solve the deficiencies mentioned in the background section above or other deficiencies in the prior art.

[0004] This application provides a method for manufacturing a semiconductor structure. The method includes: forming a first sacrificial structure penetrating a stacked structure and a gate wire slot penetrating the stacked structure and extending along a first direction, wherein the first direction is perpendicular to the stacking direction of the stacked structure; removing the first sacrificial structure to form a memory via; and forming a gate wire slot structure and a memory structure in the gate wire slot and the memory via, respectively.

[0005] In one embodiment, forming a first sacrificial structure that penetrates the stacked structure and a gate wire slot that penetrates the stacked structure and extends along a first direction includes: forming a plurality of first sacrificial structures and second sacrificial structures that penetrate the stacked structure, wherein the first sacrificial structures and second sacrificial structures are distributed adjacently along a second direction, the plurality of second sacrificial structures are arranged along a first direction, and the first direction, the second direction and the stacking direction are perpendicular to each other; removing the plurality of second sacrificial structures to form gate wire holes; and etching back the gate wire holes to penetrate adjacent gate wire holes along the first direction to form gate wire slots extending along the first direction.

[0006] In one embodiment, forming a plurality of first sacrificial structures and second sacrificial structures through a laminated structure includes: forming a plurality of first sacrificial holes and second sacrificial holes through a laminated structure; and filling the first sacrificial holes and second sacrificial holes with sacrificial material to form the first sacrificial structures and second sacrificial structures.

[0007] In one embodiment, the method includes: alternately stacking a first dielectric layer and a first conductive layer to form a stacked structure.

[0008] In one embodiment, a gate line slot structure and a storage structure are formed in the gate line slot and the storage via, respectively, including: forming a capacitor dielectric layer and an inner electrode layer sequentially from the outside to the inside in the gate line slot and the storage via, so as to form the gate line slot structure and the storage structure, respectively, wherein the capacitor dielectric layer and the inner electrode layer in the gate line slot structure extend along a first direction.

[0009] In one embodiment, a gate line slot structure and a storage structure are formed in the gate line slot and the storage hole, respectively, including: forming a first outer electrode layer, a capacitor dielectric layer and an inner electrode layer sequentially from the outside to the inside in the gate line slot and the storage hole, so as to form the gate line slot structure and the storage structure, respectively, wherein the first outer electrode layer, the capacitor dielectric layer and the inner electrode layer in the gate line slot structure extend along a first direction.

[0010] In one embodiment, the method further includes: sequentially stacking a second dielectric layer and a second conductive layer on the surface of the stacked structure to form a top select gate structure; and forming a transistor that extends through the top select gate structure and into the memory structure along the stacking direction.

[0011] In one embodiment, forming a transistor that extends along a stacking direction through a top select gate structure and into a memory structure includes: forming an opening that extends along a stacking direction through a top select gate structure and into a memory structure; and forming a dielectric layer and a channel layer sequentially from the outside to the inside within the opening, wherein the dielectric layer is in direct contact with a second conductive layer.

[0012] In one embodiment, forming a transistor that extends through a top select gate structure and into a memory structure along a stacking direction includes: forming an opening that extends through the top select gate structure and into the memory structure along a stacking direction; and forming a second outer electrode layer, a dielectric layer, and a channel layer sequentially from the outside to the inside within the opening.

[0013] In one embodiment, the method further includes: forming a plurality of bit lines extending along a first direction and connected to corresponding transistors; and forming a plurality of contact structures extending along a stacking direction to a second conductive layer.

[0014] This application also provides a semiconductor structure. The semiconductor structure includes: a memory structure extending through a stacked structure, wherein the stacked structure includes alternately stacked first dielectric layers and first conductive layers; and a gate line slot structure extending through the stacked structure along a first direction, wherein the first direction is perpendicular to the stacking direction of the stacked structure. The memory structure and the gate line slot structure sequentially include a capacitor dielectric layer and an inner electrode layer from the outside to the inside.

[0015] In one embodiment, the capacitor dielectric layer and the inner electrode layer within the gate line slot structure extend along a first direction, and the gate line slot structure divides the stacked structure into a plurality of memory blocks distributed along a second direction, wherein the first direction, the second direction, and the stacking direction are perpendicular to each other.

[0016] In one embodiment, the first conductive layer is in direct contact with the capacitor dielectric layer.

[0017] In one embodiment, the memory structure and gate line gap structure further include: a first external electrode layer located outside the capacitor dielectric layer.

[0018] In one embodiment, the semiconductor structure further includes: a top select gate structure located on the surface of the stacked structure, comprising a second dielectric layer and a second conductive layer stacked sequentially; a transistor extending through the top select gate structure and into the memory structure along the stacking direction; a plurality of bit lines extending along a first direction and connected to corresponding transistors; and a plurality of contact structures extending along the stacking direction into the second conductive layer.

[0019] In one embodiment, the materials of the first conductive layer and the inner electrode layer include at least one conductive material selected from polycrystalline silicon, titanium nitride, tungsten metal, platinum metal, and tantalum nitride.

[0020] In one embodiment, the material of the capacitor dielectric layer includes at least one of ferroelectric and antiferroelectric materials.

[0021] Another aspect of this application provides a storage system including at least one three-dimensional memory, each three-dimensional memory including a semiconductor structure as described above; and a controller coupled to the semiconductor structure for controlling the storage of data in the three-dimensional memory.

[0022] In one or more embodiments of this application, by forming a gate wire slot structure and a storage structure in the gate wire slot and the storage hole respectively, it is possible to form the gate wire slot structure and the storage structure simultaneously in one process step, which helps to reduce process steps and save costs. Attached Figure Description

[0023] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings. In the drawings:

[0024] Figure 1 This is a flowchart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of this application;

[0025] Figures 2 to 7 This is a diagram illustrating the process steps for forming the first sacrificial structure and the gate wire gap according to an exemplary embodiment of this application;

[0026] Figure 8 This is a process step diagram of forming a storage hole according to an exemplary embodiment of this application;

[0027] Figure 9 and Figure 10This is a diagram illustrating the process steps for forming the gate gap structure and the memory structure according to an exemplary embodiment of this application;

[0028] Figure 11 This is a side view schematic diagram of a gate wire slot structure and a memory structure formed in a gate wire slot and a memory hole, respectively, according to an exemplary embodiment of this application.

[0029] Figure 12 This is a side view of a gate wire slot structure and a memory structure formed in a gate wire slot and a memory hole, respectively, according to another exemplary embodiment of this application.

[0030] Figure 13 This is a process step diagram illustrating the formation of a top-select gate structure, transistor, bit line, and contact structure according to an exemplary embodiment of this application.

[0031] Figure 14 This is a side view schematic diagram of a transistor according to an exemplary embodiment of this application;

[0032] Figure 15 This is a side view schematic diagram of a transistor according to another exemplary embodiment of this application;

[0033] Figure 16 This is an exemplary block diagram of a system having a storage system according to an exemplary embodiment of this application; and

[0034] Figure 17A and Figure 17B This is a schematic diagram of a storage system according to an exemplary embodiment of this application. Detailed Implementation

[0035] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely descriptions of exemplary embodiments of this application and are not intended to limit the scope of this application in any way.

[0036] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first sacrificial structure discussed herein may also be referred to as the second sacrificial structure, and the first direction may also be referred to as the second direction, and vice versa.

[0037] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0038] Furthermore, in this text, when describing a part as being "on" another part, such as "on," "above," and "above," the meaning should be interpreted in the broadest possible sense, such that "on" not only means "directly on" something, but also includes the meaning of "on" something with intermediate features or layers in between. Moreover, "above" or "above" does not absolutely mean being above something with respect to the direction of gravity, nor does it only mean "on" something or "above" something, but can also include the meaning of "on" something or "above" something without intermediate features or layers in between (i.e., directly on) something.

[0039] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0040] This document describes the embodiments with reference to schematic diagrams of exemplary implementations. The exemplary implementations disclosed herein should not be construed as limited to the specific shapes and sizes shown, but rather include various equivalent structures capable of achieving the same function, as well as shape and size variations arising, for example, during manufacturing. The positions shown in the accompanying drawings are schematic in nature and not intended to limit the positions of the components.

[0041] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms such as those defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formalized sense unless expressly defined herein.

[0042] As used herein, the term "layer" refers to a portion of material comprising a region having height. A layer can be a region of a homogeneous or non-homogeneous continuous structure, the height of which is less than the height of the continuous structure. For example, a layer can be located at or between any set of horizontal planes on or between the top and bottom surfaces of a continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer can include multiple layers.

[0043] Furthermore, in this application, the use of "connection" or "linkage" may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or deduced from the context.

[0044] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0045] Figure 1 This is a flowchart of a method 1000 for manufacturing a semiconductor structure according to an exemplary embodiment of this application.

[0046] like Figure 1 As shown, the method 1000 for manufacturing a semiconductor structure may include: S1100, forming a first sacrificial structure penetrating the stacked structure and a gate wire slot penetrating the stacked structure and extending along a first direction, wherein the first direction is perpendicular to the stacking direction of the stacked structure; S1200, removing the first sacrificial structure to form a memory via; and S1300, forming a gate wire slot structure and a memory structure in the gate wire slot and the memory via, respectively. Steps S1100 to S1300 will be described in detail below.

[0047] In the exemplary embodiments of this application, such as Figure 7 As shown, a first sacrificial structure 1210 that penetrates the stacked structure 1100 and a gate line slot 1310 that penetrates the stacked structure 1100 and extends along a first direction Y can be formed, wherein the first direction Y is perpendicular to the stacking direction Z of the stacked structure 1100.

[0048] For example, Figures 2 to 7 This application illustrates a process for forming a first sacrificial structure 1210 and a gate line gap 1310.

[0049] The formation of a first sacrificial structure 1210 penetrating the stacked structure 1100 and a gate wire gap 1310 penetrating the stacked structure 1100 and extending along the first direction Y may include: forming a plurality of first sacrificial structures 1210 and second sacrificial structures 1410 penetrating the stacked structure 1100, wherein the first sacrificial structures 1210 and second sacrificial structures 1410 are distributed adjacently along the second direction X, and the plurality of second sacrificial structures 1410 are arranged along the first direction Y, wherein the first direction Y, the second direction X, and the stacking direction Z are perpendicular to each other. Figure 4 ); Remove multiple second sacrificial structures 1410 to form gate wire apertures 1420. Figure 6 ); and the etched gate wire hole 1420 extends to the adjacent gate wire hole 1420 along the first direction Y, forming a gate wire slot 1310 extending along the first direction Y. Figure 7 ).

[0050] Specifically, such as Figure 2 As shown, a stacked structure 1100 can be formed by alternately stacking the first dielectric layer 1110 and the first conductive layer 1120. Exemplarily, the stacked structure 1100 can be formed by sequentially stacking the first dielectric layer 1110 and the first conductive layer 1120 through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0051] It should be understood that the number and thickness of the first dielectric layer 1110 and the first conductive layer 1120 are not limited to... Figure 2 The quantities and thicknesses shown herein, without departing from the concept of this application, allow those skilled in the art to provide any number and thickness of the first dielectric layer 1110 and the first conductive layer 1120 as needed.

[0052] Furthermore, the materials of the first dielectric layer 1110 and the first conductive layer 1120 can be selected from suitable materials known in the art. For example, the material of the first dielectric layer 1110 may include an insulating material, and the material of the first conductive layer 1120 may include a conductive material. For instance, the material of the first dielectric layer 1110 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The material of the first conductive layer 1120 may include at least one of conductive materials such as poly-Si (p-Si, polycrystalline silicon), TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), and Ag (silver).

[0053] Exemplarily, a multilayer structure 1100 may be formed on the substrate 100. In one exemplary embodiment of this application, the material of the substrate 100 may include at least one of single-crystal silicon, polycrystalline silicon, single-crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art. The substrate 100 may be a single-layer structure such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate, or it may be a multilayer structure such as including a polycrystalline silicon layer, an oxide layer, and a metal silicon layer. Exemplarily, multiple layers prepared from different materials may be sequentially formed to form the substrate 100 by a thin-film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. In another exemplary embodiment of this application, the material of the substrate 100 may include at least one of glass, plastic, sapphire wafer, or other non-conductive materials known in the art.

[0054] In the exemplary embodiments of this application, such as Figure 3 As shown, a plurality of first sacrificial holes 1220 and second sacrificial holes 1430 can be formed through the laminated structure 1100. Exemplarily, the first sacrificial holes 1220 and second sacrificial holes 1430 can be distributed adjacently along the second direction X, and the plurality of second sacrificial holes 1430 can be arranged along the first direction Y.

[0055] Exemplarily, the plurality of first sacrificial vias 1220 and second sacrificial vias 1430 can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, can also be performed. The plurality of first sacrificial vias 1220 and second sacrificial vias 1430 may have a cylindrical or columnar shape extending along the stacking direction Z in the stacked structure 1100.

[0056] In this application, the first sacrificial hole 1220 and the second sacrificial hole 1430 may have approximately the same shape, and the plurality of first sacrificial holes 1220 and second sacrificial holes 1430 may be evenly distributed in the laminated structure 1100, that is, the plurality of first sacrificial holes 1220 are discontinuous, and the plurality of second sacrificial holes 1430 are also discontinuous. This arrangement can reduce the phenomenon of stress concentration in the laminated structure 1100 after the formation of the first sacrificial holes 1220 and the second sacrificial holes 1430, thereby reducing the occurrence of tilting or collapse of the laminated structure 1100.

[0057] The difference between the first sacrificial via 1220 and the second sacrificial via 1430 is that the first sacrificial via 1220 can be used to determine the position of the subsequently formed memory via, while the second sacrificial via 1430 can be used to determine the position of the subsequently formed gate via 1420. In other words, the first sacrificial via 1220 can be the initial via for the subsequently formed memory via, and the second sacrificial via 1430 can be the initial via for the subsequently formed gate via 1420.

[0058] For example, such as Figure 4 As shown, sacrificial material can be filled into the first sacrificial via 1220 and the second sacrificial via 1430 to form the first sacrificial structure 1210 and the second sacrificial structure 1410. For example, the first sacrificial structure 1210 and the second sacrificial via 1430 can be formed by filling sacrificial material into the first sacrificial via 1220 and the second sacrificial via 1430 through a thin film deposition process. The sacrificial material can be any one or a combination of carbon (such as amorphous carbon, graphite, etc.), carbon-containing organic matter, polymers, photoresist, etc.

[0059] For example, the first sacrificial structure 1210 and the second sacrificial structure 1410 may serve to support the laminated structure 1100, reducing the risk of collapse or bending of the laminated structure 1100. Figures 4 to 8 As shown, the second sacrificial structure 1410 and the first sacrificial structure 1210 can be removed sequentially.

[0060] For example, such as Figure 6 As shown, multiple second sacrificial structures 1410 can be removed to form gate wire holes 1420. In other words, gate wire holes 1420 are formed after removing the sacrificial material (i.e., the second sacrificial structure 1410) within the second sacrificial holes 1430. Therefore, gate wire holes 1420 can be approximately understood as second sacrificial holes 1430. Since the multiple first sacrificial holes 1220 are discontinuous, the multiple gate wire holes 1420 are also discontinuous.

[0061] For example, such as Figure 5 As shown, removing multiple second sacrificial structures 1410 may include: forming a patterned mask 200 on the surface of the stacked structure 1100, and using the patterned mask 200 as a mask, removing multiple second sacrificial structures 1410 by one or more dry etching and / or wet etching processes to form gate vias 1420. Figure 6 The patterned mask 200 can cover the first sacrificial structure 1210 and expose the second sacrificial structure 1410, thereby reducing the risk of the first sacrificial structure 1210 being removed during the removal of the second sacrificial structure 1410.

[0062] For example, such as Figure 7 As shown, the gate hole 1420 can be etched back to the adjacent gate hole 1420 along the first direction Y, forming a gate slot 1310 extending along the first direction Y. Exemplarily, after forming the gate slot 1310, the patterned mask 200 can be removed.

[0063] In this application, to reduce stress concentration in the stacked structure 1100, multiple first sacrificial holes 1220 and second sacrificial holes 1430 with approximately the same shape and uniformly distributed in the stacked structure 1100 can be provided. Furthermore, to subsequently divide the stacked structure 1100 into multiple memory blocks, gate wire slot structures 1300 extending along the first direction Y can be provided. Figure 9 or Figure 10 This application allows the gate line slot 1310 to extend along the first direction Y by etching back the gate line hole 1420 (which can be approximately understood as the second sacrificial hole 1430) to the adjacent gate line hole 1420 along the first direction Y. This allows the gate line slot structure 1300 subsequently formed in the gate line slot 1310 to extend along the first direction Y, so as to achieve the purpose of dividing the stacked structure 1100 into multiple memory blocks by the gate line slot structure 1300.

[0064] In the exemplary embodiments of this application, such as Figure 8 As shown, the first sacrificial structure 1210 can be removed to form the storage via 1230. For example, the first sacrificial structure 1210 can be removed by one or more dry etching and / or wet etching processes.

[0065] In the exemplary embodiments of this application, such as Figure 9 and Figure 10 As shown, a gate line slot structure 1300 and a memory structure 1200 can be formed within the gate line slot 1310 and the memory via 1230, respectively. For example, the gate line slot structure 1300 and the memory structure 1200 can be formed within the gate line slot 1310 and the memory via 1230, respectively, using a thin-film deposition process. Figure 10 As shown, the formed gate line slot structure 1300 can extend along the first direction Y to achieve the purpose of dividing the stacked structure 1100 into multiple memory blocks.

[0066] In one exemplary embodiment of this application, such as Figure 11 As shown, the gate gap structure 1300 and the storage structure 1200 can be sequentially included from the outside to the inside as a capacitor dielectric layer 210, an inner electrode layer 220 and a filling dielectric layer 230.

[0067] Specifically, forming the gate line slot structure 1300 and the memory structure 1200 may include: sequentially forming a capacitor dielectric layer 210 and an inner electrode layer 220 from the outside to the inside within the gate line slot 1310 and the memory hole 1230, respectively forming the gate line slot structure 1300 and the memory structure 1200, wherein the capacitor dielectric layer 210 and the inner electrode layer 220 within the gate line slot structure 1300 extend along a first direction Y. Exemplarily, after forming the capacitor dielectric layer 210 and the inner electrode layer 220, a filling dielectric layer 230 may be used to fill the gate line slot 1310 and the memory hole 1230 to electrically insulate adjacent inner electrode layers 220 within the gate line slot 1310 and the memory hole 1230. The filling dielectric layer 230 may include an oxide dielectric layer, such as silicon oxide. Further, during the filling process, multiple insulating gaps may be formed in the filling dielectric layer 230 by controlling the filling process to reduce structural stress.

[0068] The inner electrode layer 220 may be made of a conductive material, such as one or more of the following: polycrystalline silicon, TiN (titanium nitride), TaN (tantalum nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver), Pt (platinum).

[0069] The capacitor dielectric layer 210 of the storage structure 1200 may have a storage function. Specifically, the portions of the capacitor dielectric layer 210 and the inner electrode layer 220 corresponding to each first conductive layer 1120 may form independent storage cells with the first conductive layer 1120. The portion of each first conductive layer 1120 surrounding the capacitor dielectric layer 210 constitutes the outer electrode of the storage cell.

[0070] The number of first conductive layers 1120 is multiple, with each first conductive layer 1120 forming a memory cell by surrounding a portion of the capacitor dielectric layer 210 and the portions of the capacitor dielectric layer 210 and the inner electrode layer 220 opposite to the first conductive layer 1120. Each memory cell can be controlled by the first conductive layer 1120. Charge is stored or released in the capacitor dielectric layer 210 corresponding to the first conductive layer 1120 to realize the function of a single memory cell. Exemplarily, the first conductive layer 1120 can be used as part of a conducting circuit for transmitting signals to the memory cell.

[0071] The material of the capacitor dielectric layer 210 can include various types. In actual processes, the material of the capacitor dielectric layer 210 can be reasonably selected according to specific requirements to enable the capacitor dielectric layer 210 to have a storage effect. This application does not impose any restrictions on this. For example, the material of the capacitor dielectric layer 210 can be a ferroelectric material, an antiferroelectric material, etc.

[0072] For example, when the material of the capacitor dielectric layer 210 is a ferroelectric material, the portion of the first conductive layer 1120 surrounding the capacitor dielectric layer 210, and the portion of the capacitor dielectric layer 210 and the inner electrode layer 220 opposite to the first conductive layer 1120 form a ferroelectric capacitor, that is, the above-mentioned memory cell.

[0073] Ferroelectric materials have nonlinear characteristics. Not only can the dielectric constant of ferroelectric materials be adjusted, but the difference between the polarization states of the ferroelectric layer containing the ferroelectric material and the polarization state is very large. This makes ferroelectric capacitors smaller in size compared to other capacitors. The smaller size of the capacitor used to store charge is beneficial for achieving high-density storage.

[0074] Ferroelectric materials can be one or more of the following: zirconium oxide (ZrO2), hafnium oxide (HfO2), aluminum (Al)-doped HfO2, silicon (Si)-doped HfO2, zirconium (Zr)-doped HfO2, lanthanum (La)-doped HfO2, yttrium (Y)-doped HfO2, etc., or materials based on these materials but doped with other elements. Antiferroelectric materials exhibit good stability and can effectively avoid wake-up effects, imprinting effects, and polarization fatigue. Applying antiferroelectric materials to memory structures can result in better data retention characteristics.

[0075] In another exemplary embodiment of this application, such as Figure 12 As shown, the gate gap structure 1300 and the storage structure 1200 can be sequentially included from the outside to the inside as a first outer electrode layer 240, a capacitor dielectric layer 210, an inner electrode layer 220 and a filling dielectric layer 230.

[0076] Specifically, forming the gate line slot structure 1300 and the memory structure 1200 may include: sequentially forming a first external electrode layer 240, a capacitor dielectric layer 210, and an inner electrode layer 220 from the outside to the inside within the gate line slot 1310 and the memory hole 1230, respectively forming the gate line slot structure 1300 and the memory structure 1200, wherein the first external electrode layer 240, the capacitor dielectric layer 210, and the inner electrode layer 220 within the gate line slot structure 1300 extend along a first direction Y. For example, after forming the first external electrode layer 240, the capacitor dielectric layer 210, and the inner electrode layer 220, a filling dielectric layer 230 may be used to fill the gate line slot 1310 and the memory hole 1230. The filling dielectric layer 230 may include an oxide dielectric layer, such as silicon oxide. Further, during the filling process, multiple insulating gaps can be formed in the filling dielectric layer 230 by controlling the filling process to reduce structural stress. At this time, the portions of the first outer electrode layer 240, the capacitor dielectric layer 210, and the inner electrode layer 220 of the storage structure 1200 corresponding to each first conductive layer 1120 can form independent storage cells.

[0077] In the exemplary embodiments of this application, such as Figure 13As shown, a second dielectric layer 2110 and a second conductive layer 2120 can be sequentially stacked on the surface of the stacked structure 1100 to form a top select gate structure 2100; and a transistor 2200 is formed that passes through the top select gate structure 2100 and extends to the storage structure 1200 along the stacking direction Z.

[0078] For example, the second dielectric layer 2110 may be made of an insulating material, which may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The second conductive layer 2120 may be made of a conductive material. The conductive material may include at least one of the following conductive materials: poly-Si (p-Si, polycrystalline silicon), TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), and Ag (silver).

[0079] In one exemplary embodiment of this application, such as Figure 14 As shown, transistor 2200 can be sequentially divided into dielectric layer 310 and channel layer 320 from the outside to the inside.

[0080] Specifically, forming a transistor 2200 that extends along the stacking direction Z through the top select gate structure 2100 and into the memory structure 1200 may include: forming an opening that extends along the stacking direction Z through the top select gate structure 2100 and into the memory structure 1200; and forming a dielectric layer 310 and a channel layer 320 sequentially from the outside to the inside within the opening, wherein the dielectric layer 310 is in direct contact with the second conductive layer 2120.

[0081] Exemplarily, the material of the dielectric layer 310 may include one or more insulating materials such as SiO2 (silicon dioxide), Al2O3 (alumina), HfO2 (hafnium dioxide), ZrO2 (zirconia), TiO2 (titanium dioxide), Y2O3 (yttrium oxide), and Si3N4 (silicon nitride). The material of the channel layer 320 may include one or more semiconductor materials such as silicon and polycrystalline silicon. Exemplarily, the dielectric layer 310 and the channel layer 320 may be formed sequentially by a thin film deposition process such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0082] Exemplarily, the dielectric layer 310 may be located between the second conductive layer 2120 and the channel layer 320. The channel layer 320 may have a cylindrical structure and may extend along the stacking direction Z. The portion of the dielectric layer 310, the channel layer 320, and the second conductive layer 2120 surrounding the dielectric layer 310 may form a transistor 2200. The portion of the second conductive layer 2120 surrounding the dielectric layer 310 may form the gate of the transistor 2200. The channel layer 320 is in contact with the inner electrode layer 220 of the memory structure 1200, and the portion of the channel layer 320 in contact with the inner electrode layer 220 of the memory structure 1200 may form the source or drain of the transistor.

[0083] For example, the source of transistor 2200 is electrically connected to the inner electrode layer 220 of memory structure 1200. Similarly, the drain of transistor 2200 is electrically connected to the inner electrode layer 220 of memory structure 1200. It should be noted that the drain or source of transistor 2200 can be determined based on the direction of current flow.

[0084] In another exemplary embodiment of this application, such as Figure 15 As shown, transistor 2200 may include, from the outside to the inside, a second external electrode layer 330, a dielectric layer 310 and a channel layer 320.

[0085] Specifically, forming a transistor 2200 that extends along the stacking direction Z through the top select gate structure 2100 and into the memory structure 1200 includes: forming an opening along the stacking direction Z through the top select gate structure 2100 and into the memory structure 1200; and sequentially forming a second external electrode layer 330, a dielectric layer 310, and a channel layer 320 from the outside to the inside within the opening. Exemplarily, the material of the second external electrode layer 330 may include any suitable conductive material. In this case, the second external electrode layer 330 may form the gate of the transistor 2200.

[0086] In the exemplary embodiments of this application, such as Figure 13 As shown, a plurality of bit lines 2300 extending along the first direction Y and connected to corresponding transistors 2200 can be formed. For example, forming a plurality of bit lines 2300 extending along the first direction Y and connected to corresponding transistors 2200 may include: forming a plurality of bit line contacts 2310 penetrating the second dielectric layer 2110 and the second conductive layer 2120 and extending to the transistors 2200; and forming bit lines 2300 extending along the first direction Y and connected to the bit line contacts 2310.

[0087] Exemplarily, the materials of bit line contacts 2310 and bit lines 2300 may include conductive materials, such as metallic materials. The metallic material may be one or more of the following conductive materials: TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), and Ag (silver). Of course, the materials of bit line contacts 2310 and bit lines 2300 may be the same or different, and this application does not impose any limitations on this. When the materials of bit line contacts 2310 and bit lines 2300 are the same, they can be formed through the same process, which helps to simplify the process flow for fabricating semiconductor structures and reduce the cost of fabricating semiconductor structures.

[0088] For example, the gate of transistor 2200 is electrically connected to the second conductive layer 2120, the second electrode of transistor 2200 can be electrically connected to bit line 2300, the first ends of multiple memory cells (e.g., the inner electrode layer 220 of memory structure 1200) can be electrically connected to the first electrode of transistor 2200, and the second end of each memory cell (e.g., the outer electrode of memory structure 1200) can be electrically connected to the first conductive layer 1120.

[0089] The second conductive layer 2120 can be used to receive word line control signals, causing transistor 2200 to conduct. Bit line 2300 can be used to receive bit line control signals. When transistor 2200 is turned on under the control of the word line control signals transmitted by the second conductive layer 2120, the bit line control signals received by bit line 2300 can pass through transistor 2200 to precharge the voltage of the inner electrode layer 220 of memory structure 1200.

[0090] In the exemplary embodiments of this application, such as Figure 13 As shown, a plurality of contact structures 2400 extending along the stacking direction Z to the second conductive layer 2120 can be formed. The electrical signals provided by the plurality of contact structures 2400 can be transmitted to the second conductive layer 2120, thereby enabling the transmission of electrical signals between the top select gate structure 2100 and other circuits via the contact structures 2400.

[0091] Figure 13 This is a schematic diagram of a semiconductor structure according to an exemplary embodiment of this application.

[0092] The semiconductor structure may include a memory structure 1200 and a gate gap structure 1300.

[0093] The memory structure 1200 extends through the stacked structure 1100, which includes alternating stacked first dielectric layers 1110 and first conductive layers 1120. The gate slot structure 1300 extends through the stacked structure 1100 and extends along a first direction Y. The gate slot structure 1300 divides the stacked structure 1100 into multiple memory blocks distributed along a second direction X, wherein the first direction Y, the second direction X, and the stacking direction Z are perpendicular to each other.

[0094] It should be understood that the number and thickness of the first dielectric layer 1110 and the first conductive layer 1120 are not limited to... Figure 13 The quantities and thicknesses shown herein, without departing from the concept of this application, allow those skilled in the art to provide any number and thickness of the first dielectric layer 1110 and the first conductive layer 1120 as needed.

[0095] Furthermore, the materials of the first dielectric layer 1110 and the first conductive layer 1120 can be selected from suitable materials known in the art. For example, the material of the first dielectric layer 1110 may include an insulating material, and the material of the first conductive layer 1120 may include a conductive material. For instance, the material of the first dielectric layer 1110 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The material of the first conductive layer 1120 may include at least one of conductive materials such as poly-Si (p-Si, polycrystalline silicon), TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), and Ag (silver).

[0096] In an exemplary embodiment of this application, the memory structure 1200 and the gate line slot structure 1300 may sequentially include a capacitor dielectric layer 210 and an inner electrode layer 220 from the outside to the inside. Figure 11 Furthermore, the memory structure 1200 and the gate line slot structure 1300 may also include a filling dielectric layer 230 located inside the inner electrode layer 220 to electrically insulate adjacent inner motor layers 220 within the gate line slot 1310 and the memory via 1230. The filling dielectric layer 230 may include an oxide dielectric layer, such as silicon oxide.

[0097] For example, the capacitor dielectric layer 210, the inner electrode layer 220 and the filling dielectric layer 230 within the gate gap structure 1300 may extend along the first direction Y to divide the stacked structure 1100 into a plurality of memory blocks distributed along the second direction X.

[0098] The inner electrode layer 220 may be made of a conductive material, such as one or more of the following: polycrystalline silicon, TiN (titanium nitride), TaN (tantalum nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver), Pt (platinum).

[0099] For example, the first conductive layer 1120 may be in direct contact with the capacitor dielectric layer 210. The capacitor dielectric layer 210 of the storage structure 1200 may have a storage function. Specifically, the portions of the capacitor dielectric layer 210 and the inner electrode layer 220 corresponding to each first conductive layer 1120 may form independent storage cells with the first conductive layer 1120. The portion of each first conductive layer 1120 surrounding the capacitor dielectric layer 210 constitutes the outer electrode of the storage cell.

[0100] The number of first conductive layers 1120 is multiple, with each first conductive layer 1120 forming a memory cell by surrounding a portion of the capacitor dielectric layer 210 and the portions of the capacitor dielectric layer 210 and the inner electrode layer 220 opposite to the first conductive layer 1120. Each memory cell can be controlled by the first conductive layer 1120. Charge is stored or released in the capacitor dielectric layer 210 corresponding to the first conductive layer 1120 to realize the function of a single memory cell. Exemplarily, the first conductive layer 1120 can be used as part of a conducting circuit for transmitting signals to the memory cell.

[0101] The material of the capacitor dielectric layer 210 can include various types. In actual processes, the material of the capacitor dielectric layer 210 can be reasonably selected according to specific requirements to enable the capacitor dielectric layer 210 to have a storage effect. This application does not impose any restrictions on this. For example, the material of the capacitor dielectric layer 210 can be a ferroelectric material, an antiferroelectric material, etc.

[0102] For example, when the material of the capacitor dielectric layer 210 is a ferroelectric material, the portion of the first conductive layer 1120 surrounding the capacitor dielectric layer 210, and the portion of the capacitor dielectric layer 210 and the inner electrode layer 220 opposite to the first conductive layer 1120 form a ferroelectric capacitor, that is, the above-mentioned memory cell.

[0103] Ferroelectric materials have nonlinear characteristics. Not only can the dielectric constant of ferroelectric materials be adjusted, but the difference between the polarization states of the ferroelectric layer containing the ferroelectric material and the polarization state is very large. This makes ferroelectric capacitors smaller in size compared to other capacitors. The smaller size of the capacitor used to store charge is beneficial for achieving high-density storage.

[0104] Ferroelectric materials can be one or more of the following: zirconium oxide (ZrO2), hafnium oxide (HfO2), aluminum (Al)-doped HfO2, silicon (Si)-doped HfO2, zirconium (Zr)-doped HfO2, lanthanum (La)-doped HfO2, yttrium (Y)-doped HfO2, etc., or materials based on these materials but doped with other elements. Antiferroelectric materials exhibit good stability and can effectively avoid wake-up effects, imprinting effects, and polarization fatigue. Applying antiferroelectric materials to memory structures can result in better data retention characteristics.

[0105] In another exemplary embodiment of this application, the gate gap structure 1300 and the storage structure 1200 may sequentially include a first outer electrode layer 240, a capacitor dielectric layer 210, and an inner electrode layer 220 from the outside to the inside. Figure 12 Furthermore, the memory structure 1200 and the gate gap structure 1300 may also include a filling dielectric layer 230 located inside the inner electrode layer 220 to electrically insulate adjacent inner motor layers 220 within the gate gap 1310 and the memory via 1230. The filling dielectric layer 230 may include an oxide dielectric layer, such as silicon oxide. In this case, the portions of the first outer electrode layer 240, the capacitor dielectric layer 210, and the inner electrode layer 220 of the memory structure 1200 corresponding to each first conductive layer 1120 can form independent memory cells.

[0106] In the exemplary embodiments of this application, such as Figure 13 As shown, the semiconductor structure may further include a top-select gate structure 2100. The top-select gate structure 2100 may be located on the surface of the stacked structure 1100. The top-select gate structure 2100 may include a second dielectric layer 2110 and a second conductive layer 2120 stacked sequentially.

[0107] For example, the second dielectric layer 2110 may be made of an insulating material, which may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The second conductive layer 2120 may be made of a conductive material. The conductive material may include at least one of the following conductive materials: poly-Si (p-Si, polycrystalline silicon), TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), and Ag (silver).

[0108] In the exemplary embodiments of this application, such as Figure 13 As shown, the semiconductor structure may also include a transistor 2200. The transistor 2200 may extend along the stacking direction Z through the top select gate structure 2100 and into the memory structure 1200.

[0109] In an exemplary embodiment of this application, the transistor 2200 may sequentially include a dielectric layer 310 and a channel layer 320 from the outside to the inside. Figure 14 ).

[0110] Exemplarily, the material of the dielectric layer 310 may include one or more insulating materials such as SiO2 (silicon dioxide), Al2O3 (alumina), HfO2 (hafnium dioxide), ZrO2 (zirconia), TiO2 (titanium dioxide), Y2O3 (yttrium oxide), and Si3N4 (silicon nitride). The material of the channel layer 320 may include one or more semiconductor materials such as silicon and polycrystalline silicon. Exemplarily, the dielectric layer 310 and the channel layer 320 may be formed sequentially by a thin film deposition process such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0111] Exemplarily, the dielectric layer 310 may be located between the second conductive layer 2120 and the channel layer 320. The channel layer 320 may have a cylindrical structure and may extend along the stacking direction Z. The portion of the dielectric layer 310, the channel layer 320, and the second conductive layer 2120 surrounding the dielectric layer 310 may form a transistor 2200. The portion of the second conductive layer 2120 surrounding the dielectric layer 310 may form the gate of the transistor 2200. The channel layer 320 is in contact with the inner electrode layer 220 of the memory structure 1200, and the portion of the channel layer 320 in contact with the inner electrode layer 220 of the memory structure 1200 may form the source or drain of the transistor.

[0112] For example, the source of transistor 2200 is electrically connected to the inner electrode layer 220 of memory structure 1200. Similarly, the drain of transistor 2200 is electrically connected to the inner electrode layer 220 of memory structure 1200. It should be noted that the drain or source of transistor 2200 can be determined based on the direction of current flow.

[0113] In another exemplary embodiment of this application, the transistor 2200 may sequentially include a second external electrode layer 330, a dielectric layer 310, and a channel layer 320 from the outside to the inside. Figure 15 For example, the material of the second outer electrode layer 330 may include any suitable conductive material. In this case, the second outer electrode layer 330 may form the gate of the transistor 2200.

[0114] In the exemplary embodiments of this application, such as Figure 13 As shown, the semiconductor structure may further include a plurality of bit lines 2300. The plurality of bit lines 2300 extend along a first direction Y and are connected to corresponding transistors 2200. Exemplarily, the semiconductor structure may further include a plurality of bit line contacts 2310 that penetrate the second dielectric layer 2110 and the second conductive layer 2120 and extend to the transistors 2200, wherein the bit lines 2300 may be connected to the corresponding transistors 2200 via the bit line contacts 2310.

[0115] Exemplarily, the materials of bit line contacts 2310 and bit line 2300 may include conductive materials, such as metallic materials. The metallic material may be one or more of conductive materials such as TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), and Ag (silver). Of course, the materials of bit line contacts 2310 and bit line 2300 may be the same or different, and this application does not limit this.

[0116] For example, the gate of transistor 2200 is electrically connected to the second conductive layer 2120, the second electrode of transistor 2200 can be electrically connected to bit line 2300, the first ends of multiple memory cells (e.g., the inner electrode layer 220 of memory structure 1200) can be electrically connected to the first electrode of transistor 2200, and the second end of each memory cell (e.g., the outer electrode of memory structure 1200) can be electrically connected to the first conductive layer 1120.

[0117] The second conductive layer 2120 can be used to receive word line control signals, causing transistor 2200 to conduct. Bit line 2300 can be used to receive bit line control signals. When transistor 2200 is turned on under the control of the word line control signals transmitted by the second conductive layer 2120, the bit line control signals received by bit line 2300 can pass through transistor 2200 to precharge the voltage of the inner electrode layer 220 of memory structure 1200.

[0118] In the exemplary embodiments of this application, such as Figure 13 As shown, the semiconductor structure may further include multiple contact structures 2400. The contact structures 2400 may extend along the stacking direction Z to the second conductive layer 2120. The electrical signals provided by the multiple contact structures 2400 can be transmitted to the second conductive layer 2120, thereby enabling the transmission of electrical signals between the top select gate structure 2100 and other circuits via the contact structures 2400.

[0119] Since the content and structure described above in the method 1000 for manufacturing a semiconductor structure can be applied in whole or in part to the semiconductor structure described herein, related or similar content will not be repeated here.

[0120] Although exemplary structures and fabrication methods of semiconductor structures have been described herein, it is understood that one or more features may be omitted, substituted, or added from the fabrication methods of the semiconductor structure. Furthermore, the layers and materials described are merely exemplary.

[0121] Figure 16 This is a block diagram of a system 10 having a storage system 12 according to an exemplary embodiment of this application.

[0122] System 10 can be a mobile phone, desktop computer, laptop, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device (which has a storage system 12 located therein). Figure 16 As shown, system 10 may include a host 18 and a storage system 12, the storage system 12 having one or more three-dimensional memories 14 and a controller 16. The host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 18 may be configured to send or receive data to and from the three-dimensional memories 14.

[0123] The three-dimensional memory 14 may include the semiconductor structure described in any embodiment of this application. According to some embodiments, a controller 16 is coupled to the three-dimensional memory 14 and the host 18 and is configured to control the three-dimensional memory 14. The controller 16 may manage data stored in the three-dimensional memory 14 and communicate with the host 18. In some embodiments, the controller 16 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the controller 16 is designed to operate in a high duty cycle environment, such as an SSD or embedded multi-media card (eMMC) used as a data storage device in a mobile device, such as a smartphone, tablet, laptop, etc. The controller 16 may be configured to control the operation of the three-dimensional memory 14, such as read, erase, and program operations. The controller 16 may also be configured to manage various functions related to data stored in or to be stored in the 3D memory 14, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the controller 16 is further configured to process error correction codes (ECCs) related to data read from or written to the 3D memory 14. The controller 16 may also perform any other appropriate functions, such as formatting the 3D memory 14. The controller 16 may communicate with external devices (e.g., the host 18) according to a specific communication protocol. For example, the controller 16 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0124] The controller 16 and one or more three-dimensional memories 14 can be integrated into various types of memory systems, for example, included in the same package (such as a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 12 can be implemented and packaged into different types of end electronic products. Figure 17AIn one example shown, the controller 16 and a single three-dimensional memory 14 may be integrated into the memory card 22. The memory card 22 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 22 may further include a connection between the memory card 22 and a host (e.g., Figure 16 The host 18) is coupled to the memory card connector 24. In such a way... Figure 17B In another example shown, the controller 16 and multiple 3D memories 14 may be integrated into the SSD 26. The SSD 26 may further include a connection between the SSD 26 and a host (e.g., Figure 16 The SSD connector 28 is coupled to the host 18. In some embodiments, the storage capacity and / or operating speed of the SSD 26 is higher than that of the memory card 22.

[0125] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of disclosure in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method of fabricating a semiconductor structure, characterized by, include: A first sacrificial structure is formed that penetrates the stacked structure and a gate slot extends through the stacked structure along a first direction, wherein the first direction is perpendicular to the stacking direction of the stacked structure; Remove the first sacrificial structure to form a storage hole; as well as A grid line slot structure and a storage structure are formed in the grid line slot and the storage hole, respectively.

2. The method according to claim 1, characterized in that, The first sacrificial structure forming a through-layer structure and the gate wire slot extending through the through-layer structure along a first direction include: A plurality of first sacrificial structures and second sacrificial structures are formed throughout the stacked structure, wherein the first sacrificial structures and the second sacrificial structures are distributed adjacently along a second direction, and the plurality of second sacrificial structures are arranged along a first direction, wherein the first direction, the second direction and the stacking direction are perpendicular to each other; Remove multiple second sacrificial structures to form gate vias; and The grid hole is etched back to the adjacent grid hole along the first direction to form a grid gap extending along the first direction.

3. The method according to claim 2, characterized in that, Forming a plurality of first sacrificial structures and second sacrificial structures that penetrate the stacked structure, including: Forming a plurality of first sacrificial holes and second sacrificial holes penetrating the stacked structure; and Sacrificial material is filled into the first sacrificial hole and the second sacrificial hole to form the first sacrificial structure and the second sacrificial structure.

4. The method according to claim 1, characterized in that, The method includes: Alternating stacking of the first dielectric layer and the first conductive layer forms a stacked structure.

5. The method according to claim 1 or 2, characterized in that, A gate wire slot structure and a storage structure are formed in the gate wire slot and the storage hole, respectively, including: A capacitor dielectric layer and an inner electrode layer are formed sequentially from the outside to the inside within the gate line slot and the storage hole, respectively forming the gate line slot structure and the storage structure, wherein the capacitor dielectric layer and the inner electrode layer within the gate line slot structure extend along the first direction.

6. The method according to claim 1 or 2, characterized in that, A gate wire slot structure and a storage structure are formed in the gate wire slot and the storage hole, respectively, including: A first outer electrode layer, a capacitor dielectric layer, and an inner electrode layer are formed sequentially from the outside to the inside within the gate line slot and the storage hole, respectively forming the gate line slot structure and the storage structure, wherein the first outer electrode layer, the capacitor dielectric layer, and the inner electrode layer within the gate line slot structure extend along the first direction.

7. The method according to claim 1, characterized in that, The method further includes: A second dielectric layer and a second conductive layer are sequentially stacked on the surface of the stacked structure to form a top selection gate structure; and A transistor is formed that passes through the top selected gate structure and extends into the memory structure along the stacking direction.

8. The method according to claim 7, characterized in that, Forming a transistor that extends along the stacking direction through the top selected gate structure and into the memory structure includes: Forming an opening along the stacking direction through the top select gate structure and extending into the memory structure; and A dielectric layer and a channel layer are formed sequentially from the outside to the inside within the opening, wherein the dielectric layer is in direct contact with the second conductive layer.

9. The method according to claim 7, characterized in that, Forming a transistor that extends along the stacking direction through the top selected gate structure and into the memory structure includes: Forming an opening along the stacking direction through the top select gate structure and extending into the memory structure; and A second outer electrode layer, a dielectric layer, and a channel layer are formed sequentially from the outside to the inside within the opening.

10. The method according to any one of claims 7-9, characterized in that, The method further includes: Forming a plurality of bit lines extending along the first direction and connected to the corresponding transistors; and Multiple contact structures are formed that extend along the stacking direction to the second conductive layer.

11. A semiconductor structure, characterized in that, include: A storage structure, extending through a stacked structure, wherein the stacked structure comprises alternating stacked first dielectric layers and first conductive layers; as well as A gate line slot structure extends through the stacked structure and along a first direction, wherein the first direction is perpendicular to the stacking direction of the stacked structure, and the storage structure and the gate line slot structure sequentially include a capacitor dielectric layer and an inner electrode layer from the outside to the inside.

12. The semiconductor structure according to claim 11, characterized in that, The capacitor dielectric layer and the inner electrode layer within the gate line slot structure extend along the first direction, and the gate line slot structure divides the stacked structure into a plurality of memory blocks distributed along the second direction, wherein the first direction, the second direction, and the stacking direction are perpendicular to each other.

13. The semiconductor structure according to claim 11, characterized in that, The first conductive layer is in direct contact with the capacitor dielectric layer.

14. The semiconductor structure according to claim 11 or 12, characterized in that, The storage structure and the gate gap structure further include: a first external electrode layer located outside the capacitor dielectric layer.

15. The semiconductor structure according to claim 11, characterized in that, The semiconductor structure also includes: A top-selected gate structure is located on the surface of the stacked structure, comprising a second dielectric layer and a second conductive layer stacked sequentially. A transistor extends along the stacking direction through the top select gate structure and into the memory structure; Multiple bit lines, extending along the first direction and connected to corresponding transistors; and Multiple contact structures extend along the stacking direction to the second conductive layer.

16. The semiconductor structure according to claim 11, characterized in that, The materials of the first conductive layer and the inner electrode layer include at least one conductive material selected from polycrystalline silicon, titanium nitride, tungsten metal, platinum metal, and tantalum nitride.

17. The semiconductor structure according to claim 11, characterized in that, The material of the capacitor dielectric layer includes at least one of ferroelectric and antiferroelectric materials.

18. A storage system, characterized in that, include: At least one three-dimensional memory, each of the three-dimensional memory comprising a semiconductor structure as described in any one of claims 11 to 17; as well as A controller, coupled to the semiconductor structure, is used to control the storage of data in the three-dimensional memory.

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