High-maintaining-voltage SCR device for integrated circuit ESD protection
By adjusting the anode structure and adjusting the drainage control flow path of GGNMOS, introducing additional parasitic PNP paths and increasing the on-resistance of the STI crossover area, the problem of insufficient maintenance voltage and latch resistance of the existing ESD protection devices is solved, and the problem of insufficient maintenance voltage and latch resistance is achieved. High maintenance voltage and strong latch resistance ESD protection effect.
Patent Information
- Application Number
- CN202411423338.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-12
- Publication Date
- 2025-02-21
AI Technical Summary
Existing ESD protection devices have shortcomings in maintaining voltage and latch resistance, making it difficult to meet the ESD protection requirements of integrated circuits in multiple power domains.
By adjusting the anode structure and adjusting the drain region control shunt path of GGNMOS, changing the on-resistance of GGNMOS, introducing an additional parasitic PNP path and increasing the on-resistance of the STI crossover region to increase the maintenance voltage of the SCR.
It realizes that the maintenance voltage and latch resistance of ESD protection devices are significantly improved without changing the trigger mechanism and increasing the size, and meets the protection window requirements of different application scenarios.
Smart Images
Figure CN119497427A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of integrated circuit (IC) electrostatic discharge (ESD) protection device design, and specifically relates to an ESD protection device, especially a high holding voltage silicon controlled rectifier. Background Art
[0002] ESD events are often considered to be one of the main causes of damage to electronic components and integrated circuits. It is a phenomenon in which charge transfer occurs when objects with different electrostatic potentials come into contact. With the continuous advancement of semiconductor technology and the continuous reduction of integrated circuit process technology, the problem of IC failure caused by ESD is becoming increasingly serious. Therefore, research on ESD protection of chips is crucial.
[0003] In a specific integrated circuit process, ESD protection devices need to meet certain ESD design window requirements, that is, their safe operating range should be about 10% lower than the minimum breakdown voltage of the protected circuit and about 10% higher than the operating voltage of the circuit. For ESD protection devices with hysteresis characteristics, the trigger voltage and holding voltage must be limited to a specific design window, so the trigger voltage and holding voltage of the ESD protection device need to be adjusted to meet different application scenarios. Designing ESD protection devices that meet the requirements and have high robustness has always been the focus and difficulty in the design. Therefore, it is of great significance to develop ESD protection devices with adjustable trigger voltage and holding voltage, strong anti-latch capability and high robustness.
[0004] Among many ESD protection devices, SCR devices are recognized as highly robust devices, that is, the unit area efficiency of such devices is very high. The triggering principle is usually PN junction avalanche breakdown. When the PN junction breaks down, the current increases sharply, and the generated electrons and holes move to the anode and cathode respectively, thereby generating a potential difference in the well region, making the emitter junctions of the parasitic NPN and PNP transistors in the SCR forward biased. In addition, the collector junctions of the two parasitic transistors are both reverse biased, so the two parasitic transistors can amplify the current to form positive feedback; the increased current causes the conductivity modulation near the PN junction in the SCR, clamping the potential of the device at a lower potential for a larger current discharge. Therefore, the triggering of the SCR can be adjusted by adjusting the PN junction avalanche breakdown voltage, which is mainly related to the doping concentration on both sides of the PN junction. The lower the doping concentration, the greater the breakdown voltage; and its holding voltage is mainly related to the current amplification factor of the parasitic transistor (NPN and PNP). The larger the current amplification factor, the lower the holding voltage. Traditional SCRs have the disadvantages of high trigger voltage and low holding voltage.
[0005] GGSCR can be used to reduce the trigger voltage of SCR and increase the maintenance voltage of SCR. The structure of this device is as follows Figure 1 As shown, the device structure includes: a P-type silicon substrate 10, on which adjacent N-type well regions 11 and P-type well regions 12 are formed; an N-type heavily doped region 13 and a P-type heavily doped region 14 are formed in the N-type well region 11, and the N-type heavily doped region 13 and the P-type heavily doped region 14 are isolated by STI; an N-type heavily doped region 16 and a P-type heavily doped region 17 are formed in the P-type well region 12, and the N-type heavily doped region 16 and the P-type heavily doped region 14 are isolated by STI. 7 is isolated by STI; an N-type heavily doped jumper region 15 is formed on the surface of the junction of the N-type well region 11 and the P-type well region 12, and the N-type heavily doped jumper region 15 is isolated from the P-type heavily doped region 14 in the N-type well region 11 by STI; a thin gate oxide layer region 18 is arranged above the surface between the N-type heavily doped jumper region 15 and the N-type heavily doped region 16 in the P-type well region 12, and an N-type heavily doped polysilicon region 19 is covered above the thin gate oxide layer region 18.
[0006] In this structure, the N-type heavily doped region 13, the P-type heavily doped region 14 and the N-type heavily doped jumper region 15 in the N-type well region 11 are connected to the anode of the device; the N-type heavily doped polysilicon region 19, the N-type heavily doped region 16 and the P-type heavily doped region 17 on the P-type well region 12 side are connected to the cathode of the device.
[0007] like Figure 2 As shown, this structure uses an N-type heavily doped jumper region 15, a thin gate oxide layer region 18 and an N-type heavily doped polysilicon region 19 to introduce the NMOS structure M1 into the SCR. Since the NMOS drain-source breakdown voltage is lower than the breakdown voltage of the PN junction formed by the N-type well region 11 and the P-type well region 12, the trigger voltage can be reduced. After the gate-grounded NMOS is triggered, the holes flow to the cathode through the P-type well region 12 and the P-type heavily doped region 17. pw1 A voltage drop is generated on the P-type well region 12 and the N-type heavily doped region 16, causing the PN junction formed by the P-type well region 12 and the N-type heavily doped region 16 to be forward-conducted, and the parasitic NPN transistor Q composed of the N-type heavily doped jumper region 15, the P-type well region 12 and the N-type heavily doped region 16 is turned on. n2 The emitter junction of the SCR is forward biased, and the collector junction is reverse biased, so the GGNMOS path is turned on, and the current will first discharge the charge through the GGNMOS path; when the voltage increases further, the voltage across the SCR reaches the reverse breakdown voltage of the PN junction formed by the N-type well region 11 and the P-type well region 12, the PN junction breaks down, the current increases sharply, and the generated electrons and holes move to the anode and cathode respectively, and the formed current flows through the well resistor R pw1 and R nw1A voltage drop is generated, so that the PN junction formed by the P-type heavily doped region 14 and the N-type well region 11 and the PN junction formed by the P-type well region 12 and the N-type heavily doped region 16 are forward biased, so the parasitic NPN transistor Q composed of the N-type well region 11, the P-type well region 12, and the N-type heavily doped region 16 is forward biased. n1 The parasitic PNP transistor Q is composed of the P-type well region 12, the N-type well region 11, and the P-type heavily doped region 14. p1 The emitter junction is forward biased and the collector junction is reverse biased, and the device works in an amplification state. As the voltage increases, the two parasitic transistors form positive feedback. The increased current causes conductivity modulation near the PN junction in the SCR, clamping the device's potential at a lower potential to discharge a larger current. At this time, the current will flow through the SCR path composed of the P-type heavily doped region 14, the N-type well region 11, the P-type well region 12, and the N-type heavily doped region 16. However, the conductivity modulation of the well region in the SCR will be suppressed due to the shunting of the GGNMOS, and a larger maintenance voltage needs to be applied to enable the SCR to complete the conductivity modulation, so the maintenance voltage is increased.
[0008] However, the improvement of the holding voltage by GGSCR is still limited, and the shunt path of GGNMOS is difficult to regulate. Therefore, the present invention proposes an ESD protection device structure that can further improve the holding voltage of GGSCR. The device structure further improves the holding voltage of SCR by adjusting the anode structure and adjusting the drain region of GGNMOS to control the shunt path and change the on-resistance of GGNMOS. Summary of the invention
[0009] The purpose of the present invention is to provide a high holding voltage SCR device for integrated circuit ESD protection, which has the characteristics of high holding voltage, strong anti-latch capability and high robustness, and can be applied to integrated circuit ESD protection in various power domains. The technical solution adopted by the present invention is:
[0010] A high holding voltage SCR device for ESD protection of integrated circuits, the device can be composed of n repeating units arranged in parallel, such as Figure 3 As shown, the device structure includes:
[0011] A P-type silicon substrate 100, on which adjacent N-type well region 101 and P-type well region 102 are formed;
[0012] An N-type heavily doped crossover region 103 is formed in the N-type well region 101 and the P-type well region 102, wherein P-type heavily doped regions 104, 204, 304 ... n04 are also formed in the N-type well region 101, and the P-type heavily doped regions 104, 204, 304 ... n04 are surrounded by the N-type heavily doped crossover region 103 and isolated by STI. STI crossover regions 107, 207, 307 ... n07 are formed on the surface of the junction between the N-type well region 101 and the P-type well region 102, and the STI crossover regions 107, 207, 307 ... n07 are surrounded by the N-type heavily doped crossover region 103.
[0013] An N-type heavily doped region 105 and a P-type heavily doped region 106 are formed in the P-type well region 102, and the N-type heavily doped region 105 and the P-type heavily doped region 106 are isolated by STI; a thin oxide layer region 108 is set above the surface between the N-type heavily doped jumper region 103 and the N-type heavily doped region 106 in the P-type well region 102, and an N-type heavily doped polysilicon region 109 is covered above the thin oxide layer region 108.
[0014] In this structure, the N-type heavily doped jumper region 103 and the P-type heavily doped regions 104, 204, 304...n04 in the N-type well region 101 are connected to the anode of the device, wherein the anode contact hole at the N-type heavily doped jumper region 103 is farther away from the junction between the N-type well region 101 and the P-type well region 102 than the STI jumper regions 107, 207, 307...n07; the N-type heavily doped polysilicon region 109, the N-type heavily doped region 105 and the P-type heavily doped region 106 on the P-type well region 102 side are connected to the cathode of the device.
[0015] like Figure 3 As shown, the bold dashed box is a standard unit. The working process of the device structure is described below using the standard unit as an example. When a positive pulse is applied to the anode of the structure, the drain-source PN junction of the NMOS tube M2 formed by the N-type heavily doped jumper region 103 and the P-type well region 102 is reverse biased. When the anode voltage is greater than the PN junction breakdown voltage, a large number of electron-hole pairs will be generated near the PN junction surface. The generated electrons flow to the anode through the N-type heavily doped jumper region 103. At the same time, the holes flow to the cathode through the P-type well region 102 and the P-type heavily doped region 106. The well resistance R pw2 A voltage drop is generated on the P-type well region 102 and the N-type heavily doped region 105, causing the PN junction formed by the P-type well region 102 and the N-type heavily doped region 105 to be forward-conducted, and the parasitic NPN transistor Q composed of the N-type heavily doped jumper region 103, the P-type well region 102 and the N-type heavily doped region 105 is turned on. n4The emitter junction is forward biased, the collector junction is reverse biased, the GGNMOS path is turned on, and the current will first discharge the charge through the GGNMOS path; when the current increases further, and the voltage across the SCR reaches the reverse breakdown voltage of the PN junction formed by the N-type well region 101 and the P-type well region 102, the PN junction breaks down, and the generated electrons will flow out of the anode along the N-type well region 101 and the N-type heavily doped jumper region 103, and the current flows through the well resistor R nw2 , R nw3 When the voltage drop between the PN junction formed by the P-type heavily doped region 204 and the N-type well region 101 reaches 0.7V, the PN junction is forward-conducted, and the parasitic PNP transistor Q composed of the P-type heavily doped region 204, the N-type well region 101, and the P-type well region 102 is turned on. p2 , Q p3 Turn on; the generated holes will flow out of the cathode along the P-type well region 102 and the P-type heavily doped region 106, and the current will flow through the well resistor R pw2 When the voltage drop between the PN junction formed by the P-type well region 102 and the N-type heavily doped region 105 reaches 0.7V, the PN junction is forward-conducted, and the parasitic NPN transistor Q composed of the N-type well region 101, the P-type well region 102, and the N-type heavily doped region 105 is turned on. n3 The emitter junction is forward biased and the collector junction is reverse biased. Therefore, both parasitic bipolar transistors are turned on for positive feedback, forming an SCR current path to discharge the ESD current. Figure 2 A-A' section diagram and Figure 4 From the B-B' cross-section diagram, it can be seen that the current paths of the two devices are similar and the working mechanisms of the devices are basically the same.
[0016] Compared with GGSCR, this structure has three improvements. First, the N-type heavily doped crossover region 103 of this structure surrounds the P-type heavily doped region 204, thereby generating an additional current path, such as Figure 5 As shown in the C-C' cross-section diagram. Figure 4 The equivalent circuit of the B-B' section diagram and Figure 5 The equivalent circuit structure of the C-C' cross-section diagram is the same, the difference is that the current path in the BB' cross-section is roughly in the X direction, and the current flows through the equivalent on-resistance R along the X direction in the N-type well region 101 nw2 The potential difference is generated, so that the PN junction formed by the P-type heavily doped region 204 and the N-type well region 101 in the X direction is forward biased, which causes the parasitic PNP transistor Q formed by the P-type heavily doped region 204, the N-type well region 101 and the P-type well region 102 in the X direction to p2 The current path in the CC' section is roughly in the X→Y→X direction, and the current flows through the equivalent on-resistance R along the Y direction in the N-type well region 101. nw3The potential difference is generated, so that the PN junction formed by the P-type heavily doped region 204 and the N-type well region 101 in the Y direction is forward biased, which promotes the parasitic PNP transistor Q composed of the P-type heavily doped region 204, the N-type well region 101 and the P-type well region 102 in the X→Y→X direction. p3 Turn on. Therefore, compared with GGSCR, the additional parasitic PNP path introduced by this structure disperses the current, reduces the voltage drop caused by the resistance on the N-type well region 101, and makes it more difficult to forward bias the PN junction. Therefore, a larger voltage needs to be applied to make the PNP generate a larger current to maintain the SCR in the latched state; and this structure reduces the emitter junction injection efficiency of the PNP, so the maintenance voltage is increased. Second, the contact hole on the N-type heavily doped jumper region in this structure that is used to connect to the anode is farther away from the junction surface of the N-type well region 101 and the P-type well region 102 than the STI jumper region 207. Therefore, the STI jumper region 207 can appropriately increase the on-resistance for the GGNMOS path and the SCR path, such as Figure 4 , 5 As shown in the equivalent circuit, an equivalent resistor R is connected in series with the GGNMOS branch. ndp , thereby increasing the holding voltage. Third, the structure can adjust the area of the SCR path by adjusting the area of the STI crossover region 207. When the conductance modulation is completed, under the same current condition, the on-resistance of the SCR conduction path of the structure is increased relative to that of the GGSCR structure, so the holding voltage rises, which is equivalent to adjusting R ndp The holding voltage is changed by adjusting the resistance value.
[0017] The beneficial effects of the present invention are:
[0018] The P-type heavily doped region in the N-type well region is surrounded within the N-type heavily doped crossover region, thereby introducing an additional parasitic PNP path to disperse the current, reduce the voltage drop caused by the resistor on the N-type well region 101, and make the PN junction forward bias more difficult, so a larger voltage needs to be applied to make the PNP generate a larger current to maintain the SCR in the latched state; and this structure reduces the emitter junction injection efficiency of the PNP, so the holding voltage is increased. Secondly, the contact hole on the N-type heavily doped crossover region in this structure that is used to connect to the anode is farther away from the N-well P-well junction surface than the crossover STI, so the crossover STI region can appropriately increase the on-resistance for the GGNMOS path and the SCR path, thereby increasing the holding voltage. Finally, this structure adjusts the holding voltage of the device by adjusting the area of the P-type heavily doped region in the N-type well region and the area of the crossover STI region. In addition, without enlarging the size of the device to adjust the holding voltage, the specified protection window can be met while ensuring the device size and ESD robustness. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1This is the GGSCR layout.
[0020] Figure 2 for Figure 1 The cross-section diagram along A-A' in the layout and its equivalent circuit diagram.
[0021] Figure 3 This is the device layout of the present invention.
[0022] Figure 4 for Figure 3 The cross-section diagram along the B-B' line in the layout and its equivalent circuit diagram.
[0023] Figure 5 for Figure 3 The cross-section diagram along C-C' in the layout and its equivalent circuit diagram. DETAILED DESCRIPTION
[0024] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0025] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.
[0026] In addition, the descriptions of "first", "second", etc. in the present invention are only for descriptive purposes and cannot be understood as referring to or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include at least one of the features.
[0027] In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the fact that ordinary technicians in the field can implement it. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the present invention.
[0028] Example 1
[0029] This embodiment provides a high-maintaining voltage SCR device for ESD protection of integrated circuits. Taking a standard unit as an example, the device layout is as follows: Figure 3 As shown (the thick dotted frame in the device layout of the present invention is a standard unit).
[0030] The device described in Example 1 includes a P-type silicon substrate 100, on which adjacent N-type well region 101 and P-type well region 102 are formed;
[0031] An N-type heavily doped crossover region 103 is formed in the N-type well region 101 and the P-type well region 102, wherein a P-type heavily doped region 204 is also formed in the N-type well region 101, and the P-type heavily doped region 204 is surrounded by the N-type heavily doped region 103 and isolated by STI. An STI crossover region 207 is formed on the surface of the junction between the N-type well region 101 and the P-type well region 102, and the STI crossover region 207 is surrounded by the N-type heavily doped crossover region 103.
[0032] An N-type heavily doped region 105 and a P-type heavily doped region 106 are formed in the P-type well region 102, and the N-type heavily doped region 105 and the P-type heavily doped region 106 are isolated by STI; a thin oxide layer region 108 is set above the surface between the N-type heavily doped region 103 and the N-type heavily doped region 105 in the P-type well region 102, and an N-type heavily doped polysilicon region 109 is covered above the thin oxide layer region 108.
[0033] In this structure, the N-type heavily doped jumper region 103 and the P-type heavily doped region 204 in the N-type well region 101 are connected to the anode of the device, wherein the anode contact hole at the N-type heavily doped jumper region 103 is farther away from the junction between the N-type well region 101 and the P-type well region 102 than the STI jumper region 207; the N-type heavily doped polysilicon region 109, the N-type heavily doped region 105 and the P-type heavily doped region 106 on the P-type well region 102 side are connected to the cathode of the device.
[0034] When a positive pulse is applied to the anode of the structure, the drain-source PN junction of the NMOS tube M2 formed by the N-type heavily doped jumper region 103 and the P-type well region 102 is reverse biased. When the anode voltage is greater than the PN junction breakdown voltage, a large number of electron-hole pairs will be generated near the PN junction surface. The generated electrons flow to the anode through the N-type heavily doped jumper region 103, and at the same time, the holes flow to the cathode through the P-type well region 102 and the P-type heavily doped region 106. pw2 A voltage drop is generated on the P-type well region 102 and the N-type heavily doped region 105, causing the PN junction formed by the P-type well region 102 and the N-type heavily doped region 105 to be forward-conducted, and the parasitic NPN transistor Q composed of the N-type heavily doped jumper region 103, the P-type well region 102 and the N-type heavily doped region 105 is turned on. n4 The emitter junction is forward biased, the collector junction is reverse biased, the GGNMOS path is turned on, and the current will first discharge the charge through the GGNMOS path; when the current increases further, and the voltage across the SCR reaches the reverse breakdown voltage of the PN junction formed by the N-type well region 101 and the P-type well region 102, the PN junction breaks down, and the generated electrons will flow out of the anode along the N-type well region 101 and the N-type heavily doped jumper region 103, and the current flows through the well resistor R nw2 , Rnw3 When the voltage drop between the PN junction formed by the P-type heavily doped region 204 and the N-type well region 101 reaches 0.7V, the PN junction is forward-conducted, and the parasitic PNP transistor Q composed of the P-type heavily doped region 204, the N-type well region 101, and the P-type well region 102 is turned on. p2 , Q p3 Turn on; the generated holes will flow out of the cathode along the P-type well region 102 and the P-type heavily doped region 106, and the current will flow through the well resistor R pw2 When the voltage drop between the PN junction formed by the P-type well region 102 and the N-type heavily doped region 105 reaches 0.7V, the PN junction is forward-conducted, and the parasitic NPN transistor Q composed of the N-type well region 101, the P-type well region 102, and the N-type heavily doped region 105 is turned on. n3 The emitter junction is forward biased and the collector junction is reverse biased. Therefore, both parasitic bipolar transistors are turned on for positive feedback, forming an SCR current path to discharge the ESD current.
[0035] The N-type heavily doped crossover region 103 of the structure described in Example 1 surrounds the P-type heavily doped region 204, thereby generating an additional current path, such as Figure 5 As shown in the C-C' cross-section diagram, the current path in the C-C' cross-section is roughly in the X→Y→X direction, and the current flows through the equivalent on-resistance R along the Y direction. nw3 The potential difference is generated, so that the PN junction formed by the P-type heavily doped region 204 and the N-type well region 101 in the Y direction is forward biased, which promotes the parasitic PNP transistor Q composed of the P-type heavily doped region 04, the N-type well region 101 and the P-type well region 102 in the X→Y→X direction. p3 Turn on. Therefore, compared with GGSCR, the additional parasitic PNP path introduced by this structure disperses the current, reduces the voltage drop caused by the resistance on the N-type well region 101, and makes it more difficult to forward bias the PN junction. Therefore, a larger voltage needs to be applied to make the PNP generate a larger current to maintain the SCR in the latched state; and this structure reduces the emitter junction injection efficiency of the PNP, so the maintenance voltage is increased. Secondly, the contact hole on the N-type heavily doped jumper region in this structure that is used to connect to the anode is farther away from the junction of the N-type well region 101 and the P-type well region 102 than the STI jumper region 207. Therefore, the STI jumper region 207 can appropriately increase the on-resistance for the GGNMOS path and the SCR path, such as Figure 4 , 5 As shown in the equivalent circuit, an equivalent resistor R is connected in series with the GGNMOS branch. ndp , thereby increasing the holding voltage. Finally, the structure can adjust the area of the SCR path conductivity modulation by adjusting the area of the STI crossover region 207. When the conductivity modulation is completed, under the same current condition, the on-resistance of the SCR conduction path of the structure is increased relative to that of the GGSCR structure, so the holding voltage rises, which is equivalent to adjusting Rndp The holding voltage can be changed by adjusting the resistance value, so as to design the holding voltage of the device to meet different application requirements.
[0036] It can be seen that the present invention improves the holding voltage without changing the GGSCR trigger mechanism or increasing the size, and can maintain good robustness. The holding voltage can be changed by adjusting some key dimensions to meet a specific protection window, which is very beneficial for the compatible design of the chip.
[0037] The above examples are only used to illustrate the technical solutions of the present invention and are not intended to limit the present invention. Although the present invention has been described with reference to preferred examples, those skilled in the art should understand that any feature disclosed in this specification, unless otherwise specified, may be replaced by other alternative features that are equivalent or have similar purposes. All disclosed features, or steps in all methods or processes, except for mutually exclusive features and / or steps, may be combined in any manner without departing from the purpose and scope of the technical solutions of the present invention, and should all be included in the scope of the claims of the present invention.
Claims
1. A high holding voltage SCR device for ESD protection of integrated circuits, the device can be composed of n repeated units, for any one of the units, characterized in that: The device structure includes: a P-type silicon substrate, an N-type well region and a P-type well region are formed in the P-type silicon substrate, and the two well regions are adjacent; an N-type heavily doped crossover region is formed in the N-type well region and the P-type well region to cross the two well regions, a P-type heavily doped region is formed in the N-type well region, the P-type heavily doped region is surrounded by the N-type heavily doped crossover region, and the P-type heavily doped region and the N-type heavily doped crossover region are isolated by STI. An N-type heavily doped region and a P-type heavily doped region are formed in the P-type well region, the N-type heavily doped region and the P-type heavily doped region are successively away from the junction of the N-type well region and the P-type well region, and the N-type heavily doped region and the P-type heavily doped region in the P-type well region are isolated by STI; a thin oxide layer region is arranged above the surface between the N-type heavily doped crossover region and the N-type heavily doped region in the P-type well region, and the thin oxide layer region is covered with an N-type heavily doped polysilicon region. An STI bridging region is formed at the junction of the N-type well region and the P-type well region, and the STI bridging region is surrounded by the N-type heavily doped bridging region.
2. In this structure, the N-type heavily doped jumper region and the P-type heavily doped region in the N-type well region are connected to the anode of the device, and the contact hole at the N-type heavily doped jumper region is farther away from the junction between the N-type well region and the P-type well region than the STI jumper region; the P-type heavily doped region, the N-type heavily doped region in the P-type well region and the polysilicon region above the P-type well region are connected to the cathode of the device.