TBC battery and preparation method thereof

Abstract

The invention discloses a TBC battery and a preparation method thereof. The method comprises the following steps: providing an N-type silicon substrate; performing back surface texturing on the first region and the second region by adopting a texturing process to form a back surface textured structure; micro-polishing the surface of one side, deviating from the N-type silicon substrate, of the back suede structure to form a tower footing structure; preparing a first selective passivation contact layer and a first protection layer in the first region; preparing a second selective passivation contact layer and a second protection layer in the second region; performing front surface texturing on the front surface, and preparing a third protective layer on the front surface after the front surface texturing; and carrying out silk-screen printing and sintering on the first region and the second region to form a first electrode in contact with the first selective passivation contact layer on the surface of one side, deviating from the N-type silicon substrate, of the first protection layer and form a second electrode in contact with the second selective passivation contact layer on the surface of one side, deviating from the N-type silicon substrate, of the second protection layer, so as to prepare the TBC battery. By using the method, the filling factors of the passivation contact and the battery are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a TBC cell and a preparation method thereof. Background Art

[0002] Back junction back contact crystalline silicon cell (BC) refers to a type of solar cell in which the emitter electrode and base electrode of the cell are both located on the back of the cell. The P region and N region of the BC cell are both located on the back. After the electron-hole pairs generated by the incident photons separate, they need to pass through the entire thickness of the silicon substrate before reaching the back to be collected by the P region and N region respectively. Among them, the P region collects holes and the N region collects electrons. The TBC cell is undoubtedly the solar cell that has attracted much attention at present.

[0003] The existing method for preparing the P+ emitter of BC cells mainly adopts undoped all-aluminum back field and aluminum paste printing. However, this method will make the current transmission distance of the solar cell manufactured long, resulting in low current, poor metal-semiconductor contact performance, low fill factor, small number of photogenerated carriers generated, low cell opening voltage, and ultimately low conversion efficiency of TBC cells. Summary of the invention

[0004] The present invention provides a TBC battery and a preparation method thereof, so as to improve the passivation contact of the TBC battery, improve the fill factor and the opening voltage, and improve the conversion efficiency of the TBC battery by performing texturing and microstructure polishing on the back side of an N-type silicon substrate.

[0005] In a first aspect, the present invention provides a method for preparing a TBC battery, comprising:

[0006] An N-type silicon substrate is provided; the N-type silicon substrate comprises a front surface and a back surface, and the back surface comprises a first region and a second region alternately arranged in an interdigitated shape;

[0007] Using a texturing process, texturing the back sides of the first area and the second area to form a back side velvet structure;

[0008] Micro-polishing is performed on a surface of the back velvet structure on a side away from the N-type silicon substrate to form a tower base structure;

[0009] A first selective passivation contact layer and a first protective layer are prepared in a first region where a tower base structure is formed; a second selective passivation contact layer and a second protective layer are prepared in a second region where a tower base structure is formed;

[0010] Performing front texturing on the front surface, and preparing a third protective layer on the front surface after the front texturing;

[0011] The first region and the second region are screen printed and sintered to form a first electrode in contact with the first selective passivation contact layer on the surface of the first protective layer facing away from the N-type silicon substrate, and a second electrode in contact with the second selective passivation contact layer on the surface of the second protective layer facing away from the N-type silicon substrate, to produce a TBC battery.

[0012] Optionally, a texturing process is used to perform texturing on the back sides of the first area and the second area to form a back side suede structure, including:

[0013] Using a pre-cleaning process to pre-clean the first area and the second area;

[0014] Using a back-texturing process, back-texturing is performed on the first area and the second area after pre-cleaning;

[0015] A post-cleaning process is adopted to post-clean the first area and the second area after the back surface is textured, so as to form a back surface texture structure.

[0016] Optionally, the pre-cleaning process includes a first mixed solution formed by hydrochloric acid and hydrogen peroxide; the back texturing process includes a first alkaline solution prepared by sodium hydroxide or potassium hydroxide and a texturing additive in a first preset ratio; and the post-cleaning process includes a first acidic solution such as hydrofluoric acid or nitric acid.

[0017] Optionally, the concentration range of the first mixed solution is 0.2%-0.5%, the concentration range of the first alkaline solution is 0.4%-2%, the concentration range of the first acidic solution is 0.1%-0.3%, and / or the texturing process time is 50min-60min.

[0018] Optionally, micro-polishing is performed on a surface of the back velvet structure on a side away from the N-type silicon substrate to form a tower base structure, including:

[0019] A grooved groove body process is adopted to perform micro-polishing on the surface of the back velvet structure on the side away from the N-type silicon substrate to form a tower base structure.

[0020] Optionally, the trough process includes a second alkaline solution prepared by a first preset ratio of sodium hydroxide or potassium hydroxide and a texturing additive.

[0021] Optionally, the concentration range of the second alkaline solution is 1%-5%, the polishing temperature of the micro-polishing is 60° C.-70° C., and the polishing time is 150s-300s.

[0022] Optionally, screen printing and sintering are performed on the first region and the second region to form a first electrode in contact with the first selective passivation contact layer on a surface of the first protective layer facing away from the N-type silicon substrate, and a second electrode in contact with the second selective passivation contact layer is formed on a surface of the second protective layer facing away from the N-type silicon substrate, to prepare a TBC battery, comprising:

[0023] Performing screen silver paste printing and low-temperature sintering on the first region and the second region to form a battery cell;

[0024] The battery cell is subjected to laser-assisted sintering, and using the first sintering condition, a first electrode in contact with the first selective passivation contact layer is formed on the surface of the first protective layer on the side away from the N-type silicon substrate, and a second electrode in contact with the second selective passivation contact layer is formed on the surface of the second protective layer on the side away from the N-type silicon substrate, to produce a TBC battery.

[0025] Optionally, the first sintering condition is that the laser output voltage ranges from -5V to 12V, the marking speed is 10% to 100% of the laser rated marking speed, and the laser output power is 5% to 20% of the laser rated power.

[0026] Optionally, the first selective passivation contact layer includes a first tunneling oxide layer and a first doping layer; the second selective passivation contact layer includes a second tunneling oxide layer and a second doping layer;

[0027] The method comprises: preparing a first selective passivation contact layer and a first protective layer in a first region where a tower base structure is formed; and preparing a second selective passivation contact layer and a second protective layer in a second region where a tower base structure is formed, comprising:

[0028] Using a deposition process, a first tunneling oxide layer and a first intrinsic silicon layer are sequentially deposited on a surface of the tower base structure that is away from the N-type silicon substrate;

[0029] The N-type silicon substrate forming the first intrinsic silicon layer is doped with boron by a boron diffusion process to form a first doped layer, and a first mask layer is formed on the front surface and the surface of the first doped layer;

[0030] Removing the first mask layer, the first doping layer and the first tunneling oxide layer in the second region to expose the N-type silicon substrate in the second region;

[0031] Using a deposition process, sequentially depositing a second tunnel oxide layer and a second intrinsic silicon layer in the first region and the second region;

[0032] Using a phosphorus diffusion process, phosphorus is doped into the N-type silicon substrate forming the second intrinsic silicon layer to form a second doped layer, and a second mask layer is formed on the surface of the first doped layer on the front side and the second doped layer on the back side;

[0033] removing the second mask layer, the second doping layer and the second tunneling oxide layer in the first region;

[0034] A first passivation layer and a first anti-reflection layer are sequentially deposited on a surface of the first doped layer that is away from the N-type silicon substrate to form a first protective layer;

[0035] A second passivation layer and a second anti-reflection layer are sequentially deposited on a surface of the second doped layer that is away from the N-type silicon substrate to form a second protective layer.

[0036] Optionally, removing the first mask layer, the first doping layer, and the first tunneling oxide layer in the second region to expose the N-type silicon substrate in the second region includes:

[0037] The back surface is patterned by using laser technology to remove the first mask layer in the second area and retain the first mask layer in the first area;

[0038] Using an alkaline etching process to remove the first doping layer in the second region;

[0039] Using an acid etching process to remove the first tunneling oxide layer in the second region to expose the N-type silicon substrate;

[0040] Removing the second mask layer, the second doping layer and the second mask layer in the first region includes:

[0041] Using laser technology to remove the second mask layer in the first area;

[0042] Using an alkaline etching process to remove the second doping layer in the first region;

[0043] The second tunnel oxide layer in the first region is removed by an acid etching process.

[0044] Optionally, the front surface is subjected to texturing, and before the third protective layer is prepared on the front surface after the texturing, the method further includes:

[0045] The first mask layer and the second mask layer deposited on the front side are removed.

[0046] Optionally, after the front surface is textured and before the third protective layer is prepared on the front surface after the front surface is textured, the method further includes:

[0047] The first mask layer in the first region and the second mask layer in the second region are removed.

[0048] In a second aspect, the present invention provides a TBC battery, which is manufactured using the above-mentioned TBC battery manufacturing method.

[0049] The technical solution of the present invention provides an N-type silicon substrate; adopts a texturing process to perform back texturing on the first area and the second area to form a back velvet structure; performs micro-polishing on the surface of the back velvet structure that is away from the N-type silicon substrate to form a tower base structure; prepares a first selective passivation contact layer and a first protective layer in the first area where the tower base structure is formed; prepares a second selective passivation contact layer and a second protective layer in the second area where the tower base structure is formed; performs front texturing on the front side, and prepares a third protective layer on the front side after the front texturing; screen-prints and sinters the first area and the second area to form a first electrode in contact with the first selective passivation contact layer on the surface of the first protective layer that is away from the N-type silicon substrate, and a second electrode in contact with the second selective passivation contact layer on the surface of the second protective layer that is away from the N-type silicon substrate, to prepare a TBC battery. Using the above method, by performing texturing and micro-structure polishing on the back side of the N-type silicon substrate, the passivation contact of the TBC battery is improved, the filling factor and the opening voltage are improved, and the conversion efficiency of the TBC battery is thereby improved.

[0050] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0052] Figure 1 A flow chart of a method for preparing a TBC battery provided by an embodiment of the present invention;

[0053] Figure 2 A schematic structural diagram of a back velvet structure provided by an embodiment of the present invention;

[0054] Figure 3 A schematic structural diagram of a tower base structure provided by an embodiment of the present invention;

[0055] Figure 4 A schematic diagram of the structure of a TBC battery provided by an embodiment of the present invention;

[0056] Figure 5 A flow chart of a method for preparing a second TBC battery provided by an embodiment of the present invention;

[0057] Figure 6A flow chart of a method for preparing a third TBC battery provided by an embodiment of the present invention;

[0058] Figure 7 A flow chart of a fourth method for preparing a TBC battery provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0059] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0060] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, preparation method, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0061] In one embodiment, Figure 1 A flowchart of a method for preparing a TBC battery provided by an embodiment of the present invention, Figure 2 A schematic diagram of a back velvet structure provided by an embodiment of the present invention. Figure 3 A schematic structural diagram of a tower base structure provided by an embodiment of the present invention, Figure 4 The schematic diagram of the structure of a TBC battery provided by an embodiment of the present invention is applicable to the case where the passivation contact capability of the TBC is improved, thereby improving the opening voltage and conversion efficiency of the TBC battery, such as Figures 1 to 4 As shown, the method includes:

[0062] S110 , providing an N-type silicon substrate.

[0063] The N-type silicon substrate 1 includes a front side and a back side, and the back side includes a first region and a second region alternately arranged in an interdigitated manner. In this embodiment, the first region can be an n region or a p region, and correspondingly, the second region can be a p region or an n region.

[0064] S120, using a texturing process to texturize the back sides of the first area and the second area to form a back side velvet structure.

[0065] The texturing process is a method of performing texturing on the back side of the N-type silicon substrate 1 to form a “pyramid” shaped texturing structure on the back side.

[0066] Specifically, after providing an N-type silicon substrate 1 for preparing a TBC battery, it is necessary to perform back-texturing on the first and second regions on the back of the N-type silicon substrate 1. First, the surface of the N-type silicon substrate 1 needs to be cleaned to remove mechanical damage on the surface of the N-type silicon substrate 1 due to cutting, as well as organic matter and metal ions on the surface of the N-type silicon substrate 1. After cleaning, the first and second regions on the back of the N-type silicon substrate 1 are subjected to back-texturing under pre-configured alkaline solution conditions, so that a "pyramid"-shaped back-textured structure can be formed in the first and second regions. The microscopic image of the formed back-textured structure is shown in FIG. Figure 2 As shown, it can be seen that a large number of back velvet structures of different sizes are formed on the back. In addition, since the velvet making process will produce certain residues, the residues need to be cleaned after the velvet making is completed to ensure the neatness and flatness of the N-type silicon substrate 1.

[0067] S130, micro-polishing is performed on the surface of the back velvet structure on one side away from the N-type silicon substrate to form a tower base structure.

[0068] Among them, micro-polishing is a high-precision surface treatment technology, which reduces the surface roughness of the velvet structure on the back side of the N-type silicon substrate 1 through mechanical, chemical or electrochemical effects to obtain a bright and smooth surface. In this embodiment, micro-polishing is used to perform micro-structure polishing on the velvet structure on the back side to remove the spire structure of the velvet structure on the back side and form a tower base structure.

[0069] Specifically, after the back velvet structure is formed, since the number of "pyramids" in the back velvet structure is large and of different sizes, directly preparing a selective passivation contact layer on one side of the back velvet structure will cause the selective passivation contact layer to be uneven, which is not conducive to subsequent passivation contact, and thus reduces the conversion efficiency of the TBC battery. Therefore, it is necessary to micro-polish the rough back velvet structure so that the uneven state of the back velvet structure is polished to a flat state on the same plane to ensure the conversion efficiency of the TBC battery. In this embodiment, the back velvet structure is placed in a preset alkaline solution, and by setting conditions, the surface of one side of the back velvet structure that is away from the N-type silicon substrate 1 is micro-polished so that the back velvet structure is polished to form a tower base structure. The microscopic image of the formed tower base structure can be referred to. Figure 3 shown.

[0070] S140, preparing a first selective passivation contact layer and a first protective layer in the first area where the tower base structure is formed; and preparing a second selective passivation contact layer and a second protective layer in the second area where the tower base structure is formed.

[0071] Among them, the first selective passivation contact layer 2 and the second selective passivation contact layer 3 are both structures for improving the conversion efficiency of TBC cells. By forming a special structure on the surface of the TBC cell, it can provide a good surface passivation effect and realize the selective transmission of carriers. This structure usually includes an ultra-thin tunneling oxide layer and a highly doped polysilicon layer, which work together to achieve effective separation and transmission of carriers. The first protective layer 4 and the second protective layer 5 include a passivation layer and an anti-reflection layer, which are used to reduce the reflection of sunlight, increase the absorption of sunlight, and improve the conversion efficiency of the TBC cell. At the same time, it reduces surface recombination, increases the mobility of carriers, and improves the overall performance of the TBC cell.

[0072] Specifically, after forming the tower base structure, it is necessary to prepare a selective passivation contact layer and a protective layer on one side of the tower base structure, that is, prepare a first selective passivation contact layer 2 and a first protective layer 4 in the first area, and prepare a second selective passivation contact layer 3 and a second protective layer 5 in the second area, so as to provide a basis for the subsequent preparation of electrodes on the surface of the first selective passivation contact layer 2 and the second selective passivation contact layer 3 away from the N-type silicon substrate 1. The specific preparation method can be deposited by deposition process or the like, and can also be selectively prepared according to actual needs, and no specific restrictions are made here.

[0073] S150, performing front texturing on the front surface, and preparing a third protective layer on the front surface after the front texturing.

[0074] Among them, front texturing refers to the special treatment of the front surface of the N-type silicon substrate 1 during the production process of the TBC battery to form a rough, velvet-like structure. The third protective layer 8 includes a passivation layer and an anti-reflection layer, which are used to reduce the reflection of sunlight, increase light transmittance and light absorption; and reduce surface recombination, increase the mobility of carriers, and improve the conversion efficiency of the TBC battery.

[0075] Specifically, a texturing process is used to texturize the front surface of the N-type silicon substrate 1 to form a front velvet structure. After the front texturing is completed, a third protective layer 8 needs to be prepared on the front surface after the front texturing to reduce the surface reflection of the TBC battery, increase the surface area of ​​the TBC battery, and reduce the reflection of sunlight, thereby improving the light trapping effect of the battery and the absorption rate of sunlight, generating more photogenerated carriers, and improving the conversion efficiency of the TBC battery. The texturing process may include but is not limited to trough texturing and other processes, and the process for preparing the third protective layer includes but is not limited to low-pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition or physical vapor deposition, etc., which can be determined according to actual conditions and are not limited here.

[0076] In an optional embodiment, a trough texturing process is used to texturize the front surface in a preset alkaline solution to form a front velvet structure. The preset alkaline solution can be an alkaline solution formed by configuring a sodium hydroxide solution with a concentration of 0.5%-3% and a texturing additive in a preset ratio.

[0077] S160, screen printing and sintering the first area and the second area to form a first electrode in contact with the first selective passivation contact layer on the side surface of the first protective layer facing away from the N-type silicon substrate, and to form a second electrode in contact with the second selective passivation contact layer on the side surface of the second protective layer facing away from the N-type silicon substrate, to produce a TBC battery.

[0078] Among them, screen printing is one of the core processes in the manufacturing process of TBC battery cells, and is mainly used for electrode forming of TBC batteries. This process uses the basic principle that the mesh holes of the graphic part of the screen are transparent to the slurry, and the mesh holes of the non-graphic part are not transparent to the slurry for printing. During the printing process, the slurry is accurately squeezed onto the N-type silicon substrate 1 through the mesh holes of the screen to form the required electrode pattern. Generally, the slurry for screen printing can include but is not limited to silver paste. The pattern formed by screen printing includes metal grid lines. Sintering is used to process the electrode material screen-printed on the surface of the battery cell at a certain temperature so that the metal grid lines form a good ohmic contact with the N-type silicon substrate 1.

[0079] Specifically, after forming the first protective layer 4 and the second protective layer 5 on the back, it is necessary to form an electrode on the back so that the photogenerated carriers generated by the solar energy are converted into current and then flow to the external circuit. In this embodiment, the first area and the second area on the back are screen printed so that metal grid lines are formed on the surfaces of the first area and the second area. After the metal grid lines are formed, the formed metal grid lines need to be sintered to form a battery cell, wherein the sintering may include low-temperature sintering and high-temperature sintering, and the high-temperature sintering may include but is not limited to laser-assisted sintering, so that the sintered metal grid lines can contact the first selective passivation contact layer 2 and the second selective passivation contact layer 3 to form an ohmic contact. Specifically, after sintering, a first electrode 6 in contact with the first selective passivation contact layer 2 is formed in the first area, and a second electrode 7 in contact with the second selective passivation contact layer 3 is formed in the second area, thereby preparing a TBC battery. The polarities of the first electrode 6 and the second electrode 7 are opposite. When the first electrode 6 is a positive electrode, the corresponding second electrode 7 is a negative electrode; when the first electrode 6 is a negative electrode, the corresponding second electrode 7 is a positive electrode. In addition, when the first region is a p region, the second region is an n region, and the corresponding first electrode 6 formed in the p region is a positive electrode, and the second electrode 7 formed in the n region is a negative electrode. When the first region is an n region, the second region is a p region, and the corresponding first electrode 6 formed in the n region is a negative electrode, and the second electrode 7 formed in the p region is a positive electrode. The specific method can be determined according to the actual situation and is not limited here.

[0080] The technical solution of the embodiment of the present invention is to provide an N-type silicon substrate; use a texturing process to perform back texturing on the first area and the second area to form a back velvet structure; perform micro-polishing on the surface of the back velvet structure away from the N-type silicon substrate to form a tower base structure; prepare a first selective passivation contact layer and a first protective layer in the first area where the tower base structure is formed; prepare a second selective passivation contact layer and a second protective layer in the second area where the tower base structure is formed; perform front texturing on the front side, and prepare a third protective layer on the front side after the front texturing; screen print and sinter the first area and the second area to form a first electrode in contact with the first selective passivation contact layer on the surface of the first protective layer away from the N-type silicon substrate, and form a second electrode in contact with the second selective passivation contact layer on the surface of the second protective layer away from the N-type silicon substrate, so as to prepare a TBC battery. Using the above method, by performing texturing and micro-structure polishing on the back side of the N-type silicon substrate, the passivation contact of the TBC battery is improved, the filling factor and the opening voltage of the TBC battery are improved, and the conversion efficiency of the TBC battery is improved.

[0081] Figure 5This is a flow chart of a second method for preparing a TBC battery provided in an embodiment of the present invention. This embodiment refines the specific implementation method of S120 in the above embodiment, using a texturing process to perform back texturing on the first region and the second region to form a back velvet structure as follows:

[0082] Using a pre-cleaning process to pre-clean the first area and the second area;

[0083] Using a back-texturing process, back-texturing is performed on the first area and the second area after pre-cleaning;

[0084] A post-cleaning process is adopted to post-clean the first area and the second area after the back surface is textured, so as to form a back surface texture structure.

[0085] Furthermore, the specific implementation method of performing micro-polishing on the surface of the back velvet structure away from the N-type silicon substrate in S130 in the above embodiment to form the tower base structure is refined as follows:

[0086] A grooved groove body process is adopted to perform micro-polishing on the surface of the back velvet structure on the side away from the N-type silicon substrate to form a tower base structure.

[0087] For details not yet provided in this embodiment, please refer to the above embodiments, which will not be described in detail here.

[0088] like Figure 4 and Figure 5 As shown, the method includes:

[0089] S210 , providing an N-type silicon substrate.

[0090] S220, using a pre-cleaning process to pre-clean the first area and the second area.

[0091] Among them, pre-cleaning is a link in the TBC battery preparation process, the purpose of which is to remove the surface damage layer of the N-type silicon substrate 1 generated during the mechanical cutting process, oil stains and metal impurities on the surface of the N-type silicon substrate 1, etc., to provide a basis for the texturing process.

[0092] In this embodiment, the pre-cleaning solution in the pre-cleaning process is a first mixed solution formed by hydrochloric acid and hydrogen peroxide, and the concentration range of the first mixed solution is 0.2%-0.5%. Under this condition, the first area and the second area are pre-cleaned to remove the surface damage layer and metal impurities on the surface of the N-type silicon substrate 1.

[0093] S230, using a back surface texturing process to perform back surface texturing on the first area and the second area after pre-cleaning.

[0094] The back surface texturing process is a process for forming a texture structure similar to a "pyramid" shape on the back surface of the N-type silicon substrate 1 .

[0095] Specifically, after pre-cleaning the first area and the second area, the first area and the second area after pre-cleaning are subjected to back-texturing to form a back-textured structure to improve the light trapping effect of the battery. In this embodiment, the solution in the back-texturing process is a first alkaline solution prepared by sodium hydroxide or potassium hydroxide and a texturing additive according to a first preset ratio, and the concentration range of the prepared first alkaline solution is 0.4%-2%. Under this condition, the back-texturing of the first area and the second area is performed.

[0096] S240, using a post-cleaning process to post-clean the first area and the second area after the back surface is textured, so as to form a back surface texture structure.

[0097] Among them, the post-cleaning process is a process for cleaning the residues and organic matter generated after the velvet making is completed, so as to ensure the flatness and neatness of the velvet structure on the back.

[0098] Specifically, after the back surface is textured, the first area and the second area after the back surface is textured need to be cleaned to form a back surface texture structure. In this embodiment, a post-cleaning process is adopted, and the solution of the post-cleaning process includes a first acidic solution such as hydrofluoric acid or nitric acid, and the concentration range of the first acidic solution is 0.1%-0.3%. Under this condition, the first area and the second area are post-cleaned.

[0099] It should be noted that the total time for the texturing process of the first area and the second area, i.e., pre-cleaning, back texturing and post-cleaning, is 50-60 minutes, and the specific determination of the pre-cleaning time, back texturing time and post-cleaning time can be set according to actual conditions, and is not limited here. For example, the pre-cleaning and post-cleaning times can be the same, and the back texturing time is longer than the pre-cleaning and post-cleaning times.

[0100] S250, using a grooved groove body process, micro-polishing is performed on the surface of the back velvet structure that is away from the N-type silicon substrate to form a tower base structure.

[0101] The trough body is a reaction pool, and the reaction pool can contain a chemical solution so that the N-type silicon substrate 1 can be micro-polished under the action of the chemical solution.

[0102] Specifically, since the surface of the back velvet structure is rough, and there are a large number of them of different sizes, in order to ensure the uniformity of the subsequent deposition of the selective passivation contact layer, the back velvet structure needs to be micro-polished. In this embodiment, a trough-type tank process is adopted, and a second alkaline solution prepared by a first preset ratio of sodium hydroxide or potassium hydroxide and a velvet-making additive is added to the reaction tank of the trough-type tank, and the concentration range of the second alkaline solution is 1%-5%. Under the alkaline solution condition, the polishing temperature of the micro-polishing is set to 60°C-70°C, and the polishing time is 150s-300s, and finally the preparation of the tower base structure is completed, which is helpful for the subsequent passivation contact and improves the filling factor of the TBC battery.

[0103] S260, preparing a first selective passivation contact layer and a first protective layer in the first area where the tower base structure is formed; preparing a second selective passivation contact layer and a second protective layer in the second area where the tower base structure is formed.

[0104] S270, performing front texturing on the front surface, and preparing a third protective layer on the front surface after the front texturing.

[0105] S280, screen printing and sintering the first area and the second area to form a first electrode in contact with the first selective passivation contact layer on the side surface of the first protective layer away from the N-type silicon substrate, and to form a second electrode in contact with the second selective passivation contact layer on the side surface of the second protective layer away from the N-type silicon substrate, to produce a TBC battery.

[0106] The technical solution of the embodiment of the present invention adopts a pre-cleaning process to pre-clean the first area and the second area; adopts a back surface texturing process to texturize the first area and the second area after the pre-cleaning; adopts a post-cleaning process to post-clean the first area and the second area after the back surface texturing to form a back surface texture structure. A grooved groove body process is adopted to micro-polish the surface of the back surface texture structure away from the N-type silicon substrate to form a tower base structure. The above method improves the passivation contact, improves the filling factor and the opening voltage of the TBC battery, and thus improves the conversion efficiency of the TBC battery.

[0107] Figure 6 A flowchart of a third method for preparing a TBC battery provided in an embodiment of the present invention. In this embodiment, the first region and the second region are screen printed and sintered in the above embodiment S160 to form a first electrode in contact with the first selective passivation contact layer on a surface of the first protective layer facing away from the N-type silicon substrate, and a second electrode in contact with the second selective passivation contact layer on a surface of the second protective layer facing away from the N-type silicon substrate. The specific implementation method of preparing the TBC battery is refined as follows:

[0108] Performing screen silver paste printing and low-temperature sintering on the first region and the second region to form a battery cell;

[0109] The battery cell is subjected to laser-assisted sintering, and using the first sintering condition, a first electrode in contact with the first selective passivation contact layer is formed on the surface of the first protective layer on the side away from the N-type silicon substrate, and a second electrode in contact with the second selective passivation contact layer is formed on the surface of the second protective layer on the side away from the N-type silicon substrate, to produce a TBC battery.

[0110] For details not yet provided in this embodiment, please refer to the above embodiments, which will not be described in detail here.

[0111] refer to Figure 4 and Figure 6 As shown, the method includes:

[0112] S310 , providing an N-type silicon substrate.

[0113] S320, using a texturing process to perform texturing on the back sides of the first area and the second area to form a back side velvet structure.

[0114] S330, micro-polishing is performed on the surface of the back velvet structure on one side away from the N-type silicon substrate to form a tower base structure.

[0115] S340, preparing a first selective passivation contact layer and a first protective layer in the first area where the tower base structure is formed; preparing a second selective passivation contact layer and a second protective layer in the second area where the tower base structure is formed.

[0116] S350, performing front texturing on the front surface, and preparing a third protective layer on the front surface after the front texturing.

[0117] S360, performing screen silver paste printing and low-temperature sintering on the first region and the second region to form a battery cell.

[0118] Specifically, after forming a first protective layer 4 in the first area on the back and forming a second protective layer 5 in the second area, electrodes need to be prepared in the first area and the second area. First, screen silver paste is printed on the first area and the second area to form metal grid lines in the first area and the second area. After the metal grid lines are formed, the metal grid lines are subjected to low-temperature sintering to form a battery cell. The temperature of the low-temperature sintering may be 20° to 40° lower than the conventional sintering temperature. After low-temperature sintering, the metal grid lines can enter the first protective layer 4 and the second protective layer 5, but due to the low temperature, the corrosion is weak and no ohmic contact is formed with the selective passivation contact layer.

[0119] S370, laser-assisted sintering is performed on the battery cell, and using the first sintering condition, a first electrode in contact with the first selective passivation contact layer is formed on the surface of the first protective layer on the side away from the N-type silicon substrate, and a second electrode in contact with the second selective passivation contact layer is formed on the surface of the second protective layer on the side away from the N-type silicon substrate, to produce a TBC battery.

[0120] Optionally, the first sintering condition is that the laser output voltage ranges from -5V to 12V, the marking speed is 10% to 100% of the laser rated marking speed, and the laser output power is 5% to 20% of the laser rated power.

[0121] The laser-assisted sintering is used to promote the mutual diffusion between the silver metal grid line and the N-type silicon substrate 1 through the local current generated by laser irradiation, so as to form a good ohmic contact and form the first electrode and the second electrode.

[0122] Specifically, because the low-temperature sintering is weak in corrosiveness, the selective passivation contact layer cannot contact the metal grid line to form an electrode. Therefore, it is also necessary to perform laser-assisted sintering under high-temperature conditions on the cell after low-temperature sintering. Specifically, the first sintering condition can be set to irradiate the cell with a laser, and apply a certain magnitude of reverse voltage to the cell, such as a reverse voltage of -5V to 12V, so that a large number of carriers are generated inside the cell. The reverse voltage causes the carriers to move in a directional manner, thereby generating a large current. The current will form a breakdown in the area where the cell series resistance is low, and instantaneously generate a high temperature in a local area, so that the metal grid line contacts the first selective passivation contact layer 2 to form a first electrode 6, and the metal grid line contacts the second selective passivation contact layer 3 to form a second electrode 7, so that a TBC cell is prepared. This method can significantly reduce the contact resistance of the TBC cell, improve the contact quality between the metal grid line and the N-type silicon substrate 1, and improve the conversion efficiency of the TBC cell.

[0123] The technical solution of the embodiment of the present invention is to form a battery cell by screen printing silver paste and low-temperature sintering the first area and the second area; laser-assisted sintering is performed on the battery cell, and a first electrode in contact with the first selective passivation contact layer is formed on the surface of the first protective layer away from the N-type silicon substrate, and a second electrode in contact with the second selective passivation contact layer is formed on the surface of the second protective layer away from the N-type silicon substrate, using the first sintering condition, to obtain a TBC battery. The above method significantly reduces the contact resistance of the TBC battery, improves the contact quality between the metal grid line and the N-type silicon substrate, and improves the conversion efficiency of the TBC battery.

[0124] Figure 7 A flowchart of a fourth method for preparing a TBC battery provided in an embodiment of the present invention, referring to Figure 4 and Figure 7As shown, the contents not yet fully described in this embodiment can be referred to the above embodiments, and will not be repeated here. The preparation method comprises:

[0125] S410 , providing an N-type silicon substrate.

[0126] S411, using a texturing process to texturize the back sides of the first area and the second area to form a back side velvet structure.

[0127] S412, micro-polishing is performed on the surface of the back velvet structure on one side away from the N-type silicon substrate to form a tower base structure.

[0128] S413, using a deposition process, sequentially depositing a first tunneling oxide layer and a first intrinsic silicon layer on a surface of the tower base structure that is away from the N-type silicon substrate.

[0129] Among them, the deposition process includes low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) or physical vapor deposition (PVD), etc., which can be determined according to the specific situation and are not limited here. Among them, LPCVD is used to use chemical reactions at a relatively low pressure to induce chemical reactions between the precursor gas and the surface of the N-type silicon substrate 1 by heat, thereby forming a solid film on the N-type silicon substrate 1. PECVD is used to generate a glow discharge on the cathode of the process chamber using low-temperature plasma under low pressure. Through this process, the N-type silicon substrate 1 is heated to a predetermined temperature, and then an appropriate amount of gas is introduced. These gases undergo a series of chemical reactions and plasma reactions, and finally form a solid film on the surface of the N-type silicon substrate 1. PVD is a technology that uses physical methods under vacuum conditions to vaporize the surface of solid or liquid materials into gaseous atoms, molecules or partially ionize them into ions, and deposits a thin film with some special functions on the surface of the N-type silicon substrate 1 through a low-pressure gas (or plasma) process. The first tunneling oxide layer 21 is used to allow the majority carriers (electrons) to pass smoothly through the tunneling effect, while preventing the recombination of minority carriers (holes) to achieve selective collection of carriers, reduce surface recombination, and increase the open circuit voltage (Voc) and fill factor (FF) of the battery, thereby improving the photoelectric conversion efficiency of the TBC battery. The first intrinsic silicon layer is a silicon material layer with intrinsic semiconductor properties. Intrinsic semiconductors refer to semiconductor materials that have neither donor impurities (n-type dopants) nor acceptor impurities (p-type dopants), and their conductivity mainly depends on the generation and recombination of electron-hole pairs in the material itself.

[0130] Specifically, by using a deposition process, such as a low-pressure chemical vapor deposition process, by introducing a flow rate of 10L-30L of oxygen into the reaction chamber of the deposition process, an ultra-thin first tunneling oxide layer 21 can be deposited on the surface of the side of the tower base structure away from the N-type silicon substrate 1, and the thickness of the formed first tunneling oxide layer 21 is 1nm-2nm. After the first tunneling oxide layer 21 is formed, silane with a flow rate of 100sccm-400sccm is passed into the reaction chamber of the deposition process, and the deposition temperature is set to 550℃-600℃, so that a first intrinsic silicon layer is deposited on the surface of the side of the first tunneling oxide layer 21 away from the N-type silicon substrate 1, and the thickness of the first intrinsic silicon layer is 150nm-200nm.

[0131] S414, using a boron diffusion process to perform boron doping on the N-type silicon substrate forming the first intrinsic silicon layer to form a first doping layer, and forming a first mask layer on the front side and the surface of the first doping layer.

[0132] The boron diffusion process is a doping technology used to introduce boron atoms into the first intrinsic silicon layer to form a P-type doped region. The first doped layer 22 is a boron doped layer, which is a special semiconductor layer with a high doping concentration formed by doping boron elements. The first selective passivation contact layer 2 includes a first tunneling oxide layer 21 and a first doped layer 22.

[0133] Specifically, under normal circumstances, the process of diffusing boron into the first intrinsic silicon layer includes three steps, namely low-temperature deposition, high-temperature advancement and post-oxidation. Boron trichloride and oxygen are introduced into the reaction chamber of the low-temperature deposition process, wherein the flow rate of boron trichloride is 100sccm-300sccm, the content ratio of the introduced boron trichloride and oxygen is between 1:2-1:5, the deposition temperature is controlled between 800℃-900℃, and the low-temperature deposition time is less than 50 minutes. Under this deposition condition, the chemical reaction between boron trichloride, oxygen and the first intrinsic silicon layer is utilized to eventually deposit a layer of boron on the surface of the first intrinsic silicon layer away from the N-type silicon substrate 1. After the boron is deposited, the boron is advanced at high temperature, and the high-temperature advancement condition is set to a advancement temperature between 900℃-1000℃. This condition is used to dope boron into the first intrinsic silicon layer to form a first doping layer 22. The concentration of the formed first doping layer 22 is 1e18cm -3 -1e19cm -3After high-temperature doping to form the first doping layer 22, boron usually does not react completely to enter the first intrinsic silicon layer during the doping process, but generates certain residual organic matter during the reaction process. In order to prevent the residual organic matter from affecting the first doping layer 22, the generated residual organic matter can be post-oxidized by introducing oxygen with a flow rate of 5000sccm-20000sccm into the post-oxidation reaction chamber, and the post-oxidation time is controlled within 60 minutes, so that the residual organic matter reacts with oxygen to form a first mask layer. Usually, the first mask layer is a borosilicate glass layer, and the thickness of the formed borosilicate glass layer is between 40nm and 100nm.

[0134] It is understandable that the equipment for the boron diffusion process includes but is not limited to a boron diffusion furnace. When boron diffusion is performed in the equipment, double-sided diffusion is usually performed, or the N-type silicon substrate 1 is subjected to boron diffusion in a double-insertion manner. In this process, it cannot be guaranteed that the borosilicate glass layer produced by post-oxidation is only formed on the back side of the N-type silicon substrate 1. In the actual production process, the borosilicate glass layer will also be generated on the front side at the same time.

[0135] S415 , removing the first mask layer, the first doping layer, and the first tunneling oxide layer in the second region to expose the N-type silicon substrate in the second region.

[0136] Among them, this step can be refined as follows: using laser technology to pattern the back side to remove the first mask layer in the second area and retain the first mask layer in the first area; using an alkaline etching process to remove the first doping layer 22 in the second area; using an acid etching process to remove the first tunneling oxide layer 21 in the second area to expose the N-type silicon substrate 1.

[0137] Among them, the laser technology is a process of using a laser to remove the first mask layer of the second area on the back side according to a preset pattern. The alkaline etching process is a process of using a configured alkaline solution to chemically react with the first doping layer 22 to remove the first doping layer 22. The acid etching process, i.e., chain acid etching, is a wet etching technology widely used in the field of solar cell manufacturing, which mainly involves using a configured acidic solution to chemically treat the surface of the silicon wafer to achieve the purpose of removing a specific material layer or forming a specific structure.

[0138] Specifically, since the first tunneling oxide layer 21 and the first doping layer 22 are formed by full-surface deposition and diffusion on the back side, and the back side of the TBC battery needs to be provided with two interdigitated first and second regions for generating electrodes, it is necessary to remove the first mask layer, the first doping layer 22 and the first tunneling oxide layer 21 formed in the second region. In this embodiment, the output power of the laser is set to 15W-100W, and the laser speed is set to 3000mm / s-60000mm / s. The laser emitted under this condition is used to pattern the back side of the N-type silicon substrate 1, and the first mask layer in the second region is removed, and the first doping layer 22 in the second region is exposed. Secondly, an alkaline solution such as sodium hydroxide or potassium hydroxide with a concentration of 3%-15% is introduced into the reaction chamber of the alkaline etching process, and an etching additive is added so that the alkaline solution and the etching additive are configured in a first preset ratio. The configured alkaline solution is used, and under the etching conditions of an etching temperature of 60°C-90°C and an etching time of 150s-500s, the first doping layer 22 of the second region is removed by a chemical reaction between the alkaline solution and the first doping layer 22, thereby exposing the first tunneling oxide layer 21 of the second region. After removing the first doping layer 22, an acid etching process is used, and an acidic solution such as hydrofluoric acid is set, and the concentration of the hydrofluoric acid is set within a certain range, such as 5%-30%. The hydrofluoric acid will react chemically with the first tunneling oxide layer 21, and the first tunneling oxide layer 21 of the second region is removed, thereby exposing the N-type silicon substrate 1 of the second region.

[0139] S416 , using a deposition process, sequentially depositing a second tunnel oxide layer and a second intrinsic silicon layer in the first region and the second region.

[0140] The second tunnel oxide layer 31 has the same meaning as the first tunnel oxide layer 21 , and the second intrinsic silicon layer has the same meaning as the first intrinsic silicon layer, which can be referred to the above description and will not be described again.

[0141] Specifically, after the first selective passivation contact layer 2 and the first mask layer in the second region are removed, a deposition process can be used to pass oxygen with a flow rate of 10L-30L into the reaction chamber of the deposition process, so that a second tunneling oxide layer 31 with a thickness of 1nm-2nm can be deposited in the first region and the second region on the back side of the N-type silicon substrate 1. After the second tunneling oxide layer 31 is formed, silane with a flow rate of 100sccm-400sccm is passed into the reaction chamber of the deposition process, and the deposition temperature is set to 550°C-600°C, so that a second intrinsic silicon layer with a thickness of 100nm-200nm can be deposited on the surface of the second tunneling oxide layer 31 away from the N-type silicon substrate 1.

[0142] S417, using a phosphorus diffusion process, phosphorus-doping the N-type silicon substrate forming the second intrinsic silicon layer to form a second doped layer, and forming a second mask layer on the surface of the first doped layer on the front side and the second doped layer on the back side.

[0143] Among them, the phosphorus diffusion process is a process for forming an N-type region on an N-type silicon substrate 1 to form a PN junction. The PN junction is responsible for separating photogenerated carriers (electron-hole pairs) to achieve photoelectric conversion. The second doped layer 32 is a phosphorus doped layer, which is a special semiconductor layer with a high doping concentration formed by doping phosphorus elements. The second selective passivation contact layer 3 includes a second tunneling oxide layer 31 and a second doped layer 32.

[0144] Specifically, similar to the formation process of the first doping layer 22, the phosphorus diffusion of the second intrinsic silicon layer also includes three steps: low-temperature deposition, high-temperature advancement and post-oxidation. Nitrogen and oxygen are introduced into the reaction chamber of the low-temperature deposition process, and the content ratio of nitrogen and oxygen is between 1:2-1:7. Phosphorus oxychloride is doped in the nitrogen, and phosphorus oxychloride is the doping source of the phosphorus doping process. Under the conditions of a deposition temperature of 850°C-900°C and a deposition time of less than 50 minutes, a layer of phosphorus can be deposited on the surface of the second intrinsic silicon layer away from the N-type silicon substrate 1 by utilizing the chemical reaction between phosphorus oxychloride and oxygen. After the phosphorus is formed, the phosphorus is advanced at high temperature. Under the condition that the advancement temperature of the high-temperature advancement is 850°C-950°C, phosphorus is doped into the second intrinsic silicon layer to form a second doping layer 32. The concentration of the second doping layer 32 is 3e20cm -3 -7e20cm -3 After the second doping layer 32 is formed, the residual organic matter generated during the doping process is post-oxidized. In this embodiment, oxygen with a flow rate of 5000sccm-20000sccm is introduced into the post-oxidation reaction chamber. Under the condition of an oxidation temperature of 700°C-850°C, the oxidation time is controlled within 60 minutes, so that the residual organic matter reacts with oxygen to form a second mask layer. Usually, the second mask layer is a phosphosilicate glass layer, and the thickness of the formed phosphosilicate glass layer is between 40nm and 80nm.

[0145] It is understandable that the equipment for the phosphorus diffusion process includes but is not limited to a phosphorus diffusion furnace. When phosphorus diffusion is performed in the equipment, double-sided diffusion is usually performed, or the N-type silicon substrate 1 is phosphorus diffused in a double-insertion manner. In this process, it cannot be guaranteed that the phosphosilicate glass layer produced by post-oxidation is only formed on the back side of the N-type silicon substrate 1. In the actual production process, the phosphosilicate glass layer will also be generated on the front side at the same time.

[0146] S418, removing the second mask layer, the second doping layer, and the second tunneling oxide layer in the first region.

[0147] This step can be refined as follows: using laser technology to remove the second mask layer in the first region; using alkaline etching to remove the second doping layer 32 in the first region; and using acid etching to remove the second tunneling oxide layer 31 in the first region.

[0148] Specifically, the second tunneling oxide layer 31, the second doping layer 32 and the second mask layer are all deposited on the entire surface, that is, the above three-layer structure is also deposited in the first region. At this time, the second tunneling oxide layer 31, the second doping layer 32 and the second mask layer in the first region need to be removed. In this embodiment, the output power of the laser is set to 15W-55W, and the laser speed is 3000mm / s-50000mm / s. The laser emitted under this condition is used to etch and remove the second mask layer in the first region to expose the second doping layer 32 in the first region. Then, an alkali etching process is used to introduce an alkali solution such as sodium hydroxide or potassium hydroxide with a concentration of 0.5%-3% into the reaction chamber of the alkali etching process, and an etching additive is added so that the alkali solution and the etching additive are configured in a second preset ratio. Under this etching condition, the second doping layer 32 in the first region is removed by a chemical reaction between the alkali solution and the second doping layer 32, and the second tunneling oxide layer 31 in the first region is exposed. After removing the second doping layer 32, an acid etching process is used to set an acid solution such as hydrofluoric acid, and set the concentration of hydrofluoric acid to a certain range, such as 5%-30%. The hydrofluoric acid will chemically react with the second tunneling oxide layer 31 to remove the second tunneling oxide layer 31 in the first area.

[0149] It should be noted that in order to prevent a short circuit between the first region and the second region, when the second tunneling oxide layer 31, the second doping layer 32 and the second mask layer of the first region are etched and removed, the position where the first region and the second region are connected will also be removed synchronously, so that there is a preset spacing distance between the first region and the second region to ensure the performance of the TBC battery.

[0150] S419, removing the first mask layer and the second mask layer deposited on the front side.

[0151] Specifically, before texturing the front side, it is necessary to remove the first mask layer and the second mask layer generated on the front side in the boron diffusion process and the phosphorus diffusion process. Specifically, the removal can be performed by etching using an acidic solution formed by configuring a third preset ratio of 1%-30% hydrofluoric acid, 10%-30% nitric acid and 1%-20% sulfuric acid to expose the front side of the N-type silicon substrate 1.

[0152] S420, performing front texturing on the front surface, removing the first mask layer in the first area and the second mask layer in the second area, and preparing a third protective layer on the front surface after the front texturing.

[0153] Specifically, after removing the first mask layer and the second mask layer on the front side, the front side needs to be textured, which can be performed using a texture making process under preset texture making conditions, which can be specifically set according to actual conditions and is not limited here. After the texture making is completed, the first mask layer in the first area and the second mask layer in the second area need to be etched and removed, which can also be performed using an acidic solution such as hydrofluoric acid that has been preset. The process steps for removing the first mask layer in the first area and the second mask layer in the second area are arranged after the process of texture making on the front side, in order not to affect the first doping layer 22 and the second doping layer 32 on the back side during the texture making process on the front side, and the first mask layer and the second mask layer play a protective role to ensure the performance of the TBC battery.

[0154] After the first mask layer in the first area and the second mask layer in the second area are removed, a third protective layer 8 needs to be prepared on the front side. The third protective layer 8 includes a third passivation layer and a third anti-reflection layer. Specifically, the third passivation layer can be deposited on the front side using an atomic layer deposition process. The third passivation layer includes but is not limited to an aluminum oxide layer. The thickness of the formed third passivation layer is 3nm-10nm. After the third passivation layer is formed, a deposition process such as plasma enhanced chemical vapor deposition can be used on the surface of the third passivation layer away from the N-type silicon substrate 1 to form a third anti-reflection layer. The third anti-reflection layer includes but is not limited to a silicon nitride layer, or a stack of silicon nitride and silicon oxide, or a silicon oxynitride layer. The thickness of the formed third anti-reflection layer is 50nm-120nm, thereby forming a third protective layer 8.

[0155] S421 , depositing a first passivation layer and a first anti-reflection layer in sequence on a surface of the first doped layer facing away from the N-type silicon substrate to form a first protective layer.

[0156] S422, depositing a second passivation layer and a second anti-reflection layer in sequence on a surface of the second doped layer facing away from the N-type silicon substrate to form a second protective layer.

[0157] Among them, the first passivation layer, the second passivation layer and the third passivation layer are used to effectively inhibit the recombination of electrons and holes, reduce surface defects, and improve the conversion rate and surface quality of the battery. The first anti-reflection layer, the second anti-reflection layer and the third anti-reflection layer are used to reduce the reflection of incident sunlight, increase the absorption of sunlight intensity, and improve the conversion efficiency of the battery.

[0158] Specifically, since the first doping layer 22 and the second doping layer 32 are both located on the back side of the N-type silicon substrate 1, in order to ensure the deposition effect, the entire surface deposition can usually be performed on the back side, so the first protective layer 4 is equivalent to the second protective layer 5, that is, the first passivation layer is equivalent to the second passivation layer, and the first anti-reflection layer is equivalent to the second anti-reflection layer. In this embodiment, an atomic layer deposition process is used to deposit a passivation layer, that is, a first passivation layer or a second passivation layer, on the surface of the first doping layer 22 and the second doping layer 32 on the back side, and the thickness of the passivation layer is 3nm-10nm. Then, a deposition process such as plasma enhanced chemical vapor deposition is used to deposit an anti-reflection layer, that is, a first anti-reflection layer or a second anti-reflection layer, on the surface of the side of the passivation layer away from the N-type silicon substrate 1 to form a protective layer, and the thickness of the protective layer is 50nm-120nm.

[0159] It should be noted that, generally, in the process of preparing the passivation layer on the front and back sides, an atomic layer deposition process is usually used to deposit the passivation layer on the front and back sides at the same time, so as to reduce the process flow and shorten the preparation time. In addition, the process steps for preparing the anti-reflection layer on the front and back sides can be interchanged according to actual conditions, and are not limited here.

[0160] S423, screen printing and sintering the first area and the second area to form a first electrode in contact with the first selective passivation contact layer on the surface of the first protective layer facing away from the N-type silicon substrate, and to form a second electrode in contact with the second selective passivation contact layer on the surface of the second protective layer facing away from the N-type silicon substrate, to obtain a TBC battery.

[0161] The technical solution of the embodiment of the present invention realizes the preparation of TBC batteries, effectively suppresses the recombination of electrons and holes, reduces surface defects, improves the opening voltage and filling factor of TBC batteries, and thus improves the conversion rate and surface quality of TBC batteries.

[0162] Based on the same inventive concept, an embodiment of the present invention further provides a TBC battery, which is manufactured using the above-mentioned TBC battery preparation method and has functional modules and beneficial effects corresponding to the execution method.

[0163] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0164] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for preparing a TBC battery, characterized in that: include: Providing an N-type silicon substrate; The N-type silicon substrate comprises a front side and a back side, wherein the back side comprises a first region and a second region alternately arranged in an interdigitated shape; Using a texturing process, texturing the back sides of the first area and the second area to form the back side suede structure; Micro-polishing is performed on a surface of the back velvet structure that is away from the N-type silicon substrate to form a tower base structure; Prepare a first selective passivation contact layer and a first protective layer in the first region where the tower base structure is formed; Preparing a second selective passivation contact layer and a second protective layer in the second region where the tower base structure is formed; Performing front surface texturing on the front surface, and preparing a third protective layer on the front surface after the front surface texturing; The first region and the second region are screen printed and sintered to form a first electrode in contact with the first selective passivation contact layer on a surface of the first protective layer facing away from the N-type silicon substrate, and a second electrode in contact with the second selective passivation contact layer is formed on a surface of the second protective layer facing away from the N-type silicon substrate, to obtain the TBC battery.

2. The preparation method according to claim 1, characterized in that: The back side of the first area and the second area is subjected to back-texturing by a texturing process to form the back side suede structure, including: Using a pre-cleaning process to pre-clean the first area and the second area; Using a back-texturing process, performing back-texturing on the first area and the second area after pre-cleaning; A post-cleaning process is adopted to post-clean the first area and the second area after the back surface is textured, so as to form the back surface texture structure.

3. The preparation method according to claim 2, characterized in that: The pre-cleaning process includes a first mixed solution formed by hydrochloric acid and hydrogen peroxide; the back texturing process includes a first alkaline solution prepared by sodium hydroxide or potassium hydroxide and a texturing additive in a first preset ratio; the post-cleaning process includes a first acidic solution such as hydrofluoric acid or nitric acid.

4. The preparation method according to claim 3, characterized in that: The concentration range of the first mixed solution is 0.2%-0.5%, the concentration range of the first alkaline solution is 0.4%-2%, the concentration range of the first acidic solution is 0.1%-0.3%, and / or the time of the texturing process is 50min-60min.

5. The preparation method according to claim 1, characterized in that: Micro-polishing is performed on a surface of the back velvet structure that is away from the N-type silicon substrate to form a tower base structure, including: A grooved groove body process is adopted to perform micro-polishing on a surface of the back velvet structure on a side away from the N-type silicon substrate to form the tower base structure.

6. The preparation method according to claim 5, characterized in that: The trough-type tank process includes a second alkaline solution prepared by sodium hydroxide or potassium hydroxide and a texturing additive in a first preset ratio.

7. The preparation method according to claim 6, characterized in that: The concentration range of the second alkaline solution is 1%-5%, the polishing temperature of the micro-polishing is 60° C.-70° C., and the polishing time is 150s-300s.

8. The preparation method according to claim 1, characterized in that: The first region and the second region are screen-printed and sintered to form a first electrode in contact with the first selective passivation contact layer on a surface of the first protective layer facing away from the N-type silicon substrate, and a second electrode in contact with the second selective passivation contact layer on a surface of the second protective layer facing away from the N-type silicon substrate, to obtain the TBC battery, comprising: Performing screen silver paste printing and low-temperature sintering on the first region and the second region to form a battery cell; The cell is subjected to laser-assisted sintering, and using a first sintering condition, a first electrode in contact with the first selective passivation contact layer is formed on a surface of the first protective layer facing away from the N-type silicon substrate, and a second electrode in contact with the second selective passivation contact layer is formed on a surface of the second protective layer facing away from the N-type silicon substrate, to obtain the TBC cell.

9. The preparation method according to claim 8, characterized in that: The first sintering condition is that the laser output voltage ranges from -5V to 12V, the marking speed is 10% to 100% of the laser rated marking speed, and the laser output power is 5% to 20% of the laser rated power.

10. The preparation method according to claim 1, characterized in that: The first selective passivation contact layer includes a first tunneling oxide layer and a first doping layer; the second selective passivation contact layer includes a second tunneling oxide layer and a second doping layer; Prepare a first selective passivation contact layer and a first protective layer in the first region where the tower base structure is formed; Preparing a second selective passivation contact layer and a second protective layer in the second region where the tower base structure is formed, comprising: Using a deposition process, sequentially depositing the first tunneling oxide layer and the first intrinsic silicon layer on a surface of the tower base structure facing away from the N-type silicon substrate; Using a boron diffusion process, boron-doping the N-type silicon substrate forming the first intrinsic silicon layer to form the first doping layer, and forming a first mask layer on the front surface and the surface of the first doping layer; removing the first mask layer, the first doping layer and the first tunneling oxide layer in the second region to expose the N-type silicon substrate in the second region; Adopting the deposition process, sequentially depositing the second tunneling oxide layer and the second intrinsic silicon layer in the first region and the second region; Using a phosphorus diffusion process, phosphorus-doping the N-type silicon substrate forming the second intrinsic silicon layer to form the second doped layer, and forming a second mask layer on the surface of the first doped layer on the front side and the second doped layer on the back side; removing the second mask layer, the second doping layer and the second tunneling oxide layer in the first region; Depositing a first passivation layer and a first anti-reflection layer in sequence on a surface of the first doped layer facing away from the N-type silicon substrate to form the first protective layer; A second passivation layer and a second anti-reflection layer are sequentially deposited on a surface of the second doped layer that is away from the N-type silicon substrate to form the second protective layer.

11. The preparation method according to claim 10, characterized in that: Removing the first mask layer, the first doping layer, and the first tunneling oxide layer in the second region to expose the N-type silicon substrate in the second region includes: patterning the back surface by using laser technology to remove the first mask layer in the second area and retain the first mask layer in the first area; Using an alkaline etching process to remove the first doping layer in the second region; Using an acid etching process to remove the first tunneling oxide layer in the second region to expose the N-type silicon substrate; Removing the second mask layer, the second doping layer, and the second tunneling oxide layer in the first region includes: Using the laser technology, removing the second mask layer in the first area; Using the alkaline etching process to remove the second doping layer in the first region; The second tunneling oxide layer in the first region is removed by the acid etching process.

12. The preparation method according to claim 10, characterized in that: The front surface is subjected to front texturing, and before a third protective layer is prepared on the front surface after the front texturing, the method further comprises: The first mask layer and the second mask layer deposited on the front side are removed.

13. The preparation method according to claim 10, characterized in that: After the front surface is subjected to front texturing and before the third protective layer is prepared on the front surface after the front texturing, the method further includes: The first mask layer in the first region and the second mask layer in the second region are removed.

14. A TBC battery, characterized in that: The TBC battery is prepared by the preparation method of any one of claims 1 to 13.

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