Chip aging test method and device, electronic equipment and storage medium

Abstract

The invention discloses a chip aging test method and device, electronic equipment and a storage medium. The method comprises the following steps: converting standard five-line communication used for chip testing in a to-be-tested chip into target two-line communication through a communication protocol conversion controller to obtain a target chip; selecting a test mode for a high-voltage stress test, and determining test voltage and test time for performing the high-voltage stress test on the target chip; and in the test mode, testing the target chip according to the test voltage and the test time, and taking a test result as an aging test result of the to-be-tested chip. The target chip is obtained by converting the standard five-line communication in the to-be-tested chip into the target two-line communication, and the test result obtained by the target chip under the high-voltage stress test is obtained as the aging test result, so that the test time of each test of the chip can be shortened while all test items are completed only through two test channels, and the test efficiency is improved. The test cost is reduced, and the test efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of chip testing, and in particular to a chip aging test method, device, electronic equipment and storage medium. Background Art

[0002] Chip aging and stress testing are key steps to ensure the quality and reliability of semiconductor products. They improve the overall product quality and market competitiveness by screening out potential faulty chips during the manufacturing stage. However, in actual applications, these tests require highly accurate test equipment, complex test procedures, harsh test environments, and long test times to ensure the effectiveness of the tests. Summary of the invention

[0003] The present application provides a chip aging test method, device, electronic device and storage medium, which can complete all test items through only two test channels while reducing the test time of various chip tests, thereby reducing test costs and improving test efficiency.

[0004] According to one aspect of the present application, a chip aging test method is provided, the method comprising:

[0005] The standard five-wire communication used for chip testing inside the chip to be tested is converted into target two-wire communication by a communication protocol conversion controller to obtain a target chip;

[0006] Selecting a test mode for high voltage stress testing, and determining a test voltage and a test time for performing high voltage stress testing on the target chip;

[0007] In the test mode, the target chip is tested according to the test voltage and the test time, and the test result is used as the aging test result of the chip to be tested.

[0008] According to another aspect of the present application, a chip aging test device is provided, the device comprising:

[0009] A communication conversion module, used to convert the standard five-wire communication used for chip testing inside the chip to be tested into a target two-wire communication through a communication protocol conversion controller to obtain a target chip;

[0010] A test preparation module, used to select a test mode for a high voltage stress test, and determine a test voltage and a test time for performing a high voltage stress test on the target chip;

[0011] The aging test module is used to test the target chip according to the test voltage and the test time in the test mode, and use the test result as the aging test result of the chip to be tested.

[0012] According to another aspect of the present application, an electronic device is provided, the electronic device comprising:

[0013] at least one processor; and

[0014] a memory communicatively connected to the at least one processor; wherein,

[0015] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the chip aging test method described in any embodiment of the present invention.

[0016] According to another aspect of the present application, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the chip aging test method described in any embodiment of the present invention when executed.

[0017] The technical solution of the embodiment of the present application is to convert the standard five-wire communication used for chip testing inside the chip to be tested into target two-wire communication through a communication protocol conversion controller to obtain a target chip; select a test mode for high voltage stress testing, and determine the test voltage and test time for high voltage stress testing of the target chip; in the test mode, test the target chip according to the test voltage and the test time, and use the test result as the aging test result of the chip to be tested. The technical solution of the embodiment of the present application is to convert the standard five-wire communication inside the chip to be tested into a target chip obtained by target two-wire communication, and obtain the test result obtained by the target chip under high voltage stress testing as the aging test result, while completing all test items through only two test channels, reduce the test time of each chip test, thereby reducing the test cost and improving the test efficiency.

[0018] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 is a flow chart of a chip aging test method provided according to the first embodiment of the present application;

[0021] Figure 2 is a schematic diagram of a TP-LPCT architecture provided according to Embodiment 1 of the present application;

[0022] Figure 3 is a flow chart of a chip aging test method provided according to Embodiment 2 of the present application;

[0023] Figure 4 It is a flow chart of implementing TRST through TPCLK and TPIO according to the second embodiment of the present application;

[0024] Figure 5 It is a structural schematic diagram of a chip aging test device provided according to the third embodiment of the present application;

[0025] Figure 6 It is a structural schematic diagram of an electronic device for implementing the chip aging test method of an embodiment of the present application. DETAILED DESCRIPTION

[0026] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0027] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0028] Embodiment 1

[0029] Figure 1A flowchart of a chip aging test method is provided for the first embodiment of the present application. This embodiment is applicable to the case of performing aging test on a chip. The chip aging test method can be performed by a chip aging test device. The chip aging test device can be implemented in the form of hardware and / or software. The chip aging test device can be configured in an electronic device. Figure 1 As shown, the method includes:

[0030] S110 , converting the standard five-wire communication used for chip testing inside the chip to be tested into target two-wire communication through a communication protocol conversion controller to obtain a target chip.

[0031] The communication protocol conversion controller is a device that can realize the conversion between different communication protocols, and is used to ensure the accurate and efficient transmission of data between different devices or systems. In the embodiment of the present application, the communication protocol converter can be a two-wire serial port controller.

[0032] Among them, standard five-wire communication is an international standard electronic circuit test protocol JTAG defined by five communication channels for chip testing. Standard five-wire communication includes test clock TCK, test mode selection TMS, test data input TDI, test data output TDO and test reset TRST.

[0033] The target two-wire communication is two communication channels for chip testing obtained by converting the standard five-wire communication through a communication protocol conversion controller. The target two-wire communication includes a test clock port TPCLK and a test data input and output port TPIO.

[0034] In the embodiment of the present application, a communication protocol conversion controller can be added on the basis of the traditional JTAG, and the traditional standard five-wire communication (TCK, TMS, TDI, TDO, TRST) of JTAG can be converted into the target two-wire communication (TPCLK, TPIO) through the communication protocol conversion controller inside the chip, so as to obtain the target chip of the dual-port low pin cost test TP-LPCT architecture. For example, Figure 2 A schematic diagram of a TP-LPCT architecture is shown.

[0035] The TP-LPCT architecture is based on the IEEE1149.1 protocol and redefines the format of JTAG data packets in the form of a serial interface. This structure is close to being compatible with all test structures and ideas of IEEE1149.1. At the same time, the target chip uses the IJTAG Network based on IEEE1687 to connect various test IPs, and can also be used to implement the ATPG Pattern test of SCAN through TP-LPCT. Specifically, SCAN can be embedded in the IJTAG Network, and the SCAN test of the chip can be selected by configuring the JTAG in TP-LPCT. In addition, a logic built-in self-test (Logic BIST) controller, a burn-in test (Burn-In) controller, etc. can be introduced into the chip, and these controllers can be configured in the IJTAG Network inside the chip to further reduce the chip testing cost.

[0036] In summary, by converting the standard five-wire communication into the target two-wire communication through the communication protocol conversion controller, the target chip of the TP-LPLT architecture is obtained. Only two test channels are needed to complete the testing of all testable items of the chip, which reduces the dependence on the test channel and increases the number of simultaneous tests of the chip. More chips can be tested at the same time with a low-performance machine, thus reducing the testing cost.

[0037] S120 , selecting a test mode for high voltage stress testing, and determining a test voltage and a test time for performing high voltage stress testing on a target chip.

[0038] Among them, high voltage stress testing simulates the working state of the device under extreme conditions by applying a higher voltage based on the normal working voltage of the device. High voltage stress testing can accelerate the aging and failure process of the internal structure of the device, thereby revealing possible defects and hidden dangers of the device.

[0039] The input voltage of the target chip includes one voltage, two voltages and three voltages, which are respectively the power supply voltage VDD (CORE_1V5) used to power the core logic part of the integrated circuit, the power supply voltage VDD (CORE_5V) used to power the core logic part of the integrated circuit, and the power supply voltage VDD (IO) used to power the IO port of the integrated circuit. Accordingly, the test voltage of the target chip includes one test voltage, two test voltages and three test voltages.

[0040] In the embodiment of the present application, the test items that need to be tested for high voltage stress can be determined first, and the test mode for high voltage stress test can be selected according to these test items, and then the test voltage and test time for high voltage stress test of the target chip can be determined with reference to industry standards or technical specifications. By determining a reasonable test voltage and test time, firstly, it can be ensured that the test can accurately reflect the various performances of the chip in a high voltage stress environment, ensuring the effectiveness and accuracy of the test, and secondly, it can avoid the chip from being damaged due to excessive voltage or too long time during the test process.

[0041] S130 . In the test mode, the target chip is tested according to the test voltage and the test time, and the test result is used as the aging test result of the chip to be tested.

[0042] In the embodiment of the present application, a high voltage stress test of the target chip can be performed in the selected test mode for high voltage stress test. Specifically: the first step is to prepare the test environment and ensure that the test equipment is in good working condition; the second step is to select the test mode, determine the test mode according to the test items of the high voltage stress test as needed, and select the test pattern with the highest activation rate; the third step is to load the test parameters, input the previously determined test voltage and test time on the test equipment, and ensure that the test process can accurately simulate the working state of the chip under the high voltage stress environment; the fourth step is to perform the test, install the target chip on the test socket, ensure that the electrical connection is good, start the test equipment, and start running the chip for testing according to the selected test mode. The fifth step is to collect and analyze the test results. After the test is completed, all the data recorded during the test process are collected, the test data is analyzed, and the various performances of the chip under the high voltage stress environment are evaluated. It can be understood that after the target chip is subjected to a high voltage stress test, the test results of the target chip under the high voltage stress test can be obtained as the aging test results of the target chip, which are used to screen out products that may fail early and ensure that the delivered chips have higher reliability. Compared with traditional methods, the test process proposed in this application can reduce the test time of various chip tests and improve the efficiency of chip aging testing.

[0043] The technical solution of the embodiment of the present application is to convert the standard five-wire communication used for chip testing inside the chip to be tested into target two-wire communication through a communication protocol conversion controller to obtain a target chip; select a test mode for high voltage stress testing, and determine the test voltage and test time for high voltage stress testing of the target chip; in the test mode, test the target chip according to the test voltage and test time, and use the test result as the aging test result of the chip to be tested. The technical solution of the embodiment of the present application is to convert the standard five-wire communication inside the chip to be tested into a target chip obtained by target two-wire communication, and obtain the test result obtained by the target chip under high voltage stress testing as the aging test result, while completing all test items through only two test channels, reduce the test time of each chip test, thereby reducing the test cost and improving the test efficiency.

[0044] Embodiment 2

[0045] Figure 3 This is a flow chart of a chip aging test method provided in the second embodiment of the present application. The present embodiment is optimized based on the above embodiment. For solutions not described in detail in the present embodiment, please refer to the above embodiment. Figure 3 As shown, the method includes:

[0046] S210 , converting the standard five-wire communication used for chip testing inside the chip to be tested into target two-wire communication through a communication protocol conversion controller to obtain a target chip.

[0047] Optionally, the standard five-wire communication used for chip testing inside the chip to be tested is converted into target two-wire communication through a communication protocol conversion controller to obtain a target chip, including: generating a test clock TCK through internal frequency division of a test clock port TPCLK; time-division multiplexing the test mode selection TMS, test data input TDI, and test data output TDO in the form of data packets on a test data input and output port TPIO; and implementing a test reset TRST through the test clock port TPCLK and the test data input and output port TPIO.

[0048] Among them, time division multiplexing is a communication technology that can achieve the purpose of multi-channel transmission by transmitting different signals at different time periods using the same physical connection.

[0049] In an embodiment of the present application, the test clock TCK can be generated by the internal frequency division of the test clock port TPCLK, and the multiplexing of the test mode selection TMS, the test data input TDI and the test data output TDO in one communication channel can be realized by the test data input and output port TPIO and the time-division multiplexing technology, and the test reset TRST can be realized by the test clock port TPCLK and the test data input and output port TPIO. Thus, the standard five-wire communication for chip testing can be realized under the premise of using only two communication channels.

[0050] Optionally, the test reset TRST is implemented through the test clock port TPCLK and the test data input and output port TPIO, including: when preparing to start a new test item, the test data input and output port TPIO is used as the clock and the test clock port TPCLK is used as the data input to a group of shift registers; if the test data input and output port TPIO is used as the clock, within five consecutive clock cycles, the data input to the test clock port TPCLK is 1, triggering the test reset TRST to reset all test logics.

[0051] In the embodiment of the present application, the shift register control and the reset of the test logic can be performed through a specific timing signal. Specifically, when entering the test mode or the previous test item ends and a new test item is about to start, the shift register is provided with a clock pulse through the test data input and output port TPIO, and the shift register is provided with data input through the test clock port TPCLK. If the TPCLK signal remains in the specific state of 1 within 5 TPIO clock cycles, the test reset TRST is triggered to reset (or reset) all the test logic in the system, which means that all related test registers, counters, state machines, etc. will be reset to the initial state. At the same time, the system will enter a specific test mode according to the preset configuration or selection. Exemplarily, Figure 4 A flow chart of implementing TRST through TPCLK and TPIO is shown.

[0052] S220 , selecting a test mode for high voltage stress testing.

[0053] In an embodiment of the present application, the test items that need to be tested with high voltage stress can be determined first, and the test mode for high voltage stress testing can be selected based on these test items. Optionally, the test modes that can be used for high voltage stress testing include core scan patterns (Core SCAN Patterns), array built-in self-test patterns (Array BIST Patterns) and high-speed test patterns (At-Speed ​​Patterns), etc. Preferably, the best solution for selecting the test mode for high voltage stress testing is to select a special logic built-in self-test pattern (Logic BIST pattern) specifically used for aging testing.

[0054] S230, selecting a good chip with the same specification as the target chip as a sample chip, and determining a test voltage of the target chip according to the sample chip.

[0055] In the embodiment of the present application, good chips with excellent performance of the same specifications as the target chip can be selected as samples, and experiments can be carried out through the samples to determine the test voltage of the target chip, ensuring that the test can accurately reflect the performance of the chip in a high voltage stress environment, thereby ensuring the effectiveness and accuracy of the test.

[0056] Optionally, determining the test voltage of the target chip based on the sample includes: determining the maximum voltage defined by the product specification of the sample as the starting voltage, and determining the failure voltage of the sample based on the starting voltage; determining the breakdown voltage of the sample based on the failure voltage, and determining the test voltage of the sample based on the breakdown voltage.

[0057] Among them, the test voltage includes one test voltage, two test voltages and three test voltages, and accordingly, the starting voltage includes one starting voltage, two starting voltages and three starting voltages, the failure voltage includes one failure voltage, two failure voltages and three failure voltages, and the breakdown voltage includes one breakdown voltage, two breakdown voltages and three breakdown voltages.

[0058] In the embodiment of the present application, it can be understood that the high voltage stress test is to simulate the working state of the device under extreme conditions by applying a higher voltage on the basis of the normal working voltage of the device. Therefore, the maximum voltage defined in the product specification of the sample can be determined as the starting voltage, and the starting voltage can be increased according to the preset step size based on the starting voltage, and the failure voltage when the chip fails and the breakdown voltage when the chip is broken down can be determined in turn, and then the test voltage of the sample can be determined according to the breakdown voltage to simulate the working state of the device under extreme conditions.

[0059] Optionally, determining the failure voltage of the sample according to the starting voltage includes: fixing two voltages to the two starting voltages, fixing three voltages to the three starting voltages, starting from the one starting voltage according to a first preset step length, increasing the value of the one voltage until the chip fails, and determining the one failure voltage of the sample; fixing the one voltage to the one starting voltage, fixing the three voltages to the three starting voltages, starting from the two starting voltages according to a first preset step length, increasing the value of the two voltages until the chip fails, and determining the two failure voltages of the sample; fixing the one voltage to the one starting voltage, fixing the two voltages to the two starting voltages, starting from the three starting voltages according to a first preset step length, increasing the value of the three voltages until the chip fails, and determining the three failure voltages of the sample.

[0060] In the embodiment of the present application, the two-way voltage can be fixed as the two-way starting voltage, and the three-way voltage can be fixed as the three-way starting voltage, and then the one-way voltage value can be increased from the one-way starting voltage according to the first preset step length until the chip fails, so as to determine the one-way failure voltage of the sample. Among them, the first preset step length can be set according to the actual situation, such as 100mV, and the embodiment of the present application does not limit this. Afterwards, the two-way failure voltage and the three-way failure voltage can be determined according to the same method.

[0061] Optionally, the breakdown voltage of the sample is determined according to the failure voltage of the sample, and the test voltage of the sample is determined according to the breakdown voltage; including: fixing the two-way voltage to the difference between the two-way failure voltage and a first preset value, fixing the three-way voltage to the difference between the three-way failure voltage and the first preset value, starting from the difference between the one-way failure voltage and the first preset value according to a second preset step length, increasing the one-way voltage until the chip is broken down, and determining the one-way breakdown voltage of the sample; fixing the one-way voltage to the difference between the one-way breakdown voltage and the second preset value, fixing the three-way voltage to the difference between the three-way failure voltage and the first preset value, and increasing the one-way voltage from the two-way failure voltage to the first preset value according to the second preset step length. Starting from the difference between the set values, increase the two-way voltage until the chip is broken down, and determine the two-way breakdown voltage of the sample; fix the one-way voltage to the difference between the one-way breakdown voltage and the second preset value, fix the two-way voltage to the difference between the two-way breakdown voltage and the second preset value, start from the difference between the three-way failure voltage and the first preset value according to the second preset step, increase the three-way voltage until the chip is broken down, and determine the three-way breakdown voltage of the sample; respectively take the product of the one-way breakdown voltage and the preset coefficient, the product of the two-way breakdown voltage and the preset coefficient, and the product of the three-way breakdown voltage and the preset coefficient as the one-way test voltage, the two-way test voltage, and the three-way test voltage.

[0062] In an embodiment of the present application, the two-way voltage can be fixed to an operating voltage lower than the first preset value of the two-way failure voltage, and the three-way voltage can be fixed to an operating voltage lower than the first preset value of the three-way failure voltage. Starting from an operating voltage lower than the first preset value of the one-way failure voltage according to a second preset step, the one-way voltage is increased until the chip is broken down, and the one-way breakdown voltage of the sample is determined. Among them, the first preset value and the second preset step can be set according to actual conditions, and the embodiment of the present application is not limited to this. For example, the two-way voltage can be fixed to an operating voltage 300mV lower than the two-way failure voltage, and the three-way voltage can be fixed to an operating voltage 300mV lower than the three-way failure voltage. Starting from an operating voltage 300mV lower than the one-way failure voltage with a step of 100mV, the one-way voltage is increased until the chip is broken down, and the one-way breakdown voltage of the sample is determined. Afterwards, different from the method for determining the failure voltage, when determining the two-way breakdown voltage, the one-way voltage is fixed to the difference between the one-way breakdown voltage and the second preset value, that is, the working voltage lower than the second preset value of the one-way breakdown voltage, and when determining the three-way breakdown voltage, the one-way voltage is fixed to the difference between the one-way breakdown voltage and the second preset value, and the two-way voltage is fixed to the difference between the two-way breakdown voltage and the second preset value. Among them, the second preset value can be set according to actual conditions, such as 300mV, and the embodiment of the present application does not limit this.

[0063] After determining the one-way breakdown voltage, the two-way breakdown voltage, and the three-way breakdown voltage, the product of the one-way breakdown voltage and the preset coefficient, the product of the two-way breakdown voltage and the preset coefficient, and the product of the three-way breakdown voltage and the preset coefficient can be taken as the one-way test voltage, the two-way test voltage, and the three-way test voltage, respectively. Among them, the preset coefficient can be set according to actual conditions, such as 0.8, and the embodiment of the present application is not limited to this.

[0064] S240 , determining a test time for performing a high voltage stress test on the target chip according to a performance target of the target chip in a design determination phase.

[0065] In an embodiment of the present application, the performance target of the target chip at the signoff stage of the design determination can be clarified first, and the performance indicators and test requirements that need to be verified can be understood. Then, the test time of the high voltage stress test of the target chip can be evaluated based on the voltage tolerance capability, circuit complexity and other characteristics of the chip.

[0066] S250 . In the test mode, the target chip is tested according to the test voltage and the test time, and the test result is used as the aging test result of the chip to be tested.

[0067] The technical solution of the embodiment of the present application is to convert the standard five-wire communication used for chip testing inside the chip to be tested into target two-wire communication through a communication protocol conversion controller to obtain a target chip; select a test mode for high voltage stress testing; select a good chip with the same specifications as the target chip as a sample, and determine the test voltage of the target chip based on the sample; determine the test time for high voltage stress testing of the target chip according to the performance target of the target chip in the design determination stage; in the test mode, test the target chip according to the test voltage and test time, and use the test results as aging test results of the chip to be tested. The technical solution of the embodiment of the present application is to convert the standard five-wire communication inside the chip to be tested into a target chip obtained by target two-wire communication, and obtain the test results obtained by the target chip under high voltage stress testing as aging test results, while completing all test items through only two test channels, while reducing the test time of various chip tests, thereby reducing test costs and improving test efficiency.

[0068] Embodiment 3

[0069] Figure 5 This is a structural schematic diagram of a chip aging test device provided in Example 3 of the present application.

[0070] like Figure 5 As shown, the device comprises:

[0071] The communication conversion module 310 is used to convert the standard five-wire communication used for chip testing inside the chip to be tested into the target two-wire communication through the communication protocol conversion controller to obtain the target chip;

[0072] A test preparation module 320, used to select a test mode for a high voltage stress test, and determine a test voltage and a test time for performing a high voltage stress test on the target chip;

[0073] The aging test module 330 is used to test the target chip according to the test voltage and the test time in the test mode, and use the test result as the aging test result of the chip to be tested.

[0074] Optionally, the standard five-wire communication includes a test clock TCK, a test mode select TMS, a test data input TDI, a test data output TDO and a test reset TRST; the target two-wire communication includes a test clock port TPCLK and a test data input and output port TPIO; the communication conversion module 310 is used to:

[0075] The test clock TCK is generated by the internal frequency division of the test clock port TPCLK;

[0076] The test mode selection TMS, the test data input TDI and the test data output TDO are time-division multiplexed in the form of data packets on the test data input and output port TPIO;

[0077] The test reset TRST is realized through the test clock port TPCLK and the test data input and output port TPIO.

[0078] Optionally, the communication conversion module 310 is specifically configured to:

[0079] When preparing to start a new test item, the test data input and output port TPIO is used as the clock and the test clock port TPCLK is used as the data input to a group of shift registers;

[0080] If the test data input / output port TPIO is used as the clock, the data input to the test clock port TPCLK is all 1 within five consecutive clock cycles, triggering the test reset TRST to reset all test logics.

[0081] Optionally, the test preparation module 320 includes:

[0082] A test voltage determination unit, used for selecting a good chip with the same specification as the target chip as a sample chip, and determining a test voltage of the target chip according to the sample chip;

[0083] The test time determination unit is used to determine the test time for performing a high voltage stress test on the target chip according to the performance target of the target chip in the design determination stage.

[0084] Optionally, the test voltage determination unit includes:

[0085] A failure voltage determination subunit, used to determine the maximum voltage defined in the product specification of the sample as a starting voltage, and determine the failure voltage of the sample according to the starting voltage;

[0086] The test voltage determination subunit is used to determine the breakdown voltage of the sample according to the failure voltage, and to determine the test voltage of the sample according to the breakdown voltage.

[0087] Optionally, the starting voltage includes one-way starting voltage, two-way starting voltage and three-way starting voltage; the failure voltage includes one-way failure voltage, two-way failure voltage and three-way failure voltage; the failure voltage determination subunit is specifically used to:

[0088] Fixing the two-way voltage to the two-way starting voltage, fixing the three-way voltage to the three-way starting voltage, starting from the one-way starting voltage according to a first preset step length, increasing the value of the one-way voltage until the chip fails, and determining the one-way failure voltage of the sample;

[0089] Fixing the one-way voltage as the one-way starting voltage, fixing the three-way voltage as the three-way starting voltage, starting from the two-way starting voltage according to a first preset step length, increasing the value of the two-way voltage until the chip fails, and determining the two-way failure voltage of the sample;

[0090] The one-way voltage is fixed as the one-way starting voltage, the two-way voltage is fixed as the two-way starting voltage, and starting from the three-way starting voltage according to a first preset step, the values ​​of the three-way voltage are increased until the chip fails, and the three-way failure voltage of the sample is determined.

[0091] Optionally, the breakdown voltage includes one-way breakdown voltage, two-way breakdown voltage and three-way breakdown voltage; the test voltage includes one-way test voltage, two-way test voltage and three-way test voltage; the test voltage determination subunit is specifically used to:

[0092] Fixing the voltage of two channels to the difference between the failure voltage of two channels and a first preset value, fixing the voltage of three channels to the difference between the failure voltage of three channels and the first preset value, increasing the voltage of one channel according to a second preset step length starting from the difference between the failure voltage of one channel and the first preset value until the chip is broken down, and determining the breakdown voltage of one channel of the sample;

[0093] Fix the voltage of the first path to the difference between the breakdown voltage of the first path and a second preset value, fix the voltage of the third path to the difference between the failure voltage of the third path and the first preset value, and increase the voltage of the second path from the difference between the failure voltage of the second path and the first preset value according to the second preset step length until the chip is broken down, and determine the breakdown voltage of the second path of the sample;

[0094] Fix the voltage of the first path to the difference between the breakdown voltage of the first path and the second preset value, fix the voltage of the second path to the difference between the breakdown voltage of the second path and the second preset value, and increase the voltage of the three paths according to the second preset step length from the difference between the failure voltage of the three paths and the first preset value until the chip is broken down, and determine the breakdown voltage of the three paths of the sample;

[0095] The product of the one-way breakdown voltage and the preset coefficient, the product of the two-way breakdown voltage and the preset coefficient, and the product of the three-way breakdown voltage and the preset coefficient are respectively taken as the one-way test voltage, the two-way test voltage, and the three-way test voltage.

[0096] The chip aging test device provided in the embodiment of the present application can execute the chip aging test method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0097] Embodiment 4

[0098] Figure 6 A schematic diagram of an electronic device 10 that can be used to implement an embodiment of the present application is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0099] like Figure 6 As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0100] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0101] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as a chip aging test method.

[0102] In some embodiments, the chip aging test method may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the chip aging test method described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to execute the chip aging test method in any other appropriate manner (e.g., by means of firmware).

[0103] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0104] Computer programs for implementing the methods of the present application may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0105] In the context of the present application, a computer readable storage medium may be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, device or equipment. A computer readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer readable storage medium may be a machine readable signal medium. A more specific example of a machine readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0106] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0107] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0108] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0109] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this application can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document is not limited here.

[0110] The above specific implementations do not constitute a limitation on the protection scope of this application. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of this application.

Claims

1. A chip aging test method, characterized in that: The method comprises: The standard five-wire communication used for chip testing inside the chip to be tested is converted into target two-wire communication by a communication protocol conversion controller to obtain a target chip; Selecting a test mode for high voltage stress testing, and determining a test voltage and a test time for performing high voltage stress testing on the target chip; In the test mode, the target chip is tested according to the test voltage and the test time, and the test result is used as the aging test result of the chip to be tested.

2. The method according to claim 1, characterized in that The standard five-wire communication includes a test clock TCK, a test mode select TMS, a test data input TDI, a test data output TDO and a test reset TRST; the target two-wire communication includes a test clock port TPCLK and a test data input and output port TPIO; The communication protocol conversion controller converts the standard five-wire communication used for chip testing inside the chip to be tested into the target two-wire communication to obtain the target chip, including: The test clock TCK is generated by the internal frequency division of the test clock port TPCLK; The test mode selection TMS, the test data input TDI and the test data output TDO are time-division multiplexed in the form of data packets on the test data input and output port TPIO; The test reset TRST is realized through the test clock port TPCLK and the test data input and output port TPIO.

3. The method according to claim 1, characterized in that The test reset TRST is implemented through the test clock port TPCLK and the test data input and output port TPIO, including: When preparing to start a new test item, the test data input and output port TPIO is used as the clock and the test clock port TPCLK is used as the data input to a group of shift registers; If the test data input / output port TPIO is used as the clock, the data input to the test clock port TPCLK is all 1 within five consecutive clock cycles, triggering the test reset TRST to reset all test logics.

4. The method according to claim 1, characterized in that: Determining a test voltage and a test time for performing a high voltage stress test on the target chip, including: Select a good chip with the same specification as the target chip as a sample chip, and determine the test voltage of the target chip according to the sample chip; The test time for performing a high voltage stress test on the target chip is determined according to the performance target of the target chip in the design determination stage.

5. The method according to claim 4, characterized in that Determining a test voltage of the target chip according to the sample chip includes: Determine a maximum voltage defined in a product specification of the sample as a starting voltage, and determine a failure voltage of the sample according to the starting voltage; A breakdown voltage of the sample is determined according to the failure voltage, and a test voltage of the sample is determined according to the breakdown voltage.

6. The method according to claim 5, characterized in that The starting voltage includes one-way starting voltage, two-way starting voltage and three-way starting voltage; the failure voltage includes one-way failure voltage, two-way failure voltage and three-way failure voltage; Determining the failure voltage of the sample according to the starting voltage includes: Fixing the two-way voltage to the two-way starting voltage, fixing the three-way voltage to the three-way starting voltage, starting from the one-way starting voltage according to a first preset step length, increasing the value of the one-way voltage until the chip fails, and determining the one-way failure voltage of the sample; Fixing the one-way voltage as the one-way starting voltage, fixing the three-way voltage as the three-way starting voltage, starting from the two-way starting voltage according to a first preset step length, increasing the value of the two-way voltage until the chip fails, and determining the two-way failure voltage of the sample; The one-way voltage is fixed as the one-way starting voltage, the two-way voltage is fixed as the two-way starting voltage, and starting from the three-way starting voltage according to a first preset step, the values ​​of the three-way voltage are increased until the chip fails, and the three-way failure voltage of the sample is determined.

7. The method according to claim 5, characterized in that The breakdown voltage includes one-way breakdown voltage, two-way breakdown voltage and three-way breakdown voltage; the test voltage includes one-way test voltage, two-way test voltage and three-way test voltage; Determining a breakdown voltage of the sample according to a failure voltage of the sample, and determining a test voltage of the sample according to the breakdown voltage; comprising: Fixing the voltage of two channels to the difference between the failure voltage of two channels and a first preset value, fixing the voltage of three channels to the difference between the failure voltage of three channels and the first preset value, increasing the voltage of one channel according to a second preset step length starting from the difference between the failure voltage of one channel and the first preset value until the chip is broken down, and determining the breakdown voltage of one channel of the sample; Fix the voltage of the first path to the difference between the breakdown voltage of the first path and a second preset value, fix the voltage of the third path to the difference between the failure voltage of the third path and the first preset value, and increase the voltage of the second path from the difference between the failure voltage of the second path and the first preset value according to the second preset step length until the chip is broken down, and determine the breakdown voltage of the second path of the sample; Fix the voltage of the first path to the difference between the breakdown voltage of the first path and the second preset value, fix the voltage of the second path to the difference between the breakdown voltage of the second path and the second preset value, and increase the voltage of the three paths according to the second preset step length from the difference between the failure voltage of the three paths and the first preset value until the chip is broken down, and determine the breakdown voltage of the three paths of the sample; The product of the one-way breakdown voltage and the preset coefficient, the product of the two-way breakdown voltage and the preset coefficient, and the product of the three-way breakdown voltage and the preset coefficient are respectively taken as the one-way test voltage, the two-way test voltage, and the three-way test voltage.

8. A chip aging test device, characterized in that: The device comprises: A communication conversion module, used to convert the standard five-wire communication used for chip testing inside the chip to be tested into a target two-wire communication through a communication protocol conversion controller to obtain a target chip; A test preparation module, used to select a test mode for a high voltage stress test, and determine a test voltage and a test time for performing a high voltage stress test on the target chip; The aging test module is used to test the target chip according to the test voltage and the test time in the test mode, and use the test result as the aging test result of the chip to be tested.

9. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the chip aging test method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the chip aging test method according to any one of claims 1 to 7 when executed.

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