Analog quantity measuring circuit and analog quantity measuring equipment for chip
By designing an analog quantity measurement circuit for the chip, and connecting it with the test pins with the control circuit and switching circuit, the measurement of various voltages and analog quantities of the chip is solved, and the design difficulty and area waste caused by increasing the test pins are achieved, miniaturization and efficient measurement of the chip are achieved.
Patent Information
- Application Number
- CN202411684245.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-22
- Publication Date
- 2025-02-25
AI Technical Summary
In chip design, adding test pins for stress testing and analog measurements will increase design difficulty and waste chip area, limiting chip miniaturization.
Design an analog measurement circuit including a control circuit, a positive high voltage switch circuit, a positive low voltage switch circuit and an analog switching circuit. These circuits are connected to the test pin and control circuit of the chip to measure the positive high voltage, positive low voltage and analog quantity of the chip. Only one test pin needs to be set on the chip.
This solution reduces the difficulty of chip design, reduces the waste of chip area, realizes the miniaturization of chips, and improves the efficiency of chip pressure testing and analog measurement.
Smart Images
Figure CN119511036A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of chip technology, for example, to an analog quantity measurement circuit and an analog quantity measurement device for a chip. Background Art
[0002] At present, with the development of integrated circuit technology, the integration of chips is getting higher and higher, and the functions are increasing.
[0003] In the related art, in order to ensure the normal operation of each circuit of the chip, in addition to setting IO pins for normal driving of the chip on the die, it is also necessary to place multiple test pins for stress testing or analog quantity measurement on the chip. However, setting more test pins on the chip will increase the difficulty of chip design and waste chip area, which is not conducive to the miniaturization of the chip.
[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention
[0005] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.
[0006] The embodiments of the present disclosure provide an analog quantity measurement circuit and an analog quantity measurement device for a chip, which can reduce the difficulty of chip design, reduce the waste of chip area, and facilitate the miniaturization of the chip.
[0007] In some embodiments, an analog quantity measurement circuit for a chip includes: a control circuit, a positive high-voltage switch circuit, a positive low-voltage switch circuit and an analog quantity switch circuit; the positive high-voltage switch circuit is connected to the test pin and the control circuit of the chip, and is used to respond to a first control signal generated by the control circuit to connect the test pin of the chip to the output end of the positive high voltage to be measured; the positive low-voltage switch circuit is connected to the test pin and the control circuit of the chip, and is used to respond to a second control signal generated by the control circuit to connect the test pin of the chip to the output end of the positive low voltage to be measured; the analog quantity switch circuit is connected to the test pin and the control circuit of the chip, and is used to respond to a third control signal generated by the control circuit to connect the test pin of the chip to the output end of the analog quantity to be measured.
[0008] Optionally, the positive high-voltage switch circuit includes: a first PMOS tube, a second PMOS tube, a first level conversion circuit and a second level conversion circuit; the source and substrate of the first PMOS tube are connected to the test pin of the chip; the source and substrate of the second PMOS tube are connected to the output end of the positive high voltage to be tested, and the drain of the second PMOS tube is connected to the drain of the first PMOS tube; the first input end of the first level conversion circuit is connected to the control circuit, the second input end is connected to the test pin of the chip, and the second output end is connected to the gate of the first PMOS tube; the first input end of the second level conversion circuit is connected to the control circuit, the second input end is connected to the output end of the positive high voltage to be tested, and the second output end is connected to the gate of the second PMOS tube.
[0009] Optionally, the positive low-voltage switch circuit includes: a third PMOS tube, a fourth PMOS tube, a third level conversion circuit and a fourth level conversion circuit; the source and substrate of the third PMOS tube are connected to the test pin of the chip; the source and substrate of the fourth PMOS tube are connected to the output end of the positive low voltage to be tested, and the drain of the fourth PMOS tube is connected to the drain of the third PMOS tube; the first input end of the third level conversion circuit is connected to the control circuit, the second input end is connected to the test pin of the chip, and the second output end is connected to the gate of the third PMOS tube; the first input end of the fourth level conversion circuit is connected to the control circuit, the second input end is connected to the output end of the positive low voltage to be tested, and the second output end is connected to the gate of the fourth PMOS tube.
[0010] Optionally, the analog quantity switching circuit includes: a first NMOS tube and a fifth level conversion circuit; the source of the first NMOS tube is connected to the test pin of the chip, and the drain of the first NMOS tube is connected to the output end of the analog quantity to be measured; the first input end of the fifth level conversion circuit is connected to the control circuit, the second input end is connected to the output end of the positive low voltage to be measured, and the first output end is connected to the gate of the first NMOS tube.
[0011] Optionally, the analog quantity measurement circuit for the chip further includes: a pull-up circuit; the output end of the pull-up circuit is connected to the test pin of the chip, so as to reduce the electromagnetic interference to which the test pin of the chip is subjected when it is in a suspended state.
[0012] Optionally, the pull-up circuit includes: a pull-up power supply and a second NMOS tube; the gate of the second NMOS tube is connected to the control circuit, the source of the second NMOS tube is connected to the pull-up power supply, and the drain of the second NMOS tube is connected to the test pin of the chip.
[0013] Optionally, the analog quantity measurement circuit for the chip further includes: a protection circuit; the input end of the protection circuit is connected to the test pin of the chip, and the output end is connected to the ground line.
[0014] Optionally, the protection circuit includes: a third NMOS tube and a protection resistor; the source of the third NMOS tube is connected to the test pin of the chip, and the drain of the third NMOS tube is connected to the ground line; one end of the protection resistor is connected to the gate of the third NMOS tube, and the other end is connected to the drain of the third NMOS tube.
[0015] Optionally, the control circuit is a logic control circuit or a microcontroller.
[0016] In some embodiments, an analog quantity measuring device for a chip includes: a device body; and an analog quantity measuring circuit for a chip as described above, which is arranged in the device body.
[0017] The analog quantity measurement circuit and analog quantity measurement device for a chip provided by the embodiments of the present disclosure can achieve the following technical effects:
[0018] In an embodiment of the present disclosure, there is provided an analog quantity measurement circuit for a chip, which includes a control circuit, a positive high voltage switch circuit, a positive low voltage switch circuit, and an analog quantity switch circuit. Among them, the positive high voltage switch circuit is connected to the test pin of the chip and the control circuit, and can respond to the first control signal generated by the control circuit, so that the test pin of the chip is connected to the output end of the positive high voltage to be measured, thereby realizing the measurement of the positive high voltage of the chip. The positive low voltage switch circuit is connected to the test pin of the chip and the control circuit, and can respond to the second control signal generated by the control circuit, so that the test pin of the chip is connected to the output end of the positive low voltage to be measured, thereby realizing the measurement of the positive low voltage of the chip. The analog quantity switch circuit is connected to the test pin of the chip and the control circuit, and can respond to the third control signal generated by the control circuit, so that the test pin of the chip is connected to the output end of the analog quantity to be measured, thereby realizing the measurement of other analog quantities of the chip. In this way, only one test pin needs to be set on the chip to realize the pressure test or analog quantity measurement of the chip. Therefore, the embodiment of the present disclosure can reduce the design difficulty of the chip, reduce the waste of chip area, and realize the miniaturization of the chip.
[0019] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:
[0021] Figure 1 is a schematic diagram of an analog quantity measurement circuit for a chip provided by an embodiment of the present disclosure;
[0022] Figure 2is a schematic diagram of another analog quantity measurement circuit for a chip provided by an embodiment of the present disclosure;
[0023] Figure 3 is a schematic diagram of another analog quantity measurement circuit for a chip provided by an embodiment of the present disclosure;
[0024] Figure 4 is a schematic diagram of another analog quantity measurement circuit for a chip provided by an embodiment of the present disclosure;
[0025] Figure 5 is a schematic diagram of another analog quantity measurement circuit for a chip provided by an embodiment of the present disclosure;
[0026] Figure 6 It is a schematic diagram of another analog quantity measurement circuit for a chip provided by an embodiment of the present disclosure.
[0027] Description of reference numerals:
[0028] 10. Analog quantity measurement circuit for chip;
[0029] 100. Control circuit;
[0030] 200, positive high voltage switch circuit; 201, first PMOS transistor; 202, second PMOS transistor; 203, first level conversion circuit; 204, second level conversion circuit;
[0031] 300, positive low voltage switch circuit; 301, third PMOS tube; 302, fourth PMOS tube; 303, third level conversion circuit; 304, fourth level conversion circuit;
[0032] 400, analog switch circuit; 401, first NMOS tube; 402, fifth level conversion circuit;
[0033] 500, pull-up circuit; 501, pull-up power supply; 502, second NMOS tube;
[0034] 600, protection circuit; 601, third NMOS tube; 602, protection resistor. DETAILED DESCRIPTION
[0035] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.
[0036] The terms "first", "second", etc. in the specification and claims of the disclosed embodiments and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or precedence sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so as to describe the embodiments of the disclosed embodiments described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.
[0037] Unless otherwise stated, the term "plurality" of a feature means two or more.
[0038] In the embodiment of the present disclosure, the character " / " feature indicates that the preceding and following objects are in an "or" relationship. For example, the A / B feature indicates: A or B.
[0039] The term "and / or" is a description of the association relationship between objects, and the characteristic indicates that there can be three relationships. For example, A and / or B, the characteristic indicates: A or B, or, A and B.
[0040] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.
[0041] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other.
[0042] like Figure 1 As shown, the analog quantity measurement circuit 10 for a chip provided by the embodiment of the present disclosure (hereinafter referred to as the analog quantity measurement circuit 10 for the convenience of description) includes: a control circuit 100, a positive high voltage switch circuit 200, a positive low voltage switch circuit 300 and an analog quantity switch circuit 400. The positive high voltage switch circuit 200 is connected to the test pin of the chip and the control circuit 100, and is used to respond to the first control signal generated by the control circuit 100, so that the test pin of the chip is connected to the output terminal ( Figure 1 The positive low voltage switch circuit 300 is connected to the test pin of the chip and the control circuit 100, and is used to respond to the second control signal generated by the control circuit 100 to connect the test pin of the chip to the output terminal of the positive low voltage to be tested ( Figure 1 The analog switch circuit 400 is connected to the test pin of the chip and the control circuit 100, and is used to respond to the third control signal generated by the control circuit 100 to connect the test pin of the chip to the output terminal ( Figure 1 The port shown in C is connected.
[0043] Optionally, the control circuit 100 is a logic control circuit or a microcontroller.
[0044] Specifically, by setting the control circuit 100 and the positive high voltage switch circuit 200 in the analog quantity measurement circuit 10, and connecting the positive high voltage switch circuit 200 with the test pin of the chip and the control circuit 100, when the control circuit 100 generates the first control signal, the test pin of the chip can be connected to the output end of the positive high voltage to be measured. In this way, the voltage at the test pin is the positive high voltage to be measured, and the measurement of the positive high voltage of the chip is achieved.
[0045] Optionally, the positive high voltage to be measured may be a voltage generated by a charge pump circuit provided inside the chip, and therefore, the output end of the positive high voltage to be measured may be an output end of the charge pump circuit.
[0046] Specifically, by setting the control circuit 100 and the positive low voltage switch circuit 300 in the analog quantity measurement circuit 10, and connecting the positive low voltage switch circuit 300 with the test pin of the chip and the control circuit 100, when the control circuit 100 generates the second control signal, the test pin of the chip can be connected to the output end of the positive low voltage to be measured. In this way, the voltage at the test pin is the positive low voltage to be measured, and the measurement of the positive low voltage of the chip is achieved.
[0047] Optionally, the positive low voltage to be measured may be a voltage generated by a low voltage dropout regulator circuit provided inside the chip, and therefore, the output end of the positive low voltage to be measured may be an output end of the low voltage dropout regulator circuit.
[0048] Specifically, by setting the control circuit 100 and the analog quantity switch circuit 400 in the analog quantity measurement circuit 10, and connecting the analog quantity switch circuit 400 with the test pin of the chip and the control circuit 100, when the control circuit 100 generates the third control signal, the test pin of the chip can be connected to the output end of the analog quantity to be measured. In this way, the analog quantity at the test pin is the analog quantity to be measured, and the measurement of the analog quantity of the chip other than the positive high voltage and the positive low voltage is realized.
[0049] Optionally, the analog quantity to be measured may be a current or a voltage generated by various circuits provided inside the chip; therefore, the output end of the analog quantity to be measured may be an output end of any circuit inside the chip.
[0050] In the embodiment of the present disclosure, there is provided an analog quantity measurement circuit 10 for a chip, which includes a control circuit 100, a positive high voltage switch circuit 200, a positive low voltage switch circuit 300 and an analog quantity switch circuit 400. Among them, the positive high voltage switch circuit 200 is connected to the test pin of the chip and the control circuit 100, and can respond to the first control signal generated by the control circuit 100, so that the test pin of the chip is connected to the output end of the positive high voltage to be measured, so as to measure the positive high voltage of the chip. The positive low voltage switch circuit 300 is connected to the test pin of the chip and the control circuit 100, and can respond to the second control signal generated by the control circuit 100, so that the test pin of the chip is connected to the output end of the positive low voltage to be measured, so as to measure the positive low voltage of the chip. The analog quantity switch circuit 400 is connected to the test pin of the chip and the control circuit 100, and can respond to the third control signal generated by the control circuit 100, so that the test pin of the chip is connected to the output end of the analog quantity to be measured, so as to measure other analog quantities of the chip. In this way, only one test pin needs to be set on the chip to realize the pressure test or analog quantity measurement of the chip. Therefore, the embodiments of the present disclosure can reduce the difficulty of chip design, reduce the waste of chip area, and achieve chip miniaturization.
[0051] like Figure 2 As shown, in some embodiments, the positive high voltage switch circuit 200 includes: a first PMOS tube 201, a second PMOS tube 202, a first level conversion circuit 203, and a second level conversion circuit 204. The source and substrate of the first PMOS tube 201 are connected to the test pin of the chip. The source and substrate of the second PMOS tube 202 are connected to the output end of the positive high voltage to be tested, and the drain of the second PMOS tube 202 is connected to the drain of the first PMOS tube 201. The first input end of the first level conversion circuit 203 is connected to the control circuit 100, the second input end is connected to the test pin of the chip, and the second output end is connected to the gate of the first PMOS tube 201. The first input end of the second level conversion circuit 204 is connected to the control circuit 100, the second input end is connected to the output end of the positive high voltage to be tested, and the second output end is connected to the gate of the second PMOS tube 202.
[0052] Specifically, by setting a first PMOS tube 201, a second PMOS tube 202, a first level conversion circuit 203 and a second level conversion circuit 204, the source and substrate of the first PMOS tube 201 are connected to the test pin of the chip, the drain is connected to the drain of the second PMOS tube 202, and the gate is connected to the second output end of the first level conversion circuit 203. The source and substrate of the second PMOS tube 202 are connected to the output end of the positive high voltage to be tested, and the gate is connected to the second output end of the second level conversion circuit 204. The first input end of the first level conversion circuit 203 is connected to the control circuit 100, and the second input end is connected to the test pin of the chip. The first input end of the second level conversion circuit 204 is connected to the control circuit 100, and the second input end is connected to the output end of the positive high voltage to be tested. When the positive high voltage of the chip needs to be stress tested or analog measured, the control circuit 100 can output a first control signal (usually a power supply voltage). In this case, the first level conversion circuit 203 can convert the power supply voltage into 0V and output it to the first PMOS tube 201, so that the first PMOS tube 201 is turned on, and the second level conversion circuit 204 can convert the power supply voltage into 0V and output it to the second PMOS tube 202, so that the second PMOS tube 202 is turned on. In this way, the test pin of the chip and the output end of the positive high voltage to be tested are interconnected. When the chip is in the analog measurement mode, the positive high voltage to be tested can be measured from the test pin. When the chip is in the stress test mode, an input voltage can be applied to the output end of the positive high voltage to be tested through the test pin.
[0053] It should be noted that Figure 2 In the level conversion circuits (the first level conversion circuit 203 and the second level conversion circuit 204 ), I1 represents the first input terminal, I2 represents the second input terminal, O1 represents the first output terminal, and O2 represents the second output terminal.
[0054] It should be noted that the first output terminals of the first level conversion circuit 203 and the second level conversion circuit 204 are both in a suspended state.
[0055] In the embodiment of the present disclosure, all PMOS tubes are used in the positive high voltage switch circuit 200, instead of NMOS tubes, so no higher gate voltage is needed to control the conduction of the positive high voltage switch circuit 200. In this way, when measuring the positive high voltage or applying the positive high voltage for pressure testing, it is no longer limited by the high voltage of the gate, and the higher gate voltage needs to be generated by the charge pump. Therefore, the analog quantity measurement circuit 10 provided by the embodiment of the present disclosure does not need to set a charge pump circuit on the chip, which further reduces the chip area.
[0056] like Figure 3As shown, in some embodiments, the positive low voltage switch circuit 300 includes: a third PMOS tube 301, a fourth PMOS tube 302, a third level conversion circuit 303 and a fourth level conversion circuit 304. The source and substrate of the third PMOS tube 301 are connected to the test pin of the chip. The source and substrate of the fourth PMOS tube 302 are connected to the output end of the positive low voltage to be tested, and the drain of the fourth PMOS tube 302 is connected to the drain of the third PMOS tube 301. The first input end of the third level conversion circuit 303 is connected to the control circuit 100, the second input end is connected to the test pin of the chip, and the second output end is connected to the gate of the third PMOS tube 301. The first input end of the fourth level conversion circuit 304 is connected to the control circuit 100, the second input end is connected to the output end of the positive low voltage to be tested, and the second output end is connected to the gate of the fourth PMOS tube 302.
[0057] Specifically, by setting up a third PMOS tube 301, a fourth PMOS tube 302, a third level conversion circuit 303 and a fourth level conversion circuit 304, the source and substrate of the third PMOS tube 301 are connected to the test pin of the chip, the drain is connected to the drain of the fourth PMOS tube 302, and the gate is connected to the second output end of the third level conversion circuit 303. The source and substrate of the fourth PMOS tube 302 are connected to the output end of the positive low voltage to be tested, and the gate is connected to the second output end of the fourth level conversion circuit 304. The first input end of the third level conversion circuit 303 is connected to the control circuit 100, and the second input end is connected to the test pin of the chip. The first input end of the fourth level conversion circuit 304 is connected to the control circuit 100, and the second input end is connected to the output end of the positive low voltage to be tested. When the positive low voltage of the chip needs to be stress tested or analog measured, the control circuit 100 can output a second control signal (usually a power supply voltage). In this case, the third level conversion circuit 303 can convert the power supply voltage into 0V and output it to the third PMOS tube 301, so that the third PMOS tube 301 is turned on, and the fourth level conversion circuit 304 can convert the power supply voltage into 0V and output it to the fourth PMOS tube 302, so that the fourth PMOS tube 302 is turned on. In this way, the test pin of the chip and the output end of the positive low voltage to be tested are interconnected. When the chip is in the analog measurement mode, the positive low voltage to be tested can be measured from the test pin. When the chip is in the stress test mode, an input voltage can be applied to the output end of the positive low voltage to be tested through the test pin.
[0058] It should be noted that Figure 3 In the level conversion circuits (the third level conversion circuit 303 and the fourth level conversion circuit 304 ), I1 represents a first input terminal, I2 represents a second input terminal, O1 represents a first output terminal, and O2 represents a second output terminal.
[0059] It should be noted that the first output terminals of the third level conversion circuit 303 and the fourth level conversion circuit 304 are both in a suspended state.
[0060] In the embodiment of the present disclosure, all PMOS tubes are used in the positive low voltage switch circuit 300, instead of NMOS tubes, so no higher gate voltage is required to control the positive low voltage switch circuit 300 to be turned on. In this way, when measuring the positive low voltage or the pressure test requires the application of positive low voltage, it is no longer limited by the high voltage of the gate, and the higher gate voltage needs to be generated by the charge pump. Therefore, the analog quantity measurement circuit 10 provided by the embodiment of the present disclosure does not need to set a charge pump circuit on the chip, which further reduces the chip area.
[0061] like Figure 4 As shown, in some embodiments, the analog quantity switch circuit 400 includes: a first NMOS tube 401 and a fifth level conversion circuit 402. The source of the first NMOS tube 401 is connected to the test pin of the chip, and the drain of the first NMOS tube 401 is connected to the output end of the analog quantity to be measured. The first input end of the fifth level conversion circuit 402 is connected to the external control circuit 100, the second input end is connected to the output end of the positive low voltage to be measured, and the first output end is connected to the gate of the first NMOS tube 401.
[0062] Specifically, by setting an analog quantity switch circuit 400 including a first NMOS tube 401 and a fifth level conversion circuit 402, the source of the first NMOS tube 401 is connected to the test pin of the chip, the drain of the first NMOS tube 401 is connected to the output end of the analog quantity to be measured, and the gate of the first NMOS tube 401 is connected to the first output end of the fifth level conversion circuit 402. The first input end of the fifth level conversion circuit 402 is connected to the control circuit 100, and the second input end is connected to the output end of the positive low voltage to be measured. When it is necessary to measure the analog quantity of the chip other than the positive high voltage and the positive low voltage, the control circuit 100 can output a third control signal (usually a power supply voltage). In this case, the fifth level conversion circuit 402 will select the positive low voltage output to be measured from the power supply voltage and the positive low voltage to be measured, and output the positive low voltage to be measured to the first NMOS tube 401, so that the first NMOS tube 401 is turned on. In this way, the test pin of the chip and the output end of the analog quantity to be measured are interconnected. When the chip is in the analog quantity measurement mode, the analog quantity to be measured can be measured from the test pin.
[0063] Optionally, the analog quantity to be measured includes a current to be measured and a voltage to be measured.
[0064] It should be noted that Figure 4 In the level conversion circuit (fifth level conversion circuit 402 ), I1 represents a first input terminal, I2 represents a second input terminal, O1 represents a first output terminal, and O2 represents a second output terminal.
[0065] It should be noted that the second output terminal of the fifth level conversion circuit 402 is in a suspended state.
[0066] In the embodiment of the present disclosure, during the analog quantity measurement process of the chip, by connecting the first input terminal of the fifth level conversion circuit 402 to the control circuit 100 and the second input terminal to the low voltage to be measured, accurate control of the on and off of the first NMOS tube 401 is achieved. In this way, the high voltage signal can be effectively prevented from damaging the chip.
[0067] like Figure 5 As shown, in some embodiments, the analog quantity measurement circuit 10 further includes: a pull-up circuit 500. The output end of the pull-up circuit 500 is connected to the test pin of the chip to reduce the electromagnetic interference received by the test pin of the chip when it is in a suspended state.
[0068] Specifically, by setting a pull-up circuit 500 connected to the test pin of the chip, when the test pin of the chip is in a floating state due to the chip not being stress tested or analog quantity measured, the level at the test pin can be pulled up to a high level to prevent external interference signals from flowing into the chip through the test pin and affecting the normal operation of the chip.
[0069] like Figure 5 As shown, in some embodiments, the pull-up circuit 500 includes: a pull-up power supply 501 and a second NMOS transistor 502. The gate of the second NMOS transistor 502 is connected to the control circuit 100, the source of the second NMOS transistor 502 is connected to the pull-up power supply 501, and the drain of the second NMOS transistor 502 is connected to the test pin of the chip.
[0070] Specifically, by setting a pull-up circuit 500 including a pull-up power supply 501 and a second NMOS tube 502. When confirming that the test pin of the chip is in a suspended state, the control circuit 100 can output a fourth control signal to the gate of the second NMOS tube 502 to turn on the second NMOS tube 502. In this case, the voltage at the connection point between the test pin and the drain of the second NMOS tube 502 is the power supply voltage of the pull-up power supply 501 minus the threshold voltage of the second NMOS tube 502. In this way, the test pin can be in a high level state to prevent external interference signals from flowing into the chip through the test pin.
[0071] like Figure 6 As shown, in some embodiments, the analog quantity measurement circuit 10 further includes: a protection circuit 600. The input end of the protection circuit 600 is connected to the test pin of the chip, and the output end is connected to the ground line.
[0072] Specifically, by providing a protection circuit 600 connected to the test pin of the chip, the protection circuit 600 can absorb overcurrent and overvoltage at the test pin to prevent electrical breakdown of the chip caused by excessive voltage or excessive current.
[0073] like Figure 6 As shown, in some embodiments, the protection circuit 600 includes: a third NMOS transistor 601 and a protection resistor 602. The source of the third NMOS transistor 601 is connected to the test pin of the chip, and the drain of the third NMOS transistor 601 is connected to the ground line. One end of the protection resistor 602 is connected to the gate of the third NMOS transistor 601, and the other end is connected to the drain of the third NMOS transistor 601.
[0074] Specifically, by providing a protection circuit 600 including a third NMOS transistor 601 and a protection resistor 602, when there is an overvoltage or overcurrent at the test pin of the chip, the third NMOS transistor 601 can be turned on to guide the overvoltage or overcurrent to the ground line to prevent the chip from electrical breakdown.
[0075] In some embodiments, an analog quantity measuring device for a chip includes: a device body and the analog quantity measuring circuit for a chip as described above. The analog quantity measuring circuit for a chip is arranged in the device body.
[0076] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent only possible changes. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the claims. As used in the description of the embodiments and the claims, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of listings containing one or more associated ones. In addition, when used in the present application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.
[0077] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. The technicians may use different methods for each specific application to implement the described functions, but such implementations should not be considered to exceed the scope of the embodiments of the present disclosure. The technicians may clearly understand that, for the convenience and simplicity of description, the specific working processes of the systems, devices and units described above may refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.
[0078] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units can be only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to implement this embodiment. In addition, each functional unit in the embodiment of the present disclosure may be integrated in a processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit.
[0079] The flowchart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to the embodiment of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. In the description corresponding to the flowchart and the block diagram in the accompanying drawings, the operations or steps corresponding to different boxes can also occur in a different order from the order disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified functions or actions, or may be implemented by a combination of dedicated hardware and computer instructions.
Claims
1. An analog quantity measurement circuit for a chip, characterized in that: include: Control circuit, positive high voltage switch circuit, positive low voltage switch circuit and analog switch circuit; The positive high voltage switch circuit is connected to the test pin of the chip and the control circuit, and is used to respond to the first control signal generated by the control circuit to connect the test pin of the chip to the output end of the positive high voltage to be tested; The positive low voltage switch circuit is connected to the test pin of the chip and the control circuit, and is used to respond to the second control signal generated by the control circuit to connect the test pin of the chip with the output end of the positive low voltage to be tested; The analog quantity switch circuit is connected to the test pin of the chip and the control circuit, and is used for responding to the third control signal generated by the control circuit to connect the test pin of the chip with the output end of the analog quantity to be measured.
2. The analog quantity measurement circuit according to claim 1, characterized in that: The positive high voltage switch circuit comprises: a first PMOS tube, a second PMOS tube, a first level conversion circuit and a second level conversion circuit; The source and substrate of the first PMOS tube are connected to the test pin of the chip; The source and substrate of the second PMOS tube are connected to the output end of the positive high voltage to be measured, and the drain of the second PMOS tube is connected to the drain of the first PMOS tube; The first input end of the first level conversion circuit is connected to the control circuit, the second input end is connected to the test pin of the chip, and the second output end is connected to the gate of the first PMOS tube; The first input end of the second level conversion circuit is connected to the control circuit, the second input end is connected to the output end of the positive high voltage to be measured, and the second output end is connected to the gate of the second PMOS tube.
3. The analog quantity measurement circuit according to claim 1, characterized in that: The positive low voltage switch circuit comprises: a third PMOS tube, a fourth PMOS tube, a third level conversion circuit and a fourth level conversion circuit; The source and substrate of the third PMOS tube are connected to the test pin of the chip; The source and substrate of the fourth PMOS tube are connected to the output end of the positive low voltage to be measured, and the drain of the fourth PMOS tube is connected to the drain of the third PMOS tube; The first input end of the third level conversion circuit is connected to the control circuit, the second input end is connected to the test pin of the chip, and the second output end is connected to the gate of the third PMOS tube; The first input end of the fourth level conversion circuit is connected to the control circuit, the second input end is connected to the output end of the positive low voltage to be measured, and the second output end is connected to the gate of the fourth PMOS tube.
4. The analog quantity measurement circuit according to claim 1, characterized in that: The analog switch circuit includes: a first NMOS tube and a fifth level conversion circuit; The source of the first NMOS tube is connected to the test pin of the chip, and the drain of the first NMOS tube is connected to the output end of the analog quantity to be measured; The first input terminal of the fifth level conversion circuit is connected to the control circuit, the second input terminal is connected to the output terminal of the positive low voltage to be measured, and the first output terminal is connected to the gate of the first NMOS tube.
5. The analog quantity measuring circuit according to any one of claims 1 to 4, characterized in that: Also includes: Pull-up circuit; The output end of the pull-up circuit is connected to the test pin of the chip to reduce the electromagnetic interference received by the test pin of the chip when it is in a suspended state.
6. The analog quantity measuring circuit according to claim 5, characterized in that: The pull-up circuit includes: a pull-up power supply and a second NMOS tube; The gate of the second NMOS tube is connected to the control circuit, the source of the second NMOS tube is connected to the pull-up power supply, and the drain of the second NMOS tube is connected to the test pin of the chip.
7. The analog quantity measuring circuit according to any one of claims 1 to 4, characterized in that: Also includes: Protection circuit; The input end of the protection circuit is connected to the test pin of the chip, and the output end is connected to the ground line.
8. The analog quantity measuring circuit according to claim 7, characterized in that: The protection circuit includes: a third NMOS tube and a protection resistor; The source of the third NMOS tube is connected to the test pin of the chip, and the drain of the third NMOS tube is connected to the ground line; One end of the protection resistor is connected to the gate of the third NMOS transistor, and the other end is connected to the drain of the third NMOS transistor.
9. The analog quantity measuring circuit according to any one of claims 1 to 4, characterized in that: The control circuit is a logic control circuit or a microcontroller.
10. An analog quantity measuring device for a chip, characterized in that: include: Equipment body; The analog quantity measurement circuit for a chip as claimed in any one of claims 1 to 9 is arranged in a device body.