PSRR optimization circuit and low dropout regulator chip

Abstract

The invention discloses a PSRR optimization circuit, which relates to the technical field of integrated circuits, and is characterized by comprising an NMOS (N-channel metal oxide semiconductor) tube NM1, M NMOS tubes connected in series, an NMOS tube NM2, an NMOS tube NM3,..., an NMOS tube NMM, an NMOS tube NMM + 1, a PMOS tube PM1, a PMOS tube PM2, a PMOS tube PM3, a PMOS tube PM4, a PMOS tube PM5, N NMOS depletion tubes connected in series, an NMOS depletion tube NMOS1, an NMOS depletion tube NMOS2,..., an NMOS depletion tube NMOSN-1, an NMOS depletion tube NSN, a resistor R1, a resistor R2 and a capacitor C1, the invention further discloses a low dropout regulator chip which is provided with the PSRR optimization circuit. According to the invention, the influence of layout parasitic capacitance is eliminated, and the PSRR is obviously improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a PSRR optimization circuit and a low voltage drop linear regulator chip. Background Art

[0002] In recent years, consumer electronic products such as smart phones, PDAs, portable devices, and medical equipment have shown a growing trend. The operation of these electronic devices is inseparable from the power supply, and the power management chip is the "bridge" connecting the power supply to the circuit. As a type of power management chip, the low-dropout linear regulator has the characteristics of high PSRR (power supply rejection ratio) and low noise, which is very suitable for driving these consumer electronic products.

[0003] The traditional low voltage drop linear regulator consists of an error amplifier A1, a power tube P OW , feedback resistor R A and R B And the load capacitance C L Since the reference voltage is V Ref The output voltage is fixed, so the feedback coefficient of the resistor feedback network is also fixed. PSRR is an important indicator of low-dropout linear regulators, which characterizes the ability of low-dropout linear regulators to suppress external power supply noise. From the traditional low-dropout linear regulator architecture, it can be seen that the PSRR of the low-dropout linear regulator is mainly determined by the amplifier's gain at low frequency, and the continuous improvement of the error amplifier A1 requires more cascaded gain stages, making the amplifier structure and its compensation method more complex and difficult to implement, and is seriously affected by the layout design. Due to the influence of the layout parasitic capacitance, the PSRR indicator becomes very poor.

[0004] Therefore, technicians in this field are committed to developing a PSRR optimization circuit and a low-dropout linear regulator chip. Summary of the invention

[0005] In view of the above-mentioned defects of the prior art, the technical problem to be solved by the present invention is how to optimize the PSRR index without being affected by the layout design.

[0006] Through research, it is found that the power supply enters the circuit through a diode-connected NMOS tube M1, so that the gate and source voltages of N series-connected NMOS tubes are grounded as a reference voltage and compensated by a capacitor C1, which can greatly improve the PSRR and is not affected by the layout design.

[0007] In one embodiment of the present invention, a PSRR optimization circuit is provided, comprising an NMOS tube NM1, M NMOS tubes connected in series, including an NMOS tube NM2, an NMOS tube NM3, ..., NMOS tube NM4, ..., NMOS tube NM5, ..., NMOS tube NM6, ..., NMOS tube NM7, ..., NMOS tube NM8, ..., NMOS tube NM9, ..., NMOS tube NM10, ..., NMOS tube NM11, ..., M 、NMOS tube NMM+1 , PMOS tube PM1, PMOS tube PM2, PMOS tube PM3, PMOS tube PM4, PMOS tube PM5, N series-connected NMOS power consumption, including NMOS power consumption NMOS1, NMOS power consumption NMOS2, ..., NMOS power consumption NMOS N-1 、NMOS consumption N , resistor R1, resistor R2 and capacitor C1; The gate and drain of NMOS tube NM1, one end of capacitor C1, and the source of PMOS tube PM5 are all connected to the power supply voltage VDD, the source of NMOS tube NM1 is connected to the source of PMOS tube PM1 and PMOS tube PM2, the gates of PMOS tube PM1 and PMOS tube PM2 are connected to the drain of PMOS tube PM3, the other end of capacitor C1, and the drain of NMOS tube NMOS1 are connected, the drain of PMOS tube PM1 is connected to the source of PMOS tube PM3, the gate of PMOS tube PM3 is connected to the gate of PMOS tube PM4, and connected to VDD. b1 , N series NMOS power consumption is not limited to the gate, NMOS power consumption is not limited to the NMOS N The source of NMOS tube NM M+1 The source of NMOS1 and one end of resistor R2 are connected together to GND, the source of NMOS1 is connected to the drain of NMOS2, the source of NMOS2 is connected to the drain of NMOS3, and so on. N-1 The source and NMOS consumption of NMOS N The drain of the PMOS tube PM2 is connected to the source of the PMOS tube PM4, the drain of the PMOS tube PM4 is connected to the drain of the NMOS tube NM2, the NMOS tube NM2, the NMOS tube NM3, ..., the NMOS tube NM M+1 The gate of NMOS tube NM2 is connected to one end of resistor R1 and the other end of resistor R2, the source of NMOS tube NM2 is connected to the drain of NMOS tube NM3, the source of NMOS tube NM3 is connected to the drain of NMOS tube NM4, and so on. M The source of the NMOS tube NM M+1 The drain of PMOS tube PM5 is connected to V b2 , the drain of the PMOS tube PM5 is connected to the other end of the resistor R1.

[0008] Optionally, in the PSRR optimization circuit of the above embodiment, the channel length of the NMOS tube M1 is greater than or equal to 10 um and less than or equal to 20 um.

[0009] Preferably, in the PSRR optimization circuit of the above embodiment, the channel length of the NMOS transistor M1 is equal to 15 um.

[0010] Optionally, in the PSRR optimization circuit of any of the above embodiments, M is greater than or equal to 8 and less than or equal to 20.

[0011] Preferably, in the PSRR optimization circuit of the above embodiment, M is equal to 12.

[0012] Optionally, in the PSRR optimization circuit of any of the above embodiments, the channel length of the M series-connected NMOS tubes is greater than or equal to 10 um and less than or equal to 20 um.

[0013] Preferably, in the PSRR optimization circuit of the above embodiment, the channel length of the M series-connected NMOS tubes is equal to 15 um.

[0014] Furthermore, in the PSRR optimization circuit of the above embodiment, the width and length of the channels of the M series-connected NMOS transistors are equal.

[0015] Optionally, in the PSRR optimization circuit of any of the above embodiments, N is greater than or equal to 8 and less than or equal to 20.

[0016] Preferably, in the PSRR optimization circuit of the above embodiment, N is equal to 12.

[0017] Optionally, in the PSRR optimization circuit of any of the above embodiments, a channel length of the N series-connected NMOS transistors is greater than or equal to 10 um and less than or equal to 20 um.

[0018] Preferably, in the PSRR optimization circuit of the above embodiment, the channel length of the N series-connected NMOS transistors is equal to 15 um.

[0019] Furthermore, in the PSRR optimization circuit of the above embodiment, the width and length of the channels of the N series-connected NMOS transistors are equal.

[0020] Optionally, in the PSRR optimization circuit of any of the above embodiments, the value of the capacitor C1 is greater than or equal to 1 pF and less than or equal to 2 pF.

[0021] Preferably, in the PSRR optimization circuit of the above embodiment, the value of the capacitor C1 is equal to 1.5 pF.

[0022] Based on the above embodiments, in another embodiment of the present invention, a low voltage dropout linear regulator chip is provided. The low voltage dropout linear regulator chip is provided with the PSRR optimization circuit in any of the above embodiments.

[0023] The present invention improves the prior art, grounds the gates of N series-connected NMOS transistors, significantly suppresses ripple, and outputs a gate voltage of M series-connected NMOS transistors that is clamped and then divided by resistors R1 and R2 to obtain a voltage. By introducing NMOS transistor NM1 and capacitor C1, the influence of layout parasitic capacitance is eliminated, significantly improving PSRR.

[0024] The concept, specific structure and technical effects of the present invention will be further described below in conjunction with the accompanying drawings to fully understand the purpose, characteristics and effects of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a schematic diagram illustrating a conventional low dropout linear regulator architecture circuit according to an exemplary embodiment; Figure 2 is a structural schematic diagram illustrating a PSRR optimization circuit according to an exemplary embodiment; Figure 3 is a schematic diagram illustrating the structure of a low dropout linear regulator chip according to an exemplary embodiment. DETAILED DESCRIPTION

[0026] The following describes several preferred embodiments of the present invention with reference to the drawings in the specification, so that the technical content is clearer and easier to understand. The present invention can be embodied in many different forms of embodiments, and the protection scope of the present invention is not limited to the embodiments mentioned in the text.

[0027] In the drawings, components with the same structure are indicated by the same numerical reference numerals, and components with similar structures or functions are indicated by similar numerical reference numerals. The size and thickness of each component shown in the drawings are arbitrarily shown, and the present invention does not limit the size and thickness of each component. In order to make the illustration clearer, the thickness of the components is schematically exaggerated in some places in the drawings.

[0028] like Figure 1 As shown, the conventional low voltage dropout linear regulator includes an error amplifier A1, a power tube P OW , feedback resistor R A and R B And the load capacitance C L , because the reference voltage is V Ref is a fixed value, the output voltage is fixed, so the feedback coefficient of the resistor feedback network is also fixed. Through analysis, it can be seen that the PSRR of the traditional low-dropout linear regulator is determined by the amplifier's gain at low frequency. Continuously improving the error amplifier A1 requires cascading more gain stages, making the amplifier structure and its compensation method more complex and difficult to implement, and is seriously affected by the layout design. Due to the influence of the layout parasitic capacitance, the PSRR index becomes very poor.

[0029] This embodiment designs a PSRR optimization circuit, such as Figure 2 As shown, it includes: an NMOS tube NM1, M NMOS tubes connected in series, including an NMOS tube NM2, an NMOS tube NM3, ..., NMOS tube NM M 、NMOS tube NM M+1 , PMOS tube PM1, PMOS tube PM2, PMOS tube PM3, PMOS tube PM4, PMOS tube PM5, N series-connected NMOS power consumption, including NMOS power consumption NMOS1, NMOS power consumption NMOS2, ..., NMOS power consumption NMOS N-1 、NMOS consumption N , resistor R1, resistor R2 and capacitor C1; among them, the channel length of NMOS tube M1 is equal to 15um; M is 12, the channel length of 12 NMOS tubes connected in series is equal to 15, and the channel width and length of 12 NMOS tubes connected in series are equal; N is equal to 12, the channel length of 12 NMOS tubes connected in series is equal to 15um, and the channel width and length of 12 NMOS tubes connected in series are equal; the value of capacitor C1 is equal to 1.5pF.

[0030] The gate and drain of NMOS tube NM1, one end of capacitor C1, and the source of PMOS tube PM5 are all connected to the power supply voltage VDD, the source of NMOS tube NM1 is connected to the source of PMOS tube PM1 and PMOS tube PM2, the gates of PMOS tube PM1 and PMOS tube PM2 are connected to the drain of PMOS tube PM3, the other end of capacitor C1, and the drain of NMOS tube NMOS1 are connected, the drain of PMOS tube PM1 is connected to the source of PMOS tube PM3, the gate of PMOS tube PM3 is connected to the gate of PMOS tube PM4, and connected to VDD. b1 , 12 NMOS in series, the gate, NMOS, and NMOS 12 The source of NMOS tube NM 13 The source of NMOS1 and one end of resistor R2 are connected together to GND, the source of NMOS1 is connected to the drain of NMOS2, the source of NMOS2 is connected to the drain of NMOS3, and so on. 11 The source and NMOS consumption of NMOS 12 The drain of the PMOS tube PM2 is connected to the source of the PMOS tube PM4, the drain of the PMOS tube PM4 is connected to the drain of the NMOS tube NM2, the NMOS tube NM2, the NMOS tube NM3, ..., the NMOS tube NM 13The gate of NMOS tube NM2 is connected to one end of resistor R1 and the other end of resistor R2, the source of NMOS tube NM2 is connected to the drain of NMOS tube NM3, the source of NMOS tube NM3 is connected to the drain of NMOS tube NM4, and so on. 12 The source of the NMOS tube NM 13 The drain of PMOS tube PM5 is connected to V b2 , the drain of the PMOS tube PM5 is connected to the other end of the resistor R1.

[0031] Based on the above embodiment, the effect is verified by grounding the gate voltage of 12 NMOS power consumption tubes connected in series. When the width-to-length ratio of the 12 NMOS power consumption tubes connected in series is fixed, the current is a constant value, and the current mirror mirrors this current to the 12 NMOS tubes connected in series. When the width-to-length ratio of the 12 NMOS tubes connected in series is fixed, the gate voltage of the 12 NMOS tubes connected in series is a constant value. The output OUT is determined by resistor voltage division. When there is ripple in the power supply VDD, the gate of the 12 NMOS power consumption tubes connected in series is grounded, which significantly suppresses the ripple. The output is clamped by the gate voltage of the 12 NMOS tubes connected in series, and is obtained by voltage division by resistors R1 and R2, which can significantly improve the PSRR. , it is 72dB at 1KHz, but in the layout matching, since the drain impedance of NMOS1 to the ground is large, there is a very small parasitic capacitance to the ground at the drain of NMOS1, ranging from tens of fF to two hundred fF. At this time, a main pole will be introduced, resulting in a significant reduction in the PSRR index. At 1KHz, it is only 50dB. The NMOS tube M1 and capacitor C1 in the circuit will introduce a zero point to eliminate the influence of the parasitic capacitance caused by the layout matching. The PSRR is 72dB at 1KHz. The introduction of NMOS tube M1 and capacitor C1 improves the PSRR index and makes it unaffected by the layout matching.

[0032] Based on the above embodiments, this embodiment provides a low voltage drop linear regulator chip, such as Figure 2 As shown, the low voltage drop linear regulator chip is provided with the PSRR optimization circuit in any of the above embodiments.

[0033] The preferred specific embodiments of the present invention are described in detail above. It should be understood that a person skilled in the art can make many modifications and changes based on the concept of the present invention without creative work. Therefore, any technical solution that can be obtained by a person skilled in the art through logical analysis, reasoning or limited experiments based on the concept of the present invention on the basis of the prior art should be within the scope of protection determined by the claims.

Claims

1. A PSRR optimization circuit, characterized in that: include: NMOS tube NM1, M NMOS tubes connected in series, including NMOS tube NM2, NMOS tube NM3, ..., NMOS tube NM M 、NMOS tube NM M+1 , PMOS tube PM1, PMOS tube PM2, PMOS tube PM3, PMOS tube PM4, PMOS tube PM5, N series-connected NMOS power consumption, including NMOS power consumption NMOS1, NMOS power consumption NMOS2, ..., NMOS power consumption NMOS N-1 、NMOS consumption N , resistor R1, resistor R2 and capacitor C1; The gate and drain of the NMOS tube NM1, one end of the capacitor C1, and the source of the PMOS tube PM5 are all connected to the power supply voltage VDD, the source of the NMOS tube NM1 is connected to the source of the PMOS tube PM1 and the PMOS tube PM2, the gates of the PMOS tube PM1 and the PMOS tube PM2 are connected to the drain of the PMOS tube PM3, the other end of the capacitor C1, and the drain of the NMOS tube NMOS1, the drain of the PMOS tube PM1 is connected to the source of the PMOS tube PM3, the gate of the PMOS tube PM3 is connected to the gate of the PMOS tube PM4, and VDD is connected to the gate of the PMOS tube PM4. b1 , the N series-connected NMOS power consumption gate, the NMOS power consumption NMOS N The source of the NMOS tube NM M+1 The source of the NMOS consumption NMOS1 and one end of the resistor R2 are connected together to GND, the source of the NMOS consumption NMOS1 is connected to the drain of the NMOS consumption NMOS2, the source of the NMOS consumption NMOS2 is connected to the drain of the NMOS consumption NMOS3, and so on. N-1 The source of the NMOS consumes N The drain of the PMOS tube PM2 is connected to the source of the PMOS tube PM4, the drain of the PMOS tube PM4 is connected to the drain of the NMOS tube NM2, the NMOS tube NM2, the NMOS tube NM3, ..., the NMOS tube NM M+1 The gate of the NMOS tube NM2 is connected to one end of the resistor R1 and the other end of the resistor R2, the source of the NMOS tube NM2 is connected to the drain of the NMOS tube NM3, the source of the NMOS tube NM3 is connected to the drain of the NMOS tube NM4, and so on. M The source of the NMOS tube NM M+1 The drain of the PMOS tube PM5 is connected to V b2 , the drain of the PMOS tube PM5 is connected to the other end of the resistor R1.

2. The PSRR optimization circuit according to claim 1, characterized in that: The channel length of the NMOS tube M1 is greater than or equal to 10 um and less than or equal to 20 um.

3. The PSRR optimization circuit according to claim 1, characterized in that: The M is greater than or equal to 8 and less than or equal to 20.

4. The PSRR optimization circuit as claimed in claim 3, characterized in that: The channel length of the M series-connected NMOS tubes is greater than or equal to 10 um and less than or equal to 20 um.

5. The PSRR optimization circuit as claimed in claim 4, characterized in that: The width and length of the channels of the M series-connected NMOS tubes are equal.

6. The PSRR optimization circuit according to claim 1, characterized in that: The N is greater than or equal to 8 and less than or equal to 20.

7. The PSRR optimization circuit according to claim 6, characterized in that: The channel length of the N series-connected NMOS transistors is greater than or equal to 10 um and less than or equal to 20 um.

8. The PSRR optimization circuit according to claim 7, characterized in that: The width and length of the channels of the N series-connected NMOS transistors are equal.

9. The PSRR optimization circuit according to claim 1, characterized in that: The value of the capacitor C1 is greater than or equal to 1 pF and less than or equal to 2 pF.

10. A low voltage dropout linear regulator chip, characterized in that: A PSRR optimization circuit as described in any one of claims 1 to 9 is provided.

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