Flash memory classification method and memory chip

Abstract

The invention provides a flash memory classification method and a storage chip, and belongs to the technical field of storage. The data storage method comprises the following steps of: reading, writing and erasing a flash memory for multiple times at a preset temperature; scoring a plurality of performance parameters when each flash memory block is read, written and erased; multiplying the score of each performance parameter by the weight, and adding the products of the scores and the weights of all the performance parameters to obtain the total score of the performance parameters of each flash memory block; according to the performance parameter total score of each flash memory block, dividing the flash memory block into a good block, a bad block and a weak block; wherein the total score of the performance parameters of the weak blocks is larger than the total score of the performance parameters of the bad blocks, the total score of the performance parameters of the weak blocks is smaller than the total score of the performance parameters of the good blocks, and the bad blocks are used as single-layer storage units. According to the flash memory classification method and the data storage system provided by the invention, the storage capacity of the storage chip can be improved.

Description

Technical Field

[0001] The present invention belongs to the field of storage technology, and in particular relates to a flash memory classification method and a storage chip. Background Art

[0002] Before the memory chip leaves the factory, it will be tested and the flash memory blocks in the memory chip will be divided into good blocks and bad blocks according to the test results. The bad blocks include factory bad blocks and newly added bad blocks with poor performance. After a flash memory block is confirmed to be a bad block, it will not be used in the subsequent use of the product.

[0003] However, as the capacity of the memory chip increases, the number of new bad blocks in the memory chip gradually increases, which reduces the actual data storage capacity of the memory chip and further affects the performance of the memory chip. Summary of the invention

[0004] The object of the present invention is to provide a flash memory classification method and a storage chip, which can solve the problem that too many newly added bad blocks affect the storage capacity of the storage chip.

[0005] To achieve the above object, the present invention provides a flash memory classification method and a storage chip, and the flash memory classification method at least includes the following steps: Read, write and erase the flash memory multiple times at a preset temperature; Scoring multiple performance parameters for each flash block when reading, writing, and erasing; Multiplying the score of each performance parameter by the weight, and adding the product of the scores of all performance parameters and the weight to obtain a total performance parameter score of each flash memory block; and According to the total score of the performance parameter of each flash memory block, the flash memory blocks are divided into good blocks, bad blocks and weak blocks; Among them, the total score of the performance parameters of the weak block is greater than the total score of the performance parameters of the bad block, and the total score of the performance parameters of the weak block is less than the total score of the performance parameters of the good block, and the bad block is used as a single-layer storage unit.

[0006] In one embodiment of the present invention, the multiple performance parameters include average erase time, average write time, average read time, number of erase failures, number of write failures, number of read failures and average number of read error bits.

[0007] In one embodiment of the present invention, the flash memory classification method also includes the following steps: setting a classification standard for the flash memory blocks, and comparing the total score of the performance parameters of each flash memory block with the classification standard to distinguish the flash memory blocks into good blocks, bad blocks and weak blocks.

[0008] In one embodiment of the present invention, the flash memory classification method further includes the following steps: Setting a first threshold and a second threshold, wherein the second threshold is greater than the first threshold; When the total score of the performance parameters of the flash memory block is greater than or equal to the second threshold, the flash memory block is the good block; when the total score of the performance parameters of the flash memory block is less than the second threshold and greater than the first threshold, the flash memory block is the weak block; when the total score of the performance parameters of the flash memory block is less than the first threshold, the flash memory block is the bad block.

[0009] In one embodiment of the present invention, when the flash memory block is a multi-layer storage unit, a triple-layer storage unit or a quad-layer storage unit, the flash memory block is used as a pseudo single-layer storage unit.

[0010] In an embodiment of the present invention, non-essential information of the storage chip is stored in the weak block.

[0011] In an embodiment of the present invention, the flash memory classification method further includes the following steps: according to the score of the weak block, setting the maximum erasure times of each weak block.

[0012] In one embodiment of the present invention, the maximum erasure count of the weak block is inversely proportional to the score of the weak block.

[0013] In one embodiment of the present invention, the maximum erasure count of the weak block is less than the maximum erasure count of the good block, and the maximum erasure count of the weak block is greater than the maximum erasure count of the bad block.

[0014] The present invention also provides a storage chip, in which the good blocks, the bad blocks and the weak blocks are obtained by any one of the flash memory classification methods described above.

[0015] In summary, the present invention provides a flash memory classification method and a storage chip, which distinguishes between bad blocks in normal use and completely unusable bad blocks through the total score of the performance parameters of the flash memory blocks, and the weak blocks that are available and less stable than the good blocks, thereby expanding the storage capacity of the storage chip. At the same time, the weak blocks are used as single-layer storage units and store non-essential information of the storage chip, thereby ensuring that the stability of the weak blocks does not affect the security of the storage chip data. Finally, the maximum number of erase times of the weak blocks is set according to the total score of the performance parameters of the weak blocks to ensure the stability of the weak blocks during their service life. Therefore, through the flash memory classification method provided by the present application, the storage capacity of the storage chip is increased without affecting the basic performance of the storage chip, thereby improving the competitiveness of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0017] Figure 1 It is a schematic diagram of the structure of a storage chip in one embodiment of the present application.

[0018] Figure 2 It is a flow chart of a flash memory classification method in one embodiment of the present application.

[0019] Figure 3 It is a schematic diagram of the structure of an electronic device in one embodiment of the present application. DETAILED DESCRIPTION

[0020] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thoroughly and comprehensively understood.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0022] In the description of the present invention, it should be understood that the orientations or positional relationships indicated by the terms "center", "upper", "lower", "front", "back", "left", "right", etc. are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. The degrees indicated by "high" and "low" are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or component referred to must have high and low, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0023] See also Figure 1As shown, compared with traditional magnetic disks, the storage chip 200 using Nand flash memory as the storage medium has the characteristics of non-volatility, fast read and write speed, shock resistance, low power consumption, and small size. It has been widely used in embedded systems, consumer electronics, aerospace and other fields. According to the different protocols of communication between the storage chip 200 and the host 100, it can be divided into embedded memory standard specifications (Embedded Multi Media Card, eMMC), universal flash storage (Universal Flash Storage, UFS), serial hard disk (Serial ATA, SATA) and high-speed serial computer expansion bus standard (peripheral component interconnect express, PCIe), etc.

[0024] See also Figure 1 As shown, in the memory chip 200, a controller 201 and a non-volatile memory unit 202 are provided. The controller 201 can execute a plurality of logic gates or control instructions implemented in hardware or firmware, and perform operations such as writing, reading and erasing data in the non-volatile memory unit 202 according to the instructions of the host 100. Among them, the non-volatile memory unit 202 includes a plurality of flash memory blocks 203, and the flash memory blocks 203 may belong to the same memory die or to different memory die. And the flash memory blocks 203 are composed of single-level cells (SLC), multi-level cells (MLC), triple-level cells (Triple Level Cell), quad-level cells (QLC) or a combination of two or more of these cells. Among them, a single-layer storage unit can store, for example, 1 bit (one data unit) of data, a multi-layer storage unit can store, for example, 2 bits (two data units) of data, a triple-layer storage unit can store, for example, 3 bits (three data units) of data, and a quad-layer storage unit can store, for example, 4 bits (four data units) of data. Compared with single-layer storage units and multi-layer storage units, triple-layer storage units and quad-layer storage units store larger amounts of data, but have shorter erase and write lifespans and relatively poor read and write performances.

[0025] See also Figure 1 and Figure 2As shown, in one embodiment of the present invention, before the memory chip 200 leaves the factory, the memory chip 200 will be tested to detect bad blocks of the memory chip 200. Among them, some bad blocks are bad blocks when the solid-state drive 20 leaves the factory. And during the use of the solid-state drive 20, when the flash memory block 203 is erased and written too many times, it may cause permanent damage to the flash memory block 203 and the appearance of new bad blocks. However, this method of marking bad blocks will cause the actual storage capacity of the memory chip 200 to be significantly reduced. The present application provides a flash memory classification method, which classifies the flash memory blocks 203 and can increase the storage capacity of the memory chip 200. Specifically includes steps S101 to S104.

[0026] Step S101: read, write and erase the flash memory multiple times at a preset temperature.

[0027] Step S102: Score multiple performance parameters of each flash memory block when reading, writing and erasing.

[0028] Step S103: Obtain the total performance parameter score of each flash memory block according to the score and weight of the performance parameter.

[0029] Step S104: setting a classification standard for the flash memory blocks, and classifying the flash memory blocks into good blocks, weak blocks and bad blocks according to the relationship between the total score of the performance parameters of each flash memory block and the classification standard.

[0030] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, in step S101, the preset temperature is a high temperature environment of, for example, 100° C. In the high temperature environment, the host 100 reads, writes, and erases the flash memory in the storage chip 200, and classifies the flash memory according to the performance parameters of the flash memory block 203 during the reading, writing, and erasing processes.

[0031] See also Figure 1 and Figure 2As shown, in one embodiment of the present invention, in step S102, the multiple performance parameters of each flash memory block 203 during reading, writing and erasing include the average erase time, the average write time, the average read time, the number of erase failures, the number of write failures, the number of read failures and the average number of read error bits. In other embodiments, the performance parameters of each flash memory block 203 during reading, writing and erasing may also include other related performance parameters, and this application only uses seven common performance parameters as examples for illustration. When obtaining the scores of the multiple performance parameters of each flash memory block 203 during reading, writing and erasing, the score may be scored using a percentage system. And the shorter the average erase time, the average write time and the average read time, the higher the score of the average time, the average write time and the average read time. And the fewer the number of erase failures, the number of write failures, the number of read failures and the average number of read error bits, the higher the score of the number of erase failures, the number of write failures, the number of read failures and the average number of read error bits. That is, the larger the score of each performance parameter of each flash memory block 203, the more stable the performance of the flash memory block 203, and the better the quality of the flash memory block 203.

[0032] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, in step S103, after obtaining the scores of multiple performance parameters of each flash memory block 203 during reading, writing and erasing in a high temperature environment, the total score of the performance parameters of each flash memory block 203 is obtained through the scores and weights of the multiple performance parameters. First, the weight of each performance parameter is set. In this embodiment, seven performance parameters correspond to seven weights. The average erase time has a first weight R1%, the average write time has a second weight R2%, the average read time has a third weight R3%, the number of erase failures has a fourth weight R4%, the number of write failures has a fifth weight R5%, the number of read failures has a sixth weight R6%, and the average number of read error bits has a seventh weight R7%. Among them, the sum of the weights of multiple performance parameters is 100%. In this embodiment, the sum of the first weight R1%, the second weight R2%, the third weight R3%, the fourth weight R4%, the fifth weight R5%, the sixth weight R6% and the seventh weight R7% is 100%, and the specific values ​​of the first weight R1%, the second weight R2%, the third weight R3%, the fourth weight R4%, the fifth weight R5%, the sixth weight R6% and the seventh weight R7% can be set according to the requirements. In one embodiment of the present invention, the values ​​of the first weight R1%, the second weight R2%, the third weight R3%, the fourth weight R4%, the fifth weight R5% and the sixth weight R6% are, for example, 15%, and the value of the seventh weight R7% is, for example, 10%. In another embodiment of the present invention, the values ​​of the first weight R1%, the second weight R2%, the third weight R3%, the fourth weight R4%, the fifth weight R5% and the sixth weight R6% are, for example, 10%, and the value of the seventh weight R7% is, for example, 40%.

[0033] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, after obtaining the scores of multiple performance parameters of each flash memory block 203 during the reading, writing and erasing process in a high temperature environment and confirming the weight of each performance parameter, the score of each performance parameter is multiplied by the weight of each performance parameter, and the product of the scores of all performance parameters and the weight is added to obtain the total score of the performance parameters of each flash memory block 203. Specifically, in this embodiment, the score of the average erase time is X1, the score of the average write time is X2, the score of the average read time is X3, the score of the number of erase failures is X4, the score of the number of write failures is X5, the score of the number of read failures is X6, and the score of the average number of read error bits is X7. Then the total performance parameter score Y of each flash memory block 203 is obtained by the following formula: Y=R1%×X1+R2%×X2+R3%×X3+R4%×X4+R5%×X5+R6%×X6+R7%×X7.

[0034] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, after obtaining the total score of the performance parameters of each flash memory block 203, the classification standard of the flash memory block 203 is set, the total score of the performance parameters of the flash memory block 203 is compared with the classification standard, and the flash memory block 203 is divided into a good block, a weak block and a bad block. In this embodiment, two thresholds are set, namely a first threshold and a second threshold, and the second threshold is much larger than the first threshold. When the total score of the performance parameters of the flash memory block 203 is greater than or equal to the second threshold, the flash memory block 203 is classified as a good block. When the total score of the performance parameters of the flash memory block 203 is less than the second threshold and greater than the first threshold, the flash memory block 203 is classified as a weak block. When the total score of the performance parameters of the flash memory block 203 is less than or equal to the first threshold, the flash memory block 203 is classified as a bad block. In one embodiment of the present invention, the first threshold is, for example, 0, and the second threshold is, for example, 100. That is, in this embodiment, when the average erase time, average write time, average read time, number of erase failures, number of write failures, number of read failures and average number of read error bits of the flash memory block 203 meet the standard of a good block, the average erase time, average write time, average read time, number of erase failures, number of write failures, number of read failures and average number of read error bits are scored as full marks, i.e., 100 points. When the average erase time, average write time, average read time, number of erase failures, number of write failures, number of read failures and average number of read error bits of the flash memory block 203 are the same as the standard of a factory bad block, the average erase time, average write time, average read time, number of erase failures, number of write failures, number of read failures and average number of read error bits are scored as zero points, i.e., 0 points. In other embodiments, the range of the first threshold is 10-30, specifically, for example, 10, 15, 20, 25 or 30, etc. The range of the second threshold is 80-90, specifically, for example, 90, 85 or 80, etc.

[0035] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, when the flash memory block 203 is a good block, the flash memory block 203 can be used normally. When the flash memory block 203 is a bad block, the flash memory block 203 is a newly added bad block that cannot be used. When the flash memory block 203 is a weak block, the flash memory block 203 is used as a single-layer storage unit. In this embodiment, when the flash memory block 203 is a single-layer storage unit, the flash memory block 203 is used normally. When the flash memory block 203 is a multi-layer storage unit, a three-layer storage unit or a four-layer storage unit, the flash memory block 203 is used as a pseudo single-layer storage unit (Pseudo Single Level Cell, pSLC). Because the stability of the flash memory block 203 in the single-layer storage unit mode is higher than that of the flash memory block 203 in the multi-layer storage unit, the three-layer storage unit or the four-layer storage unit mode. The performance of the weak block is not very stable. Using the weak block as a single-layer storage unit can ensure the stability of the data stored in the weak block.

[0036] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, non-essential information of the storage chip 200 is stored in the weak block. Among them, the non-essential information includes, for example, log information and debugging information. Compared with the flash memory block 203 of the multi-layer storage unit, the three-layer storage unit or the four-layer storage unit, the flash memory block 203 of the single-layer storage unit has higher stability, so the most important information, such as important information such as storage mapping table or storage firmware, will be stored in the flash memory block 203 of the single-layer storage unit. Although the weak block is used as a single-layer storage unit, the performance of the weak block is not very stable compared to the good block, so the weak block will be used to store non-essential information. At this time, it will not have a negative impact on the storage chip 200, and at the same time, the number of newly added bad blocks is reduced, and the utilization rate of the flash memory block 203 is improved.

[0037] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, the classification method of flash memory also includes setting the maximum number of erasures of each weak block according to the score of each weak block. Among them, the maximum number of erasures of weak blocks is inversely proportional to the score of weak blocks, that is, the higher the score of weak blocks, the greater the maximum number of erasures of weak blocks. The maximum number of erasures of flash memory block 203 reflects the life of flash memory block 203. The greater the number of erasures of flash memory block 203, the longer the life of flash memory block 203. When the memory chip 200 leaves the factory, the maximum number of erasures of all good blocks will be uniformly set, and a uniform life will be set. In the present application, for weak blocks, the maximum number of erasures of all weak blocks is not uniformly set, but the maximum number of erasures of weak blocks is set according to the score of weak blocks, which can avoid excessive use of weak blocks and cause loss of data stored in weak blocks.

[0038] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, the maximum number of erasures of all good blocks is, for example, 5000 times, and the maximum number of erasures of bad blocks is, for example, 0 times, that is, the bad blocks are completely unusable. In this embodiment, the second threshold is 100, and the first threshold is 0, then the maximum number of erasures of good blocks with a score of 100 is 5000, and the maximum number of erasures of bad blocks with a score of 0 is 0. The score of the weak block is less than 100 and greater than 0. The maximum number of erasures of the weak block is also less than the maximum number of erasures of the good block and greater than the maximum number of erasures of the bad block, and as the weak score decreases, the maximum number of erasures of the weak block decreases. In this embodiment, for every 1 point reduction in the score of the weak block, the maximum number of erasures of the weak block decreases by 50. That is, the maximum number of erasures of the weak block with a score of 99 is 4950, and so on, the maximum number of erasures of the weak block with a score of 1 is 50, and the maximum number of erasures of the weak block with a score of 2 is 100. Therefore, the weak blocks with lower scores will stop being used after fewer erasures. Weak blocks with higher scores will stop being used only after a greater number of erasures, thus ensuring the quality of unstable weak blocks within the maximum number of erasures, thus preventing the instability of weak blocks from being exposed.

[0039] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, if there are a total of, for example, 1000 flash memory blocks 203 in the storage chip 200, there are, for example, 900 good blocks, 20 bad blocks, and 80 weak blocks. And the flash memory block 203 is a three-layer storage unit, and the storage space of each flash memory block 203 is, for example, 1GB. At this time, if all weak blocks are regarded as newly added bad blocks, the capacity of the storage chip 200 is equal to 900×1GB, that is, 900GB. If all weak blocks are used as single-layer storage units, the capacity of the storage chip 200 is equal to 900×1GB+80×(1GB / 3), that is, 926.67GB. The utilization rate of the flash memory in the storage chip 200 is increased by (926.67-900) / 900, that is, 3%. Therefore, by dividing the flash memory block 203 into good blocks, bad blocks and weak blocks, the utilization rate of the flash memory can be improved without affecting the normal use of the storage chip 200.

[0040] See also Figure 1 As shown, the flash memory blocks 203 in the storage chip 200 provided by the present invention include good blocks, bad blocks and weak blocks formed using the above method.

[0041] See also Figure 3 As shown, the present invention provides an electronic device, which includes a processor 301, a memory 302, and a program stored in the memory 302 and executable on the processor 301, and the processor 301 executes the above-mentioned flash memory classification method.

[0042] See also Figure 3 As shown, the memory 302 includes at least one type of readable storage medium, and the readable storage medium includes a flash memory, a mobile hard disk, a multimedia card, a card-type memory (for example, SD or DX memory, etc.), a magnetic memory, a disk, an optical disk, etc. In some embodiments, the memory may be an internal storage unit of an electronic device, such as a mobile hard disk of the electronic device. In other embodiments, the memory may also be an external storage device of an electronic device, such as a plug-in mobile hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc. equipped on the electronic device. Further, the memory may also include both an internal storage unit of the electronic device and an external storage device. The memory may be used not only to store application software and various types of data installed in the electronic device, but also to temporarily store data that has been output or is to be output.

[0043] See also Figure 3 As shown, in some embodiments, the processor 301 can be composed of an integrated circuit, for example, it can be composed of a single packaged integrated circuit, or it can be composed of multiple packaged integrated circuits with the same function or different functions, including one or more central processing units (CPU), microprocessors, digital processing chips, graphics processors and a combination of various control chips.

[0044] The processor executes the operating system of the vehicle-mounted device and various installed application programs. The processor executes the application programs to implement the steps in the above method embodiment.

[0045] Exemplarily, the program may be divided into one or more modules, which are stored in the memory and executed by the processor to implement the present invention. The one or more modules may be a series of program instruction segments capable of implementing specific functions, which are used to describe the execution process of the program in the vehicle-mounted device.

[0046] The above-mentioned integrated unit implemented in the form of a software function module can be stored in a computer-readable storage medium. The above-mentioned software function module is stored in a storage medium, and includes a number of instructions for enabling a computer device (which can be a personal computer, a computer device, or a network device, etc.) or a processor to perform part of the functions of the lithium battery cold solder joint detection method of each embodiment of the present invention.

[0047] In summary, the present invention provides a flash memory classification method and a storage chip, the flash memory classification method includes the steps of reading, writing and erasing the flash memory multiple times at a preset temperature. Then, the multiple performance parameters of each flash memory block when reading, writing and erasing are scored, and the total performance parameter score of each flash memory block is obtained based on the score and weight of the performance parameter. Finally, the classification standard of the flash memory block is set, and the flash memory block is divided into good blocks, weak blocks and bad blocks based on the relationship between the total performance parameter score of each flash memory block and the classification standard. The newly added bad blocks of the storage chip are greatly reduced, and the weak blocks with less stability than the good blocks are effectively utilized, instead of setting all the flash memory blocks whose stability cannot reach the good block standard as newly added bad blocks, thereby increasing the storage capacity of the storage chip.

[0048] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A flash memory classification method, characterized in that: At least the following steps are included: Read, write and erase the flash memory multiple times at a preset temperature; Scoring multiple performance parameters for each flash block when reading, writing, and erasing; Multiplying the score of each performance parameter by the weight, and adding the product of the scores of all performance parameters and the weight to obtain a total performance parameter score of each flash memory block; as well as According to the total score of the performance parameter of each flash memory block, the flash memory blocks are divided into good blocks, bad blocks and weak blocks; Among them, the total score of the performance parameters of the weak block is greater than the total score of the performance parameters of the bad block, and the total score of the performance parameters of the weak block is less than the total score of the performance parameters of the good block, and the bad block is used as a single-layer storage unit.

2. A flash memory classification method according to claim 1, characterized in that: The multiple performance parameters include average erase time, average write time, average read time, number of erase failures, number of write failures, number of read failures and average number of read error bits.

3. A flash memory classification method according to claim 1, characterized in that: The flash memory classification method also includes the following steps: setting a classification standard for the flash memory blocks, and comparing the total score of the performance parameters of each flash memory block with the classification standard to classify the flash memory blocks into good blocks, bad blocks and weak blocks.

4. A flash memory classification method according to claim 1, characterized in that: The flash memory classification method further comprises the following steps: Setting a first threshold and a second threshold, wherein the second threshold is greater than the first threshold; When the total score of the performance parameters of the flash memory block is greater than or equal to the second threshold, the flash memory block is the good block; when the total score of the performance parameters of the flash memory block is less than the second threshold and greater than the first threshold, the flash memory block is the weak block; when the total score of the performance parameters of the flash memory block is less than the first threshold, the flash memory block is the bad block.

5. The flash memory classification method according to claim 1, characterized in that: When the flash memory block is a multi-layer storage unit, a triple-layer storage unit or a quad-layer storage unit, the flash memory block is used as a pseudo single-layer storage unit.

6. A flash memory classification method according to claim 1, characterized in that: The weak block stores non-essential information of the storage chip.

7. A flash memory classification method according to claim 1, characterized in that: The flash memory classification method further comprises the following steps: according to the score of the weak block, setting the maximum erasure times of each weak block.

8. A flash memory classification method according to claim 7, characterized in that: The maximum erasure count of the weak block is inversely proportional to the score of the weak block.

9. The flash memory classification method according to claim 7, characterized in that: The maximum erasure count of the weak block is less than the maximum erasure count of the good block, and the maximum erasure count of the weak block is greater than the maximum erasure count of the bad block.

10. A memory chip, characterized in that: The storage chip includes the good blocks, the bad blocks and the weak blocks obtained by the flash memory classification method according to any one of claims 1 to 9.

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