Load balancing processing system, method and chip

Abstract

The invention provides a load balancing processing system which at least comprises a queue unit, a storage unit, a data transfer unit, an arbitration unit, an address selector and a plurality of calculation units, and the arbitration unit is connected with the queue unit, the data transfer unit, the address selector and the calculation units through data lines. The invention also discloses a corresponding method and a chip. According to the method and the device, after the CPU sends the operands and the operator configurations of the calculation tasks to the storage unit and the queue respectively, the CPU can continue to execute other services, the data moving unit and the arbitration unit automatically complete distribution of the calculation tasks, and resources of the CPU are not occupied. The chip circuit has the advantages of load balancing and high efficiency, meanwhile, the operands and the operation results can be stored in the storage unit, the corresponding operands can be covered with the operation results, and the area of the chip circuit can be reduced.

Description

Technical Field

[0001] The present application relates to the technical field of data computing and storage, and in particular to a load balancing processing system, method and chip related to a computing unit. Background Art

[0002] In fields such as servers, data centers, and artificial intelligence, there are usually a large number of business scenarios deployed on many CPUs (processors). These business scenarios generally contain a large number of data computing scenarios, so multiple computing units are usually required to complete data calculations.

[0003] A computing unit is often an independent computing module that inputs operation configuration and operands and gives the calculation result after completing the calculation. In these scenarios, we usually face a problem: how to distribute a large number of computing tasks to each computing unit in a balanced and efficient manner without occupying a large amount of CPU resources? The usual practice is to bind a computing unit to a CPU when the CPU has a computing task, and the CPU sends the operation configuration and operands to the computing unit, and then waits for the computing unit to complete the calculation and retrieve the calculation result.

[0004] However, this existing processing method has some shortcomings: when the number of computing units is greater than the number of CPUs, some computing units will be idle, causing load imbalance; when the number of computing units is less than the number of CPUs, the CPU will be fully occupied by computing units, and other CPUs will be blocked and waiting when they have tasks, resulting in low CPU business processing efficiency. Summary of the invention

[0005] The technical problem to be solved by the present application is to provide a load balancing processing system, method and chip, which can realize load balancing of computing resources in the chip, with efficient calculation, and at the same time can reduce the area of ​​the chip circuit.

[0006] To solve the above technical problems, as one aspect of the present application, a load balancing processing system is provided, which at least includes: a queue unit, a storage unit, a data moving unit, an arbitration unit, an address selector and a plurality of computing units, wherein:

[0007] The queue unit is used to sequentially store operators, valid indication bits and priorities of computing tasks from the CPU, wherein the valid indication bits are used to indicate the valid state of the corresponding computing tasks;

[0008] The storage unit is used to store the operands of the computing tasks from the CPU and the operation results from the computing unit;

[0009] The arbitration unit is used to arbitrate according to the effective state and priority of each computing task in the queue unit and the idle state of each computing unit, and select the authorized computing task and the corresponding idle computing unit;

[0010] The data moving unit is used to read out the operator corresponding to the authorized computing task according to the arbitration result, and send it to the corresponding idle computing unit;

[0011] The address selector is used to obtain the storage address of the operand in the storage unit corresponding to the authorized computing task according to the arbitration result;

[0012] The calculation unit is used to read out the corresponding operand according to the storage address of the operation data obtained by the address selector, perform calculation processing in combination with the operator from the data moving unit, and write the calculation result to the storage unit after the calculation is completed.

[0013] The arbitration unit adopts a fair round-robin or strict priority arbitration strategy, and obtains the authorized computing task sequence number and the sequence number of the idle computing unit after arbitration.

[0014] The storage address of the operand in each computing task is related to its computing task sequence number, or is mapped one-to-one with the computing task queue;

[0015] The address selector decodes and obtains the base address of the operand in the storage unit according to at least one of the authorized computing task sequence number and the sequence number of the idle computing unit in the arbitration result, and obtains the storage address of the operand in combination with the authorized computing task sequence number.

[0016] The calculation unit writes the calculation result to the storage unit after the calculation is completed, further comprising:

[0017] The computing unit stores the computing result in the storage unit, covering the operands of the computing task.

[0018] Wherein, the computing unit is further used to modify its own state to an idle state after the computing is completed;

[0019] The queue unit is further used to modify the corresponding computing task to a completed state after the computing unit writes the computing result into the storage unit.

[0020] The computing task of the computing unit includes at least one of a modular exponentiation operation, a point multiplication operation, a point addition operation, a modular inverse operation, a modular multiplication operation, a multiplication operation and a division operation.

[0021] The arbitration unit is respectively connected with the queue unit, the data moving unit, the address selector and each calculation unit through data lines.

[0022] Accordingly, as another aspect of the present application, a load balancing processing method is also provided, which is implemented by the aforementioned system, and the method comprises the following steps:

[0023] The CPU writes the operands of the computing task into the storage unit, and writes the operator, valid indicator bit and priority of the computing task into the queue unit;

[0024] The arbitration unit arbitrates according to the effective status and priority of each computing task and the idle status of each computing unit, and selects the authorized computing task and the corresponding idle computing unit;

[0025] The data moving unit reads out the operator corresponding to the authorized computing task according to the arbitration result, and sends it to the corresponding idle computing unit;

[0026] The address selector obtains the storage address of the operand in the storage unit corresponding to the authorized computing task according to the arbitration result;

[0027] According to the storage address of the operation data obtained by the address selector, the corresponding operand is read out, combined with the operator from the data moving unit, the calculation process is performed, and the calculation result is written to the storage unit after the calculation is completed.

[0028] Among them, further include:

[0029] The arbitration unit obtains the authorized computing task sequence number and the sequence number of the idle computing unit after arbitration, wherein the strategy adopted by the arbitration unit is a fair polling or strict priority arbitration strategy.

[0030] The address selector obtains the storage address of the operand in the storage unit corresponding to the authorized computing task according to the arbitration result, further comprising:

[0031] The address selector decodes and obtains the base address of the operand in the storage unit according to at least one of the authorized computing task sequence number and the sequence number of the idle computing unit in the arbitration result, and obtains the storage address of the operand in combination with the authorized computing task sequence number;

[0032] Wherein, in the storage unit, the storage address of the operand in each computing task is related to its computing task sequence number, or is mapped one-to-one with the computing task queue.

[0033] The calculation unit writes the calculation result to the storage unit after the calculation is completed, further comprising:

[0034] The computing unit stores the computing result in the storage unit, covering the operand of the computing task;

[0035] After the calculation is completed, the computing unit changes its own state to the idle state.

[0036] Among them, further include:

[0037] After the computing unit writes the computing result into the storage unit, the queue unit modifies the corresponding computing task into a completed state.

[0038] Accordingly, as another aspect of the present application, a chip is also provided, which is deployed with the aforementioned system.

[0039] Implementing the embodiments of the present application has the following beneficial effects:

[0040] The present application provides a load balancing processing system, method and chip. The queue unit and storage unit are used to store the operators and operands of the computing tasks from the CPU respectively, and the arbitration unit performs arbitration according to the existing task volume of the queue and the idle state of the computing unit, and selects the idle computing unit for computing operations, which has the advantages of load balancing and can make full use of the resources of the computing unit;

[0041] In this application, if the CPU encounters a computing task when running a business, it only needs to send down the operator and the operand, and then continue to execute other tasks; the arbitration unit and the address selector in this application will automatically complete the distribution and calculation of the computing task without occupying the CPU resources; therefore, this application has the advantages of load balancing and high efficiency, and solves the problems of load imbalance and CPU blocking in the prior art;

[0042] In the present application, since the operands and the operation results are stored in the storage unit, and the operation results can be further overwritten with the corresponding operands in the storage unit, the size of the storage unit can be reduced, thereby reducing the area of ​​the chip circuit;

[0043] In addition, the signal lines required by the arbitration unit are all connected to the arbitration unit in the form of direct lines. Compared with the data reading and writing paths, reading and writing data is faster, and the arbitration process can be quickly implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, without paying creative labor, other drawings obtained based on these drawings still belong to the scope of the present application.

[0045] Figure 1 A schematic diagram of the structure of an embodiment of a load balancing processing system provided by the present application;

[0046] Figure 2 A schematic diagram of the main process of an embodiment of a load balancing processing method provided in the present application. DETAILED DESCRIPTION

[0047] In order to make the objectives, technical solutions and advantages of the present application more clear, the present application will be further described in detail below in conjunction with the accompanying drawings.

[0048] like Figure 1 As shown, a structural schematic diagram of an embodiment of a load balancing processing system provided by the present application is shown; in this embodiment, the load balancing processing system 1 at least includes: a queue unit 10, a storage unit 11, an arbitration unit 12, a data moving unit 13, an address selector 14 and multiple computing units 15, wherein the arbitration unit 12 is respectively connected to the queue unit 10, the data moving unit 13, the address selector 14 and each computing unit 15 through a data line.

[0049] Specifically, in this embodiment, the queue unit 10 is used to sequentially store the operator, valid indication bit and priority of the computing task from the CPU; wherein the valid indication bit is used to indicate the valid state of the corresponding computing task; in a specific example, the queue unit can be composed of registers, and the queue can be input and output according to the first-in-first-out (FIFO) principle;

[0050] The storage unit 11 is used to store the operands of the computing tasks from the CPU and the operation results from the computing unit; in a specific example, the storage unit 11 is usually composed of a storage medium such as SRAM or DRAM;

[0051] In some examples, the storage address of the operand in each computing task is related to its computing task sequence number, or is mapped one-to-one with the computing task queue; for example, the base address of the operand in the memory can be obtained by the task sequence number or specified by the task queue. In some other examples, an address mapping strategy can also be pre-set, which defines how to find the corresponding operand address according to the sequence number of the task and the sequence number of the computing unit; the strategy can be based on a certain rule or algorithm, or it can be implemented by looking up a mapping table;

[0052] In a specific example, the computing task of the computing unit 15 includes at least one of a modular exponentiation operation, a point multiplication operation, a point addition operation, a modular inverse operation, a modular multiplication operation, a multiplication operation, and a division operation.

[0053] The arbitration unit 12 is used to arbitrate according to the effective state and priority of each computing task in the queue unit and the idle state of each computing unit, and select the authorized computing task and the corresponding idle computing unit; the result obtained by the arbitration unit 12 is the serial number of the authorized computing task and the serial number of the idle computing unit, and the strategy of the arbitration unit includes but is not limited to fair polling (Round Robin), strict priority (Strict Priority), etc.;

[0054] The data moving unit 13 is used to read the operator corresponding to the authorized computing task from the storage unit according to the arbitration result, and send it to the corresponding idle computing unit;

[0055] The address selector 14 is used to obtain the storage address of the operand in the storage unit corresponding to the authorized computing task according to the arbitration result;

[0056] The address selector 14 decodes and obtains the base address of the operand in the storage unit according to at least one of the authorized computing task sequence number and the sequence number of the idle computing unit in the arbitration result, and obtains the storage address of the operand in combination with the authorized computing task sequence number;

[0057] Specifically, in some examples, according to the serial number of the authorized computing task and the serial number of the idle computing unit in the arbitration result, the address of the computing unit read / write operand and the result path of the corresponding sequence is decoded to the operand base address in the storage unit corresponding to the serial number. The operand base address is usually a starting address used to calculate the position of the operand of a specific task in the storage unit. In a specific example, the base address plus the offset (such as the serial number) can obtain the storage address of the specific operand.

[0058] It can be understood that by combining the task sequence number and the computing unit sequence number, the system can flexibly handle the situation of multiple tasks and multiple computing units. Different tasks and computing units can be assigned to different storage areas to avoid address conflicts and data confusion; this setting makes the system easier to expand. When more tasks or computing units are added to the system, only the address mapping strategy needs to be updated or the mapping table needs to be adjusted, without making a lot of modifications to the hardware structure of the address selector. In addition, through a specific address mapping strategy, the system can ensure that only authorized computing units can access specific operands or storage areas, thereby improving the security of the system.

[0059] The calculation unit 15 is used to read out the corresponding operand according to the storage address of the operation data obtained by the address selector, perform calculation processing in combination with the operator from the data moving unit, and write the calculation result to the storage unit after the calculation is completed.

[0060] In some examples, the calculation unit 15 writes the calculation result to the storage unit 11 after the calculation is completed, further comprising:

[0061] The calculation unit 15 stores the calculation result in the storage unit 11, covering the operands of the calculation task.

[0062] The calculation unit 15 is further used to change its own state to an idle state after the calculation is completed;

[0063] The queue unit 10 is further used to modify the corresponding computing task to a completed state after the computing unit writes the computing result into the storage unit, and notify the CPU through an interrupt or the like.

[0064] In some other examples, the address selector may be replaced by a second data moving unit, and the second data moving unit completes the reading and writing operations of the operands and the operation results according to the arbitration result.

[0065] It can be understood that the system of the present application includes a queue unit, a storage unit, an arbitration unit, a data moving unit, an address selector, etc. The present application can solve the problem of load imbalance when the processor computing tasks are assigned to the computing units, and the processing between the CPU tasks and the computing units is independent of each other. After the CPU sends the operands and operator configurations of the computing tasks to the storage unit and the queue respectively, it can continue to execute other services; the distribution of computing tasks is automatically completed by the data moving unit and the arbitration unit, and the CPU resources do not need to be occupied. Therefore, the present application has the advantages of load balancing and high efficiency, and solves the problems of load imbalance and CPU blocking in the prior art. Since the operands and operation results usually have a large amount of data, the present application further reduces the area of ​​the chip circuit by storing the operands and operation results in the storage unit, and in an optional solution, the operation results can cover the operands of the corresponding tasks.

[0066] In the present application, the queue status signal lines (including but not limited to valid status bits, priority signals), computing unit status signal lines (including but not limited to idle status indication lines) and arbitration result lines (including but not limited to authorized task sequence numbers and computing unit sequence numbers) connected to the arbitration unit are all direct lines, which can achieve fast arbitration.

[0067] like Figure 2 As shown, a main flow diagram of an embodiment of a load balancing processing method provided by the present application is shown, which adopts the above-mentioned Figure 1 In this embodiment, the method comprises the following steps:

[0068] Step S10, the CPU writes the operands of the computing tasks into the storage unit, and writes the operators, valid indication bits and priorities of the computing tasks into the queue unit; wherein, in the storage unit, the storage addresses of the operands in each computing task are related to its computing task sequence number, or are mapped one-to-one with the computing task queue;

[0069] Step S11, the arbitration unit arbitrates according to the effective state and priority of each computing task and the idle state of each computing unit, and selects the authorized computing task and the corresponding idle computing unit;

[0070] Among them, further include:

[0071] The arbitration unit obtains the authorized computing task sequence number and the sequence number of the idle computing unit after arbitration, wherein the strategy adopted by the arbitration unit is a fair polling or strict priority arbitration strategy;

[0072] Step S12, the data moving unit reads out the operator corresponding to the authorized computing task according to the arbitration result, and sends it to the corresponding idle computing unit;

[0073] Step S13, the address selector obtains the storage address of the operand in the storage unit corresponding to the authorized computing task according to the arbitration result;

[0074] In a specific example, the step S13 further includes:

[0075] The address selector decodes and obtains the base address of the operand in the storage unit according to at least one of the authorized computing task sequence number and the sequence number of the idle computing unit in the arbitration result, and obtains the storage address of the operand in combination with the authorized computing task sequence number;

[0076] Step S14, according to the storage address of the operation data obtained by the address selector, the corresponding operand is read out, combined with the operator from the data moving unit, calculation processing is performed, and the calculation result is written to the storage unit after the calculation is completed.

[0077] The calculation unit writes the calculation result to the storage unit after the calculation is completed, further comprising:

[0078] The computing unit stores the computing result in the storage unit, covering the operand of the computing task;

[0079] After the calculation is completed, the computing unit changes its own state to the idle state.

[0080] After the computing unit writes the computing result into the storage unit, the queue unit modifies the corresponding computing task to a completed state and notifies the CPU through an interrupt or the like.

[0081] In order to further understand the principle of the method of the present application, a specific example is provided below for illustration.

[0082] In this example, it is assumed that there are 4 computing units in the system and all of them are currently idle. The CPU has a multiplication task to perform, which is to multiply operand A by operand B and store the result back.

[0083] The specific steps of this application include:

[0084] CPU writes operands: The CPU first calculates the values ​​of operands A and B and writes them into the storage unit. The storage unit may be composed of storage media such as SRAM or DRAM, which has an address space for storing operands and the final calculation results;

[0085] The CPU writes the operator and related information: The CPU writes the multiplication operator (e.g., a specific encoding representing the multiplication operation) into the queue. In this example, the operator might be a simple instruction code telling the computational unit to perform a multiplication.

[0086] At the same time, the CPU also writes a valid flag (eg, 1 indicates that the task is valid) and a priority value (eg, set according to the urgency or importance of the task) into the queue.

[0087] The arbitration unit performs task arbitration: The arbitration unit checks the tasks in the queue. Since this is a new task and all computing units are idle, the arbitration unit can easily decide which task should be executed (in this example there is only one task).

[0088] The arbitration unit also decides which compute unit should be assigned to perform this task. Since all compute units are idle, it can choose any one. For simplicity, we assume that it chooses the first compute unit.

[0089] The data movement unit moves the operator: According to the decision of the arbitration unit, the data movement unit reads the multiplication operator from the queue and sends it to the selected calculation unit (ie, the first calculation unit).

[0090] The address selector performs address decoding: After receiving the decision of the arbitration unit, the address selector calculates the addresses of operands A and B in the storage unit based on the sequence number of the task (in this case, the index of the task in the queue) and the sequence number of the computing unit (in this case, 1).

[0091] The address selector provides this address information to the computation unit so that it can correctly read the operands from the memory cells.

[0092] The calculation unit performs calculations: After receiving the operator, the calculation unit reads operands A and B from the storage unit through the address provided by the address selector. The calculation unit performs a multiplication operation, that is, multiplying operand A by operand B.

[0093] After the calculation is completed, the calculation unit writes the result back to the address specified in the storage unit. This address may be the same as the address of operand A or B, or a new address is used to store the result.

[0094] Queues and interrupts notify the CPU: Once the computation is complete, the queue marks the task as completed.

[0095] The system may notify the CPU through an interrupt or other mechanism that the task has completed and the result can be read.

[0096] Through this multiplication operation example, it can be seen that in this application, the CPU is responsible for generating tasks and providing data, the queue and storage unit are responsible for storing tasks and data, the arbitration unit is responsible for task scheduling, the data moving unit is responsible for data transmission, the address selector is responsible for address management, and the computing unit is responsible for the actual computing work. These units work together to achieve load balancing and efficient execution of computing tasks.

[0097] Accordingly, as another aspect of the present application, a chip is also provided, which is deployed as described above. Figure 1 For more details on the described system, please refer to the aforementioned Figure 1 The description is not repeated here.

[0098] Accordingly, as another aspect of the present application, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the above-mentioned Figure 2 For more details, please refer to the above Figure 2 The description is not repeated here.

[0099] Implementing the embodiments of the present application has the following beneficial effects:

[0100] The present application provides a load balancing processing system, method and chip. The queue unit and storage unit are used to store the operators and operands of the computing tasks from the CPU respectively, and the arbitration unit performs arbitration according to the existing task volume of the queue and the idle state of the computing unit, and selects the idle computing unit for computing operations, which has the advantages of load balancing and can make full use of the resources of the computing unit;

[0101] In this application, if the CPU encounters a computing task when running a business, it only needs to send down the operator and the operand, and then continue to execute other tasks; the arbitration unit and the address selector in this application will automatically complete the distribution and calculation of the computing task without occupying the CPU resources; therefore, this application has the advantages of load balancing and high efficiency, and solves the problems of load imbalance and CPU blocking in the prior art;

[0102] In the present application, since the operands and the operation results are stored in the storage unit, and the operation results can be further overwritten with the corresponding operands in the storage unit, the size of the storage unit can be reduced, thereby reducing the area of ​​the chip circuit;

[0103] In addition, the signal lines required by the arbitration unit are all connected to the arbitration unit in the form of direct lines. Compared with the data reading and writing paths, reading and writing data is faster, and the arbitration process can be quickly implemented.

[0104] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, devices, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0105] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0106] The above disclosure is only a preferred embodiment of the present application, and certainly cannot be used to limit the scope of rights of the present application. Therefore, equivalent changes made according to the claims of the present application are still within the scope covered by the present application.

Claims

1. A load balancing processing system, characterized in that: At least: Queue unit, storage unit, data movement unit, arbitration unit, address selector and multiple computing units, among which: The queue unit is used to store the operator, the valid indication bit and the priority of the computing task from the CPU, wherein the valid indication bit is used to indicate the valid state of the corresponding computing task; The storage unit is used to store the operands of the computing tasks from the CPU and the operation results from the computing unit; The arbitration unit is used to arbitrate according to the effective state and priority of each computing task in the queue unit and the idle state of each computing unit, and select the authorized computing task and the corresponding idle computing unit; The data moving unit is used to read out the operator corresponding to the authorized computing task according to the arbitration result, and send it to the corresponding idle computing unit; The address selector is used to obtain the storage address of the operand in the storage unit corresponding to the authorized computing task according to the arbitration result; The calculation unit is used to read out the corresponding operand according to the storage address of the operation data obtained by the address selector, perform calculation processing in combination with the operator from the data moving unit, and write the calculation result to the storage unit after the calculation is completed.

2. The system according to claim 1, characterized in that The arbitration unit adopts a fair polling or strict priority arbitration strategy, and obtains the authorized computing task sequence number and the sequence number of the idle computing unit after arbitration.

3. The system according to claim 2, characterized in that In the storage unit, the storage address of the operand in each computing task is related to its computing task sequence number, or is mapped one-to-one with the computing task queue; The address selector decodes and obtains the base address of the operand in the storage unit according to at least one of the authorized computing task sequence number and the sequence number of the idle computing unit in the arbitration result, and obtains the storage address of the operand in combination with the authorized computing task sequence number.

4. The system according to claim 3, characterized in that The calculation unit writes the calculation result to the storage unit after the calculation is completed, further comprising: The computing unit stores the computing result in the storage unit, covering the operands of the computing task.

5. The system according to claim 4, characterized in that in: The computing unit is further configured to, after the computing is completed, modify its own state to an idle state; The queue unit is further used to modify the corresponding computing task to a completed state after the computing unit writes the computing result into the storage unit.

6. The system according to any one of claims 1 to 4, characterized in that: The computing task of the computing unit includes at least one of a modular exponentiation operation, a point multiplication operation, a point addition operation, a modular inverse operation, a modular multiplication operation, a multiplication operation, and a division operation.

7. The system according to claim 6, characterized in that The arbitration unit is respectively connected with the queue unit, the data moving unit, the address selector and each calculation unit through data lines.

8. A load balancing processing method, characterized in that: The method is implemented by using the system according to any one of claims 1 to 7, and comprises the following steps: The CPU writes the operands of the computing task into the storage unit, and writes the operator, valid indicator bit and priority of the computing task into the queue unit; The arbitration unit arbitrates according to the effective status and priority of each computing task and the idle status of each computing unit, and selects the authorized computing task and the corresponding idle computing unit; The data moving unit reads out the operator corresponding to the authorized computing task according to the arbitration result, and sends it to the corresponding idle computing unit; The address selector obtains the storage address of the operand in the storage unit corresponding to the authorized computing task according to the arbitration result; According to the storage address of the operation data obtained by the address selector, the corresponding operand is read out, combined with the operator from the data moving unit, the calculation process is performed, and the calculation result is written to the storage unit after the calculation is completed.

9. The method according to claim 8, characterized in that The address selector obtains the storage address of the operand in the storage unit corresponding to the authorized computing task according to the arbitration result, further comprising: The address selector decodes and obtains the base address of the operand in the storage unit according to at least one of the authorized computing task sequence number and the sequence number of the idle computing unit in the arbitration result, and obtains the storage address of the operand in combination with the authorized computing task sequence number; Wherein, in the storage unit, the storage address of the operand in each computing task is related to its computing task sequence number, or is mapped one-to-one with the computing task queue.

10. A chip, characterized in that: It is deployed with a system as claimed in any one of claims 1 to 7.

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