A high speed, low power Static Random Access Memory (SRAM) Array, which includes a 4T cell with two integrated Schottky Barrier Diodes (SBD) is provided. In a preferred embodiment, the cell bulk area and speed advantage is 30%, and AC power saving is 75% compared with the 6T CFET cell. The physical construct of the 4T cell saves capacitance in all critical nodes intra or inter cell wise, eliminates pass transistors, reduces the well noises. Typical embodiment uses a 0.15-um-rule based layout, and 1.5V supports operation at 5 ns cycles. SBD are used extensively with CFET to form a CMOS version of the Diode Transistor Logic circuitry. Generic control functions can be implemented including NAND/NOR gates, level shifting, decoding, voltage generator, ESD and latch-up protection, leakage control, and dynamic VT setting while in operation. Product applications include DRAM, SRAM, PLD, DRAM, CAM, Flash, Computing, Networking, and Communication devices as standalone system component or embedded into any ASIC.