Debugging jig, debugging system and debugging method of liquid-cooled hard disk backboard

Abstract

The invention discloses a debugging jig, a debugging system and a debugging method of a liquid-cooled hard disk backboard, and the method comprises the steps: when a to-be-debugged mode of a to-be-tested backboard is an SGPIO mode, a first CPLD module is used for generating a first analog signal, and also generating an SGPIO signal for controlling an indication module; and when the to-be-debugged mode is a Legacy VPP or NPEM mode, the first CPLD module is used for reading a target I2C address of the to-be-tested backboard, generating a second analog signal, receiving an interrupt signal sent by the second CPLD module, and generating an I2C signal for controlling the indication module, so that before the to-be-tested backboard and a mainboard are assembled and put into a cooling liquid, the function debugging of the firmware of the to-be-tested backboard can be realized, and the debugging efficiency is improved. And meanwhile, SGPIO, Legacy VPP and NPEM modes are supported, so that the situation that problems occur after assembly is avoided, and the production efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of hard disk backplane testing, and in particular to a debugging fixture, a debugging system and a debugging method of a liquid-cooled hard disk backplane. Background Art

[0002] Liquid-cooled servers, as an efficient, energy-saving and environmentally friendly heat dissipation solution, have received increasing attention. Among them, immersion liquid cooling is to completely immerse the server in the refrigerant and rely on the circulation of liquid flow to remove heat. The liquid cooling backplane, as an important component of the liquid-cooled server, is mainly used to connect the server's storage hard disk and provide a management interface for the management of the storage hard disk. However, since the liquid-cooled server is completely immersed in the coolant when working, it becomes very inconvenient to debug the CPLD (Complex Programmable Logic Device) firmware on the hard disk backplane.

[0003] In addition, the current patent publication number CN115640186A discloses a NVMe hard drive backplane test system and test method. This solution can only test the backplane of a specific hard drive, and the CPLD function verification part is only for a certain CPLD firmware, resulting in certain limitations and unable to fully cover different types of hard drive backplanes and CPLD firmware. Summary of the invention

[0004] The embodiment of the present invention provides a debugging fixture, a debugging system and a debugging method for a liquid-cooled hard disk backplane, aiming to solve the problems of inconvenience in debugging CPLD firmware on the hard disk backplane and certain limitations in debugging in the prior art.

[0005] In a first aspect, an embodiment of the present invention provides a debugging fixture for a liquid-cooled hard disk backplane, which is applied to a backplane to be tested, and the debugging fixture comprises a first CPLD module, a display module, a first connection module, a key module and a cable module; the display module, the first connection module, the key module and the cable module are all connected to the first CPLD module; the first CPLD module is connected to the hard disk connection module of the backplane to be tested through the cable module; the first CPLD module is connected to the second CPLD module of the backplane to be tested through the first connection module and the second connection module of the backplane to be tested, and the second CPLD module is connected to the indication module of the backplane to be tested;

[0006] Among them, when the first CPLD module determines that the mode to be debugged is the SGPIO mode through the display module and the button module, the first CPLD module is used to generate a first analog signal that simulates the hard disk accessing the hard disk connection module, and is also used to generate an SGPIO signal for controlling the indication module of the backplane to be tested; when the first CPLD module determines that the mode to be debugged is the Legacy VPP mode or the NPEM mode through the display module and the button module, the first CPLD module is used to read the target I2C address of the backplane to be tested, and is also used to generate a second analog signal that simulates the hard disk accessing the hard disk connection module, and is also used to receive and detect the interrupt signal sent by the second CPLD module, and is also used to generate an I2C signal for controlling the indication module of the backplane to be tested.

[0007] In a second aspect, an embodiment of the present invention provides a debugging system for a liquid-cooled hard disk backplane, comprising a debugging fixture for the liquid-cooled hard disk backplane as described in the first aspect, and also comprising a backplane to be tested, wherein the hard disk connection module of the backplane to be tested is connected to the cable module in the debugging fixture, the second connection module of the backplane to be tested is connected to the first connection module in the debugging fixture, the second connection module is also connected to the second CPLD module of the backplane to be tested, and the second CPLD module is connected to the indication module of the backplane to be tested.

[0008] In a third aspect, an embodiment of the present invention further provides a method for debugging a liquid-cooled hard disk backplane, which is applied to the debugging system for the liquid-cooled hard disk backplane described in the first aspect, comprising:

[0009] When the first CPLD module of the debugging fixture receives an information selection instruction through the display module and the key module of the debugging fixture, target information corresponding to the backplane to be tested is selected from the preset information according to the information selection instruction; wherein the target information includes a target mode to be debugged and the number of target hard disks, and the target mode to be debugged includes an SGPIO mode, a Legacy VPP mode, and an NPEM mode;

[0010] If the first CPLD module determines that the target mode to be debugged is the SGPIO mode, it generates a first analog signal, and sends the first analog signal to the first target hard disk connectors in the hard disk connection module of the backplane to be tested, which are equal to the number of the target hard disks, through the first target cable components in the cable module of the debugging fixture, which are equal to the number of the target hard disks, and generates an SGPIO signal of the indication module for controlling the backplane to be tested, and sends the SGPIO signal to the second CPLD module of the backplane to be tested through the first connection module of the debugging fixture and the second connection module of the backplane to be tested;

[0011] If the first CPLD module determines that the target mode to be debugged is the Legacy VPP or NPEM mode, the target I2C address is read from the preset I2C address, and a second analog signal is generated, and the second analog signal is sent to the second target hard disk connectors in the hard disk connection module, which are equal in number to the target hard disks, through the second target cable components in the cable module, which are equal in number to the target hard disks, and the interrupt signal sent by the second CPLD module is received and detected through the first connection module and the second connection module;

[0012] If the first CPLD module detects that the interrupt signal corresponds one-to-one with the target hard disk, the first CPLD module controls to end the interrupt detection, generates an I2C signal for controlling the indicator module of the backplane to be tested, and sends the I2C signal to the second CPLD module through the first connection module and the second connection module based on the target I2C address;

[0013] The second CPLD module performs state control on the indication module of the backplane to be tested according to the SGPIO signal or the I2C signal to obtain a first state indication result or a second state indication result, and sends the first state indication result or the second state indication result to the first CPLD module;

[0014] If the first CPLD module detects that the first state indication result is consistent with the first preset state or the second state indication result is consistent with the second preset state, the debugging of the backplane to be tested is controlled to end.

[0015] The embodiment of the invention discloses a debugging fixture, a debugging system and a debugging method of a liquid-cooled hard disk backplane. The debugging fixture comprises a first CPLD module, a display module, a first connection module, a key module and a cable module. When the debugging mode of the backplane to be tested is the SGPIO mode, the first CPLD module is used to generate a first analog signal and also generate an SGPIO signal of a control indication module. When the debugging mode is the Legacy VPP or NPEM mode, the first CPLD module is used to read a target I2C address of the backplane to be tested, generate a second analog signal, receive an interrupt signal sent by the second CPLD module, and also generate an I2C signal of the control indication module. Thus, before the backplane to be tested is assembled with a mainboard and put into the cooling liquid, the function debugging of the firmware of the backplane to be tested can be realized, and the SGPIO, Legacy VPP and NPEM modes are supported at the same time, thereby avoiding the situation where problems occur after assembly and improving production efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying any creative work.

[0017] Figure 1 A schematic diagram of the structure of a debugging system for a liquid-cooled hard disk backplane provided by an embodiment of the present invention;

[0018] Figure 2 Another structural schematic diagram of the debugging system of the liquid-cooled hard disk backplane provided by an embodiment of the present invention;

[0019] Figure 3 A schematic flow chart of a method for debugging a liquid-cooled hard disk backplane provided in an embodiment of the present invention.

[0020] Among them, the reference numerals in the figures are as follows:

[0021] 10. Debugging system for liquid-cooled hard disk backplane; 100. Debugging fixture; 110. First CPLD module; 120. Display module; 130. First connection module; 131. First connector; 132. Second connector; 133. Third connector; 134. Fourth connector; 140. Key module; 141. Reset key; 142. Function selection key; 143. Function confirmation key; 150. Cable module; 151. First cable component; 152. Second cable component; 153. Third cable component; 154. Fourth cable component; 200. Backplane to be tested ; 210, second CPLD module; 220, hard disk connection module; 221, first hard disk connector; 222, second hard disk connector; 223, third hard disk connector; 224, fourth hard disk connector; 230, second connection module; 231, fifth connector; 232, sixth connector; 233, seventh connector; 234, eighth connector; 240, indication module; 241, first indicator light; 242, second indicator light; 243, third indicator light; 244, fourth indicator light; 250, field replaceable unit; 260, temperature sensor. DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0023] It should be understood that when used in this specification and the appended claims, the terms "include" and "comprises" indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0024] It should also be understood that the terms used in this specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the specification of the present invention and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0025] It should be further understood that the term "and / or" used in the present description and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0026] In order to more clearly understand the technical solution of the present application, the terminals involved are described in detail below. The present application describes the technical solution from the perspectives of the sending end and the server.

[0027] See also Figure 1 and Figure 2 , Figure 1 A schematic diagram of the structure of a debugging system for a liquid-cooled hard disk backplane provided by an embodiment of the present invention; Figure 2 Another structural schematic diagram of the debugging system of the liquid-cooled hard disk backplane provided by the embodiment of the present invention. The debugging fixture 100 of the liquid-cooled hard disk backplane of the embodiment of the present invention is applied to the backplane 200 to be tested, and the debugging fixture 100 includes a first CPLD module 110, a display module 120, a first connection module 130, a button module 140 and a cable module 150; the display module 120, the first connection module 130, the button module 140 and the cable module 150 are all connected to the first CPLD module 110; the first CPLD module 110 is connected to the hard disk connection module 220 of the backplane 200 to be tested through the cable module 150; the first CPLD module 110 is connected to the second CPLD module 210 of the backplane 200 to be tested through the first connection module 130 and the second connection module 230 of the backplane 200 to be tested, and the second CPLD module 210 is connected to the indication module 240 of the backplane 200 to be tested;

[0028] Among them, when the first CPLD module 110 determines that the mode to be debugged is the SGPIO mode through the display module 120 and the button module 140, the first CPLD module 110 is used to generate a first analog signal simulating the hard disk access to the hard disk connection module 220, and is also used to generate the SGPIO signal of the indication module 240 that controls the backplane 200 to be tested; when the first CPLD module 110 determines that the mode to be debugged is the LegacyVPP mode or the NPEM mode through the display module 120 and the button module 140, the first CPLD module 110 is used to read the target I2C address of the backplane 200 to be tested, and is also used to generate a second analog signal simulating the hard disk access to the hard disk connection module 220, and is also used to receive and detect the interrupt signal sent by the second CPLD module 210, and is also used to generate the I2C signal of the indication module 240 that controls the backplane 200 to be tested.

[0029] In this embodiment, the debugging fixture 100 of the liquid-cooled hard disk backplane includes a first CPLD module 110, a display module 120, a first connection module 130, a button module 140 and a cable module 150; wherein the display module 120, the first connection module 130, the button module 140 and the cable module 150 are all connected to the first CPLD module 110; preferably, the display module 120 in this embodiment can be an LCD1602 display module 120, the display module 120 is connected to the first CPLD module 110 through an IO interface, and the display module 120 can be used to display information and status during the debugging process; the button module 140 is used for the user to input and select the mode and parameters to be debugged; the first connection module 130 is connected to the second connection module 230 of the backplane 200 to be tested, so as to connect the first CPLD module 110 and the second CPLD module 210 of the backplane 200 to be tested; the cable module 150 is used to connect the first CPLD module 110 and the hard disk connection module 220 of the backplane 200 to be tested.

[0030] In specific implementation, the first CPLD module 110 controls the display module 120 to display "mode:" through the IO interface. At this time, based on the type of the backplane 200 to be tested, the mode to be debugged is determined through the key module 140, wherein the mode to be debugged includes SGPIO mode, Legacy VPP mode, and NPEM mode. In addition, the first CPLD module 110 can also control the display module 120 to display "SAS / SATA QTY:" through the IO interface, wherein the display module 120 also displays the number of conventional hard disks for user selection, such as 2 / 4 / 8 / 16 / 24. In addition, if the number of conventional hard disks cannot meet user needs, the number of hard disks can also be automatically adjusted through the key module 140. In addition, after completing the selection of the debugging mode and the target number of hard disks of the backplane 200 to be tested, when the first CPLD module 110 determines that the debugging mode of the backplane 200 to be tested is the SGPIO mode through the display module 120 and the button module 140, the generated first analog signal is sent to the Pin4 and Pin10 pins of the target hard disk connector in the hard disk connection module 220 of the backplane 200 to be tested through the cable module 150, wherein, when no hard disk is connected to the hard disk connector of the hard disk connection module 220, the Pin4 and Pin10 pins of the hard disk connector are high level, and after receiving the first analog signal, the Pin4 pin of the hard disk connector is controlled to change from high level to low level, and the Pin10 pin is controlled to change from high level 1 to low level, so as to simulate the SAS / SATA hard disk being connected to the hard disk connection module 220. Then, the first CPLD module 110 is connected to the second CPLD module 210 through the first connection module 130 and the second connection module 230, so that the SGPIO signal generated by the first CPLD module 110 is parsed by the second CPLD module 210, and the parsed result is sent to the corresponding indicator light in the indication module 240, so as to control the working state of the target indicator light in the indication module 240, and then the working state of the target indicator light is used to indicate the state of the hard disk connected to the hard disk connection module 220; for example, the state of the SAS / SATA hard disk includes four states: OK, positioning, error and reconstruction, and the four states of the SAS / SATA hard disk can be indicated by the indicator light working in four working states of off, 4Hz flashing, always on and 1Hz flashing respectively; wherein, the indication module 240 in this embodiment preferably includes a first indicator light 241, a second indicator light 242, a third indicator light 243 and a fourth indicator light 244, and the number of the indicator lights in the indication module 240 can be set according to the number of connected hard disks.In addition, when the first CPLD module 110 determines through the display module 120 and the button module 140 that the debugging mode of the backplane 200 to be tested is the Legacy VPP mode or the NPEM mode, the first CPLD module 110 first controls the display module 120 to display "I2CADDR0:" through the IO interface, and selects the target I2C address from the preset I2C addresses 0x40, 0x42, 0x44, 0x46, 0x48, 0x4A, 0x4C, and 0x4E through the button module 140, so that the first CPLD module 110 reads the target I2C address to facilitate the subsequent storage of the I2C signal. Then, the first CPLD module 110 sends the generated second analog signal to Pin4 and Pin10 of the target hard disk connector in the hard disk connection module 220 through the cable module 150, wherein, when no hard disk is connected to the hard disk connector of the hard disk connection module 220, the Pin4 and Pin10 of the hard disk connector are at a high level. After receiving the second analog signal, the Pin10 of the hard disk connector remains at a high level, and Pin4 changes from a high level 1 to a low level to simulate the NVMe hard disk connected to the hard disk connection module 220; and, in order to verify the interrupt function of the panel to be tested, the second CPLD module 210 sends an interrupt signal to the first CPLD module 110 through the second connection module 230 and the first connection module 130. If the first CPLD module 110 receives the analog signal connected to the hard disk connection module 220, The interrupt signal of the NVMe hard disk corresponds one to one, and the same I2C signal is sent based on each I2C address in the target I2C address, and the I2C signal is sent in parallel to each PCA9555 chip in the second CPLD module 210 through the first connection module 130 and the second connection module 230 for analysis, and the parsed result is sent to the target indicator light in the indication module 240 connected to the second CPLD module 210, so as to control the working state of the target indicator light in the indication module 240, and then indicate the state of the NVMe hard disk connected to the hard disk connection module 220 through the working state of the target indicator light, for example: the state of the NVMe hard disk includes four states: OK, positioning, error and reconstruction, and the four states of the NVM hard disk can be indicated by the indicator light working in four working states of off, 4Hz flashing, always on and 1Hz flashing.

[0031] Wherein, when the debugging mode is the Legacy VPP mode, the PCA9555 chip in the second CPLD module 210 parses the serial data of the I2C signal, and controls the target indicator light (i.e., LED) in the indication module 240 through the IOx.0 pin and the IOx.1 pin on the IO port of the PCA9555 chip with the parsed result, and the control method is shown in the following Table 1:

[0032] Table 1

[0033] Hard disk status Fault(IOx.0) Locate(IOx.1) LED Status OK 0 0 closure position 0 1 4Hz flashing mistake 1 0 Always on reconstruction 1 1 1Hz flashing

[0034] When the debugging mode is the NPEM mode, the PCA9555 chip in the second CPLD module 210 parses the serial data of the I2C signal, and controls the target indicator light (i.e., LED) in the indication module 240 through the IO0.2 pin, IO0.3, IO0.4, and IO0.5 pin on the IO port of the PCA9555 chip with the parsed result, and the control method is shown in the following Table 2:

[0035] Table 2

[0036]

[0037]

[0038] The debugging fixture of the liquid-cooled hard disk backplane provided in the embodiment of the present invention realizes the functional debugging of the backplane firmware to be tested, and supports SGPIO, Legacy VPP and NPEM modes at the same time, solving the problems of inconvenient debugging of CPLD firmware on the hard disk backplane and certain limitations in debugging.

[0039] In one embodiment, if Figure 1 and 2 As shown, the first connection module 130 includes a first connector 131, a second connector 132, a third connector 133 and a fourth connector 134, the first connector 131 is connected to the first CPLD module 110 via an SGPIO bus, the second connector 132 is connected to the first CPLD module 110 via an I2C bus, the third connector 133 is connected to the first CPLD module 110 via an I2C bus, and the fourth connector 134 is connected to the first CPLD module 110 via an I2C bus.

[0040] In this embodiment, the first CPLD module 110 serves as the host end of the SGPIO signal and the I2C signal, the first connector 131 is connected to the first CPLD module 110 through the SGPIO bus to transmit the SGPIO signal generated by the first CPLD module 110, the second connector 132 is connected to the first CPLD module 110 through the I2C bus to transmit the I2C signal generated by the first CPLD module 110, and the third connector 133 is connected to the first CPLD module 110 through the I2C bus to transmit the The first CPLD module 110 generates an I2C signal, and the fourth connector 134 is connected to the first CPLD module 110 through the I2C bus, so as to transmit the acquired information of the backplane 200 to be tested to the first CPLD module 110, wherein the information of the backplane 200 to be tested includes the firmware version of the second CPLD module 210, the information of the field replaceable unit 250 and the temperature of the backplane 200 to be tested; and the SGPIO bus and the I2C bus can be one group or multiple groups, which is determined by the indication module 240 on the backplane 200 to be tested, and is not specifically limited in this embodiment.

[0041] In one embodiment, if Figure 1 and 2 As shown, the button module 140 includes a reset button 141 , a function selection button 142 and a function confirmation button 143 , and the reset button 141 , the function selection button 142 and the function confirmation button 143 are all connected to the first CPLD module 110 .

[0042] In this embodiment, the reset button 141, the function selection button 142 and the function confirmation button 143 in the button module 140 are all connected to the first CPLD module 110 to determine the mode to be debugged and the number of hard disks connected to the first CPLD module 110; specifically, when the first CPLD module 110 controls the display module 120 to display "mode:" through the IO interface, the user can switch the mode to be debugged through the function selection button 142 in the button module 140, and confirm the selected mode to be debugged through the function confirmation button 143 in the button module 140. In addition, when the first CPLD module 110 also controls the display module 120 to display "SAS / SATAQTY:" through the IO interface, the user can switch the preset number of hard disks, such as 2 / 4 / 8 / 16 / 24, through the function selection button 142 in the button module 140, and confirm the number of selected target hard disks through the function confirmation button 143 in the button module 140. And when the preset number of hard disks cannot meet user needs, the user can also long press the function selection button 142 in the button module 140 until the preset number of hard disks on the display module 120 becomes 0 and flashes, and then short press the function selection button 142 to increase the number until the number to be selected appears on the display module 120, and then confirm through the function confirmation button 143 to adjust the preset number of hard disks.

[0043] In one embodiment, if Figure 1 and 2 As shown, the cable module 150 includes a first cable component 151 , a second cable component 152 , a third cable component 153 and a fourth cable component 154 , and the first cable component 151 , the second cable component 152 , the third cable component 153 and the fourth cable component 154 are all connected to the first CPLD module 110 .

[0044] In this embodiment, in order to transmit the first analog signal and the second analog signal generated by the first CPLD module 110 for simulating the hard disk access to the hard disk connection module 220 to the hard disk connection module 220 of the backplane 200 to be tested, the first CPLD module 110 externally leads the IO interface to the first cable component 151, the second cable component 152, the third cable component 153 and the fourth cable component 154 of the cable module 150. Among them, the first cable component 151 includes a first cable connector and a first cable line, and the first cable line is connected to the first CPLD module 110 through the first cable connector; the second cable component 152 includes a second cable connector and a second cable line, and the second cable line is connected to the second CPLD module 210 through the second cable connector; the third cable component 153 includes a third cable connector and a third cable line, and the third cable line is connected to the first CPLD module 110 through the third cable connector; the fourth cable component 154 includes a fourth cable connector and a fourth cable line, and the fourth cable line is connected to the first CPLD module 110 through the fourth cable connector. Since the cable components of the cable module 150 correspond one-to-one to the cable connectors in the hard disk connection module 220, the hard disk connection module 220 in this embodiment includes a first hard disk connector 221, a second hard disk connector 222, a third hard disk connector 223, and a fourth hard disk connector 224. In a specific implementation, when the first CPLD module 110 controls the display module 120 to display "SAS / SATAQTY:" through the IO interface, the user switches the preset number of hard disks through the function selection button 142 in the button module 140, and after confirming the number of target hard disks selected through the function confirmation button 143 in the button module 140, the cable components with the same number as the target hard disks are selected from the cable module 150 based on the number of target hard disks. For example, when the number of the target hard disks is 2, the first cable component 151 and the second cable component 152 are selected from the cable module 150, and the first cable line in the first cable component 151 is connected to the first hard disk connector 221 of the hard disk connection module 220; the first cable line in the first cable component 151 is connected to the first hard disk connector 221 of the hard disk connection module 220 to transmit the first analog signal or the second analog signal generated by the first CPLD module 110 to the corresponding first hard disk connector 221 and second hard disk connector 222, thereby realizing the connection of the simulated hard disk to the hard disk connection module 220.

[0045] See also Figure 1 and Figure 2The embodiment of the present invention further provides a debugging system 10 for a liquid-cooled hard disk backplane, comprising any embodiment of the aforementioned debugging fixture 100 for a liquid-cooled hard disk backplane, and further comprising a backplane 200 to be tested, wherein a hard disk connection module 220 of the backplane 200 to be tested is connected to the cable module 150 in the debugging fixture 100, a second connection module 230 of the backplane 200 to be tested is connected to the first connection module 130 in the debugging fixture 100, the second connection module 230 is also connected to the second CPLD module 210 of the backplane 200 to be tested, and the second CPLD module 210 is connected to the indication module 240 of the backplane 200 to be tested.

[0046] In this embodiment, the working principle of the debugging system 10 of the liquid-cooled hard disk backplane is consistent with the working principle after the debugging fixture 100 of the liquid-cooled hard disk backplane is connected to the backplane 200 to be tested, and will not be described one by one here. The debugging system of the liquid-cooled hard disk backplane provided by the embodiment of the present invention can realize the functional debugging of the firmware of the backplane 200 to be tested before the backplane 200 to be tested is assembled with the mainboard and placed in the coolant, and supports SGPIO, Legacy VPP and NPEM modes at the same time, thereby avoiding the situation where problems occur after the backplane 200 to be tested is assembled with the mainboard, and improving production efficiency.

[0047] In one embodiment, if Figure 1 and 2 As shown, the second connection module 230 includes a fifth connector 231, a sixth connector 232, a seventh connector 233 and an eighth connector 234, the fifth connector 231 is connected to the second CPLD module 210 via an SGPIO bus, the sixth connector 232 is connected to the second CPLD module 210 via an I2C bus, the seventh connector 233 is connected to the second CPLD module 210 via an I2C bus, the eighth connector 234 is connected to the second CPLD module 210, and is also connected to both the field replaceable unit 250 and the temperature sensor 260.

[0048] In this embodiment, the first connection module 130 in the debugging fixture 100 of the liquid-cooled hard disk backplane includes a first connector 131, a second connector 132, a third connector 133 and a fourth connector 134. Correspondingly, the second connection module 230 connected to the first connection module 130 on the backplane 200 to be tested includes a fifth connector 231, a sixth connector 232, a seventh connector 233 and an eighth connector 234, wherein the fifth connector 231 is connected to the second CPLD module 210 through the SGPIO bus, the sixth connector 232 is connected to the second CPLD module 210 through the I2C bus, the seventh connector 233 is connected to the second CPLD module 210 through the I2C bus, and the eighth connector 234 is connected to the second The CPLD module 210 is connected, and is also connected to the field replaceable unit 250 and the temperature sensor 260; and the fifth connector 231 is connected to the first connector 131 through a high-speed cable to transmit the SGPIO signal for controlling the target indicator light in the indication module 240; the sixth connector 232 is connected to the second connector 132 through a high-speed cable, and the seventh connector 233 is connected to the third connector 133 through a high-speed cable to transmit the I2C signal for controlling the target indicator light in the indication module 240; the eighth connector 234 is connected to the fourth connector 134 through a low-speed cable to obtain the hard disk backplane information such as the firmware version of the second CPLD module 210, the field replaceable unit 250 information and the temperature of the backplane 200 to be tested.

[0049] The embodiment of the present invention further provides a method for debugging a liquid-cooled hard disk backplane. The method for debugging a liquid-cooled hard disk backplane is applied to the debugging system of the liquid-cooled hard disk backplane. Specifically, please refer to Figure 3 , Figure 3 This is a schematic flow chart of a method for debugging a liquid-cooled hard disk backplane provided by an embodiment of the present invention. The method for debugging a liquid-cooled hard disk backplane provided by an embodiment of the present invention includes steps S101 to S106.

[0050] S101. When the first CPLD module of the debugging fixture receives an information selection instruction through the display module and the button module of the debugging fixture, target information corresponding to the backplane to be tested is selected from the preset information according to the information selection instruction; wherein the target information includes a target mode to be debugged and the number of target hard disks, and the target mode to be debugged includes an SGPIO mode, a Legacy VPP mode, and an NPEM mode.

[0051] In this embodiment, the information selection instruction can be triggered by relevant staff, wherein the target information corresponding to the backplane 200 to be tested is selected from the preset information according to the information selection instruction, including: the first CPLD module 110 decomposes the information selection instruction to obtain a mode acquisition instruction and a hard disk quantity acquisition instruction; obtains the target mode to be debugged of the backplane 200 to be tested from the preset information according to the mode acquisition instruction; and obtains the number of the target hard disks from the preset information according to the hard disk quantity acquisition instruction. Specifically, when the first CPLD module 110 controls the display module 120 of the debugging fixture 100 to display the mode to be debugged through the IO interface, if the key module 140 of the debugging fixture 100 receives the mode acquisition instruction for the mode to be debugged, the target mode to be debugged is determined through the mode acquisition instruction; and the first CPLD module 110 also controls the display module 120 to display the number of hard disks through the IO interface, and if the key module 140 receives the hard disk quantity acquisition instruction for the number of hard disks, the number of the target hard disks is determined through the hard disk quantity acquisition instruction.

[0052] S102. If the first CPLD module determines that the target mode to be debugged is the SGPIO mode, it generates a first analog signal, and sends the first analog signal to the first target hard disk connectors in the hard disk connection module of the backplane to be tested, which are equal to the number of the target hard disks, through the first target cable components in the cable module of the debugging fixture, which are equal to the number of the target hard disks, and generates an SGPIO signal of the indication module for controlling the backplane to be tested, and sends the SGPIO signal to the second CPLD module of the backplane to be tested through the first connection module of the debugging fixture and the second connection module of the backplane to be tested.

[0053] In this embodiment, after completing the steps of selecting the target mode to be debugged and the number of target hard disks, if the first CPLD module 110 determines that the current target mode to be debugged is the SGPIO mode, it generates a first analog signal, and the first analog signal is used to simulate the SAS / SATA hard disk being connected to the hard disk connection module 220; specifically, the first CPLD module 110 sends the first analog signal to the first target hard disk connectors in the hard disk connection module 220 of the backplane 200 to be tested, which are equal to the number of the target hard disks, through the first target cable components in the cable module 150 of the debugging fixture 100, which are equal to the number of the target hard disks, to control the Pin4 and Pin10 pins of each hard disk connector in the first target hard disk connector, thereby controlling the Pin4 pin of each hard disk connector to change from a high level to a low level, and the Pin10 pin to change from a high level 1 to a low level, thereby simulating the SAS / SATA hard disk being connected to the hard disk connection module 220. Furthermore, the first CPLD module 110 generates an SGPIO signal for controlling the indicator module 240 of the backplane 200 to be tested, and controls the SCPIO bus to send the SGPIO signal to the second CPLD module 210 of the backplane 200 to be tested through the first connection module 130 of the debugging fixture 100 and the second connection module 230 of the backplane 200 to be tested, so that the corresponding indicator lights on the indicator module 240 are controlled by the SGPIO signal to simulate the SAS / SATA hard disk in the OK, positioning, error, and rebuilding states in sequence, thereby indicating the working state of the SAS / SATA hard disk connected to the hard disk connection module 220. In addition, the display module 120 connected to the first CPLD module 110 will also synchronously display the state corresponding to the serial data stream of the current SGPIO signal, namely "OK", "Locate", "Fault" and "Rebuild" in real time.

[0054] S103. If the first CPLD module determines that the target mode to be debugged is the Legacy VPP or NPEM mode, it reads the target I2C address from the preset I2C address and generates a second analog signal, and sends the second analog signal to the second target hard disk connectors in the hard disk connection module that are equal to the number of the target hard disks through the second target cable components in the cable module that are equal to the number of the target hard disks, and receives and detects the interrupt signal sent by the second CPLD module through the first connection module and the second connection module.

[0055] In this embodiment, if the first CPLD module 110 determines that the current target mode to be debugged is the LegacyVPP mode or the NPEM mode, each I2C address in the target I2C address is read from the preset I2C address through the display module 120 and the button module 140. Specifically, the first CPLD module 110 controls the display module 120 to display "I2C ADDR0:" through the IO interface, and selects the target I2C address from the preset I2C addresses 0x40, 0x42, 0x44, 0x46, 0x48, 0x4A, 0x4C, and 0x4E through the function selection button 142 in the button module 140, and confirms the target I2C address through the function confirmation button 143 in the button module 140, so that the first CPLD module 110 can generate an I2C signal based on each I2C address in the target I2C address and send it. Then, the first CPLD module 110 generates a second analog signal, and the second analog signal is used to simulate the NVMe hard disk being connected to the hard disk connector of the hard disk connection module 220; specifically, the first CPLD module 110 sends the second analog signal to the second target hard disk connectors in the hard disk connection module 220 of the backplane 200 to be tested, which are equal to the number of the target hard disks, through the second target cable components in the cable module 150 of the debugging fixture 100, which are equal to the number of the target hard disks, so as to control the Pin4 and Pin10 pins of each hard disk connector in the second target hard disk connector, thereby controlling the Pin10 pin of each hard disk connector to maintain a high level, and the Pin4 pin changes from a high level 1 to a low level, thereby simulating the NVMe hard disk being connected to the hard disk connection module 220. At this time, if there is no problem with the firmware design of the second CPLD module 210 of the backplane 200 to be tested, the first CPLD module 110 receives and detects the interrupt signal sent by the second CPLD module 210 through the first connection module 130 and the second connection module 230. At the same time, the first CPLD module 110 controls the display module 120 to synchronously display "NVMe1 / 2 / 3 / 4...ADDInterrupt" in sequence to realize interrupt verification of each NVMe hard disk connected to the hard disk connection module 220.

[0056] In one embodiment, after the first connection module 130 and the second connection module 230 receive and detect the interrupt signal sent by the second CPLD module 210, the method further includes:

[0057] If the first CPLD module 110 detects that the interrupt signal does not correspond one-to-one to the target hard disk, it generates interrupt exception information.

[0058] In this embodiment, if during the interrupt verification process, it is detected that the interrupt signal does not correspond one-to-one to the target hard disk (that is, the second CPLD module 210 does not receive a one-to-one corresponding interrupt signal when the NVMe hard disk simulates access to the corresponding hard disk connector), it indicates that there is a problem with the interrupt detection code in the second CPLD module 210 of the backplane 200 to be tested. At this time, interrupt exception information is generated and sent to the display module 120 for display, so as to prompt relevant staff to modify the current interrupt detection code in the second CPLD module 210 and perform other operations.

[0059] S104. If the first CPLD module detects that the interrupt signal corresponds one-to-one with the target hard disk, it controls the end of interrupt detection and generates an I2C signal for controlling the indication module of the backplane to be tested, and sends the I2C signal to the second CPLD module through the first connection module and the second connection module based on the target I2C address.

[0060] In this embodiment, after receiving the interrupt signal, the first CPLD module 110 controls the display module 120 to display "NVMe1 / 2 / 3 / 4...ADDInterrupt Pass" in sequence until the last NVMe hard disk completes the interrupt verification. If during the interrupt verification process, the first CPLD module 110 detects that the interrupt signal corresponds one-to-one with the target hard disk (that is, the first CPLD module 110 receives the corresponding interrupt signal when the NVMe hard disk is simulated to be connected to the corresponding hard disk connector), the first CPLD module 110 controls the end of the interrupt detection of the second CPLD module 210, and generates an I2C signal for controlling the indication module 240 of the backplane 200 to be tested, and based on the target I2C address, the I2C signal is sent to the second CPLD module 210 of the backplane 200 to be tested through the first connection module 130 of the debugging fixture 100 and the second connection module 230 of the backplane 200 to be tested, so as to control the target indicator light on the indication module 240 through the I2C signal to simulate the NVMe hard disk in the OK, positioning, error, and rebuilding states in turn, thereby indicating the working state of the hard disk simulated to be connected to the hard disk connection module 220. In addition, the display module 120 connected to the first CPLD module 110 will also synchronously display the status corresponding to the serial data stream of the current I2C signal, namely, "OK", "Locate", "Fault" and "Rebuild" in real time.

[0061] S105. The second CPLD module performs state control on the indication module of the backplane to be tested according to the SGPIO signal or the I2C signal to obtain a first state indication result or a second state indication result, and sends the first state indication result or the second state indication result to the first CPLD module.

[0062] In this embodiment, after receiving the SGPIO signal or the I2C signal, the second CPLD module 210 controls the target indicator light in the indication module 240 according to the SGPIO signal or the I2C signal to obtain the first state indication result or the second state indication result of the target indicator light, and sends the first state indication result or the second state indication result to the first CPLD module 110 for detection through the second connection module 230 and the second connection module 230, so as to subsequently determine whether the first state indication result is consistent with the first preset state or whether the second state indication result is consistent with the second preset state.

[0063] In one embodiment, the second CPLD module 210 performs state control on the indication module 240 of the backplane 200 to be tested according to the SGPIO signal or the I2C signal to obtain a first state indication result or a second state indication result, including:

[0064] The second CPLD module 210 analyzes the SGPIO signal or the I2C signal to obtain a first analysis result or a second analysis result;

[0065] The second CPLD module 210 controls the states of the target indicator lights in the indication module 240, the number of which is equal to the number of the target hard disks, according to the first analysis result or the second analysis result, to obtain a first state indication result or a second state indication result.

[0066] In the present embodiment, after receiving the SGPIO signal or the I2C signal, the second CPLD module 210 specifically first parses the SGPIO signal or the I2C signal to obtain a first parsing result corresponding to the SGPIO signal or a second parsing result corresponding to the I2C signal; and controls the states of the target indicator lights in the indication module 240 equal to the number of the target hard disks according to the first parsing result or the second parsing result to obtain a first state indication result or a second state indication result of the target indicator lights, so that the first CPLD module 110 subsequently compares the first state indication result with the first preset state or the second state indication result with the second preset state to confirm whether they are consistent, thereby realizing functional debugging of the firmware of the second CPLD module 210.

[0067] S106. If the first CPLD module detects that the first state indication result is consistent with the first preset state or the second state indication result is consistent with the second preset state, control to end the debugging of the backplane to be tested.

[0068] In this embodiment, after obtaining the first state indication result or the second state indication result, the first CPLD module 110 detects whether the first state indication result is consistent with the first preset state or whether the second state indication result is consistent with the second preset state; wherein, if the first CPLD module 110 detects that the first state indication result is consistent with the first preset state or the second state indication result is consistent with the second preset state, it indicates that there is no abnormality in the firmware of the second CPLD module 210 of the backplane 200 to be tested, and at this time, the debugging of the backplane 200 to be tested is controlled to end to end the debugging process.

[0069] In one embodiment, after obtaining the first status indication result or the second status indication result, the method further includes:

[0070] If the first CPLD module 110 detects that the first state indication result is inconsistent with the first preset state or the second state indication result is inconsistent with the second preset state, it generates lighting abnormality prompt information.

[0071] In the present embodiment, after receiving the first state indication result or the second state indication result, the first CPLD module 110 further includes: if the first CPLD module 110 detects that the first state indication result is inconsistent with the first preset state or the second state indication result is inconsistent with the second preset state, it indicates that there is an abnormality in the firmware of the lighting operation in the second CPLD module 210 of the backplane 200 to be tested, and at this time, a lighting abnormality prompt information is generated, and the lighting abnormality prompt information is sent to the display module 120 for display, so that relevant staff can re-change, burn and verify the code of the second CPLD module 210 based on the lighting abnormality prompt information, and then complete the final debugging of the second CPLD module 210 code to avoid problems after the backplane 200 to be tested is assembled with the mainboard.

[0072] The debugging method of the liquid-cooled hard disk backplane provided in the embodiment of the present invention can realize the functional debugging of the backplane firmware to be tested before the backplane to be tested is assembled with the mainboard and placed in the coolant, and supports SGPIO, Legacy VPP and NPEM modes at the same time, thereby avoiding the situation where problems occur after the backplane to be tested is assembled with the mainboard, thereby improving production efficiency.

[0073] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present invention, and these modifications or replacements should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A debugging fixture for a liquid-cooled hard disk backplane, characterized in that: Applied to a backplane to be tested, the debugging fixture comprises a first CPLD module, a display module, a first connection module, a key module and a cable module; the display module, the first connection module, the key module and the cable module are all connected to the first CPLD module; the first CPLD module is connected to the hard disk connection module of the backplane to be tested through the cable module; the first CPLD module is connected to the second CPLD module of the backplane to be tested through the first connection module and the second connection module of the backplane to be tested, and the second CPLD module is connected to the indication module of the backplane to be tested; Among them, when the first CPLD module determines that the mode to be debugged is the SGPIO mode through the display module and the button module, the first CPLD module is used to generate a first analog signal that simulates the hard disk accessing the hard disk connection module, and is also used to generate an SGPIO signal for controlling the indication module of the backplane to be tested; when the first CPLD module determines that the mode to be debugged is the Legacy VPP mode or the NPEM mode through the display module and the button module, the first CPLD module is used to read the target I2C address of the backplane to be tested, and is also used to generate a second analog signal that simulates the hard disk accessing the hard disk connection module, and is also used to receive and detect the interrupt signal sent by the second CPLD module, and is also used to generate an I2C signal for controlling the indication module of the backplane to be tested.

2. The debugging fixture for the liquid-cooled hard disk backplane according to claim 1, characterized in that: The first connection module includes a first connector, a second connector, a third connector and a fourth connector, the first connector is connected to the first CPLD module via an SGPIO bus, the second connector is connected to the first CPLD module via an I2C bus, the third connector is connected to the first CPLD module via an I2C bus, and the fourth connector is connected to the first CPLD module via an I2C bus.

3. The debugging fixture for the liquid-cooled hard disk backplane according to claim 1, characterized in that: The button module includes a reset button, a function selection button and a function confirmation button, and the reset button, the function selection button and the function confirmation button are all connected to the first CPLD module.

4. The debugging fixture for the liquid-cooled hard disk backplane according to claim 1, characterized in that: The cable module includes a first cable component, a second cable component, a third cable component and a fourth cable component, and the first cable component, the second cable component, the third cable component and the fourth cable component are all connected to the first CPLD module.

5. A debugging system for a liquid-cooled hard disk backplane, characterized in that: A debugging fixture comprising a liquid-cooled hard disk backplane as described in any one of claims 1 to 4, and also comprising a backplane to be tested, wherein the hard disk connection module of the backplane to be tested is connected to the cable module in the debugging fixture, the second connection module of the backplane to be tested is connected to the first connection module in the debugging fixture, the second connection module is also connected to the second CPLD module of the backplane to be tested, and the second CPLD module is connected to the indication module of the backplane to be tested.

6. The debugging system for a liquid-cooled hard disk backplane according to claim 5, characterized in that: The second connection module includes a fifth connector, a sixth connector, a seventh connector and an eighth connector, the fifth connector is connected to the second CPLD module via an SGPIO bus, the sixth connector is connected to the second CPLD module via an I2C bus, the seventh connector is connected to the second CPLD module via an I2C bus, the eighth connector is connected to the second CPLD module, and is also connected to both the field replaceable unit and the temperature sensor.

7. A method for debugging a liquid-cooled hard disk backplane, characterized in that: The debugging system applied to the liquid-cooled hard disk backplane described in claims 5-6 comprises: When the first CPLD module of the debugging fixture receives an information selection instruction through the display module and the key module of the debugging fixture, target information corresponding to the backplane to be tested is selected from the preset information according to the information selection instruction; wherein the target information includes a target mode to be debugged and the number of target hard disks, and the target mode to be debugged includes an SGPIO mode, a Legacy VPP mode, and an NPEM mode; If the first CPLD module determines that the target mode to be debugged is the SGPIO mode, it generates a first analog signal, and sends the first analog signal to the first target hard disk connectors in the hard disk connection module of the backplane to be tested, which are equal to the number of the target hard disks, through the first target cable components in the cable module of the debugging fixture, which are equal to the number of the target hard disks, and generates an SGPIO signal of the indication module for controlling the backplane to be tested, and sends the SGPIO signal to the second CPLD module of the backplane to be tested through the first connection module of the debugging fixture and the second connection module of the backplane to be tested; If the first CPLD module determines that the target mode to be debugged is the Legacy VPP or NPEM mode, the target I2C address is read from the preset I2C address, and a second analog signal is generated, and the second analog signal is sent to the second target hard disk connectors in the hard disk connection module, which are equal in number to the target hard disks, through the second target cable components in the cable module, which are equal in number to the target hard disks, and the interrupt signal sent by the second CPLD module is received and detected through the first connection module and the second connection module; If the first CPLD module detects that the interrupt signal corresponds one-to-one with the target hard disk, the first CPLD module controls to end the interrupt detection, generates an I2C signal for controlling the indicator module of the backplane to be tested, and sends the I2C signal to the second CPLD module through the first connection module and the second connection module based on the target I2C address; The second CPLD module performs state control on the indication module of the backplane to be tested according to the SGPIO signal or the I2C signal to obtain a first state indication result or a second state indication result, and sends the first state indication result or the second state indication result to the first CPLD module; If the first CPLD module detects that the first state indication result is consistent with the first preset state or the second state indication result is consistent with the second preset state, the debugging of the backplane to be tested is controlled to end.

8. The method for debugging a liquid-cooled hard disk backplane according to claim 7, characterized in that: The second CPLD module performs state control on the indication module of the backplane to be tested according to the SGPIO signal or the I2C signal to obtain a first state indication result or a second state indication result, including: The second CPLD module analyzes the SGPIO signal or the I2C signal to obtain a first analysis result or a second analysis result; The second CPLD module controls the states of target indicator lights in the indication module, the number of which is equal to the number of the target hard disks, according to the first analysis result or the second analysis result, to obtain a first state indication result or a second state indication result.

9. The method for debugging a liquid-cooled hard disk backplane according to claim 7, characterized in that: After the first connection module and the second connection module receive and detect the interrupt signal sent by the second CPLD module, the method further includes: If the first CPLD module detects that the interrupt signal does not correspond one-to-one to the target hard disk, interrupt exception information is generated.

10. The method for debugging a liquid-cooled hard disk backplane according to claim 7, characterized in that: After obtaining the first status indication result or the second status indication result, the method further includes: If the first CPLD module detects that the first state indication result is inconsistent with the first preset state or the second state indication result is inconsistent with the second preset state, it generates lighting abnormality prompt information.

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