Chip testing device based on multi-station parallelism and optimization method

Abstract

The invention provides a chip testing device and optimization method based on multi-station parallelism, and relates to the technical field of chip testing, and the method comprises the steps: executing the chip testing of a first testing link according to a first priority sequence, and outputting a first testing result set; performing feature extraction according to the second associated features to obtain a second feature set, inputting the first test result set and the second feature set into a second fault prediction unit, and outputting a second prediction probability set; and setting a second priority sequence according to the second prediction probability set to execute the chip test of the second test link. According to the chip testing method and device, the technical problems that the chip testing priority setting is unreasonable, the testing resource utilization rate is low and the chip testing efficiency is influenced due to the fact that the chip fault risk cannot be accurately evaluated in an existing chip testing method can be solved, the scientificity and the accuracy of the chip testing priority setting can be improved, and the chip testing efficiency is improved. Potential faults can be found and processed earlier, and follow-up testing time is shortened.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and in particular to a chip testing device and optimization method based on multi-station parallelism. Background Art

[0002] In today's semiconductor manufacturing industry, chip testing is a crucial link. With the continuous advancement of technology, the complexity of chips continues to increase, and the requirements for testing are getting higher and higher. In this context, multi-station parallel chip testing methods have emerged. This method can test multiple chips at the same time, thereby greatly improving testing efficiency and production efficiency.

[0003] At present, the existing multi-station parallel chip testing method is unable to accurately assess the chip failure risk in each testing link, resulting in unreasonable chip testing priority setting, low test resource utilization, and technical problems affecting chip testing efficiency and production efficiency. Summary of the invention

[0004] The purpose of this application is to provide a chip testing device and optimization method based on multi-station parallelism, so as to solve the technical problem that the existing multi-station parallel chip testing method cannot accurately evaluate the chip failure risk in each test link, resulting in unreasonable chip test priority setting, low test resource utilization, and affecting chip testing efficiency and production efficiency.

[0005] In view of the above problems, the present application provides a chip testing device and optimization method based on multi-station parallelism.

[0006] In a first aspect, the present application provides a chip test optimization method based on multi-station parallelism, which is implemented by a chip test device based on multi-station parallelism, including: reading a chip test process, determining multiple test links and multiple expected indicators, wherein the test link has a sequence identifier; selecting a first test link from the multiple test links, obtaining a first test indicator of the first test link, determining a first correlation feature based on the first test indicator, performing feature extraction on a target chip set according to the first correlation feature to obtain a first feature set, inputting the first feature set into a first fault prediction unit, and outputting a first prediction probability set; setting a first priority sequence according to the first prediction probability set, performing chip testing of the first test link of the target chip set according to the first priority sequence, and outputting a first test result set; determining a second correlation feature based on a second test indicator, performing feature extraction on the target chip set according to the second correlation feature to obtain a second feature set, inputting the first test result set and the second feature set into a second fault prediction unit, and outputting a second prediction probability set; setting a second priority sequence according to the second prediction probability set, performing chip testing of the second test link of the target chip set according to the second priority sequence, and outputting a second test result set; performing iterative testing based on the second test result set until the chip test process is completed and multiple test result sets are output.

[0007] In a second aspect, the present application further provides a chip testing device based on multi-station parallelism, which is used to execute a chip testing optimization method based on multi-station parallelism as described in the first aspect, including: a chip testing process reading module, which is used to read the chip testing process, determine multiple testing links and multiple expected indicators, wherein the testing links have a sequence identifier; a first fault prediction module, which is used to select a first testing link from the multiple testing links, obtain a first test indicator of the first testing link, determine a first associated feature based on the first test indicator, extract features of a target chip set according to the first associated feature, obtain a first feature set, input the first feature set into a first fault prediction unit, and output a first prediction probability set; a first priority sequence setting module, which is used to set a first priority sequence according to the first prediction probability set. A priority sequence is used to perform chip testing of the first test phase of the target chip set according to the first priority sequence, and output a first test result set; a second fault prediction module is used to determine a second associated feature based on a second test indicator, extract features of the target chip set according to the second associated feature, obtain a second feature set, input the first test result set and the second feature set into a second fault prediction unit, and output a second prediction probability set; a second priority sequence setting module is used to set a second priority sequence according to the second prediction probability set, perform chip testing of the second test phase of the target chip set according to the second priority sequence, and output a second test result set; an iterative testing module is used to perform iterative testing based on the second test result set until the chip testing process is completed, and output multiple test result sets.

[0008] One or more technical solutions provided in this application have at least the following technical effects or advantages: By analyzing and determining a first correlation feature based on a first test indicator of the first test link, the first correlation feature refers to a chip feature that is highly correlated with the first test result, and then extracting features from a target chip set based on the first correlation feature to obtain a first feature set, and then inputting the first feature set into a first fault prediction unit, outputting a first prediction probability set, and further setting a first priority sequence based on the first prediction probability set, the accuracy and rationality of chip test priority setting in the first test link can be improved; then, the chip test of the first test link of the target chip set is performed according to the first priority sequence, and a first test result set is output; then, a second correlation feature is determined based on a second test indicator, and features are extracted from the target chip set based on the second correlation feature to obtain a second feature set; then, the first test link is used as the first priority sequence to output the first test result set; The test result set and the second feature set are input into the second fault prediction unit, and the second prediction probability set is output. The second priority sequence is set according to the second prediction probability set, which can improve the accuracy and rationality of the chip test priority setting in the second test link; then the chip test of the second test link of the target chip set is performed according to the second priority sequence, and the second test result set is output; finally, the same method is used to perform iterative testing until the entire chip test process is completed, and multiple test result sets are output; the above steps can improve the scientificity and accuracy of the chip test priority setting, and by giving priority to testing high-risk chips, potential faults can be discovered and handled earlier, reducing subsequent testing time, and improving test resource utilization and chip testing efficiency, thereby achieving the technical effect of improving the overall chip production efficiency.

[0009] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented according to the contents of the specification, and in order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are specifically cited below. It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present application, nor is it intended to limit the scope of the present application. Other features of the present application will become easy to understand through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the present application or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only exemplary, and for ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0011] Figure 1 A schematic diagram of a chip test optimization method based on multi-station parallelism for this application; Figure 2A schematic diagram of a flow chart of iterative testing based on a second test result set in a chip testing optimization method based on multi-station parallelism in the present application; Figure 3 This is a schematic diagram of the structure of a chip testing device based on multi-station parallelism in the present application.

[0012] Description of reference numerals: Chip test process reading module 11, first fault prediction module 12, first priority sequence setting module 13, second fault prediction module 14, second priority sequence setting module 15, iterative test module 16. DETAILED DESCRIPTION

[0013] This application provides a chip testing device and optimization method based on multi-station parallelism, which solves the technical problem that the existing multi-station parallel chip testing method cannot accurately evaluate the chip failure risk in each test link, resulting in unreasonable chip test priority setting, low test resource utilization, and affecting chip test efficiency and production efficiency. The scientificity and accuracy of chip test priority setting can be improved. By giving priority to testing high-risk chips, potential faults can be discovered and handled earlier, reducing subsequent test time, improving test resource utilization and chip test efficiency, thereby achieving the technical effect of improving the overall chip production efficiency.

[0014] Below, the technical solutions in the present application will be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments of the present application. It should be understood that the present application is not limited to the example embodiments described herein. Based on the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present application. It should also be noted that, for the convenience of description, only the parts related to the present application are shown in the accompanying drawings, rather than all of them.

[0015] For example, please refer to the attached Figure 1 The present application provides a chip testing optimization method based on multi-station parallelism, which is applied to a chip testing device based on multi-station parallelism, and specifically includes the following steps: Step 1: Read the chip test process, determine multiple test links and multiple expected indicators, where the test links have a sequence mark.

[0016] Specifically, the chip testing process includes multiple test links with a sequence, and each link will test different characteristics or functions of the chip. First, read the chip testing process to determine multiple test links and multiple expected indicators, where the test links and expected indicators correspond one to one and can be set according to actual conditions. For example, the test links can be divided into functional tests, performance tests, aging tests, environmental tests, etc.; expected indicators refer to the detection standards corresponding to each test link. For example, the expected indicators of the performance test link include processing speed indicators, power consumption indicators, frequency response indicators, etc. By determining multiple test links and multiple expected indicators, support is provided for the next step of fine-grained chip testing.

[0017] Step 2: Select a first test link from the multiple test links, obtain a first test indicator of the first test link, determine a first correlation feature based on the first test indicator, extract features of the target chip set according to the first correlation feature to obtain a first feature set, input the first feature set into a first fault prediction unit, and output a first prediction probability set.

[0018] Specifically, first, the first test link is selected from the multiple test links, the first test link refers to the starting test link of the chip test process, and the first test indicator of the first test link is obtained. For example, the first test link is a functional test, and the first test indicator includes logic function verification indicators, arithmetic operation indicators, and read-write indicators.

[0019] Construct a feature database of the target chip, which contains multiple features of the target chip, such as material properties, process parameters, geometric dimensions, circuit layout, circuit channels, welding features, etc., which can be set according to actual conditions; then, based on the feature database, sequentially perform correlation analysis on multiple chip features and the first test index, and use statistical methods or machine learning algorithms to perform correlation analysis on the collected data, such as Pearson correlation coefficient, regression analysis, etc., and select one or more features with a high degree of correlation as the first correlation feature. Further, extract features from multiple target chips in the target chip set based on the first correlation feature, for example, various test equipment and tools, such as probe stations, electron microscopes, etc., can be used to obtain the first feature set.

[0020] Configure a fault prediction operator, wherein the fault prediction operator includes at least a BP neural network, a support vector machine, and a random decision forest. A person skilled in the art may also add additional operators according to actual needs; then construct a first fault prediction unit based on the fault prediction operator, and obtain a sample data set to train the first fault prediction unit to a convergence state, wherein the input data of the first fault prediction unit is the first feature, and the output data is the fault prediction probability. By constructing a fault prediction unit based on a BP neural network, a support vector machine, and a random decision forest, the advantages of the three algorithms can be combined to reduce the prediction error of a single algorithm, thereby improving the accuracy, robustness, and reliability of fault prediction.

[0021] Then, multiple first features in the first feature set are respectively input into the first fault prediction unit to output a first prediction probability set, wherein the first prediction probability corresponds to the target chip one-to-one, and the larger the prediction probability, the greater the risk level of the target chip in the first test link.

[0022] Step three: setting a first priority sequence according to the first prediction probability set, executing chip testing of the first test phase of the target chipset according to the first priority sequence, and outputting a first test result set.

[0023] Specifically, a first priority sequence is set according to the first prediction probability set, that is, the target chip set is sorted from high to low according to the predicted failure probability according to the first prediction probability set. The chips with higher predicted probabilities have higher priorities, which means that they will be tested first. Then, test resources are allocated according to the priority sequence, such as high-risk chips should be allocated to experienced test engineers and more accurate test equipment to ensure that potential problems can be accurately identified and diagnosed; further, according to the first priority sequence, the chip test of the first test link is performed on the target chip set to obtain a first test result set.

[0024] By setting the first priority sequence according to the first prediction probability set to perform chip testing in the first stage, the accuracy and scientificity of chip priority setting in the first testing stage can be improved, thereby improving the utilization rate of testing resources in the first testing stage.

[0025] Step 4: Determine a second correlation feature based on the second test indicator, extract features of the target chip set according to the second correlation feature to obtain a second feature set, input the first test result set and the second feature set into a second fault prediction unit, and output a second prediction probability set.

[0026] Specifically, a second test link is selected from the multiple test links, wherein the second test link is the next test link adjacent to the first test link, and a second test indicator of the second test link is obtained; then, based on the feature database of the target chip, a second associated feature is determined according to the second test indicator, and the second associated feature refers to a chip feature with a high degree of association with the second test indicator. Further, feature extraction is performed on the target chip set according to the second associated feature to obtain a second feature set. On the other hand, the correlation between multiple test indicators in the first test result set and the second test indicator is analyzed, and test indicators with a high degree of association are selected to construct a first test feature set.

[0027] A second fault prediction unit is constructed based on the fault prediction operator, wherein the input data of the second fault prediction unit is the first test feature and the second feature, and the output data is the second prediction probability; the first test feature set and the second feature set are further input into the second fault prediction unit, and the second prediction probability set is output.

[0028] Step 5: Set a second priority sequence according to the second prediction probability set, perform chip testing of the second test phase of the target chipset according to the second priority sequence, and output a second test result set.

[0029] Specifically, according to the second prediction probability set, multiple target chips in the target chip set are reordered from large to small according to the second prediction probability, and the priority of the second test link is determined, wherein the chips with higher prediction probabilities will be tested first, and a second priority sequence is generated. Then, according to the second priority sequence, test resources are allocated to ensure that high-risk chips receive appropriate attention and resources; further, the chip test of the second test link of the target chip set is performed according to the second priority sequence, and a second test result set is output.

[0030] By setting the second priority sequence according to the second prediction probability set to perform chip testing in the second stage, the accuracy and scientificity of chip priority setting in the second testing stage can be improved, thereby improving the utilization rate of testing resources in the second testing stage.

[0031] Step six: Perform iterative testing based on the second test result set until the chip test process is completed and multiple test result sets are output.

[0032] Specifically, the above method is used to perform iterative testing, that is, through the fault prediction model, the fault prediction probability set of the subsequent test link is output, and a new priority sequence is set accordingly; further according to the new priority sequence, the subsequent test links are executed until all the predetermined test links in the chip test process are completed, wherein each iteration performs a fault probability prediction based on the test results of the previous link to improve the targetedness and efficiency of the test; and finally, multiple test result sets are output, wherein the test result sets correspond to the target chips one by one.

[0033] The chip test optimization method based on multi-station parallelism is applied to a chip test device based on multi-station parallelism, which can solve the technical problem that the chip test priority setting in the existing multi-station parallelism method is unreasonable due to the inability to accurately evaluate the chip failure risk of each test link, resulting in low test resource utilization, affecting chip test efficiency and production efficiency. The first correlation feature is determined by analyzing the first test indicator based on the first test link, and the first correlation feature refers to the chip feature with a high degree of correlation with the first test result. Then, the target chip set is feature extracted according to the first correlation feature to obtain a first feature set, and then the first feature set is input into the first fault prediction unit, and the first prediction probability set is output. The first priority sequence is further set according to the first prediction probability set, which can improve the accuracy and rationality of the chip test priority setting in the first test link; then the chip test of the first test link of the target chip set is performed according to the first priority sequence, and the first test result set is output; then the second correlation feature is determined based on the second test indicator, and the target chip set is feature extracted according to the second correlation feature to obtain a second feature set; then the first test link is performed according to the first priority sequence, and the chip test of the first test link is performed according to the first priority sequence, and the first test result set is output; then the second correlation feature is determined based on the second test indicator, and the second feature set is obtained by extracting the feature of the target chip set according to the second correlation feature ... chip test of the first test link is performed according to the first priority sequence, and the chip test of the first test link is performed according to the first priority sequence, and the chip test of the first test link is performed according to the The test result set and the second feature set are input into the second fault prediction unit, and the second prediction probability set is output. The second priority sequence is set according to the second prediction probability set, which can improve the accuracy and rationality of the chip test priority setting in the second test link; then the chip test of the second test link of the target chip set is performed according to the second priority sequence, and the second test result set is output; finally, the same method is used to perform iterative testing until the entire chip test process is completed, and multiple test result sets are output; the above steps can improve the scientificity and accuracy of the chip test priority setting, and by giving priority to testing high-risk chips, potential faults can be discovered and handled earlier, reducing subsequent testing time, and improving test resource utilization and chip testing efficiency, thereby achieving the technical effect of improving the overall chip production efficiency.

[0034] Further, based on the first test indicator, the first correlation feature is determined, and step 2 of the present application includes: Execute feature enumeration of the target chip and construct a chip feature system, wherein the chip feature system includes multiple chip features; perform correlation analysis on the multiple chip features and the first test indicator respectively to determine multiple correlation coefficients; judge the multiple correlation coefficients according to a predetermined correlation threshold, and select the chip feature corresponding to the correlation coefficient greater than the predetermined correlation threshold to set it as the first correlation feature.

[0035] Specifically, first, perform feature enumeration of the target chip, that is, list the chip features of the target chip before chip testing, such as material type, circuit channel, physical structure, welding features and other data. Material type refers to the type of semiconductor material used in the chip, such as silicon, germanium, gallium arsenide, etc.; circuit channel refers to the circuit layout and channel design on the chip, including the configuration of metal layers, insulating layers and connecting lines; physical structure refers to the physical size and structure of the chip, such as transistor size, interconnection length, chip thickness, etc.; welding features refer to the characteristics of welding points during chip packaging, including solder type, welding quality and the physical structure of welding points; determine multiple chip features to construct a chip feature system.

[0036] Then, correlation analysis is performed on the multiple chip features and the first test indicator respectively to determine multiple correlation coefficients; for example, a statistical method or a machine learning algorithm is used to analyze the correlation between the chip features and the first test indicator, for example, the Pearson correlation coefficient, a decision tree, etc. For each chip feature, the correlation coefficient between it and the first test indicator is calculated. This coefficient is a quantitative indicator, which represents the degree of correlation between the chip feature and the test indicator, wherein the larger the correlation coefficient, the greater the degree of correlation.

[0037] Then, according to business needs and data characteristics, a predetermined correlation threshold is configured. This threshold is a standard used to determine which characteristics corresponding to which correlation coefficients are sufficiently correlated with the first test indicator; then, the multiple correlation coefficients are judged according to the predetermined correlation threshold, and the chip characteristics corresponding to the correlation coefficients greater than the predetermined correlation threshold are selected and set as the first correlation characteristics.

[0038] Further, the first fault prediction unit is constructed, and step 2 of the present application includes: Taking the attribute information of the target chip and the first expected indicator as constraints, the network is used to perform homologous information retrieval to obtain a first sample data set, wherein the first sample data includes a first feature of the sample and a first fault probability of the sample; a fault prediction operator is configured, wherein the fault prediction operator includes at least a BP neural network, a support vector machine and a random decision forest; the first sample data set is divided into Q equal parts, and Q parts are selected with replacement for Q times to generate a first sample set, and Q sample sets are selected iteratively for Q times to obtain Q sample sets, wherein Q is the number of fault prediction operators; taking the first feature of the sample as input and the first fault probability of the sample as supervision, the BP neural network, the support vector machine and the random decision forest are supervised and trained and cross-validated using the Q sample sets to obtain a first prediction model, a second prediction model and a third prediction model that meet the expected convergence constraints; a fault prediction layer is constructed based on the first prediction model, the second prediction model and the third prediction model, and the first fault prediction unit is constructed in combination with the mean calculation layer.

[0039] Specifically, the attribute information of the target chip and the first expected indicator are used as retrieval constraints, wherein the attribute information of the target chip includes chip type, design specifications, material properties and other data, and homologous information retrieval is performed online to obtain a first sample data set, wherein the first sample data includes a sample first feature and a sample first failure probability.

[0040] Then configure the fault prediction operator, which includes at least BP neural network, support vector machine and random decision forest. Those skilled in the art can also add additional prediction operators according to actual needs. BP neural network is a multi-layer feedforward neural network. It adjusts the network weights through the back propagation algorithm to minimize the prediction error. It is suitable for dealing with nonlinear problems and can capture complex relationships in data. Support vector machine finds an optimal hyperplane to separate data points of different categories and maximizes the margin. It is suitable for classification and regression problems. Random decision forest improves the accuracy of prediction by building multiple decision trees and voting. It is suitable for high-dimensional feature space. By combining multiple algorithms for ensemble learning, the accuracy and robustness of prediction can be improved.

[0041] Then the first sample data set is divided into Q parts, where Q is the number of fault prediction operators. Then, the Q parts of the data set are selected with replacement Q times to generate a first sample set. The same method is used to iteratively select Q times to obtain Q sample sets. Then, the first feature of the sample is used as input, the first fault probability of the sample is used as supervision, and the Q sample sets are used to perform supervised training on the BP neural network, support vector machine and random decision forest respectively. For example, model training can be performed through back propagation algorithm, gradient descent algorithm, etc. After the predetermined number of training times is met, the sample sets are exchanged for verification training until the predetermined convergence constraints are met to obtain the first prediction model, the second prediction model and the third prediction model.

[0042] Based on the first prediction model, the second prediction model and the third prediction model, a fault prediction layer is constructed, and a mean calculation layer is set, wherein the mean calculation layer is used to calculate and output the mean of the output results of the first prediction model, the second prediction model and the third prediction model; finally, the first fault prediction unit is constructed based on the fault prediction layer and the mean calculation layer, wherein the output of the first fault prediction unit is the mean of the output results of the first fault prediction model, the second fault prediction model and the third fault prediction model. By constructing a fault prediction unit based on BP neural network, support vector machine and random decision forest, the advantages of the three algorithms can be combined to reduce the prediction error of a single algorithm, thereby improving the accuracy, robustness and reliability of fault prediction.

[0043] Further, the second prediction probability set is outputted, and step 4 of the present application includes: Acquire multiple first indicator features of the first test indicator, perform correlation analysis on the second test indicator and the multiple first indicator features respectively, and select the first indicator feature whose correlation coefficient is greater than a predetermined coefficient threshold as the first test feature to generate a first test feature set; perform feature extraction on the first test result set according to the first test feature set to obtain multiple first test feature data; input the multiple first test feature data and the second feature set into the second fault prediction unit, and output the second prediction probability set.

[0044] Specifically, first, multiple first indicator characteristics of the first test indicator are obtained. Assuming that the first test indicator is an electrical parameter test, the first characteristic indicator includes parameters such as voltage, current, and power; then, the second test indicator and the multiple first indicator characteristics are respectively analyzed for correlation, and the analysis can be performed through an adaptive algorithm or machine learning to obtain multiple correlation coefficients; then, the first indicator characteristic whose correlation coefficient is greater than a predetermined coefficient threshold is selected and set as the first test feature to obtain a first test feature set.

[0045] Further, feature extraction is performed on the first test result set according to the first test feature set to obtain a plurality of first test feature data; then the plurality of first test feature data and the second feature set are input into a second fault prediction unit for fault prediction, and a second prediction probability set is output.

[0046] Further, to output the second prediction probability set, the present application further comprises the following steps: Based on the first test result set, an overall deviation analysis is performed on the first test results of multiple target chips in turn according to the deviation analysis strategy to determine multiple first deviation coefficients, wherein the deviation analysis strategy includes mean deviation, standard deviation, and maximum and minimum deviations; based on the multiple first deviation coefficients, mapping compensation is performed on the second prediction probability set, and the second prediction probability set is output, wherein the deviation coefficient is proportional to the probability increase.

[0047] Specifically, a deviation analysis strategy is configured, wherein the deviation analysis strategy includes mean deviation, standard deviation, and maximum and minimum deviations, and each deviation analysis indicator includes a weight value, and the weight value is set based on the degree of influence on the overall deviation, and the greater the degree of influence, the greater the corresponding weight; then based on the first test result set, an overall deviation analysis is performed on the first test results of multiple target chips in turn according to the deviation analysis strategy, that is, the mean deviation, standard deviation, and maximum and minimum deviations of the first test results are weightedly calculated to obtain multiple first deviation coefficients, and the deviation coefficient characterizes the overall deviation degree of the first test result.

[0048] Then, based on the multiple first deviation coefficients, the second prediction probability set is mapped and compensated, wherein the deviation coefficient is proportional to the probability increase. For example, a standard deviation coefficient can be set, and then the deviation of the multiple first deviation coefficients is calculated based on the standard deviation coefficient to obtain multiple first deviation values, wherein the first deviation value is the difference between the first deviation coefficient and the standard deviation coefficient; if the first deviation value is greater than 0, the probability is increasing, wherein the larger the deviation value, the greater the probability increase; if the first deviation value is less than 0, the probability is decreasing, wherein the smaller the deviation value, the greater the probability decrease. The second prediction probability set after mapping compensation is obtained. By calculating the overall deviation of the first test result to optimize and compensate the second prediction probability, the accuracy and reliability of the second prediction probability setting can be further improved.

[0049] Further, to construct a second fault prediction unit, the present application also includes the following steps: Taking the attribute information of the target chip and the second expected indicator as constraints, retrieve and obtain the second sample data set, wherein the second sample data includes the sample first test feature data, the sample second feature and the sample second failure probability; taking the sample first test feature data and the sample second feature as input, and taking the sample second failure probability as supervision, supervised training and cross-validation are performed on the BP neural network, support vector machine and random decision forest through the second sample data set to obtain the second fault prediction unit.

[0050] Specifically, the attribute information of the target chip and the second expected index are used as the search constraint conditions, and the same source information is retrieved online to obtain the second sample data set, wherein the second sample data includes the first test feature data of the sample, the second feature of the sample, and the second fault probability of the sample. Further, the first test feature data of the sample and the second feature of the sample are used as input, and the second fault probability of the sample is used as supervision. The BP neural network, support vector machine, and random decision forest are supervised and cross-validated through the second sample data set, wherein the training method of the second fault prediction unit is the same as that of the first fault prediction unit, and the training method of the first fault prediction unit can be referred to, and will not be described in detail here.

[0051] Further, an iterative test is performed based on the second test result set, as shown in the attached Figure 2 As shown, step six of this application includes: Determine a third correlation feature based on the third test indicator, perform feature extraction on the target chip set according to the third correlation feature, and obtain a third feature set; input the third feature set, the first test result set, and the second test result set into a third fault prediction unit, and output a third prediction probability set; set a third priority sequence based on the third prediction probability set, and perform iterative testing on the target chip set according to the third priority sequence.

[0052] Specifically, the third test indicator of the third test link is obtained, and the third associated feature is determined according to the third test indicator; further, the target chip set is feature extracted according to the third associated feature to obtain a third feature set; on the other hand, based on the first test result set and the second test result set, the third test indicator is respectively associated and analyzed to obtain first test feature data and second test feature data; then a third fault prediction unit is constructed based on the fault prediction operator, wherein the input data of the third fault prediction unit is the third feature set, the first test feature data and the second test feature data, and the output data is the third fault prediction probability; then the third feature set, the first test feature data and the second test feature data are input into the third fault prediction unit, and a third prediction probability set is output; finally, a third priority sequence is set based on the third prediction probability set, and iterative testing is performed on the target chip set according to the third priority sequence until the entire chip testing process is completed.

[0053] In summary, the chip testing optimization method based on multi-station parallelism provided by the present application has the following technical effects: 1. Determine a first correlation feature by analyzing a first test indicator based on a first test link, the first correlation feature refers to a chip feature that is highly correlated with a first test result, then extract features of a target chip set based on the first correlation feature to obtain a first feature set, then input the first feature set into a first fault prediction unit, output a first prediction probability set, and further set a first priority sequence based on the first prediction probability set, so as to improve the accuracy and rationality of chip test priority setting in the first test link; then perform chip testing of the first test link of the target chip set according to the first priority sequence, and output a first test result set; then determine a second correlation feature based on a second test indicator, extract features of the target chip set based on the second correlation feature, and obtain a second feature set; then input the first feature set into a first fault prediction unit, output a first prediction probability set, and further set a first priority sequence based on the first prediction probability set, so as to improve the accuracy and rationality of chip test priority setting in the first test link; then perform chip testing of the first test link of the target chip set according to the first priority sequence, and output a first test result set; then determine a second correlation feature based on a second test indicator, and extract features of the target chip set based on the second correlation feature to obtain a second feature set; then The test result set and the second feature set are input into the second fault prediction unit, and the second prediction probability set is output. The second priority sequence is set according to the second prediction probability set, which can improve the accuracy and rationality of the chip test priority setting in the second test link; then the chip test of the second test link of the target chip set is performed according to the second priority sequence, and the second test result set is output; finally, the same method is used to perform iterative testing until the entire chip test process is completed, and multiple test result sets are output; the above steps can improve the scientificity and accuracy of the chip test priority setting, and by giving priority to testing high-risk chips, potential faults can be discovered and handled earlier, reducing subsequent testing time, and improving test resource utilization and chip testing efficiency, thereby achieving the technical effect of improving the overall chip production efficiency.

[0054] 2. By constructing a fault prediction unit based on BP neural network, support vector machine and random decision forest, the advantages of the three algorithms can be combined to reduce the prediction error of a single algorithm, thereby improving the accuracy, robustness and reliability of fault prediction.

[0055] Embodiment 2, based on the chip test optimization method based on multi-station parallelism in the previous embodiment, the same inventive concept, this application also provides a chip test device based on multi-station parallelism, please refer to the attached Figure 3 ,include: The chip test process reading module 11 is used to read the chip test process and determine multiple test links and multiple expected indicators, wherein the test links have a sequence identifier.

[0056] The first fault prediction module 12 is used to select a first test link from the multiple test links, obtain a first test indicator for the first test link, determine a first correlation feature based on the first test indicator, extract features of a target chip set according to the first correlation feature to obtain a first feature set, input the first feature set into a first fault prediction unit, and output a first prediction probability set.

[0057] The first priority sequence setting module 13 is used to set a first priority sequence according to the first prediction probability set, perform chip testing of the first test link of the target chipset according to the first priority sequence, and output a first test result set.

[0058] The second fault prediction module 14 is used to determine a second correlation feature based on a second test indicator, perform feature extraction on a target chip set according to the second correlation feature to obtain a second feature set, input the first test result set and the second feature set into a second fault prediction unit, and output a second prediction probability set.

[0059] The second priority sequence setting module 15 is used to set a second priority sequence according to the second prediction probability set, perform chip testing of the second test link of the target chipset according to the second priority sequence, and output a second test result set.

[0060] The iterative testing module 16 is used to perform iterative testing based on the second test result set until the chip testing process is completed and output multiple test result sets.

[0061] Furthermore, the multi-station parallel chip testing device is also used for: Determine a third correlation feature based on the third test indicator, perform feature extraction on the target chip set according to the third correlation feature, and obtain a third feature set; input the third feature set, the first test result set, and the second test result set into a third fault prediction unit, and output a third prediction probability set; set a third priority sequence based on the third prediction probability set, and perform iterative testing on the target chip set according to the third priority sequence.

[0062] Furthermore, the multi-station parallel chip testing device is also used for: Execute feature enumeration of the target chip and construct a chip feature system, wherein the chip feature system includes multiple chip features; perform correlation analysis on the multiple chip features and the first test indicator respectively to determine multiple correlation coefficients; judge the multiple correlation coefficients according to a predetermined correlation threshold, and select the chip feature corresponding to the correlation coefficient greater than the predetermined correlation threshold to set it as the first correlation feature.

[0063] Furthermore, the multi-station parallel chip testing device is also used for: Taking the attribute information of the target chip and the first expected indicator as constraints, the network is used to perform homologous information retrieval to obtain a first sample data set, wherein the first sample data includes a first feature of the sample and a first fault probability of the sample; a fault prediction operator is configured, wherein the fault prediction operator includes at least a BP neural network, a support vector machine and a random decision forest; the first sample data set is divided into Q equal parts, and Q parts are selected with replacement for Q times to generate a first sample set, and Q sample sets are selected iteratively for Q times to obtain Q sample sets, wherein Q is the number of fault prediction operators; taking the first feature of the sample as input and the first fault probability of the sample as supervision, the BP neural network, the support vector machine and the random decision forest are supervised and trained and cross-validated using the Q sample sets to obtain a first prediction model, a second prediction model and a third prediction model that meet the expected convergence constraints; a fault prediction layer is constructed based on the first prediction model, the second prediction model and the third prediction model, and the first fault prediction unit is constructed in combination with the mean calculation layer.

[0064] Furthermore, the multi-station parallel chip testing device is also used for: Acquire multiple first indicator features of the first test indicator, perform correlation analysis on the second test indicator and the multiple first indicator features respectively, and select the first indicator feature whose correlation coefficient is greater than a predetermined coefficient threshold as the first test feature to generate a first test feature set; perform feature extraction on the first test result set according to the first test feature set to obtain multiple first test feature data; input the multiple first test feature data and the second feature set into the second fault prediction unit, and output the second prediction probability set.

[0065] Furthermore, the multi-station parallel chip testing device is also used for: Based on the first test result set, an overall deviation analysis is performed on the first test results of multiple target chips in turn according to the deviation analysis strategy to determine multiple first deviation coefficients, wherein the deviation analysis strategy includes mean deviation, standard deviation, and maximum and minimum deviations; based on the multiple first deviation coefficients, mapping compensation is performed on the second prediction probability set, and the second prediction probability set is output, wherein the deviation coefficient is proportional to the probability increase.

[0066] Furthermore, the multi-station parallel chip testing device is also used for: Taking the attribute information of the target chip and the second expected indicator as constraints, retrieve and obtain the second sample data set, wherein the second sample data includes the sample first test feature data, the sample second feature and the sample second failure probability; taking the sample first test feature data and the sample second feature as input, and taking the sample second failure probability as supervision, supervised training and cross-validation are performed on the BP neural network, support vector machine and random decision forest through the second sample data set to obtain the second fault prediction unit.

[0067] Each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The chip test optimization method based on multi-station parallelism and the specific examples in the aforementioned embodiment 1 are also applicable to a chip test device based on multi-station parallelism in this embodiment. Through the aforementioned detailed description of a chip test optimization method based on multi-station parallelism, those skilled in the art can clearly know the chip test device based on multi-station parallelism in this embodiment, so for the sake of brevity of the specification, it will not be described in detail here. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0068] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

[0069] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application belong to the scope of the present application and its equivalent technology, the present application is also intended to include these modifications and variations.

Claims

1. A chip test optimization method based on multi-station parallelism, characterized in that: include: Read the chip test process, determine multiple test links and multiple expected indicators, where the test links have a sequence mark; Selecting a first test link from the multiple test links, obtaining a first test indicator of the first test link, determining a first correlation feature based on the first test indicator, performing feature extraction on a target chipset according to the first correlation feature to obtain a first feature set, inputting the first feature set into a first fault prediction unit, and outputting a first prediction probability set; Setting a first priority sequence according to the first prediction probability set, performing chip testing of a first test phase of a target chipset according to the first priority sequence, and outputting a first test result set; Determine a second correlation feature based on a second test indicator, extract features of a target chipset according to the second correlation feature to obtain a second feature set, input the first test result set and the second feature set into a second fault prediction unit, and output a second prediction probability set; Setting a second priority sequence according to the second prediction probability set, performing chip testing of a second test phase of the target chipset according to the second priority sequence, and outputting a second test result set; Iterative testing is performed based on the second test result set until the chip test process is completed, and multiple test result sets are output.

2. The chip test optimization method based on multi-station parallelism according to claim 1 is characterized in that: Performing iterative testing based on the second test result set includes: Determine a third correlation feature based on the third test indicator, and extract features of the target chipset according to the third correlation feature to obtain a third feature set; Inputting the third feature set, the first test result set and the second test result set into a third fault prediction unit, and outputting a third prediction probability set; A third priority sequence is set based on the third prediction probability set, and an iterative test is performed on the target chipset according to the third priority sequence.

3. The chip testing optimization method based on multi-station parallelism according to claim 1 is characterized in that: Determining a first correlation feature based on the first test indicator includes: Perform feature enumeration of a target chip and construct a chip feature system, wherein the chip feature system includes multiple chip features; Performing correlation analysis on the plurality of chip features and the first test index respectively to determine a plurality of correlation coefficients; The plurality of correlation coefficients are judged according to a predetermined correlation threshold, and a chip feature corresponding to a correlation coefficient greater than the predetermined correlation threshold is selected and set as the first correlation feature.

4. The chip testing optimization method based on multi-station parallelism according to claim 1 is characterized in that: Constructing a first fault prediction unit, including: Taking the attribute information of the target chip and the first expected indicator as constraints, performing homologous information retrieval online to obtain a first sample data set, wherein the first sample data includes a first sample feature and a first sample failure probability; Configure a fault prediction operator, wherein the fault prediction operator includes at least a BP neural network, a support vector machine, and a random decision forest; Divide the first sample data set into Q equal parts, select Q parts with replacement, generate a first sample set, iterate and select Q parts Q times, and obtain Q sample sets, where Q is the number of fault prediction operators; Taking the first feature of the sample as input and the first failure probability of the sample as supervision, Q sample sets are used to perform supervised training and cross-validation on the BP neural network, support vector machine and random decision forest respectively, and the first prediction model, the second prediction model and the third prediction model that meet the expected convergence constraints are obtained; A fault prediction layer is built based on the first prediction model, the second prediction model and the third prediction model, and the first fault prediction unit is constructed in combination with the mean calculation layer.

5. The chip testing optimization method based on multi-station parallelism according to claim 1 is characterized in that: Output the second predicted probability set, including: Acquire multiple first indicator features of the first test indicator, perform correlation analysis on the second test indicator and the multiple first indicator features respectively, select a first indicator feature whose correlation coefficient is greater than a predetermined coefficient threshold as the first test feature, and generate a first test feature set; Perform feature extraction on the first test result set according to the first test feature set to obtain a plurality of first test feature data; The plurality of first test feature data and the second feature set are input into a second fault prediction unit, and the second prediction probability set is output.

6. The chip test optimization method based on multi-station parallelism according to claim 5 is characterized in that: Outputting the second prediction probability set includes: Based on the first test result set, performing overall deviation analysis on the first test results of the plurality of target chips in sequence according to a deviation analysis strategy to determine a plurality of first deviation coefficients, wherein the deviation analysis strategy includes mean deviation, standard deviation, and maximum and minimum deviations; Mapping compensation is performed on the second prediction probability set based on the multiple first deviation coefficients, and the second prediction probability set is output, wherein the deviation coefficient is proportional to the probability increase amplitude.

7. The chip test optimization method based on multi-station parallelism according to claim 5 is characterized in that: Construct a second fault prediction unit, including: Retrieving and acquiring a second sample data set based on the attribute information of the target chip and the second expected index, wherein the second sample data includes sample first test feature data, sample second feature, and sample second failure probability; Taking the first test feature data of the sample and the second feature of the sample as input and the second fault probability of the sample as supervision, the BP neural network, support vector machine and random decision forest are supervised trained and cross-validated through the second sample data set to obtain the second fault prediction unit.

8. A chip testing device based on multi-station parallel operation, characterized in that: The steps for implementing the multi-station parallel chip test optimization method according to any one of claims 1 to 7 include: A chip test process reading module is used to read the chip test process and determine multiple test links and multiple expected indicators, wherein the test links have a sequence mark; A first fault prediction module, configured to select a first test link from the multiple test links, obtain a first test indicator of the first test link, determine a first correlation feature based on the first test indicator, perform feature extraction on a target chipset according to the first correlation feature to obtain a first feature set, input the first feature set into a first fault prediction unit, and output a first prediction probability set; A first priority sequence setting module, configured to set a first priority sequence according to the first prediction probability set, perform chip testing of a first test link of a target chipset according to the first priority sequence, and output a first test result set; A second fault prediction module, configured to determine a second correlation feature based on a second test indicator, extract features of a target chipset according to the second correlation feature to obtain a second feature set, input the first test result set and the second feature set into a second fault prediction unit, and output a second prediction probability set; A second priority sequence setting module, configured to set a second priority sequence according to the second prediction probability set, perform chip testing of a second test link of a target chipset according to the second priority sequence, and output a second test result set; The iterative testing module is used to perform iterative testing based on the second test result set until the chip testing process is completed and multiple test result sets are output.

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