Method and device for automatically testing I2c peripheral

Abstract

The invention relates to a method and a device for automatically testing I2c peripherals, by adopting the testing method, testing of functions and fault points of all the I2c peripherals can be completed in an extremely short time period, the time of a chip testing and verifying stage can be greatly saved, the chip research and development period can be shortened, pressure testing can be carried out in the mode, and the testing efficiency is improved. Therefore, the operation condition of the I2c peripheral module under the limit condition is measured, and the pressure resistance and robustness of the I2c peripheral module are tested. Besides, compared with a traditional test mode, the test method is simpler to use, chips of different models are also simple to transplant, the test time can be greatly shortened when the I2c peripheral test in the chip is carried out, and manpower and physical cost expenditure can be received.

Description

Technical Field

[0001] The invention belongs to the technical field of peripheral testing, and relates to a method and a device for automatically testing I2C peripherals. Background Art

[0002] With the increase in the number of on-board sensors and the improvement in the requirements for test accuracy, a more convenient, reliable and economical on-board data communication solution is needed. I2c (Inter-Integrated Circuit) is a serial communication bus protocol that is widely used in short-distance, low-speed data transmission occasions, such as communication between microcontrollers and sensors. The test of I2c peripherals is crucial to the reliability of its application in on-board data communication. At present, the traditional test methods for I2c peripherals are: one test method is to use I2c (sensor) peripherals as test input, but the sensor can only cover one scenario, while as a peripheral test, it is necessary to cover various I2c functions, modes and test various possible I2c faults; therefore, this test method cannot meet the actual test requirements and can only be used as a sampling test. Another test method is to build a test platform, constantly modify the test code and artificially create communication faults to verify the various functions, modes and faults of I2c. Although this test method can cover the functional modes and various faults of I2C, each verification requires rebuilding the test platform and manually reproducing the fault. This test method requires a lot of manpower and material resources and is time-consuming and labor-intensive. Summary of the invention

[0003] In view of the problems existing in the above-mentioned conventional technology, the present invention proposes a method for automatically testing an I2C peripheral and a device for automatically testing an I2C peripheral, which can efficiently and automatically implement the test of the I2C peripheral.

[0004] In order to achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: On the one hand, a method for automating the testing of I2C peripherals is provided, comprising the steps of: The host computer sends the test instructions of this test to the slave computer through the serial port; each test instruction is used to test a function point or fault point corresponding to the I2C peripheral to be tested; The MCU of the lower computer sets the level signals of the first GPIO pin and the second GPIO pin according to the test instruction and sends the test data to the I2C peripheral to be tested by the I2C protocol; the first GPIO pin is connected to the data line of the I2C peripheral to be tested, and the second GPIO pin is connected to the clock line of the I2C peripheral to be tested; After the I2C peripheral to be tested has read the test data, it re-establishes the communication connection with the lower computer and sends the read test data to the lower computer; The lower computer reads the test data sent by the I2C peripheral to be tested from the first GPIO pin and compares the test data sent by the lower computer for consistency, and determines whether the address of the I2C peripheral to be tested is consistent before receiving the data and when sending the data; When the result of the consistency comparison is consistent and the address is consistent, the lower computer determines that the I2C peripheral to be tested has passed the test in this test, and uploads the test pass as the test result of this test to the upper computer.

[0005] On the other hand, a device for automatically testing an I2C peripheral is also provided, comprising an upper computer, a lower computer and an I2C peripheral to be tested, wherein the upper computer is connected to the lower computer via a serial port, a first GPIO pin of an MCU in the lower computer is connected to a data line of the I2C peripheral to be tested and a second GPIO pin is connected to a clock line of the I2C peripheral to be tested; The host computer sends the test instructions of this test to the slave computer through the serial port; each test instruction is used to test a function point or fault point corresponding to the I2C peripheral to be tested; The MCU of the lower computer sets the level signals of the first GPIO pin and the second GPIO pin according to the test instruction and sends the test data to the I2C peripheral device to be tested by I2C protocol; After the I2C peripheral to be tested has read the test data, it re-establishes the communication connection with the lower computer and sends the read test data to the lower computer; The lower computer reads the test data sent by the I2C peripheral to be tested from the first GPIO pin and compares the test data sent by the lower computer for consistency, and determines whether the address of the I2C peripheral to be tested is consistent before receiving the data and when sending the data; When the result of the consistency comparison is consistent and the address is consistent, the lower computer determines that the I2C peripheral to be tested has passed the test in this test, and uploads the test pass as the test result of this test to the upper computer.

[0006] One of the above technical solutions has the following advantages and beneficial effects: The above-mentioned method and device for automatic testing of I2C peripherals are based on a test platform composed of a host computer, a slave computer and an I2C peripheral to be tested. The MCU chip of the slave computer simulates the level signal changes of the data line and the clock line in the I2C protocol by controlling its GPIO interface, thereby communicating with the I2C peripheral to be tested to complete the automatic testing of the I2C peripherals. It only needs to send each test instruction to the slave computer through a unified host computer, and the functions and fault points of all I2C peripherals can be tested in a very short time period, which can greatly save the time of the chip test verification stage and shorten the chip development cycle. Stress testing can also be performed in this way to measure the operation of the I2C peripheral module under extreme conditions and test its pressure resistance and robustness. In addition, compared with the traditional test method, it is simpler to use, and it is also simple to transplant between chips of different models. When testing the I2C peripherals in the chip, the test time, receiving manpower and physical cost expenses can be greatly shortened. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0008] Figure 1 A schematic diagram of a flow chart of a method for automatically testing I2C peripherals in one embodiment; Figure 2 A block diagram of an overall automated testing platform in one embodiment; Figure 3 A flowchart of the instruction and result transmission of a function point test in one embodiment; Figure 4 A schematic diagram of a test receiving process in an embodiment; Figure 5 A schematic diagram of a test sending process in an embodiment; Figure 6 FIG. 1 is a schematic diagram of a module structure of an apparatus for automatically testing I2C peripherals in an embodiment. DETAILED DESCRIPTION

[0009] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and Examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0010] It should be noted that the reference to "embodiment" in this article means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The presentation of this phrase at various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It will be appreciated by those skilled in the art that the embodiments described herein may be combined with other embodiments. The term "and / or" used in the specification of the present invention and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0011] The following will describe the implementation of the present invention in detail with reference to the accompanying drawings in the embodiment diagram of the present invention.

[0012] In one embodiment, Figure 1 As shown, a method for automatically testing an I2C peripheral is provided, which may include the following processing steps S10 to S18: S10, sending the test instructions of this test to the slave computer through the serial port of the upper computer; each test instruction is used to test a function point or fault point corresponding to the I2C peripheral to be tested; S12, setting the level signals of the first GPIO pin and the second GPIO pin according to the test instruction by the MCU of the lower computer to send test data to the I2C peripheral to be tested in accordance with the I2C protocol; the first GPIO pin is connected to the data line of the I2C peripheral to be tested, and the second GPIO pin is connected to the clock line of the I2C peripheral to be tested; S14, after the I2C peripheral to be tested reads the test data sent by the lower computer, it re-establishes the communication connection with the lower computer and sends the read test data to the lower computer; S16, the lower computer reads the test data sent by the I2C peripheral to be tested from the first GPIO pin and compares the test data sent by the lower computer for consistency, and determines whether the address of the I2C peripheral to be tested is consistent before receiving the data and when sending the data; S18, when the result of the consistency comparison is consistent and the address is consistent, the lower computer determines that the I2C peripheral to be tested has passed the test in this test, and uploads the test pass as the test result of this test to the upper computer.

[0013] It can be understood that the I2C protocol is a synchronous, half-duplex, serial low-speed protocol. The I2C protocol only needs two signal lines to link multiple slave devices to one or more host devices; the two signal lines are SDA (data line, used to transmit data) and SCL (clock line, providing a synchronous clock signal). The MCU chip simulates the level signal changes of the data line and clock line in the I2C protocol by controlling the GPIO interface, thereby communicating with the I2C peripheral to be tested to complete the automated test of the I2C peripheral. The overall automated test platform block diagram is shown below. Figure 2 As shown, it mainly includes a host computer, a slave computer and the I2C peripheral to be tested.

[0014] When the lower computer receives the instruction from the upper computer, the MCU chip of the lower computer will control its own GPIO interface to simulate the corresponding I2C signal; the corresponding I2C peripheral reads the test data sent in the I2C signal; and then uploads the acquired test data to the lower computer after the test data is received to confirm the accuracy of the test data.

[0015] Specifically, the host computer can set various test instructions, each of which corresponds to a test point (i.e., function or fault point) of I2C. When the host computer sends information to the slave computer through the serial port, the MCU chip of the slave computer will read the level signal on its own GPIO interface, or control its own GPIO interface to simulate the I2C signal to send the corresponding test data to the I2C peripheral to be tested. When the test of this function point executed by the slave computer is completed, the corresponding test results will be uploaded to the host computer. The specific flow chart can be as follows: Figure 3 shown.

[0016] The above-mentioned method for automatic testing of I2c peripherals is based on a test platform composed of a host computer, a slave computer and an I2c peripheral to be tested. The MCU chip of the slave computer simulates the level signal changes of the data line and the clock line in the I2c protocol by controlling its GPIO interface, thereby communicating with the I2c peripheral to be tested to complete the automatic testing of the I2c peripherals. It only needs to send each test instruction to the slave computer through a unified host computer, and the functions and fault points of all I2c peripherals can be tested in a very short time period, which can greatly save the time of the chip test verification stage and shorten the chip development cycle. Stress testing can also be performed in this way to measure the operation of the I2c peripheral module under extreme conditions and test its pressure resistance and robustness. In addition, compared with the traditional test method, it is simpler to use, and it is also simple to transplant between chips of different models. When testing the I2c peripherals in the chip, the test time, receiving manpower and physical cost expenses can be greatly shortened.

[0017] In one embodiment, this test is to test the host communication of I2C in the seven-bit addressing mode of the I2C peripheral to be tested. The I2C peripheral to be tested first sends an address and a request for reading information to the subordinate computer; The lower computer reads the level signals of the first GPIO pin and the second GPIO pin to determine that the I2C peripheral to be tested correctly sends a start signal; the first GPIO pin and the second GPIO pin are configured as clock line falling edge interrupts; When the clock line has a rising edge, the lower computer reads the level in the data line and records the read level inside the MCU of the lower computer, obtains the eight-bit data sent by the I2C peripheral to be tested and determines whether the eighth bit of data is 0; If the eighth bit of data is 0, the lower computer pulls up the level signal of the data line through the first GPIO pin; The MCU of the lower computer randomly selects test data and uses the first GPIO pin to simulate the I2C protocol and send it to the I2C peripheral to be tested.

[0018] Specifically, the working principle of the lower computer is as follows: when the serial port of the lower computer receives the test command from the upper computer, it will automatically parse the test command and control its own GPIO interface to respond. For example, when the seven-bit addressing mode of the I2C peripheral and the I2C host communication need to be tested, the two GPIO pins (such as GPIO1 and GPIO2) of the MCU chip of the lower computer are connected to the two pins (i.e., the data line and the clock line) of the I2C peripheral; the lower computer prepares a total of 256 data from 0 to 0xFF as test data.

[0019] At the beginning of the test, the I2C peripheral will first send an address and a request to read information; the lower computer will first read the level signals on the GPIO1 interface and the GPIO2 interface. When the start signal in the I2C protocol is met (that is, when the data line is at a high level, the clock line has a falling edge) (in order to be able to read the instantaneous falling edge of the clock line, the GPIO is set to a falling edge interrupt when the operation starts, and the interrupt function is entered when the GPIO has a falling edge), it is determined whether the data line is still at a high level at this time. If so, the I2C peripheral correctly sends a start signal at this time.

[0020] After the start signal occurs, the lower computer continues to read the level signal of the clock line and continues to read the level signal in the I2C bus. When the clock line has a rising edge, the lower computer reads the level in the data line and records the current level inside the MCU chip of the lower computer (high level is 1, low level is 0). At this time, the first bit of the address sent by the I2C peripheral is obtained. In this way, a total of eight bits of data are read back and forth and it is determined whether the eighth bit of data is 0. If the eighth bit of data is 0, it means that the read command sent by the I2C peripheral is received normally, and then the lower computer pulls up the level signal of the data line through GPIO to indicate that the communication is established normally.

[0021] At this time, the MCU chip of the lower computer randomly selects one data from 256 data according to the time change and uses the GPIO interface to simulate the I2c protocol to send it to the I2c peripheral; that is, when the clock line changes with a rising edge, the data bit is pulled low or high according to the 8-bit data. When the 8-bit data is sent, it is necessary to determine whether the data line is pulled low within a period of time after the rising edge of the clock line. If so, it means that the I2c peripheral is receiving normally, otherwise it means that a Stop signal is generated and the reception stops. When the I2c peripheral has read all the data, the peripheral I2c will re-establish the communication connection with the lower computer to send the data just received to the lower computer; at this time, the lower computer will compare whether the data read from the GPIO interface is consistent with the data sent by itself, and compare whether the addresses read from the GPIO interface in the two communications are consistent. If they are consistent, it means that this communication has passed and the test result is uploaded to the upper computer through the serial port, otherwise the test result that this communication has failed will be reported to the upper computer through the serial port. Figure 4 The test receiving flow chart is shown as follows: Figure 5 Shown is the test sending flow chart.

[0022] In a fault embodiment, when the function point is the deadlock release function, after the lower computer establishes communication with the I2C peripheral to be tested, the level signal of the data line is pulled down through the first GPIO pin to create a deadlock for the I2C peripheral to be tested.

[0023] It can be understood that using the GPIO interface to simulate I2c is more friendly for testing the fault points of I2c peripherals. For example, when testing the I2c deadlock release function, it is necessary to create a deadlock in advance; usually it is necessary to constantly reset the deadlock phenomenon, which is more troublesome; but using the GPIO interface simulation, as long as the GPIO interface directly pulls down the pin level corresponding to the data line after the communication connection is established, the deadlock phenomenon can be created to test the I2c peripheral deadlock release function.

[0024] In one embodiment, the MCU of the lower computer outputs an erroneous level signal to the data line through the first GPIO pin to test the fault feedback mechanism of the I2C peripheral to be tested.

[0025] Specifically, the working principle of the chip where the I2c peripheral to be tested is located: the I2c peripheral has high reusability, and only one code is needed for the function point to be tested; a normal I2c module is prepared in the chip where the I2c peripheral is located to receive and send code with the slave after being the host. Then obtain the correct and faulty code in the code, and run the next function point when the previous function point runs correctly; when testing the fault feedback mechanism, it is only necessary for the I2c peripheral to work normally, and the MCU chip of the lower computer to create an erroneous level signal.

[0026] In one embodiment, the level signals on the data line and the clock line are read by a logic analyzer and then waveform analysis is performed; the I2C protocol waveform obtained after the waveform analysis is used to monitor the test errors of the I2C peripheral to be tested.

[0027] It can be understood that in order to enhance the reliability of the system, the overall automated testing platform may also include a logic analyzer (such as an oscilloscope or other types of digital signal waveform analyzers) to read the level signals on the data lines and clock lines to more accurately verify the integrity of the test, thereby increasing the reliability of the system.

[0028] Specifically, the test pins (i.e., data lines and clock lines) can be connected to the oscilloscope in the peripheral circuit of the overall automated test platform, such as Figure 2 As shown, each time a functional point is tested, the waveform analyzed in the oscilloscope can be observed. When a test error occurs, the waveform of the fault at the test site can be retained, allowing testers to quickly locate the problem, thereby improving test efficiency.

[0029] It should be understood that although Figure 1 The steps in the method are shown in sequence as indicated by the arrows, but the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of the steps, and the steps can be executed in other orders. Figure 1 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequentially, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0030] In one embodiment, Figure 6 As shown, a device 100 for automatically testing an I2C peripheral is provided, which may include a host computer, a slave computer, and an I2C peripheral to be tested. The host computer is connected to the slave computer via a serial port, and the first GPIO pin of the MCU in the slave computer is connected to the data line of the I2C peripheral to be tested and the second GPIO pin is connected to the clock line of the I2C peripheral to be tested. The host computer sends a test instruction of this test to the slave computer from the serial port; each test instruction is used to test a function point or fault point corresponding to the I2C peripheral to be tested.

[0031] The MCU of the lower computer sets the level signals of the first GPIO pin and the second GPIO pin according to the test instruction, and sends the test data to the I2c peripheral to be tested by the I2c protocol. After reading the test data, the I2c peripheral to be tested re-establishes the communication connection with the lower computer, and sends the read test data to the lower computer. After the lower computer reads the test data sent by the I2c peripheral to be tested from the first GPIO pin, it compares the consistency with the test data sent by the lower computer, and determines whether the address of the I2c peripheral to be tested is consistent before receiving the data and when sending the data. When the result of the consistency comparison is consistent and the address is consistent, the lower computer determines that the I2c peripheral to be tested has passed the test in this test, and uploads the test pass as the test result of this test to the upper computer.

[0032] The above-mentioned device 100 for automatically testing I2c peripherals is based on a test platform composed of a host computer, a slave computer and an I2c peripheral to be tested. The MCU chip of the slave computer simulates the level signal changes of the data line and the clock line in the I2c protocol by controlling its GPIO interface, thereby communicating with the I2c peripheral to be tested to complete the automated test of the I2c peripheral. It only needs to send each test instruction to the slave computer through a unified host computer, and the functions and fault points of all I2c peripherals can be tested in a very short time period, which can greatly save the time of the chip test verification stage and shorten the chip development cycle. Stress testing can also be performed in this way to measure the operation of the I2c peripheral module under extreme conditions and test its pressure resistance and robustness. In addition, compared with the traditional test method, it is simpler to use, and it is also simple to transplant between chips of different models. When testing the I2c peripherals in the chip, the test time, receiving manpower and physical cost expenses can be greatly shortened.

[0033] In one embodiment, this test is to test the host communication of I2c in the seven-bit addressing mode of the I2c peripheral to be tested. The I2c peripheral to be tested first sends an address and a request for reading information to the lower computer. The lower computer reads the level signal of the first GPIO pin and the second GPIO pin to determine that the I2c peripheral to be tested correctly sends a start signal; the first GPIO pin and the second GPIO pin are configured as clock line falling edge interrupts. When the clock line has a rising edge, the lower computer reads the level in the data line and records the read level inside the MCU of the lower computer, obtains the eight-bit data sent by the I2c peripheral to be tested, and determines whether the eighth bit of data is 0. If the eighth bit of data is 0, the lower computer pulls up the level signal of the data line through the first GPIO pin. The test data is randomly selected by the MCU of the lower computer and sent to the I2c peripheral to be tested using the first GPIO pin to simulate the I2c protocol.

[0034] In one embodiment, when the function point is the deadlock release function, after the lower computer establishes communication with the I2C peripheral to be tested, the level signal of the data line is pulled down through the first GPIO pin to create a deadlock for the I2C peripheral to be tested.

[0035] In one embodiment, the MCU of the lower computer outputs an erroneous level signal to the data line through the first GPIO pin to test the fault feedback mechanism of the I2C peripheral to be tested.

[0036] In one embodiment, the above-mentioned device 100 for automatically testing I2C peripherals may also include a logic analyzer, which is used to read the level signals on the data line and the clock line and then perform waveform analysis; the I2C protocol waveform obtained after the waveform analysis is used to monitor the test errors of the I2C peripheral to be tested.

[0037] It can be understood that, for specific definitions of the apparatus 100 for automatically testing an I2C peripheral, reference can be made to the corresponding definitions of the method for automatically testing an I2C peripheral in the above text, which will not be repeated here.

[0038] Each module in the above-mentioned device 100 for automatically testing I2C peripherals can be implemented in whole or in part by software, hardware, or a combination thereof. Each of the above-mentioned modules can be embedded in or independent of a device having a data processing function in the form of hardware, or can be stored in the memory of the above-mentioned device in the form of software, so that the processor can call and execute the operations corresponding to each of the above modules. The above-mentioned device can be, but is not limited to, various types of computing terminals available in the art.

[0039] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided by the present invention can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus dynamic random access memory (RambusDRAM, referred to as RDRAM) and interface dynamic random access memory (DRDRAM).

[0040] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0041] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of protection of the invention. It should be pointed out that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the attached claims.

Claims

1. A method for automatically testing I2C peripherals, characterized in that: Includes steps: The upper computer sends the test instructions of this test to the lower computer through the serial port; each of the test instructions is used to test a function point or fault point corresponding to the I2C peripheral to be tested; The MCU of the lower computer sets the level signals of the first GPIO pin and the second GPIO pin according to the test instruction and sends the test data to the I2C peripheral to be tested in accordance with the I2C protocol; the first GPIO pin is connected to the data line of the I2C peripheral to be tested, and the second GPIO pin is connected to the clock line of the I2C peripheral to be tested; After the I2C peripheral device to be tested reads the test data, it re-establishes the communication connection with the lower computer and sends the read test data to the lower computer; The lower computer reads the test data sent by the I2C peripheral to be tested from the first GPIO pin, and then performs consistency comparison with the test data sent by the lower computer, and determines whether the address of the I2C peripheral to be tested is consistent before receiving the data and when sending the data; When the result of the consistency comparison is consistent and the address is consistent, the lower computer determines that the I2C peripheral to be tested has passed the test in this test, and uploads the test pass as the test result of this test to the upper computer.

2. The method for automated testing of I2C peripherals according to claim 1, characterized in that: This test is to test the host communication of the seven-bit addressing mode I2c of the I2c peripheral to be tested. The I2c peripheral to be tested first sends an address and a request for reading information to the slave computer; The lower computer reads the level signals of the first GPIO pin and the second GPIO pin to determine that the I2C peripheral to be tested correctly sends a start signal; the first GPIO pin and the second GPIO pin are configured as clock line falling edge interrupts; When a rising edge occurs on the clock line, the lower computer reads the level in the data line and records the read level inside the MCU of the lower computer, obtains the eight-bit data sent by the I2C peripheral to be tested, and determines whether the eighth bit of data is 0; If the eighth bit of data is 0, the lower computer pulls up the level signal of the data line through the first GPIO pin; The MCU of the lower computer randomly selects test data and uses the first GPIO pin to simulate the I2C protocol and send it to the I2C peripheral device to be tested.

3. The method for automated testing of I2C peripherals according to claim 1 or 2, characterized in that: When the function point is a deadlock release function, after the lower computer establishes communication with the I2C peripheral to be tested, the level signal of the data line is pulled down through the first GPIO pin to create a deadlock for the I2C peripheral to be tested.

4. The method for automated testing of I2C peripherals according to claim 1 or 2, characterized in that: The MCU of the lower computer outputs an erroneous level signal to the data line through the first GPIO pin to test the fault feedback mechanism of the I2C peripheral to be tested.

5. The method for automated testing of I2C peripherals according to claim 1, characterized in that: Reading the level signals on the data line and the clock line through a logic analyzer and performing waveform analysis; The I2C protocol waveform obtained after waveform analysis is used to monitor the test errors of the I2C peripheral device to be tested.

6. A device for automatically testing I2C peripherals, characterized in that: The method comprises an upper computer, a lower computer and an I2C peripheral to be tested, wherein the upper computer is connected to the lower computer via a serial port, a first GPIO pin of an MCU in the lower computer is connected to a data line of the I2C peripheral to be tested and a second GPIO pin is connected to a clock line of the I2C peripheral to be tested; The host computer sends the test instructions of this test to the slave computer from the serial port; each of the test instructions is used to test a function point or fault point corresponding to the I2C peripheral to be tested; The MCU of the lower computer sets the level signals of the first GPIO pin and the second GPIO pin according to the test instruction and sends the test data to the I2C peripheral device to be tested using the I2C protocol; After the I2C peripheral device to be tested reads the test data, it re-establishes the communication connection with the lower computer and sends the read test data to the lower computer; The lower computer reads the test data sent by the I2C peripheral to be tested from the first GPIO pin, and then performs consistency comparison with the test data sent by the lower computer, and determines whether the address of the I2C peripheral to be tested is consistent before receiving the data and when sending the data; When the result of the consistency comparison is consistent and the address is consistent, the lower computer determines that the I2C peripheral to be tested has passed the test in this test, and uploads the test pass as the test result of this test to the upper computer.

7. The device for automated testing of I2C peripherals according to claim 6, characterized in that: This test is to test the host communication of the seven-bit addressing mode I2c of the I2c peripheral to be tested. The I2c peripheral to be tested first sends an address and a request for reading information to the slave computer; The lower computer reads the level signals of the first GPIO pin and the second GPIO pin to determine that the I2C peripheral to be tested correctly sends a start signal; the first GPIO pin and the second GPIO pin are configured as clock line falling edge interrupts; When a rising edge occurs on the clock line, the lower computer reads the level in the data line and records the read level inside the MCU of the lower computer, obtains the eight-bit data sent by the I2C peripheral to be tested, and determines whether the eighth bit of data is 0; If the eighth bit of data is 0, the lower computer pulls up the level signal of the data line through the first GPIO pin; The MCU of the lower computer randomly selects test data and uses the first GPIO pin to simulate the I2C protocol and send it to the I2C peripheral device to be tested.

8. The device for automatically testing I2C peripherals according to claim 6 or 7, characterized in that: When the function point is a deadlock release function, after the lower computer establishes communication with the I2C peripheral to be tested, the level signal of the data line is pulled down through the first GPIO pin to create a deadlock for the I2C peripheral to be tested.

9. The device for automated testing of I2C peripherals according to claim 6 or 7, characterized in that: The MCU of the lower computer outputs an erroneous level signal to the data line through the first GPIO pin to test the fault feedback mechanism of the I2C peripheral to be tested.

10. The device for automated testing of I2C peripherals according to claim 6, characterized in that: It also includes a logic analyzer, which is used to read the level signals on the data line and the clock line and then perform waveform analysis; the I2C protocol waveform obtained after the waveform analysis is used to monitor the test errors of the I2C peripheral to be tested.

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