Test program generation method and device, computer equipment and readable storage medium

Abstract

The invention provides a test program generation method and device, computer equipment and a readable storage medium, and belongs to the technical field of software development. The test program generation method comprises the steps of obtaining a test requirement document of a target chip; analyzing the test demand document to obtain keyword information corresponding to the test demand document; based on a preset test development model and the keyword information, obtaining test demand development model information; according to the test requirement, developing model information, calling at least one artificial intelligence interface in a preset large language model, and generating a plurality of test codes; and according to the plurality of test codes, generating a target test program corresponding to the target chip. According to the method, the effects of shortening the development period of the test program and improving the development efficiency of the test program can be achieved.

Description

Technical Field

[0001] The present application relates to the technical field of software development, and in particular to a test program generation method, apparatus, computer equipment and readable storage medium. Background Art

[0002] In the field of test program development, the traditional test program development method mainly relies on programmers to manually write codes, which is inefficient and error-prone. Therefore, an efficient program development method is urgently needed.

[0003] In the related art, general chip test programs mainly rely on manual development by test engineers. Test engineers need to understand the chip test specification manual, and then manually write the test program according to the requirements of the chip test specification manual to complete the development of the chip test program.

[0004] However, when developing chip test programs based on related technologies, there are problems such as long test program development cycle and low test program development efficiency. Summary of the invention

[0005] The purpose of the present application is to provide a test program generation method, apparatus, computer device and readable storage medium, which can shorten the development cycle of the test program and improve the development efficiency of the test program.

[0006] The embodiment of the present application is implemented as follows:

[0007] In a first aspect of an embodiment of the present application, a test program generation method is provided, the method comprising:

[0008] Obtain the test requirement document of the target chip;

[0009] Parse the test requirement document to obtain the keyword information corresponding to the test requirement document;

[0010] Based on the preset test development model and keyword information, the test requirement development model information is obtained;

[0011] Develop model information according to test requirements, call at least one artificial intelligence interface in the preset large language model, and generate multiple test codes;

[0012] A target test program corresponding to the target chip is generated according to the multiple test codes.

[0013] As a possible implementation method, obtain the test requirement document of the target chip, including:

[0014] In response to a trigger action of a user on a graphical user interface, a test requirement document of a target chip to be tested is imported and obtained, wherein the test requirement document includes: a function to be tested of the target chip and a test condition of the target chip.

[0015] As a possible implementation method, the test requirement document is parsed to obtain keyword information corresponding to the test requirement document, including:

[0016] According to the document rules corresponding to the test requirement document, the test requirement document is parsed, and keyword information corresponding to the test requirement document is extracted.

[0017] As a possible implementation method, based on the preset test development model and keyword information, the test requirement development model information is obtained, including:

[0018] Fill in the keyword information corresponding to the test requirement document into the preset test development model to obtain the test requirement development model information corresponding to the test requirement document. The test requirement development model information includes: the model of the target chip, the test items of the target chip, the test machine type of the target chip, the normal power voltage of the target chip, the package type of the target chip, the clock frequency of the target chip, the clock waveform of the target chip, the test vector of the target chip and the circuit characteristics of the target chip.

[0019] As a possible implementation method, model information is developed according to test requirements, at least one artificial intelligence interface in a preset large language model is called, and multiple test codes are generated, including:

[0020] According to the model of the target chip, the test machine type of the target chip, the normal power voltage of the target chip, the package type of the target chip, and the circuit characteristics of the target chip in the test requirement development model information, the first type of artificial intelligence interface of the large language model is called, and the first interface feedback information of the large language model is obtained;

[0021] Generate a first test code according to the information returned by the first interface, wherein the first test code includes: test configuration items, and the test configuration items include: basic configuration items, pin resource configuration items, pin configuration items, and binning result configuration items;

[0022] Develop test items of the target chip in the model information according to the test requirements, call the second type of artificial intelligence interface in the preset large language model, and obtain the second interface feedback information of the large language model;

[0023] Generate a second test code according to the information returned by the second interface, the second test code including: a plurality of functional test code segments, each functional test code segment is used to test one or more chip functions;

[0024] According to the test requirement development model information, the clock frequency of the target chip and the clock waveform of the target chip are called, the third type of artificial intelligence interface in the preset large language model is called, and the third interface feedback information of the large language model is obtained;

[0025] Generate a third test code according to the information returned by the third interface, where the third test code is used to test the clock frequency and waveform of the target chip;

[0026] Develop a test vector of the target chip in the model information according to the test requirements, call the fourth type of artificial intelligence interface in the preset large language model, and obtain the fourth interface feedback information of the large language model;

[0027] A fourth test code is generated according to the information returned by the fourth interface, and the fourth test code is used to run the test vector corresponding to the target chip.

[0028] As a possible implementation manner, generating a first test code according to information returned by the first interface includes:

[0029] Fill the first node information in the first interface return information into the first target node;

[0030] Fill the second node information in the first interface return information into the second target node;

[0031] Fill the third node information in the first interface return information into the third target node;

[0032] Fill the fourth node information in the first interface return information into the fourth target node;

[0033] The first target node, the second target node, the third target node, and the fourth target node are combined into a first test code.

[0034] As a possible implementation method, a target test program corresponding to a target chip is generated according to multiple test codes, including:

[0035] According to the test rules of the target chip, the first test code, the second test code, the third test code and the fourth test code are spliced ​​to obtain a target test program corresponding to the target chip.

[0036] According to a second aspect of an embodiment of the present application, a test program generating device is provided, the test program generating device comprising:

[0037] An acquisition module is used to obtain the test requirement document of the target chip;

[0038] A parsing module is used to parse the test requirement document to obtain keyword information corresponding to the test requirement document;

[0039] A development module is used to obtain test requirement development model information based on a preset test development model and keyword information;

[0040] The first generation module is used to develop model information according to test requirements, call at least one artificial intelligence interface in a preset large language model, and generate multiple test codes;

[0041] The second generating module is used to generate a target test program corresponding to the target chip according to the multiple test codes.

[0042] According to a third aspect of an embodiment of the present application, a computer device is provided, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the computer program is executed by the processor, the test program generation method described in the first aspect is implemented.

[0043] According to a fourth aspect of an embodiment of the present application, a computer-readable storage medium is provided, which stores a computer program. When the computer program is executed by a processor, the test program generation described in the first aspect is implemented.

[0044] The beneficial effects of the embodiments of the present application include:

[0045] A test program generation method provided by an embodiment of the present application imports the test requirement document of the target chip edited by the user to obtain the test requirement document of the target chip; parses the test requirement document of the target chip and extracts keyword information from the parsing result of the test requirement document; fills the keyword information corresponding to the test requirement document into a pre-set test development model to obtain the test requirement development model information corresponding to the test requirement document; calls at least one artificial intelligence interface of a preset large language model according to the test requirement development model information, and the preset large language model generates a plurality of corresponding test codes based on the test requirement development model information received by each artificial intelligence interface; splices and organizes each test code according to the test rules of the target chip to obtain the test program of the target chip. In this way, there is no need for a test engineer to study the test specification manual of the target chip, nor is there a need for a test engineer to manually code, which can shorten the development cycle of the test program and improve the development efficiency of the test program. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0047] Figure 1 A flowchart of a first test program generation method provided in an embodiment of the present application;

[0048] Figure 2 A system block diagram of an analytical model provided in an embodiment of the present application;

[0049] Figure 3 A schematic diagram of an interface of a demand development model provided in an embodiment of the present application;

[0050] Figure 4 A flowchart of a second test program generation method provided in an embodiment of the present application;

[0051] Figure 5 A flowchart of a third test program generation method provided in an embodiment of the present application;

[0052] Figure 6 A complete flow chart of the test program generation method provided in the embodiment of the present application;

[0053] Figure 7 A schematic diagram of the structure of a test program generating device provided in an embodiment of the present application;

[0054] Figure 8 A schematic diagram of the structure of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0056] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0057] At present, chip test programs mainly rely on manual development by test engineers. Test engineers need to study the chip test specifications and manually write test programs according to the requirements of the chip test specifications to complete the development of chip test programs. However, this solution requires test engineers to devote a lot of energy to studying the chip test specifications and also requires test engineers to invest a lot of manual coding, which results in a long chip test program development cycle and low chip test program development efficiency.

[0058] To this end, the embodiment of the present application provides a test program generation method, the user edits the test requirement document of the target chip to be tested, and imports the test requirement document of the target chip into the test program generation system through a graphical user interface; the parsing program in the test program generation system parses the test requirement document of the target chip, and extracts keyword information from the parsing result of the test requirement document; the keyword information corresponding to the test requirement document is filled into the test requirement development model to obtain the test requirement development model information corresponding to the test requirement document; at least one artificial intelligence interface of the preset large language model is called based on the test requirement development model information; the preset large language model generates multiple corresponding test codes based on the test requirement development model information received by each artificial intelligence interface; each test code is spliced ​​according to the test rules of the target chip to be tested to obtain the test program of the target chip. In this way, there is no need for the test engineer to study the test specification manual of the target chip, and there is no need for the test engineer to manually code, which can greatly shorten the development cycle of the test program to improve the development efficiency of the test program.

[0059] The test program generation method provided in the embodiment of the present application is explained in detail below with reference to the accompanying drawings.

[0060] Figure 1 This is a flowchart of a test program generation method provided by the present application, which can be applied to computer equipment, see Figure 1 , the embodiment of the present application provides a test program generation method, comprising:

[0061] S101. Obtain a test requirement document for a target chip.

[0062] Optionally, the target chip is used to indicate the chip that the user wants to test. The test requirement document of the target chip is a document edited by the tester based on the test requirements. The test requirement document is used to indicate the test case description of the target chip. Based on the test requirement document of the target chip, the functions of the target chip that the tester wants to test and the basic testing information of the target chip can be determined.

[0063] S102: Parse the test requirement document to obtain keyword information corresponding to the test requirement document.

[0064] Optionally, the test requirement document of the target chip is parsed, and keyword information contained in the test requirement document is extracted from the parsed results of the test requirement document, where the keyword information refers to keywords in the test requirement document that are related to the target chip test, and the keyword information includes; the name of the target chip, the model of the target chip, the type of test machine for testing the target chip, the pin resources of the target chip, the communication protocol of the target chip, the packaging type of the target chip, the clock frequency of the target chip, the clock waveform of the target chip, the test conditions of the target chip, etc., which are not specifically limited in this application.

[0065] S103: Based on the preset test development model and keyword information, obtain test requirement development model information.

[0066] Optionally, the preset test development model is a test development model constructed in advance by testers based on multiple iterative training of test programs for a large number of test chips. By filling the keyword information corresponding to the test requirement document of the target chip into the preset test development model, the test requirement development model information of the target chip can be obtained. The test requirement development model information is used to indicate the basic information required for the test program development of the target chip. The preset test development model can be regarded as providing a test program development template for test program development, and the keywords corresponding to the test requirement document are filled into the corresponding positions in the preset test development model.

[0067] S104: Develop model information according to test requirements, call at least one artificial intelligence interface in a preset large language model, and generate multiple test codes.

[0068] Optionally, the preset large language model is implemented by a Chat GPT model, and the preset large language model includes multiple AI interfaces, i.e., multiple artificial intelligence interfaces. At least one AI interface in the Chat GPT model is called according to the type of each keyword information in the test requirement development model information, and each AI interface in the Chat GPT model is used to receive the test requirement development model information of the target chip. After receiving the test requirement development model information, the Chat GPT model generates multiple test codes, and the test codes are used to indicate the program code corresponding to the function to be tested of the target chip.

[0069] It is worth noting that the multiple test codes generated by the preset large language model are unrelated. The preset large language model only develops model information based on the test requirements received by each AI interface and outputs the corresponding program code from each AI interface.

[0070] S105. Generate a target test program corresponding to the target chip according to the multiple test codes.

[0071] Optionally, there are many kinds of test rules for IC chips, and by combining multiple test codes according to the test rules of the target chip, a target test program suitable for the target chip can be obtained.

[0072] Optionally, the target test program is used to indicate a program that meets the test requirements specified by the test user, and the target test program can be applicable to the target chip specified by the tester.

[0073] In an embodiment of the present application, the test requirement document of the target chip edited by the user is imported to obtain the test requirement document of the target chip; the test requirement document of the target chip is parsed, and keyword information is extracted from the parsed result of the test requirement document; the keyword information corresponding to the test requirement document is filled into the pre-set test development model to obtain the test requirement development model information corresponding to the test requirement document; at least one artificial intelligence interface of the preset large language model is called according to the test requirement development model information, and the preset large language model generates a plurality of corresponding test codes based on the test requirement development model information received by each artificial intelligence interface; each test code is spliced ​​and sorted according to the test rules of the target chip to obtain the test program of the target chip. In this way, there is no need for the test engineer to study the test specification manual of the target chip, and there is no need for the test engineer to manually code, which can shorten the development cycle of the test program and improve the development efficiency of the test program.

[0074] In an optional implementation manner, the specific operation of the above step S101 may be:

[0075] In response to a trigger action of a user on a graphical user interface, a test requirement document of a target chip to be tested is imported and obtained, wherein the test requirement document includes: a function to be tested of the target chip and a test condition of the target chip.

[0076] Optionally, the target chip to be tested is used to indicate an IC chip that the user wants to test but has not been tested yet. The test requirement document includes: the function to be tested of the target chip and the test conditions of the target chip. The function to be tested is used to indicate that the user wants to test the performance of the target chip. The function to be tested may be the circuit characteristics, pin resources, etc. of the target chip; the test conditions of the target chip correspond one-to-one to the function to be tested, and the test conditions are used as prerequisites for the test of the function to be tested, such as the pin voltage of the target chip under a high level, the pin voltage of the target chip under a low level, etc. This application does not make specific limitations on this.

[0077] Optionally, the graphical user interface is a development user interface based on winform development. The user clicks a "spec selection" button on the graphical user interface, and the computer device starts to import the test requirement document of the target chip.

[0078] In an optional implementation manner, the specific operation of the above step S102 may be:

[0079] According to the document rules corresponding to the test requirement document, the test requirement document is parsed, and keyword information corresponding to the test requirement document is extracted.

[0080] Optionally, the document rules corresponding to the test requirement document are used to indicate the document editing format of the test requirement document. The document rules of the test requirement document can be PDF format, word document, picture, etc. This application does not make specific limitations on this.

[0081] Optionally, different parsing models are called according to the document rules corresponding to the test requirement document, and the document rules corresponding to the test requirement document select an adapted parsing model to parse the test requirement document and extract keyword information from the test document.

[0082] Figure 2 A system block diagram of an analytical model provided in this application, see Figure 2 ,The parsing model can parse the test requirement document of the target chip from multiple angles, Figure 2 As an example, the analysis is mainly performed from five perspectives, namely, test items, pins, package types, communication protocols, and clock waveforms. That is, the analysis model divides the test requirement document of the target chip into five parts.

[0083] In an optional implementation manner, the specific operation of the above step S103 may be:

[0084] Fill in the keyword information corresponding to the test requirement document into the preset test development model to obtain the test requirement development model information corresponding to the test requirement document. The test requirement development model information includes: the model of the target chip, the test items of the target chip, the test machine type of the target chip, the normal power voltage of the target chip, the package type of the target chip, the clock frequency of the target chip, the clock waveform of the target chip, the test vector of the target chip and the circuit characteristics of the target chip.

[0085] Optionally, by filling the keyword information corresponding to the test requirement document into the preset test development model, the test requirement development model information corresponding to the test requirement document can be obtained. Among them, the model of the target chip is used to indicate the production specifications of the target chip, the test items of the target chip are used to indicate the functions to be tested of the target chip, the test machine type of the target chip is used to indicate the type of the test machine that executes the test target chip, the constant voltage of the target chip is used to indicate the pin voltage of the target chip, the package type of the target chip is used to indicate the pin package type of the target chip, the clock frequency of the target chip is used to indicate the clock frequency to be tested of the target chip, the clock waveform of the target chip is used to indicate the rising edge, falling edge and period of the clock frequency of the target chip, the test vector of the target chip is used to indicate the pin level of the target chip, and the circuit characteristics of the target chip are used to indicate the open circuit characteristics, short circuit characteristics, open circuit characteristics, leakage characteristics and normal working range of the target chip.

[0086] Figure 3 A schematic diagram of the interface of a demand development model provided for this application, see Figure 3 , an interface of demand development model information provided by an embodiment of the present application mainly includes: product model, FT / CP, machine type, constant power voltage, clk clock frequency, waveform, circuit characteristics OS (force voltage, clamping current, maximum effective current and minimum effective current), test vector scan pattern and multiple test items. Among them, the product model is used to indicate the model of the target chip, FT is used to indicate the packaging test of the target chip, CP is used to indicate the wafer test of the target chip, the machine type is used to indicate the type of machine that executes the test program to test the target chip, the constant power voltage is used to indicate the voltage of each pin tested when the target chip is operating normally, the clock frequency is used to indicate the clock frequency of the target chip, the waveform is used to indicate the rising edge, falling edge and clock cycle of the clock waveform of the target chip, the circuit characteristics are used to indicate the open circuit, short circuit, leakage, etc. of the test target chip, and the test item is used to indicate the test function of the target chip.

[0087] In an optional embodiment, see Figure 4 , the specific operation of the above step S104 may be:

[0088] S401. According to the target chip model, target chip test machine type, target chip normal power voltage, target chip packaging type and target chip circuit characteristics in the test requirement development model information, call the first type of artificial intelligence interface of the large language model and obtain the first interface feedback information of the large language model.

[0089] Optionally, the first type of artificial intelligence interface is used to indicate the AI ​​interface set called by the Chat GPT model to receive the model of the target chip, the test machine type of the target chip, the normal power voltage of the target chip, the packaging type of the target chip and the circuit characteristics of the target chip in the test requirement development model information. The first interface feedback information is composed of a large number of strings. After the first type of artificial intelligence interface of the Chat GPT model receives the test requirement development model information, it generates the first interface feedback information. The first interface feedback information is used to characterize the basic test configuration information of the target chip.

[0090] S402. Generate a first test code according to the information returned by the first interface. The first test code includes: test configuration items. The test configuration items include: basic configuration items, pin resource configuration items, pin configuration items, and binning result configuration items.

[0091] Optionally, the basic configuration item is used to indicate the test summary information of the target chip, the test summary information includes the pin definition of the target chip, the clock definition of the target chip, the name of the target chip, etc. The pin resource configuration item is used to indicate the connection relationship between each pin of the target chip and the pin of the test machine, and the pin configuration is used to indicate the set of pins contained in the target chip; the binning result configuration item is used to indicate the binning of the test results of the target chip.

[0092] Optionally, test summary information of the target chip, pin resource information of the target chip, pin set of the target chip and test result binning information of the target chip are extracted from the information returned by the first interface, and basic configuration items, pin resource configuration items, pin configuration items and binning result configuration items are generated according to these information respectively, and the test configuration items are used to indicate the definition of the basic configuration information of the target chip.

[0093] S403. Develop test items of the target chip in the model information according to the test requirements, call the second type of artificial intelligence interface in the preset large language model, and obtain the second interface feedback information of the large language model.

[0094] Optionally, the second type of artificial intelligence interface is used to indicate the set of AI interfaces called by the test items of the target chip in the test requirement development model information received by the Chat GPT model. The second interface feedback information is composed of a large number of strings. After the second type of artificial intelligence interface of the Chat GPT model receives the test requirement development model information, it generates second interface feedback information. The second interface feedback information is used to characterize the function to be tested of the target chip.

[0095] S404: Generate a second test code according to the information returned by the second interface, wherein the second test code includes: a plurality of functional test code segments, each functional test code segment being used to test one or more chip functions.

[0096] Optionally, the test code related to the function to be tested of the target chip is extracted from the information returned by the second interface to obtain the second test code, wherein the second test code can be implemented by a .prg file.

[0097] S405. Develop the clock frequency of the target chip and the clock waveform of the target chip in the model information according to the test requirements, call the third type of artificial intelligence interface in the preset large language model, and obtain the third interface feedback information of the large language model.

[0098] Optionally, the third type of artificial intelligence interface is used to indicate the AI ​​interface set called by the Chat GPT model to receive the clock frequency of the target chip and the clock waveform of the target chip in the test requirement development model information. The third interface feedback information is composed of a large number of strings. After the third type of artificial intelligence interface of the Chat GPT model receives the test requirement development model information, it generates third interface feedback information. The third interface feedback information is used to characterize the clock signal to be tested of the target chip.

[0099] S406. Generate a third test code according to the information returned by the third interface, where the third test code is used to test the clock frequency and waveform of the target chip.

[0100] Optionally, test code related to the clock frequency and clock waveform of the target chip is extracted from the information returned by the third interface to obtain a third test code, wherein the third test code can be implemented by a .tim file.

[0101] Exemplarily, a third test code is as follows:

[0102] @@TIMING_DEFINE

[0103] @@GROUP_1

[0104] @@AC_SET_1

[0105] [NAME=TIM_138]

[0106] [TS]

[0107] PERIOD=200T

[0108] ALLPINS:{DRV_RS=50T}

[0109] {DRV_FL = 150T}

[0110] {STB_RS=180T}

[0111] [END_TS]

[0112] [FMT]

[0113] ALLPINS:{DRV_FMT=NRZ}

[0114] [END_FMT]

[0115] @@END_AC_SET_1

[0116] @@END_GROUNP_1

[0117] @@END_TIMING_DEFINE

[0118] S407. Develop a test vector of the target chip in the model information according to the test requirements, call the fourth type of artificial intelligence interface in the preset large language model, and obtain the fourth interface feedback information of the large language model.

[0119] Optionally, the fourth type of artificial intelligence interface is used to indicate the AI ​​interface set called by the Chat GPT model to receive the test vector of the target chip in the test requirement development model information. The fourth interface feedback information is composed of a large number of strings. After the fourth type of artificial intelligence interface of the Chat GPT model receives the test requirement development model information, it generates fourth interface feedback information. The fourth interface feedback information is used to characterize the test level of the target chip.

[0120] S408. Generate a fourth test code according to the information returned by the fourth interface, where the fourth test code is used to run a test vector corresponding to the target chip.

[0121] Optionally, test code related to the test vector of the target chip is extracted from the information returned by the fourth interface to obtain a fourth test code, wherein the fourth test code can be implemented by a .sd file.

[0122] Exemplarily, a fourth test code including only one test vector is as follows:

[0123]

[0124] In an optional embodiment, see Figure 5 , the specific operation of the above step S402 may be:

[0125] S501: Fill the first node information in the first interface return information into the first target node.

[0126] Optionally, the first target node can be implemented by a @@START_UP_TABLE node, and the first node information is used to indicate summary information of the test program.

[0127] Exemplarily, the first node information can be: TEST_DIE=1 indicates several sites are tested, and the numbers 1, 2, 3... correspond to several sites; Program_Name=Plan.prg indicates that the test item execution file is Plan.prg, PATTERN_HEAD=PIN_HEAD.hed indicates in which file the Pattern pin is defined, TIMING_NAME=DIE_TIM.tim indicates in which file the pin clock is defined, SYTEM_CLK=200MHz indicates that the test machine clock is 200MHz, DEV_NAME=SN73S138 indicates the product name of the IC, DVC_PINCOUNT=768 indicates the maximum number of pins supported by the test machine, and CSV_FILE_OUTPUT=ON indicates that the switch for outputting test data to the CSV file is turned on.

[0128] S502: Fill the second node information in the first interface return information into the second target node.

[0129] Optionally, the second target node can be implemented by a @@PIN_DEFINE_TABLE node, and the second node information is used to indicate the pin resource information of the target chip.

[0130] For example, A, io, 1, 1 defines IC pin A as an input / output pin, with a logic number of 1, connected to the physical pin 1 of the test machine; VCC_DPS PWR 1001LOGIC_DPS1: IC pin VCC_DPS, with a logic number of 1001, connected to the LOGIC_DPS1 power pin of the test machine.

[0131] S503: Fill the third node information in the first interface return information into the third target node.

[0132] Optionally, the third target node can be implemented by a @@PIN_GROUP_TABLE node, and the third node information is used to indicate a pin set of the target chip.

[0133] For example, INPINS, ["1-6"] uses INPINS to represent a set of pins logically numbered 1 to 6.

[0134] S504: Fill the fourth node information in the first interface return information into the fourth target node.

[0135] Optionally, the fourth target node can be implemented by a @@BIN_MAP node, and the fourth node information is used to indicate the binning result information of the target chip.

[0136] For example, 1, 0x00000001, 1, 0 The test result is 1, and it is sorted into box 1; 2, 0x00000002, 0, 1 The test result is 2, and it is sorted into box 2.

[0137] S505 , combining the first target node, the second target node, the third target node, and the fourth target node into a first test code.

[0138] In an optional implementation manner, the operation of step S105 may specifically be:

[0139] According to the test rules of the target chip, the first test code, the second test code, the third test code and the fourth test code are spliced ​​to obtain a target test program corresponding to the target chip.

[0140] Optionally, the test rules of the target chip are used to indicate the inertia of the target chip in running the test program. After the first test code, the second test code, the third test code and the fourth test code are arranged and spliced ​​according to the test rules of the target chip, a target test program that can be run on the target chip is obtained.

[0141] Figure 6 For a complete flow chart of the test program generation method provided for this application, see Figure 6 , the specific implementation process of the test program generation method provided in the embodiment of the present application is as follows: S1, the user edits the test requirement document of the target chip to be tested, and imports the test requirement document of the target chip into the test program generation system through the graphical user interface; S2, the test program generation system calls the corresponding mechanical program to parse the test requirement document of the target chip according to the document rules corresponding to the test requirement document of the target chip, and extracts keyword information from the parsing result of the test requirement document;

[0142] S3. Fill the keyword information corresponding to the test requirement document into the test requirement development model to obtain the test requirement development model information corresponding to the test requirement document; S4. Call multiple artificial intelligence interfaces of the preset large language model based on the test requirement development model information; S5. The preset large language model generates multiple corresponding test codes based on the test requirement development model information received by each artificial intelligence interface; S6. Arrange and splice each test code according to the test rules of the target chip to be tested to obtain the test program of the target chip.

[0143] The following describes the apparatus, device, and computer-readable storage medium used to execute the test program generation method provided in the present application. The specific implementation process and technical effects are described above and will not be repeated below.

[0144] Figure 7This is a schematic diagram of the structure of a test program generation device provided by this application, see Figure 7 , the device comprises:

[0145] An acquisition module 701 is used to acquire a test requirement document of a target chip;

[0146] The parsing module 702 is used to parse the test requirement document to obtain keyword information corresponding to the test requirement document;

[0147] Development module 703, used to obtain test requirement development model information based on a preset test development model and keyword information;

[0148] The first generating module 704 is used to develop model information according to the test requirements, call at least one artificial intelligence interface in the preset large language model, and generate multiple test codes;

[0149] The second generating module 705 is used to generate a target test program corresponding to the target chip according to the multiple test codes.

[0150] In a possible implementation manner, the acquisition module 701 is specifically used for:

[0151] In response to a trigger action of a user on a graphical user interface, a test requirement document of a target chip to be tested is imported and obtained, wherein the test requirement document includes: a function to be tested of the target chip and a test condition of the target chip.

[0152] In a possible implementation manner, the parsing module 702 is specifically used for:

[0153] According to the document rules corresponding to the test requirement document, the test requirement document is parsed, and keyword information corresponding to the test requirement document is extracted.

[0154] In a possible implementation manner, the development module 703 is specifically used for:

[0155] Fill in the keyword information corresponding to the test requirement document into the preset test development model to obtain the test requirement development model information corresponding to the test requirement document. The test requirement development model information includes: the model of the target chip, the test items of the target chip, the test machine type of the target chip, the normal power voltage of the target chip, the package type of the target chip, the clock frequency of the target chip, the clock waveform of the target chip, the test vector of the target chip and the circuit characteristics of the target chip.

[0156] In a possible implementation manner, the first generating module 704 is specifically configured to:

[0157] According to the model of the target chip, the test machine type of the target chip, the normal power voltage of the target chip, the package type of the target chip, and the circuit characteristics of the target chip in the test requirement development model information, the first type of artificial intelligence interface of the large language model is called, and the first interface feedback information of the large language model is obtained;

[0158] Generate a first test code according to the information returned by the first interface, the first test code including: test configuration items, the test configuration items including: chip model configuration items, machine type configuration items, voltage configuration items, package type configuration items and circuit characteristic configuration items;

[0159] Develop test items of the target chip in the model information according to the test requirements, call the second type of artificial intelligence interface in the preset large language model, and obtain the second interface feedback information of the large language model;

[0160] Generate a second test code according to the information returned by the second interface, the second test code including: a plurality of functional test code segments, each functional test code segment is used to test one or more chip functions;

[0161] According to the test requirement development model information, the clock frequency of the target chip and the clock waveform of the target chip are called, the third type of artificial intelligence interface in the preset large language model is called, and the third interface feedback information of the large language model is obtained;

[0162] Generate a third test code according to the information returned by the third interface, where the third test code is used to test the clock frequency and waveform of the target chip;

[0163] Develop a test vector of the target chip in the model information according to the test requirements, call the fourth type of artificial intelligence interface in the preset large language model, and obtain the fourth interface feedback information of the large language model;

[0164] A fourth test code is generated according to the information returned by the fourth interface, and the fourth test code is used to run the test vector corresponding to the target chip.

[0165] In a possible implementation manner, the first generating module 704 is further configured to:

[0166] Fill the first node information in the first interface return information into the first target node;

[0167] Fill the second node information in the first interface return information into the second target node;

[0168] Fill the third node information in the first interface return information into the third target node;

[0169] Fill the fourth node information in the first interface return information into the fourth target node;

[0170] The first target node, the second target node, the third target node, and the fourth target node are combined into a first test code.

[0171] In a possible implementation manner, the second generating module 705 is specifically used for:

[0172] According to the test rules of the target chip, the first test code, the second test code, the third test code and the fourth test code are spliced ​​to obtain a target test program corresponding to the target chip.

[0173] The above-mentioned device is used to execute the method provided by the aforementioned embodiment, and its implementation principle and technical effect are similar, which will not be repeated here.

[0174] The above modules may be one or more integrated circuits configured to implement the above methods, such as one or more application specific integrated circuits (ASICs), or one or more microprocessors, or one or more field programmable gate arrays (FPGAs). For another example, when a module is implemented in the form of a processing element scheduling program code, the processing element may be a general-purpose processor, such as a central processing unit (CPU) or other processor that can call program code. For another example, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).

[0175] Figure 8 This is a schematic diagram of the structure of a computer device provided by this application, see Figure 8 The computer device includes: a memory 801 and a processor 802. The memory 801 stores a computer program that can be run on the processor 802. When the processor 802 executes the computer program, the steps in any of the above method embodiments are implemented.

[0176] An embodiment of the present application further provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments can be implemented.

[0177] Optionally, the present application also provides a program product, such as a computer-readable storage medium, including a program, which is used to execute any of the above-mentioned test program generation method embodiments when executed by a processor.

[0178] In the several embodiments provided by the present invention, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0179] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0180] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0181] The above-mentioned integrated unit implemented in the form of a software functional unit can be stored in a computer-readable storage medium. The above-mentioned software functional unit is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor (English: processor) to perform some steps of the methods of various embodiments of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (English: Read-Only Memory, abbreviated: ROM), random access memory (English: Random Access Memory, abbreviated: RAM), disk or optical disk and other media that can store program codes.

[0182] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0183] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A test program generation method, characterized in that: The method comprises: Obtain the test requirement document of the target chip; Parsing the test requirement document to obtain keyword information corresponding to the test requirement document; Based on the preset test development model and the keyword information, obtain the test requirement development model information; Develop model information according to the test requirements, call at least one artificial intelligence interface in a preset large language model, and generate multiple test codes; A target test program corresponding to the target chip is generated according to the multiple test codes.

2. The test program generation method according to claim 1, characterized in that: The step of obtaining the test requirement document of the target chip includes: In response to a trigger action of a user in a graphical user interface, the test requirement document of the target chip to be tested is imported and acquired, wherein the test requirement document includes: a function to be tested of the target chip and a test condition of the target chip.

3. The test program generation method according to claim 1, characterized in that: The parsing of the test requirement document to obtain keyword information corresponding to the test requirement document includes: According to the document rules corresponding to the test requirement document, the test requirement document is parsed, and keyword information corresponding to the test requirement document is extracted.

4. The test program generation method according to claim 1, characterized in that: The test requirement development model information is obtained based on the preset test development model and the keyword information, including: Fill the keyword information corresponding to the test requirement document into the preset test development model to obtain the test requirement development model information corresponding to the test requirement document, wherein the test requirement development model information includes: the model of the target chip, the test items of the target chip, the test machine type of the target chip, the normal power voltage of the target chip, the package type of the target chip, the clock frequency of the target chip, the clock waveform of the target chip, the test vector of the target chip and the circuit characteristics of the target chip.

5. The test program generation method according to claim 1, characterized in that: The developing model information according to the test requirements, calling at least one artificial intelligence interface in a preset large language model, and generating multiple test codes include: According to the target chip model, the target chip test machine type, the target chip normal power voltage, the target chip packaging type and the target chip circuit characteristics in the test requirement development model information, the first type artificial intelligence interface of the large language model is called, and the first interface feedback information of the large language model is obtained; Generate a first test code according to the information returned by the first interface, wherein the first test code includes: test configuration items, and the test configuration items include: basic configuration items, pin resource configuration items, pin configuration items, and binning result configuration items; Developing test items of the target chip in the model information according to the test requirements, calling the second type of artificial intelligence interface in the preset large language model, and obtaining the second interface feedback information of the large language model; Generate a second test code according to the information returned by the second interface, wherein the second test code includes: a plurality of functional test code segments, each functional test code segment is used to test one or more chip functions; According to the clock frequency of the target chip and the clock waveform of the target chip in the test requirement development model information, the third type of artificial intelligence interface in the preset large language model is called, and the third interface feedback information of the large language model is obtained; Generate a third test code according to the information returned by the third interface, wherein the third test code is used to test the clock frequency and waveform of the target chip; Developing a test vector of the target chip in the model information according to the test requirement, calling a fourth type of artificial intelligence interface in a preset large language model, and obtaining feedback information from the fourth interface of the large language model; A fourth test code is generated according to the information returned by the fourth interface, and the fourth test code is used to run the test vector corresponding to the target chip.

6. The test program generation method according to claim 5, characterized in that: The step of generating a first test code according to the information returned by the first interface includes: Fill the first node information in the first interface return information into the first target node; Fill the second node information in the first interface return information into the second target node; Fill the third node information in the first interface return information into the third target node; Fill the fourth node information in the first interface return information into the fourth target node; The first target node, the second target node, the third target node and the fourth target node are combined into the first test code.

7. The test program generation method according to claim 1, characterized in that: Generating a target test program corresponding to the target chip according to the multiple test codes includes: According to the test rule of the target chip, the first test code, the second test code, the third test code and the fourth test code are spliced ​​to obtain a target test program corresponding to the target chip.

8. A test program generating device, characterized in that: The device comprises: An acquisition module is used to obtain the test requirement document of the target chip; A parsing module, used to parse the test requirement document to obtain keyword information corresponding to the test requirement document; A development module, used to obtain test requirement development model information based on a preset test development model and the keyword information; A first generating module is used to develop model information according to the test requirements, call at least one artificial intelligence interface in a preset large language model, and generate multiple test codes; The second generating module is used to generate a target test program corresponding to the target chip according to the multiple test codes.

9. A computer device, characterized in that: include: A memory and a processor, wherein the memory stores a computer program that can be run on the processor, and when the processor executes the computer program, the steps of the method described in any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of the method according to any one of claims 1 to 7.

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