Implementation method for fast parameter adjustment of high-speed serial bus
By calculating link loss on the receiver end of the high-speed serial bus and setting the initial equalization parameters using the equalization matrix table, the adaptive non-convergence and long time problems caused by inappropriate initial parameter configuration are solved, and the problem of adaptive non-convergence and long time is achieved. Fast adaptation and power consumption reduction effects.
Patent Information
- Application Number
- CN202411605644.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-12
- Publication Date
- 2025-02-25
AI Technical Summary
In the prior art In high-speed serial bus, inappropriate initial parameter configuration results in the possibility of non-convergence of adaptation or the adaptation time is too long, affecting the efficiency and stability of data transmission.
The link loss is calculated by sampling the ratio of the low-frequency differential amplitude and the high-frequency differential amplitude in the receiver side. The loss equalization matrix table is used to set the initial received equalization parameters and the transmitter equalization parameters, and perform adaptive equalization, and the parameters are quickly adjusted to avoid non-convergence and long-term adaptation.
Avoid the problem of adaptive non-convergence of initial parameters, shorten the adaptive convergence time, short links can turn off the judgment feedback equalizer to reduce power consumption, and flexibly configure DFE and CTLE to reduce power consumption.
Smart Images
Figure CN119513013A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of high-speed serial buses, and in particular relates to a method for implementing fast parameter adjustment of a high-speed serial bus. Background Art
[0002] High-speed serial bus is a communication technology widely used in modern electronic systems. With the increasing speed, the length of the link varies greatly, and the range of insertion loss is also increasing. In order to compensate for the link insertion loss, the serial receiver has an equalizer. Due to the large range of insertion loss, the adjustment range of the equalization parameter is also increasing. The existing receiving equalization technology initializes an equalization parameter, which usually includes continuous linear equalization parameters, decision feedback equalization parameters or forward feedback equalization parameters, and uses real-time adaptive mode to find the optimal solution. If the initial parameter configuration is not appropriate, the adaptive mode may not converge or the adaptive mode may take too long to exceed the bus negotiation time.
[0003] In the prior art, after reaching the specified rate, the initial receiving end equalization parameters are set by the firmware, and then the training of the peer sending end equalization parameter operation and the receiving end equalization parameter adaptation are performed. If the initial receiving end equalization parameters are not matched, the training and adaptation may result in parameter convergence failure, the receiving end cannot receive data, and when the link loss is very small, the DFE or part of the DFE Tap cannot be dynamically closed to reduce power consumption. Figure 1 Parameterize the process for existing technologies.
[0004] Therefore, rapid adaptation of initial parameters is necessary. Summary of the invention
[0005] The purpose of the present invention is to propose a method for implementing fast parameter adjustment of a high-speed serial bus to solve the technical problem that the initial parameter configuration of the prior art proposed in the above background technology is inappropriate, resulting in the possibility of non-convergence of adaptation or too long adaptation time.
[0006] To achieve the above object, the present invention provides the following technical solutions: A method for implementing fast parameter adjustment of a high-speed serial bus comprises the following steps: Step 1: The device to be trained and the device to be linked are switched to the target rate; Step 2: The device to be trained and the link-building target device enter the T1 phase, and the transmitter continues to send the N0 / N1 pattern and the 0101 pattern alternately; Step 3: In the T1 phase, the analog-to-digital converters at the receiving end of the device to be trained and the device to be linked perform average maximum swing and average minimum swing sampling to calculate the channel loss. Step 4: In the T1 phase, the receiver searches the loss equalization matrix table to find the optimal combination of transmit and receive equalization parameters corresponding to the loss; Step 5: In the T1 stage, the training device and the link-building target device complete the configuration of the receiving end equalization parameters of the local end, and the state jumps to T2, otherwise it times out; Step 6: In the T2 stage, the device to be trained and the device to establish a link configure the local physical layer transmission parameters according to the negotiation requirements, and send the current equalization parameters of the local end and the request for the other end to send the equalization parameters in the bit stream; Step 7: In the T2 stage, the training device and the link-building target device confirm that the configuration of the sending end of the other end is completed, the receiving end is self-adapted, and multiple consecutive correct code streams are received. The state jumps to T3, otherwise it times out; Step 8: In the T3 stage, the device to be trained and the link-building object device send logical idle code streams. After receiving multiple consecutive logical idle code streams, they enter the normal working L0 state, otherwise they time out and exit.
[0007] Furthermore, in step 2, the N0 / N1 code type N≥32, the sending duration of different code types is 50~500us, and the duration t1, t1≥6ms.
[0008] Furthermore, in step 3, the sampling time is 10-50us, and the channel loss calculation formula is: IL=20log(A01 / AN)-K (dB), Where K is a rate-dependent constant, A01 is the swing detected by the 1010 pattern, and AN is the swing detected by the N0 / N1 pattern.
[0009] Furthermore, the wear leveling matrix table is established by testing the chip in a statistical manner.
[0010] Furthermore, step 5 is completed within t1+2ms and includes whether to turn off the decision feedback equalizer.
[0011] Furthermore, in step 7, at least two consecutive correct code streams are received within no less than 12 ms.
[0012] Preferably, in step 7, three consecutive correct code streams are received within 12 ms.
[0013] Furthermore, in step 8, at least two consecutive logical idle code streams are received within no less than 6 ms.
[0014] Preferably, in step 8, three consecutive logical idle code streams are received within 6 ms.
[0015] The present invention has the following beneficial effects: 1. Avoid the problem of initial parameter adaptation not converging and shorten the adaptive convergence time.
[0016] 2. For short links, the decision feedback equalizer (DFE) can be turned off to avoid convergence problems and reduce power consumption.
[0017] 3. DFE and continuous time linear equalizer (CTLE) can be flexibly configured to reduce power consumption.
[0018] The present invention calculates the link loss by sampling the ratio of the low-frequency differential amplitude and the high-frequency differential amplitude through a built-in analog-to-digital converter (ADC) at the receiving end (RX), and then sets the initial receiving equalization parameters and the transmitting end (TX) equalization parameters by means of a matrix lookup table, and then performs adaptive equalization, thereby avoiding the problems of parameter non-convergence or long convergence time caused by the initial parameters being too far away, and at the same time, some DFEs can be closed according to the link loss size to achieve the purpose of reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.
[0020] Figure 1 This is a schematic diagram of the parameter adjustment process of the prior art; Figure 2 This is a flowchart of the parameter adjustment process of the present invention; Figure 3 It is a schematic diagram of the working mode of the present invention. DETAILED DESCRIPTION
[0021] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0022] See also Figure 2-3 As shown in the figure, a method for realizing fast parameter adjustment of a high-speed serial bus is shown in the flowchart. Figure 2 As shown, the following steps are included: Step 1: The device to be trained and the device to be linked are switched to the target rate.
[0023] Step 2: The device to be trained and the link-building target device enter the T1 phase. The transmitter sends N0 / N1 (N≥32) code patterns for 50~500us and 0101 code patterns for 50~500us alternately, with a duration of t1 (t1≥6ms).
[0024] Step 3: In the T1 phase, the analog-to-digital converter (ADC) at the receiving end of the device to be trained and the target device to be linked samples the average maximum swing and the average minimum swing within 10 to 50 us (preferably 10 us) to calculate the channel loss: IL=20log(A01 / AN)-K (dB), Where K is a rate-dependent constant, A01 is the swing detected by the 0101 pattern, and AN is the swing detected by the N0 / N1 pattern.
[0025] Step 4: In the T1 phase, the receiver searches the loss-balancing matrix table to find the optimal combination of transmit and receive equalization parameters corresponding to the loss. Before the chip leaves the factory, various losses and equalization parameters are tested, and a loss-balancing matrix table is established through data statistics.
[0026] Step 5: In the T1 phase, the device to be trained and the link-building target device complete the configuration of the equalization parameters of the local receiving end (RX) and whether to close the decision feedback equalizer (DFE) within (t1+2) ms, and the state jumps to T2, otherwise it times out.
[0027] Step 6: In the T2 phase, the device to be trained and the link-building partner device configure the local physical layer transmission parameters according to the negotiation requirements, and send the current equalization parameters of the local end and the request for the other end to send the equalization parameters in the bitstream.
[0028] Step 7: In the T2 stage, the device to be trained and the link-building target device confirm that the configuration of the transmitter (TX) of the other end is complete, the receiver (RX) is self-adapted, and at least 2 (preferably 3) consecutive correct code streams are received within no less than 12ms, that is, the valid code stream specified by the protocol, and the state jumps to T3, otherwise it times out.
[0029] Step 8: In the T3 phase, the device to be trained and the device to be linked send logical idle code streams. After receiving at least 2 (preferably 3) consecutive logical idle code streams within no less than 6ms, they enter the normal working L0 state, otherwise they time out and exit.
[0030] Figure 2 middle: The T1 state indicates that the EQ has just entered the state, and the main function is to determine the link loss function.
[0031] T2 state indicates the EQ interactive parameter stage and RX adaptive stage The T3 state indicates that EQ is completed and the link is about to enter a relay state of the L0 state.
[0032] The working mode of the present invention is as follows Figure 3 As shown, the details are as follows: After switching to the specified rate, the transmitter (TX) sends 32 0 / 32 1 code and 0101 code alternately at an interval of 500us. The analog-to-digital converter (ADC) at the receiver (RX) reads the differential amplitude of the high frequency and low frequency, thereby calculating the loss of the channel. By finding the relationship between the equalization (EQ) parameters and the loss matrix of the Channel, the appropriate TX / RX EQ is found. After the configuration is completed and takes effect, EQ adaptation is completed, thereby shortening the time of multiple parameter trainings and avoiding parameter non-convergence caused by inappropriate initial parameters. For ultra-short link DFE non-convergence, DFE or part of DFE tap can be turned off to ensure link stability while reducing power consumption.
[0033] The present invention is applicable to high-speed serial buses such as PCIE / SAS / USB / EARTHNET / MIPI, and is particularly applicable to scenarios where the link length is not fixed, such as changing the adapter card length, cable length, etc. The present invention can quickly adapt to the optimal parameters, and at the same time reduce power consumption in ultra-short link scenarios, and significantly shorten the equalization (EQ) parameter training time.
[0034] The preferred embodiments of the present invention disclosed above are only used to help explain the present invention. The preferred embodiments do not describe all the details in detail, nor do they limit the invention to the specific implementation methods described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well.
Claims
1. A method for implementing fast parameter adjustment of a high-speed serial bus, characterized in that: The following steps are involved: Step 1: The device to be trained and the device to be linked are switched to the target rate; Step 2: The device to be trained and the link-building target device enter the T1 phase, and the transmitter continues to send the N0 / N1 pattern and the 0101 pattern alternately; Step 3: In the T1 phase, the analog-to-digital converters at the receiving end of the device to be trained and the device to be linked perform average maximum swing and average minimum swing sampling to calculate the channel loss. Step 4: In the T1 phase, the receiver searches the loss equalization matrix table to find the optimal combination of transmit and receive equalization parameters corresponding to the loss; Step 5: In the T1 stage, the training device and the link-building target device complete the configuration of the receiving end equalization parameters of the local end, and the state jumps to T2, otherwise it times out; Step 6: In the T2 stage, the device to be trained and the device to establish a link configure the local physical layer transmission parameters according to the negotiation requirements, and send the current equalization parameters of the local end and the request for the other end to send the equalization parameters in the bit stream; Step 7: In the T2 stage, the training device and the link-building target device confirm that the configuration of the sending end of the other end is completed, the receiving end is self-adapted, and multiple consecutive correct code streams are received. The state jumps to T3, otherwise it times out; Step 8: In the T3 stage, the device to be trained and the link-building object device send logical idle code streams. After receiving multiple consecutive logical idle code streams, they enter the normal working L0 state, otherwise they exit due to timeout.
2. The method for implementing fast parameter adjustment of a high-speed serial bus according to claim 1, characterized in that: In step 2, the N0 / N1 code type N≥32, the sending time of different code types is 50~500us, and the duration t1, t1≥6ms.
3. The method for implementing fast parameter adjustment of a high-speed serial bus according to claim 1, characterized in that: In step 3, the sampling time is 10-50us, and the channel loss calculation formula is: IL=20log(A01 / AN)-K (dB), Where K is a rate-dependent constant, A01 is the swing detected by the 1010 pattern, and AN is the swing detected by the N0 / N1 pattern.
4. The method for implementing fast parameter adjustment of a high-speed serial bus according to claim 1, characterized in that: The loss leveling matrix table is established by testing the chip in a data statistical manner.
5. The method for implementing fast parameter adjustment of a high-speed serial bus according to claim 1, characterized in that: The step 5 is completed within t1+2ms and includes whether to turn off the decision feedback equalizer.
6. A method for implementing fast parameter adjustment of a high-speed serial bus according to claim 1 or 5, characterized in that: In step 7, at least two consecutive correct code streams are received within no less than 12 ms.
7. The method for implementing fast parameter adjustment of a high-speed serial bus according to claim 6, characterized in that: Preferably, three consecutive correct code streams are received within 12ms.
8. A method for implementing fast parameter adjustment of a high-speed serial bus according to any one of claims 1, 5 and 7, characterized in that: In step 8, at least two consecutive logical idle code streams are received within no less than 6 ms.
9. The method for implementing fast parameter adjustment of a high-speed serial bus according to claim 8, characterized in that: Preferably, three consecutive logical idle code streams are received within 6 ms.