Verilog-A model optimization method and device for simulating neuron characteristics and probability calculation unit and method

Abstract

The invention provides a Verilog-A model optimization method and device for simulating neuron characteristics and a probability calculation unit and method. The method comprises the following steps: establishing an equivalent model of neurons based on a volatile memristor; simulating the dynamic characteristics of the volatile memristor, a first corresponding relation between the conduction probability and the input pulse amplitude, a second corresponding relation between the conduction speed and the input pulse frequency, and a third corresponding relation between the conduction frequency, the conduction current and the grid voltage; and based on the dynamic characteristics of the volatile memristor, the first corresponding relation, the second corresponding relation and the third corresponding relation, performing parameter debugging on the Verilog-A model of the neuron based on the volatile memristor. The dynamic characteristics, the first corresponding relation, the second corresponding relation and the third corresponding relation of the volatile memristor are enabled to accord with experimental characteristics of neurons based on the volatile memristor. According to the method, the high-order neuron performance of the volatile memristor model can be enhanced, and simulation realization of a large-scale memristor neural network circuit is facilitated.

Description

Technical Field

[0001] The present invention relates to the technical field of novel circuit element models, and in particular to a Verilog-A model optimization method and device for simulating neuron characteristics, and a probability calculation unit and method. Background Art

[0002] With the rapid development of computationally intensive technologies such as neural networks, scientists are trying to implement neural networks in circuits. Traditional CMOS circuits are difficult to meet the needs of large-scale neural networks due to their high complexity and high power consumption when simulating neuronal behavior.

[0003] Currently, researchers are exploring new computing elements in order to achieve dynamic characteristics and efficiency that are closer to biological neural systems. Volatile memristors have become an important research object in this field because of their unique storage and computing integration characteristics and their ability to simulate the dynamic behavior of neurons, such as adjustable threshold voltage and signal processing capabilities.

[0004] However, although previous studies have attempted to simulate the basic behavior of memristors through various methods, these models often fail to fully consider the dynamics and adjustability of volatile memristors in practical applications, as well as the accuracy and flexibility in simulating the behavior of complex neural networks. Therefore, before applying volatile memristors to actual neural networks, their high-order neural properties cannot be accurately captured. Summary of the invention

[0005] The present invention provides a Verilog-A model optimization method and device for simulating neuron characteristics, and a probability calculation unit and method, so as to solve the defect that the high-order neural characteristics of a volatile memristor cannot be accurately captured before it is applied to an actual neural network in the prior art, and meet the demand for building an efficient and low-power artificial neural network by realizing more accurate simulation and high adjustability of an adjustable neuron model based on a volatile memristor.

[0006] The present invention provides a Verilog-A model optimization method for simulating neuron characteristics, comprising: Establish an equivalent model of a neuron based on a volatile memristor, wherein the equivalent model includes a top electrode port, a bottom electrode port and a gate electrode port of the volatile memristor, and the top electrode port and the bottom electrode port control the process of growth or breakage of the filaments inside the volatile memristor by applying different voltages; the gate electrode port controls the speed and degree of growth or breakage of the filaments inside the volatile memristor by applying different voltages; Simulating dynamic characteristics of the volatile memristor, wherein the dynamic characteristics include the growth, conduction, retention and breaking process of the filaments inside the volatile memristor; Simulating a first corresponding relationship between a turn-on probability of the volatile memristor and an input pulse amplitude; Simulating a second corresponding relationship between a conduction speed of the volatile memristor and an input pulse frequency; Simulating a third corresponding relationship among the conduction frequency, conduction current and gate voltage of the volatile memristor; Based on the dynamic characteristics of the volatile memristor, the first correspondence, the second correspondence and the third correspondence, parameters of the Verilog-A model of the neuron based on the volatile memristor are debugged to make the dynamic characteristics of the volatile memristor, the first correspondence, the second correspondence and the third correspondence consistent with the experimental characteristics of the neuron based on the volatile memristor.

[0007] According to the Verilog-A model optimization method for simulating neuron characteristics provided by the present invention, the step of simulating the dynamic characteristics of the volatile memristor specifically includes: Preset threshold voltage V hold , a varying voltage difference V is applied between the top electrode port and the bottom electrode port tb , to simulate the dynamic characteristics of the volatile memristor; When V tb Higher than V hold , and V tb When the current gradually increases, the filaments inside the volatile memristor begin to grow until they are turned on, the current increases suddenly, and more filaments are turned on; When V tb As the current gradually decreases, the filaments inside the volatile memristor begin to break, and when the last conductive filament breaks, the current drops sharply.

[0008] According to the Verilog-A model optimization method for simulating neuron characteristics provided by the present invention, the step of simulating the first corresponding relationship between the conduction probability of the volatile memristor and the input pulse amplitude specifically includes: When the gate voltage is kept at 0V, a plurality of voltage pulses with different preset amplitudes are applied to the top electrode port of the volatile memristor to obtain a first corresponding relationship between the conduction probability of the volatile memristor and the voltage pulse amplitude.

[0009] According to the Verilog-A model optimization method for simulating neuron characteristics provided by the present invention, the step of simulating the second corresponding relationship between the conduction speed of the volatile memristor and the input pulse frequency specifically includes: Under the condition of the same gate voltage, input pulse width and input pulse amplitude, voltage pulses of different frequencies are applied to the top electrode port to simulate the second corresponding relationship between the conduction speed of the volatile memristor and the input pulse frequency.

[0010] According to the Verilog-A model optimization method for simulating neuron characteristics provided by the present invention, the step of simulating the third corresponding relationship between the on-frequency, on-current and the gate voltage of the volatile memristor specifically includes: When the same input voltage is applied to the top electrode port, different gate voltages are applied to the gate electrode port to simulate a third corresponding relationship among the conduction frequency, conduction current and the gate voltage of the volatile memristor.

[0011] According to the Verilog-A model optimization method for simulating neuron characteristics provided by the present invention, the step of performing parameter debugging on the Verilog-A model of the neuron based on the volatile memristor specifically includes: S61, adjusting the parameters in the growth formula of the conductive filaments so that the growth of the conductive filaments is affected by the voltage of the top electrode and the gate electrode in accordance with the actual experimental results; S62, adjusting the parameters in the fracture formula of the conductive filament so that the fracture degree and fracture probability of the conductive filament are affected by the voltage between the top electrode and the gate electrode when the top electrode voltage drops, which are consistent with the actual experimental results; S63. Adjust the parameters of the on-current formula when the conductive filament is turned on, so that the influence of the top electrode and gate electrode voltages on the on-current at different stages is consistent with the actual experimental results.

[0012] The present invention also provides a probability calculation unit, comprising: a volatile memristor, a voltage comparator, a load resistor and a reference voltage terminal; The volatile memristor comprises a top electrode port, a bottom electrode port and a gate electrode port, and the top electrode port and the bottom electrode port control the growth or breaking process of the filaments inside the volatile memristor by applying different voltages; the gate electrode port controls the speed and degree of the growth or breaking of the filaments inside the volatile memristor by applying different voltages; The volatile memristor is parameter-adjusted by the Verilog-A model optimization method for simulating neuron characteristics as described in any one of the above items; The bottom electrode of the volatile memristor is connected to the positive electrode of the voltage comparator, and the negative electrode of the voltage comparator is connected to the reference voltage terminal.

[0013] According to the probability calculation unit provided by the present invention, the probability calculation unit is used as a true random number generator with controllable probability in the probability calculation algorithm simulation.

[0014] The present invention also provides a probability calculation method, which is implemented by the probability calculation unit as described in any one of the above items, and the method comprises: adjusting the input voltage of the top electrode of the volatile memristor to simulate a fourth corresponding relationship between the output voltage of the probability calculation unit and the input voltage of the top electrode; According to the fourth corresponding relationship, a relationship curve between the output voltage of the probability calculation unit and the input voltage of the top electrode of the volatile memristor is obtained by fitting.

[0015] The present invention also provides a Verilog-A model optimization device for simulating neuron characteristics, comprising: An equivalent model establishment module, used to establish an equivalent model of a neuron based on a volatile memristor, wherein the equivalent model includes a top electrode port, a bottom electrode port and a gate electrode port of the volatile memristor, the top electrode port and the bottom electrode port control the process of growth or breakage of the internal filaments of the volatile memristor by applying different voltages; the gate electrode port controls the speed and degree of growth or breakage of the internal filaments of the volatile memristor by applying different voltages; A first simulation module, used to simulate the dynamic characteristics of the volatile memristor, wherein the dynamic characteristics include the growth, conduction, retention and breaking process of the filament inside the volatile memristor; A second simulation module, used for simulating a first corresponding relationship between the conduction probability of the volatile memristor and the input pulse amplitude; A third simulation module, used to simulate a second corresponding relationship between the conduction speed of the volatile memristor and the input pulse frequency; A fourth simulation module, used to simulate a third corresponding relationship between the conduction frequency, the conduction current and the gate voltage of the volatile memristor; A parameter debugging module is used to perform parameter debugging on the Verilog-A model of the neuron based on the volatile memristor based on the dynamic characteristics of the volatile memristor, the first corresponding relationship, the second corresponding relationship and the third corresponding relationship, so that the dynamic characteristics of the volatile memristor, the first corresponding relationship, the second corresponding relationship and the third corresponding relationship are consistent with the experimental characteristics of the neuron based on the volatile memristor.

[0016] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the processor implements any one of the above-described Verilog-A model optimization methods for simulating neuron characteristics or the above-described probability calculation method.

[0017] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements any of the above-described Verilog-A model optimization methods for simulating neuron characteristics or the above-described probability calculation methods.

[0018] The present invention also provides a computer program product, comprising a computer program, which, when executed by a processor, implements any one of the above-mentioned Verilog-A model optimization methods for simulating neuron characteristics or the above-mentioned probability calculation method.

[0019] The Verilog-A model optimization method and device for simulating neuron characteristics provided by the present invention, as well as the probability calculation unit and method, comprehensively consider the design of the Verilog-A model for simulating neuron characteristics, the dynamic characteristics of the volatile memristor, the regulation of the gate voltage and other factors, and can accurately capture the growth and breaking process of the memristor filaments, thereby accurately representing the neuron characteristics consistent with the experimental data; compared with other volatile memristor calculation models, the present invention reduces the complexity of the volatile memristor state calculation, considers the regulation properties of the gate electrode, enhances the high-order neuron performance of the volatile memristor model, and is conducive to the simulation and realization of large-scale memristor neural network circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 A schematic flow chart of a Verilog-A model optimization method for simulating neuron characteristics provided in an embodiment of the present invention.

[0022] Figure 2 The IV curve diagram of the volatile memristor provided in the embodiment of the present invention and the particle growth state in each stage.

[0023] Figure 3 Simplified growth and breaking logic of filaments provided for embodiments of the present invention.

[0024] Figure 4 The present invention provides a volatile memristor with conduction characteristics under different input pulse amplitudes.

[0025] Figure 5 The present invention provides a volatile memristor with conduction characteristics at different input intervals.

[0026] Figure 6 The present invention provides a volatile memristor with conduction characteristics at different gate voltages.

[0027] Figure 7A schematic diagram of the structure of a probability calculation unit provided in an embodiment of the present invention.

[0028] Figure 8 The output voltage V of the probability calculation unit provided in the embodiment of the present invention is out With input voltage V in 's changing trend chart.

[0029] Fig. 9 The diagram is a schematic diagram of a two-dimensional Metropolis-Hastings algorithm simulation using a Verilog-A model for simulating neuron characteristics provided by an embodiment of the present invention.

[0030] Fig.10 It is a schematic diagram of the structure of a Verilog-A model optimization device for simulating neuron characteristics provided by an embodiment of the present invention.

[0031] Fig.11 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0033] The present invention is described in detail below in conjunction with the accompanying drawings of the specification. The specific operating method in the method embodiment can also be applied to the device embodiment or the system embodiment. In the description of the present invention, unless otherwise specified, "at least one" includes one or more. "Multiple" refers to two or more. For example, at least one of A, B and C includes: A exists alone, B exists alone, A and B exist at the same time, A and C exist at the same time, B and C exist at the same time, and A, B and C exist at the same time. In the present invention, " / " means or, for example, A / B can mean A or B; "and / or" in this article is only a kind of association relationship that describes the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0034] The present invention will be described in detail below in conjunction with specific implementation modes.

[0035] In some specific embodiments of the present invention, Figure 1 As shown, this scheme provides a Verilog-A model optimization method for simulating neuron characteristics, including the following steps: Step 100: Establish an equivalent model of a neuron based on a volatile memristor, wherein the equivalent model includes a top electrode port, a bottom electrode port and a gate electrode port of the volatile memristor, and the top electrode port and the bottom electrode port control the growth or breakage process of the filaments inside the volatile memristor by applying different voltages; the gate electrode port controls the speed and degree of the growth or breakage of the filaments inside the volatile memristor by applying different voltages; Step 200, simulating the dynamic characteristics of the volatile memristor, wherein the dynamic characteristics include the growth, conduction, retention and breaking process of the filaments inside the volatile memristor; Step 300, simulating a first corresponding relationship between the conduction probability of the volatile memristor and the input pulse amplitude; Step 400, simulating a second corresponding relationship between the conduction speed of the volatile memristor and the input pulse frequency; Step 500, simulating a third corresponding relationship among the conduction frequency, conduction current and the gate voltage of the volatile memristor; Step 600: Based on the dynamic characteristics of the volatile memristor, the first correspondence, the second correspondence, and the third correspondence, parameter debugging is performed on the Verilog-A model of the neuron based on the volatile memristor, so that the dynamic characteristics of the volatile memristor, the first correspondence, the second correspondence, and the third correspondence are consistent with the experimental characteristics of the neuron based on the volatile memristor.

[0036] It should be noted that the existing schemes for simulating the basic behavior of memristors cannot achieve real-time adjustability, and it is difficult to accurately simulate the dynamics and adjustability of volatile memristors in practical applications. The simulation efficiency is low, and it is difficult to meet the requirements of accuracy and flexibility when simulating complex neural network behaviors.

[0037] Therefore, the present invention meets the demand for building an efficient and low-power artificial neural network through more accurate simulation and high adjustability by constructing a new type of adjustable neuron model based on volatile memristors, that is, the Verilog-A model of neurons based on volatile memristors as described above.

[0038] In some possible implementations of the present invention, the step of simulating the dynamic characteristics of the volatile memristor specifically includes: Preset threshold voltage V hold , a varying voltage difference V is applied between the top electrode port and the bottom electrode port tb , to simulate the dynamic characteristics of the volatile memristor; When V tb Higher than V hold , and V tbWhen the current gradually increases, the filaments inside the volatile memristor begin to grow until they are turned on, the current increases suddenly, and more filaments are turned on; When V tb As the current gradually decreases, the filaments inside the volatile memristor begin to break, and when the last conductive filament breaks, the current drops sharply.

[0039] Specifically, this embodiment provides an implementation method for simulating the dynamic characteristics of the volatile memristor by applying a varying voltage difference V between the top electrode port and the bottom electrode port. tb , according to V tb With the preset threshold voltage V hold The comparison results between them are used to simulate the dynamic characteristics of the volatile memristor.

[0040] In a possible embodiment, Figure 2 As shown, Figure 2 The IV curve diagram of the volatile memristor provided by the embodiment of the present invention and the particle growth state at each stage, Figure 2 The implementation logic of the Verilog-A model using volatile memristors to simulate neuron characteristics is shown, including the growth, conduction, retention, and breakage of filaments. When the voltage difference between the top electrode and the bottom electrode (V tb ) is higher than V hold When the filaments begin to grow until they are turned on, causing a sudden increase in current, and then more filaments are turned on. Figure 1 (e), (c), and (d) correspond to the filament growth process. As V tb The filaments begin to break, and when the last conducting filament breaks, the current drops sharply. Figure 1 (c), (b), and (a) correspond to the filament breakage process.

[0041] Furthermore, during the growth, conduction, retention and breakage of the filament, the implementation of the gate voltage will affect the memristor properties such as the conduction speed, breakage speed, and breakage degree of the filament, thereby changing the excitability or inhibition of the neuron.

[0042] Depend on Figure 2 It can be clearly seen in Figure (b) that the parameter "gjump" decreases. The parameter "gjump" is used to characterize the influence of different numbers of connected conductive filaments on the increase of current. The decrease in this parameter represents a certain degree of weakening effect on the current caused by the reduction in the number of conductive filaments that are connected before the last conductive filament breaks.

[0043] Depend on Figure 2 It can be clearly seen in Figure (c) that as the voltage difference between the top electrode and the bottom electrode increases, more conductive filaments appear in the volatile memristor.

[0044] Depend on Figure 2 It can be clearly seen in Figure (d) that when the voltage difference between the top electrode and the bottom electrode reaches a preset voltage threshold, the volatile memristor is in a low-resistance state and a conductive current flows through it.

[0045] Depend on Figure 2 It can be clearly seen from Figure (e) that as the voltage between the top electrode and the bottom electrode gradually increases, the filaments in the memristor begin to grow and the current is weak. At this time, the memristor is in a high-resistance state.

[0046] In a possible embodiment, at higher gate voltages, the breaking of the filaments is more drastic.

[0047] The above process can also be explained by the simplified growth and breakage logic of filaments. Figure 3 The simplified growth and breakage logic of the filaments provided by the embodiments of the present invention is as follows: Figure 3 As shown, first determine the voltage difference (V tb ) is higher than the preset holding voltage threshold V hold , in judging V tb Higher than V hold When V is determined, it is determined that the filaments of the volatile memristor begin to grow, otherwise it is determined that the filaments in the volatile memristor begin to dissolve; tb Higher than V hold In the case of, it is determined whether the conductive gap in the volatile memristor is the minimum gap, if so, it is determined that the conductive current passes, otherwise, a weak current passes.

[0048] The above-mentioned arrangement of the embodiment of the present invention can directly estimate the growth and breakage of the filaments without solving equations, thus reducing the amount of calculation and showing neuron-like properties.

[0049] In some possible implementations of the present invention, the step of simulating the first corresponding relationship between the conduction probability of the volatile memristor and the input pulse amplitude specifically includes: When the gate voltage is kept at 0V, a plurality of voltage pulses with different preset amplitudes are applied to the top electrode port of the volatile memristor to obtain a first corresponding relationship between the conduction probability of the volatile memristor and the voltage pulse amplitude.

[0050] Specifically, this embodiment provides an implementation method for simulating the relationship between the conduction probability and input pulse amplitude of a volatile memristor, by applying multiple voltage pulses with different preset amplitudes to the top electrode port to simulate the corresponding relationship between the conduction probability and input pulse amplitude of the volatile memristor.

[0051] In a possible embodiment, Figure 4 As shown, Figure 4The conduction characteristics of the volatile memristor provided by the embodiment of the present invention under different input pulse amplitudes, Figure 4 The figure shows the memristor current under different input pulse amplitudes. By applying pulses of 2.6V, 2.4V, 2.2V, and 2.0V with a period of 10ms and a duty cycle of 40% to the top electrode of the memristor, and keeping the gate voltage at 0V, it is finally obtained that as the input amplitude decreases, the probability of the memristor turning on decreases accordingly.

[0052] In some possible implementations of the present invention, the step of simulating the second corresponding relationship between the conduction speed of the volatile memristor and the input pulse frequency specifically includes: Under the condition of the same gate voltage, input pulse width and input pulse amplitude, voltage pulses of different frequencies are applied to the top electrode port to simulate the second corresponding relationship between the conduction speed of the volatile memristor and the input pulse frequency.

[0053] Specifically, this embodiment provides an implementation method for simulating the relationship between the conduction speed and input pulse frequency of a volatile memristor, by applying voltage pulses of different frequencies to the top electrode port to simulate the corresponding relationship between the conduction speed and input pulse frequency of the volatile memristor.

[0054] In a possible embodiment, Figure 5 As shown, Figure 5 The conduction characteristics of the volatile memristor provided by the embodiment of the present invention under different input intervals, Figure 5 The memristor current under different input intervals is shown. By changing the input frequency to 150Hz, 100Hz, and 50Hz under the same gate voltage, input pulse width, and input amplitude, it is finally obtained that the smaller the input interval, the faster the memristor turns on.

[0055] In some possible implementations of the present invention, the step of simulating the third corresponding relationship between the on-frequency, on-current and the gate voltage of the volatile memristor specifically includes: When the same input voltage is applied to the top electrode port, different gate voltages are applied to the gate electrode port to simulate a third corresponding relationship among the conduction frequency, conduction current and the gate voltage of the volatile memristor.

[0056] Specifically, this embodiment provides an implementation method for simulating the relationship between the on-frequency, on-current and gate voltage of a volatile memristor, and applies different gate voltages through the gate electrode port to simulate the corresponding relationship between the on-frequency, on-current and gate voltage of the volatile memristor.

[0057] In a possible embodiment, Figure 6 As shown, Figure 6The conduction characteristics of the volatile memristor provided by the embodiment of the present invention at different gate voltages, Figure 6 The turn-on characteristics under the same gate voltage are shown. By changing the gate voltage to 0~-4V under the same input (amplitude 3V, period 10ms, duty cycle 50%), the result is that the higher the gate voltage, the higher the turn-on frequency and the turn-on current.

[0058] In some possible implementations of the present invention, the step of performing parameter debugging on the Verilog-A model of the neuron based on the volatile memristor specifically includes: Step 61, adjusting the parameters in the growth formula of the conductive filaments so that the growth of the conductive filaments is affected by the voltage of the top electrode and the gate electrode in accordance with the actual experimental results; Step 62, adjusting the parameters in the fracture formula of the conductive filament so that the fracture degree and fracture probability of the conductive filament are affected by the voltage between the top electrode and the gate electrode when the top electrode voltage drops and are consistent with the actual experimental results; Step 63, adjusting the parameters of the on-current formula when the conductive filament is turned on, so that the influence of the top electrode and gate electrode voltages on the on-current at different stages is consistent with the actual experimental results.

[0059] Specifically, this embodiment provides an implementation method for parameter debugging of a Verilog-A model of a neuron based on a volatile memristor, by finely adjusting key parameters such as the growth, breakage, and on-current of the conductive filaments of the volatile memristor in the Verilog-A model, so that the behavior of the simulation model can accurately reproduce the on-characteristics of the memristor observed in the actual experiment under different electrode voltage conditions, thereby ensuring the reliability of the simulation results and a high degree of consistency with the physical device. The above-mentioned setting of the embodiment of the present invention, after parameter debugging, the neuron characteristics are consistent with the experimental data, and can be applied to large-scale circuit simulation.

[0060] The Verilog-A model optimization method for simulating neuron characteristics provided by the embodiment of the present invention takes into account the growth and breakage of volatile memristor filaments, the dynamic characteristics of the device, and the regulation of the gate voltage; the regulation process of the gate voltage on the neuron is taken into account, and a lower gate voltage makes the on-current smaller, the probability of filament breakage is greater, and the degree of breakage is stronger. Taking into account the dynamic characteristics of the device, the filament growth process and the degree of breakage both show a certain degree of randomness, and the probability is regulated by the voltage of the three ports. The complexity of the volatile memristor calculation is reduced, and the high-order neuron performance of the volatile memristor model is enhanced, which is conducive to the simulation and realization of large-scale memristor neural network circuits.

[0061] In some specific embodiments of the present invention, the present solution provides an equivalent model of a neuron based on a volatile memristor, comprising: a top electrode port, a bottom electrode port, and a gate electrode port; Wherein, the top electrode port and the bottom electrode port are used to control the growth or breaking of the filaments of the volatile memristor; The gate electrode port is used to control the speed and degree of the growth or breaking of the filaments of the volatile memristor.

[0062] Specifically, this embodiment provides an implementation of an equivalent model of a neuron based on a volatile memristor, by setting a top electrode and a bottom electrode port for controlling the growth or breakage of the memristor filaments, and a gate electrode for controlling the degree of inhibition or excitation of the neurons. The model takes into account the growth and breakage of the volatile memristor filaments, the dynamic characteristics of the device, and the regulation of the gate voltage; different gate voltages are applied through the gate electrode port to simulate the corresponding relationship between the on-frequency, on-current and gate voltage of the volatile memristor, thereby realizing the real-time adjustability of the volatile memristor.

[0063] Furthermore, by directly estimating the growth and breakage of the filaments, there is no need to solve equations, which reduces the amount of calculation and makes the volatile memristor exhibit neuron-like properties. Therefore, the complexity of volatile memristor calculations is reduced, and the high-order neuron performance of the volatile memristor model is enhanced, which helps to realize the simulation of large-scale memristor neural network circuits.

[0064] The Verilog-A model optimization method for simulating neuron characteristics provided in an embodiment of the present invention takes into account factors such as the design of the cation-based volatile memristor model, the dynamic characteristics of the device, and the regulation of the gate voltage. By simulating the growth and breaking process of the cation-based memristor filaments, the high-order characteristics of neurons can be accurately realized, thereby achieving the purpose of large-scale neural network circuit simulation.

[0065] In some specific embodiments of the present invention, Figure 7 As shown, the present solution provides a probability calculation unit, including: a volatile memristor, a voltage comparator, a load resistor and a reference voltage terminal; The volatile memristor includes a top electrode port, a bottom electrode port and a gate electrode port. The top electrode port and the bottom electrode port control the growth or breaking process of the filaments inside the volatile memristor by applying different voltages. The gate electrode port controls the speed and degree of the growth or breaking of the filaments inside the volatile memristor by applying different voltages. The volatile memristor is parameter-adjusted by using the Verilog-A model optimization method for simulating neuron characteristics in any of the above embodiments; The bottom electrode of the volatile memristor is connected to the positive electrode of the voltage comparator, and the negative electrode of the voltage comparator is connected to the reference voltage terminal.

[0066] In some specific embodiments of the present invention, a probability calculation method is further provided. The method is implemented by the probability calculation unit described in the above embodiment, and the method comprises: adjusting the input voltage of the top electrode of the volatile memristor to simulate a fourth corresponding relationship between the output voltage of the probability calculation unit and the input voltage of the top electrode; According to the fourth corresponding relationship, a relationship curve between the output voltage of the probability calculation unit and the input voltage of the top electrode of the volatile memristor is obtained by fitting.

[0067] Specifically, this embodiment provides an implementation of a probability calculation method, in which a volatile memristor is used in a probability calculation unit to fit a relationship curve between an output voltage and an input voltage of the probability calculation unit.

[0068] In a possible embodiment, Figure 8 As shown, Figure 8 The output voltage V of the probability calculation unit provided in the embodiment of the present invention is out With input voltage V in The changing trend chart of Figure 8 The variation trend of Vout with Vin in the probability calculation unit is shown in Figure 7 Apply different input voltage amplitudes to the probability calculation unit to obtain different V out The average value can be obtained by fitting an S curve.

[0069] In some possible implementations of the present invention, the probability calculation unit is used as a true random number generator with controllable probability in the probability calculation algorithm simulation.

[0070] In a possible embodiment, Fig. 9 As shown, Fig. 9 A schematic diagram of a two-dimensional Metropolis-Hastings algorithm simulation using the Verilog-A model provided by an embodiment of the present invention, Fig. 9 It can be seen that in the two-dimensional Metropolis-Hastings algorithm simulation using the Verilog-A model, the probability calculation unit composed of the Verilog-A model can be used as a true random number generator with controllable probability to simulate the probability calculation algorithm.

[0071] The embodiment of the present invention provides a new and efficient method for the simulation and parameter debugging of large-scale memristor neural network circuits by introducing a Verilog-A model of adjustable neurons based on volatile memristors. It not only greatly improves the computational efficiency, but also can accurately express the high-order characteristics of neurons, showing simulation results that are highly consistent with experimental data, and reveals its wide application potential in probability computing circuit simulation.

[0072] In some embodiments of the present invention, Fig.10 As shown, a Verilog-A model optimization device for simulating neuron characteristics is also provided, including: An equivalent model establishment module 1001 is used to establish an equivalent model of a neuron based on a volatile memristor, wherein the equivalent model includes a top electrode port, a bottom electrode port and a gate electrode port of the volatile memristor, and the top electrode port and the bottom electrode port control the process of growth or breakage of the filaments inside the volatile memristor by applying different voltages; the gate electrode port controls the speed and degree of growth or breakage of the filaments inside the volatile memristor by applying different voltages; A first simulation module 1002, used to simulate the dynamic characteristics of the volatile memristor, wherein the dynamic characteristics include the growth, conduction, retention and breaking process of the filament inside the volatile memristor; A second simulation module 1003, used to simulate a first corresponding relationship between the conduction probability of the volatile memristor and the input pulse amplitude; A third simulation module 1004, used to simulate a second corresponding relationship between the conduction speed of the volatile memristor and the input pulse frequency; A fourth simulation module 1005, used to simulate a third corresponding relationship between the conduction frequency, the conduction current and the gate voltage of the volatile memristor; The parameter debugging module 1006 is used to perform parameter debugging on the Verilog-A model of the neuron based on the volatile memristor based on the dynamic characteristics of the volatile memristor, the first correspondence, the second correspondence and the third correspondence, so that the dynamic characteristics of the volatile memristor, the first correspondence, the second correspondence and the third correspondence are consistent with the experimental characteristics of the neuron based on the volatile memristor.

[0073] Fig.11 An example of a physical structure diagram of an electronic device is shown in FIG. Fig.11As shown, the electronic device may include: a processor 1110, a communication interface 1120, a memory 1130 and a communication bus 1140, wherein the processor 1110, the communication interface 1120 and the memory 1130 communicate with each other through the communication bus 1140. The processor 1110 may call the logic instructions in the memory 1130 to execute the Verilog-A model optimization method for simulating neuron characteristics, the method comprising: establishing an equivalent model of a neuron based on a volatile memristor, wherein the equivalent model comprises a top electrode port, a bottom electrode port and a gate electrode port of the volatile memristor, wherein the top electrode port and the bottom electrode port control the process of the growth or breakage of the filament inside the volatile memristor by applying different voltages; the gate electrode port controls the speed and degree of the growth or breakage of the filament inside the volatile memristor by applying different voltages; simulating the dynamic characteristics of the volatile memristor, wherein the dynamic characteristics include the growth, conduction and The invention relates to a method for simulating a first correspondence between the turn-on probability of the volatile memristor and the input pulse amplitude; a second correspondence between the turn-on speed of the volatile memristor and the input pulse frequency; a third correspondence between the turn-on frequency, the turn-on current and the gate voltage of the volatile memristor; and a Verilog-A model of the neuron based on the volatile memristor is parameterized based on the dynamic characteristics of the volatile memristor, the first correspondence, the second correspondence and the third correspondence, so that the dynamic characteristics of the volatile memristor, the first correspondence, the second correspondence and the third correspondence are consistent with the experimental characteristics of the neuron based on the volatile memristor.

[0074] In addition, the logic instructions in the above-mentioned memory 1130 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0075] On the other hand, the present invention also provides a computer program product, which includes a computer program. The computer program can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the Verilog-A model optimization method for simulating neuron characteristics provided by the above methods, the method comprising: establishing an equivalent model of a neuron based on a volatile memristor, wherein the equivalent model includes a top electrode port, a bottom electrode port and a gate electrode port of the volatile memristor, the top electrode port and the bottom electrode port control the process of growth or breakage of the filaments inside the volatile memristor by applying different voltages; the gate electrode port controls the speed and degree of growth or breakage of the filaments inside the volatile memristor by applying different voltages; simulating the dynamic behavior of the volatile memristor The invention relates to a method for simulating a first correspondence between the conduction probability of the volatile memristor and the input pulse amplitude; simulating a second correspondence between the conduction speed of the volatile memristor and the input pulse frequency; simulating a third correspondence between the conduction frequency, the conduction current and the gate voltage of the volatile memristor; and performing parameter debugging on the Verilog-A model of the neuron based on the volatile memristor based on the dynamic characteristics of the volatile memristor, the first correspondence, the second correspondence and the third correspondence, so that the dynamic characteristics of the volatile memristor, the first correspondence, the second correspondence and the third correspondence are consistent with the experimental characteristics of the neuron based on the volatile memristor.

[0076] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to execute the Verilog-A model optimization method for simulating neuron characteristics provided by the above-mentioned methods, the method comprising: establishing an equivalent model of a neuron based on a volatile memristor, wherein the equivalent model comprises a top electrode port, a bottom electrode port and a gate electrode port of the volatile memristor, the top electrode port and the bottom electrode port controlling the process of growth or breakage of filaments inside the volatile memristor by applying different voltages; the gate electrode port controlling the speed and degree of growth or breakage of filaments inside the volatile memristor by applying different voltages; simulating the dynamic characteristics of the volatile memristor, wherein the dynamic characteristics include The invention relates to a method for simulating the growth, conduction, retention and breaking process of the filaments inside the volatile memristor; simulating the first corresponding relationship between the conduction probability of the volatile memristor and the input pulse amplitude; simulating the second corresponding relationship between the conduction speed of the volatile memristor and the input pulse frequency; simulating the third corresponding relationship between the conduction frequency, the conduction current and the gate voltage of the volatile memristor; and based on the dynamic characteristics of the volatile memristor, the first corresponding relationship, the second corresponding relationship and the third corresponding relationship, performing parameter debugging on the Verilog-A model of the neuron based on the volatile memristor, so that the dynamic characteristics of the volatile memristor, the first corresponding relationship, the second corresponding relationship and the third corresponding relationship are consistent with the experimental characteristics of the neuron based on the volatile memristor.

[0077] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0078] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0079] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A Verilog-A model optimization method for simulating neuron characteristics, characterized in that: include: Establish an equivalent model of a neuron based on a volatile memristor, wherein the equivalent model includes a top electrode port, a bottom electrode port and a gate electrode port of the volatile memristor, and the top electrode port and the bottom electrode port control the process of growth or breakage of the filaments inside the volatile memristor by applying different voltages; the gate electrode port controls the speed and degree of growth or breakage of the filaments inside the volatile memristor by applying different voltages; Simulating dynamic characteristics of the volatile memristor, wherein the dynamic characteristics include the growth, conduction, retention and breaking process of the filaments inside the volatile memristor; Simulating a first corresponding relationship between a turn-on probability of the volatile memristor and an input pulse amplitude; Simulating a second corresponding relationship between a conduction speed of the volatile memristor and an input pulse frequency; Simulating a third corresponding relationship among the conduction frequency, conduction current and gate voltage of the volatile memristor; Based on the dynamic characteristics of the volatile memristor, the first correspondence, the second correspondence and the third correspondence, parameters of the Verilog-A model of the neuron based on the volatile memristor are debugged to make the dynamic characteristics of the volatile memristor, the first correspondence, the second correspondence and the third correspondence consistent with the experimental characteristics of the neuron based on the volatile memristor.

2. The Verilog-A model optimization method for simulating neuron characteristics according to claim 1, characterized in that: The step of simulating the dynamic characteristics of the volatile memristor specifically comprises: Preset threshold voltage V hold , a varying voltage difference V is applied between the top electrode port and the bottom electrode port tb , to simulate the dynamic characteristics of the volatile memristor; When V tb Higher than V hold , and V tb When the current gradually increases, the filaments inside the volatile memristor begin to grow until they are turned on, the current increases suddenly, and more filaments are turned on; When V tb As the current gradually decreases, the filaments inside the volatile memristor begin to break, and when the last conductive filament breaks, the current drops sharply.

3. The Verilog-A model optimization method for simulating neuron characteristics according to claim 2, characterized in that: The step of simulating a first corresponding relationship between the conduction probability of the volatile memristor and the input pulse amplitude specifically includes: When the gate voltage is kept at 0V, a plurality of voltage pulses with different preset amplitudes are applied to the top electrode port of the volatile memristor to obtain a first corresponding relationship between the conduction probability of the volatile memristor and the voltage pulse amplitude.

4. The Verilog-A model optimization method for simulating neuron characteristics according to claim 3, characterized in that: The step of simulating the second corresponding relationship between the conduction speed of the volatile memristor and the input pulse frequency specifically includes: Under the condition of the same gate voltage, input pulse width and input pulse amplitude, voltage pulses of different frequencies are applied to the top electrode port to simulate the second corresponding relationship between the conduction speed of the volatile memristor and the input pulse frequency.

5. The Verilog-A model optimization method for simulating neuron characteristics according to claim 1, characterized in that: The step of simulating a third corresponding relationship between the on-frequency, on-current and the gate voltage of the volatile memristor specifically includes: When the same input voltage is applied to the top electrode port, different gate voltages are applied to the gate electrode port to simulate a third corresponding relationship among the conduction frequency, conduction current and the gate voltage of the volatile memristor.

6. The Verilog-A model optimization method for simulating neuron characteristics according to any one of claims 1 to 5, characterized in that: The step of performing parameter debugging on the Verilog-A model of the neuron based on the volatile memristor specifically includes: S61, adjusting the parameters in the growth formula of the conductive filaments so that the growth of the conductive filaments is affected by the voltage of the top electrode and the gate electrode in accordance with the actual experimental results; S62, adjusting the parameters in the fracture formula of the conductive filament so that the fracture degree and fracture probability of the conductive filament are affected by the voltage between the top electrode and the gate electrode when the top electrode voltage drops, which are consistent with the actual experimental results; S63. Adjust the parameters of the on-current formula when the conductive filament is turned on, so that the influence of the top electrode and gate electrode voltages on the on-current at different stages is consistent with the actual experimental results.

7. A probability calculation unit, characterized in that: include: A volatile memristor, a voltage comparator, a load resistor and a reference voltage terminal; wherein the volatile memristor comprises a top electrode port, a bottom electrode port and a gate electrode port, and the top electrode port and the bottom electrode port control the process of the growth or breaking of the filaments inside the volatile memristor by applying different voltages; the gate electrode port controls the speed and degree of the growth or breaking of the filaments inside the volatile memristor by applying different voltages; The volatile memristor is parameter-adjusted by the Verilog-A model optimization method for simulating neuron characteristics according to any one of claims 1 to 6; The bottom electrode of the volatile memristor is connected to the positive electrode of the voltage comparator, and the negative electrode of the voltage comparator is connected to the reference voltage terminal.

8. The probability calculation unit according to claim 7, characterized in that: The probability calculation unit is used as a true random number generator with controllable probability in the probability calculation algorithm simulation.

9. A probability calculation method, characterized in that: The method is implemented by the probability calculation unit according to claim 7 or 8, and comprises: adjusting the input voltage of the top electrode of the volatile memristor to simulate a fourth corresponding relationship between the output voltage of the probability calculation unit and the input voltage of the top electrode; According to the fourth corresponding relationship, a relationship curve between the output voltage of the probability calculation unit and the input voltage of the top electrode of the volatile memristor is obtained by fitting.

10. A Verilog-A model optimization device for simulating neuron characteristics, characterized in that: include: An equivalent model establishment module, used to establish an equivalent model of a neuron based on a volatile memristor, wherein the equivalent model includes a top electrode port, a bottom electrode port and a gate electrode port of the volatile memristor, the top electrode port and the bottom electrode port control the process of growth or breakage of the internal filaments of the volatile memristor by applying different voltages; the gate electrode port controls the speed and degree of growth or breakage of the internal filaments of the volatile memristor by applying different voltages; A first simulation module, used to simulate the dynamic characteristics of the volatile memristor, wherein the dynamic characteristics include the growth, conduction, retention and breaking process of the filament inside the volatile memristor; A second simulation module, used for simulating a first corresponding relationship between the conduction probability of the volatile memristor and the input pulse amplitude; A third simulation module, used to simulate a second corresponding relationship between the conduction speed of the volatile memristor and the input pulse frequency; A fourth simulation module, used to simulate a third corresponding relationship between the conduction frequency, the conduction current and the gate voltage of the volatile memristor; A parameter debugging module is used to perform parameter debugging on the Verilog-A model of the neuron based on the volatile memristor based on the dynamic characteristics of the volatile memristor, the first corresponding relationship, the second corresponding relationship and the third corresponding relationship, so that the dynamic characteristics of the volatile memristor, the first corresponding relationship, the second corresponding relationship and the third corresponding relationship are consistent with the experimental characteristics of the neuron based on the volatile memristor.

Images