Time sequence sign-off method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention discloses a time sequence sign-off method and device, electronic equipment and a storage medium, relates to the technical field of integrated circuits, and can effectively reduce the pessimistic degree and complexity of time sequence sign-off of a three-dimensional integrated chip. The method comprises the following steps: obtaining a first standard cell library corresponding to each crystal grain in a chip to be signed, each standard cell in the first standard cell library having own three-dimensional process corner time sequence parameter, the three-dimensional process corner time sequence parameters comprise the average time delay of each standard unit under the three-dimensional process corner and the standard deviation of the time delay of the standard unit under the three-dimensional process corner; wherein the to-be-signed chip is obtained by three-dimensional integration of at least two crystal grains; and performing time sequence sign-off on the chip to be signed-off by using the first standard cell library. The method is suitable for time sequence sign-off of the chip.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular to a timing sign-off method and device, electronic equipment, and storage medium. Background Art

[0002] Before a chip is commissioned to be processed by a wafer fab, it needs to undergo a timing sign-off. Timing sign-off refers to checking the timing of the chip design to ensure that the chip can work properly under different PVT (Process Voltage Temperature) scenarios.

[0003] Due to process variation (or deviation variation) in chip production, a certain degree of pessimistic estimation of chip timing is often required during sign-off. However, overly pessimistic estimation will seriously affect chip performance. In order to avoid overly pessimistic estimation of chip timing, for 2D chips, a combination of global corner (or global standard deviation) and local variation (i.e. POCV (parametric on chip variation)) is generally used to perform timing sign-off.

[0004] However, for 3D integrated chips, since the process conditions of each die are highly random, if the above method is used for cross-die sign-off, on the one hand, there will be more sign-off process corner combinations (or sign-off condition combinations), which makes the timing analysis too complicated. On the other hand, as the number of die stacks increases, the above sign-off method will become more and more pessimistic, resulting in over-design and loss of product performance. Summary of the invention

[0005] In view of this, embodiments of the present invention provide a timing sign-off method and apparatus, an electronic device, and a storage medium, which can effectively reduce the pessimism and complexity of timing sign-off of a 3D integrated chip.

[0006] In a first aspect, an embodiment of the present invention provides a timing sign-off method, comprising: obtaining a first standard cell library corresponding to each die in a chip to be signed off, each standard cell in the first standard cell library having its own 3D process angle timing parameter, the 3D process angle timing parameter comprising an average delay of each of the standard cells under the 3D process angle and a standard deviation of the delay of the standard cell under the 3D process angle; wherein the chip to be signed off is obtained by 3D integration of at least two die; and performing timing sign-off on the chip to be signed off using the first standard cell library.

[0007] In one embodiment, before obtaining the first standard cell library corresponding to each die in the chip to be signed off, the method further includes: obtaining a second standard cell library corresponding to each die in the chip to be signed off, each standard cell in the second standard cell library having its own 2D process angle timing parameters, the 2D process angle timing parameters including: an average delay of each standard cell under 2D conditions and a local standard deviation of the delay of the standard cell under 2D conditions; determining an average delay of the standard cell under the 3D process angle according to the average delay of each standard cell under 2D conditions to obtain a first average delay, and determining a standard deviation of the delay of the standard cell under the 3D process angle according to the local standard deviation of the delay of each standard cell under 2D conditions to obtain a first standard deviation; configuring each of the first average delays and each of the first standard deviations to the second standard cell library to form the first standard cell library.

[0008] In one embodiment, determining the average delay of the standard unit under the 3-dimensional process angle according to the average delay of each standard unit under 2-dimensional conditions to obtain the first average delay includes: determining the average delay of the standard unit under the 3-dimensional process angle according to the average delay of each standard unit under the typical process angle under 2-dimensional conditions to obtain the first average delay.

[0009] In one embodiment, determining the standard deviation of the delay of each standard unit under the 3-dimensional process angle according to the local standard deviation of the delay of each standard unit under the 2-dimensional condition to obtain the first standard deviation includes: determining the total standard deviation of the delay of each device in each grain in the chip to be signed and the local standard deviation of the delay of the device through a device model provided by the wafer factory or through simulation; determining the standard deviation expansion coefficient of the device according to the total standard deviation of the delay of each device and the local standard deviation of the delay of the device; determining the standard deviation of the delay of the standard unit under the 3-dimensional process angle according to the local standard deviation of the delay of each standard unit under the 2-dimensional condition and the standard deviation expansion coefficient of the device corresponding to the standard unit, to obtain the first standard deviation.

[0010] In one embodiment, the standard deviation expansion coefficient of each of the devices is equal to the ratio of the total standard deviation of the delay of the device to the local standard deviation of the delay of the device; the first standard deviation of each of the standard units is equal to the product of the local standard deviation of the delay of the standard unit under 2D conditions and the standard deviation expansion coefficient of the device corresponding to the standard unit.

[0011] In one embodiment, the use of the first standard cell library to perform timing sign-off on the chip to be signed includes: determining a delay parameter of a first section of a target path in the chip to be signed based on the first standard cell library, and determining a delay parameter of a second section of the target path based on a metal wire delay model, wherein the first section is a portion of the target path located inside each grain, and the second section is a portion of the target path located between adjacent grains; determining a delay parameter of the target path based on the delay parameter of the first section and the delay parameter of the second section; and determining whether the target path is signed off based on whether the delay parameter of the target path is within a preset parameter range.

[0012] In one embodiment, the delay parameters of the first section include the average delay of the first section and the standard deviation of the delay of the first section; the delay parameters of the second section include the average delay of the second section and the standard deviation of the delay of the second section; determining the delay parameters of the target path based on the delay parameters of the first section and the delay parameters of the second section includes: adding the average delay of each of the first sections and the average delay of each of the second sections to obtain the average delay of the target path; adding the sum of the squares of the standard deviations of the delays of each of the first sections and the sum of the squares of the standard deviations of the delays of each of the second sections, and taking the arithmetic square root of the sum to obtain the standard deviation of the delay of the target path.

[0013] In a second aspect, an embodiment of the present invention further provides a timing sign-off device, comprising: a first acquisition unit, used to acquire a first standard cell library corresponding to each grain in a chip to be signed off, each standard cell in the first standard cell library having its own 3D process angle timing parameter, the 3D process angle timing parameter comprising an average delay of each of the standard cells under the 3D process angle and a standard deviation of the delay of the standard cell under the 3D process angle; wherein the chip to be signed off is obtained by 3D integration of at least two grains; a sign-off unit, used to perform timing sign-off on the chip to be signed off using the first standard cell library.

[0014] In one embodiment, the device further includes: a second acquisition unit, used to acquire a second standard cell library corresponding to each die in the chip to be signed off before acquiring the first standard cell library corresponding to each die in the chip to be signed off, each standard cell in the second standard cell library having its own 2D process angle timing parameters, the 2D process angle timing parameters including: an average delay of each standard cell under 2D conditions and a local standard deviation of the delay of the standard cell under 2D conditions; a determination unit, used to determine the average delay of the standard cell under the 3D process angle according to the average delay of each standard cell under 2D conditions to obtain a first average delay, and determine the standard deviation of the delay of the standard cell under the 3D process angle according to the local standard deviation of the delay of each standard cell under 2D conditions to obtain a first standard deviation; a configuration unit, used to configure each of the first average delays and each of the first standard deviations to the second standard cell library to form the first standard cell library.

[0015] In one embodiment, the determining unit includes a first determining module, configured to determine the average delay of each standard cell under the 3D process angle according to the average delay of a typical process angle under 2D conditions, to obtain the first average delay.

[0016] In one embodiment, the determination unit includes a second determination module, which is used to: determine the total standard deviation of the delay of each device in each grain in the chip to be signed and the local standard deviation of the delay of the device through a device model provided by the wafer factory or through simulation; determine the standard deviation expansion coefficient of the device according to the total standard deviation of the delay of each device and the local standard deviation of the delay of the device; determine the standard deviation of the delay of the standard unit under the 3D process angle according to the local standard deviation of the delay of each standard unit under 2D conditions and the standard deviation expansion coefficient of the device corresponding to the standard unit, and obtain the first standard deviation.

[0017] In one embodiment, the standard deviation expansion coefficient of each of the devices is equal to the ratio of the total standard deviation of the delay of the device to the local standard deviation of the delay of the device; the first standard deviation of each of the standard units is equal to the product of the local standard deviation of the delay of the standard unit under 2D conditions and the standard deviation expansion coefficient of the device corresponding to the standard unit.

[0018] In one embodiment, the sign-off unit includes: a third determination module, used to determine the delay parameter of the first section of the target path in the chip to be signed off based on the first standard cell library, and determine the delay parameter of the second section of the target path based on the metal wire delay model, wherein the first section is the portion of the target path located inside each grain, and the second section is the portion of the target path located between adjacent grains; a fourth determination module, used to determine the delay parameter of the target path according to the delay parameter of the first section and the delay parameter of the second section; a fifth determination module, used to determine whether the target path is signed off according to whether the delay parameter of the target path is within a preset parameter range.

[0019] In one embodiment, the delay parameters of the first section include the average delay of the first section and the standard deviation of the delay of the first section; the delay parameters of the second section include the average delay of the second section and the standard deviation of the delay of the second section; the fourth determination module is specifically used to: add the average delay of each of the first sections and the average delay of each of the second sections to obtain the average delay of the target path; add the sum of the squares of the standard deviations of the delays of each of the first sections and the sum of the squares of the standard deviations of the delays of each of the second sections, and take the arithmetic square root of the sum to obtain the standard deviation of the delay of the target path.

[0020] In a third aspect, an embodiment of the present invention further provides an electronic device, comprising: a processor and a memory, wherein the processor is electrically connected to the memory; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to implement any one of the timing sign-off methods provided in the embodiments of the present invention.

[0021] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the timing sign-off method provided in any embodiment of the present invention.

[0022] The timing sign-off method and device, electronic device, and storage medium provided by the embodiments of the present invention can obtain the first standard cell library corresponding to each die in the chip to be signed off, and use the first standard cell library to perform timing sign-off on the chip to be signed off. Since the chip to be signed is obtained by 3D integration of at least two grains, and in the first standard cell library corresponding to each grain, each standard cell has its own 3D process angle timing parameters, and the 3D process angle timing parameters include the average delay of each standard cell under the 3D process angle and the standard deviation of the delay of the standard cell under the 3D process angle, therefore, when performing timing sign-off on the chip to be signed, the 3D process angle timing parameters of each standard cell can be directly used for timing sign-off. Since the 3D process angle timing parameters are timing parameters under the process angle specially customized for the 3D integration situation, they can be closer to the 3D integration application scenario, without the need to use the 2D sign-off process angle of each grain for various combinations as in the prior art, which leads to overly pessimistic and complex sign-off, thereby effectively reducing the pessimism and complexity of the timing sign-off of the 3D integrated chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 A flow chart of a timing sign-off method provided by an embodiment of the present invention;

[0025] Figure 2 A schematic diagram showing the relationship between different standard deviations in an embodiment of the present invention;

[0026] Figure 3 A flow chart of performing timing sign-off on a chip to be signed off in an embodiment of the present invention;

[0027] Figure 4 A detailed flow chart of a timing sign-off method provided by an embodiment of the present invention;

[0028] Figure 5 A schematic diagram of the structure of a timing sign-off device provided by an embodiment of the present invention;

[0029] Figure 6 A schematic structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0030] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0031] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] In a first aspect, an embodiment of the present invention provides a timing sign-off method, which can effectively reduce the pessimism and complexity of timing sign-off of a 3D integrated chip.

[0033] like Figure 1 As shown, an embodiment of the present invention provides a timing sign-off method, comprising:

[0034] S11, obtaining a first standard cell library corresponding to each die in the chip to be signed off, wherein each standard cell in the first standard cell library has its own 3D process angle timing parameter, and the 3D process angle timing parameter includes an average delay of each standard cell under the 3D process angle and a standard deviation of the delay of the standard cell under the 3D process angle; wherein the chip to be signed off is obtained by 3D integration of at least two die;

[0035] In an embodiment of the present invention, the chip to be signed off is a chip that needs to be signed off on a timing basis. The chip to be signed off may include at least two crystal grains, which may be integrated together in a 3D manner, for example, electrical interconnection between different crystal grains may be achieved through through silicon vias (TSV), hybrid bonding, etc. It should be noted that in an embodiment of the present invention, 3D integration is a broad concept, which may generally refer to 2.5D integration, 3D integration, 3.5D integration, etc.

[0036] Each die of the chip to be signed can include many different devices. When designing the circuit, these devices can be implemented by different standard cells in the first standard cell library. Devices in different die can be designed using the same first standard cell library or different first standard cell libraries. In an embodiment of the present invention, the first standard cell library is different from the traditional standard cell library suitable for 2D chip scenarios in that at least each standard cell in the first standard cell library has its own 3D process angle timing parameters, and the 3D process angle timing parameters include the average delay of each standard cell under the 3D process angle and the standard deviation of the delay of the standard cell under the 3D process angle. Here, the 3D process angle may refer to the process angle corresponding to the die in the case of three-dimensional integration, the delay may refer to the time taken for the signal to be transmitted on a preset path in the chip to be signed, the average delay may refer to the average value of the time, and the standard deviation of the delay may refer to the standard deviation of the time.

[0037] Specifically, for chips in 2D scenarios, the standard cell library generally contains timing parameters of standard cells in various process corners of 2D scenarios, such as the delay of FFG (fast N fast P Global, fast N-type transistor fast P-type transistor global deviation point) process corner is 20 nanoseconds, SSG (slow N slow P Global, slow N-type transistor slow P-type transistor global deviation point) process corner is 45 nanoseconds, etc., so it is very convenient to sign off on chips in 2D scenarios. However, if such a standard cell library is used to sign off on 3D integrated chips, problems such as increased pessimism and overly complex sign-off will be encountered. To this end, in this step, the first standard cell library corresponding to each die in the chip to be signed off can be obtained, and each standard cell in the first standard cell library has its own 3D process corner timing parameters, and the 3D process corner timing parameters include the average delay of each standard cell in the 3D process corner and the standard deviation of the delay of the standard cell in the 3D process corner, so as to use the 3D process corner timing parameters in the first standard cell library to sign off on the chip to be signed off.

[0038] S12: Performing a timing sign-off on the chip to be signed off by using the first standard cell library.

[0039] After obtaining the first standard cell library, the first standard cell library can be used to perform timing check on the chip to be checked. The first standard cell library is used to perform timing check on the chip to be checked, that is, the timing parameters of the standard cells in the first standard cell library are used to calculate whether the delay of each path in the chip to be checked meets the requirements, for example, whether it is within a preset range. In this way, the timing analysis of the 3D integrated chip across the die is converted into a statistical analysis based on the 3D integrated process angle (Statistical On 3DIC Variation).

[0040] The timing sign-off method provided by the embodiment of the present invention can obtain the first standard cell library corresponding to each die in the chip to be signed off, and use the first standard cell library to perform timing sign-off on the chip to be signed off. Since the chip to be signed off is obtained by 3D integration of at least two die, and each standard cell in the first standard cell library corresponding to each die has its own 3D process angle timing parameter, and the 3D process angle timing parameter includes the average delay of each standard cell under the 3D process angle and the standard deviation of the delay of the standard cell under the 3D process angle, therefore, when performing timing sign-off on the chip to be signed off, the 3D process angle timing parameter of each standard cell can be directly used for timing sign-off, and since the 3D process angle timing parameter is a timing parameter under a process angle specially customized for the 3D integration situation, it can be closer to the 3D integration application scenario, without using the 2D sign-off process angle of each die for various combinations as in the prior art, which leads to overly pessimistic and complex sign-off, thereby effectively reducing the pessimism and complexity of the timing sign-off of the 3D integrated chip.

[0041] Specifically, in one embodiment of the present invention, in order to use the first standard cell library for timing sign-off, the first standard cell library can be established first. For example, before obtaining the first standard cell library corresponding to each die in the chip to be signed off in step S11, the timing sign-off method provided by the embodiment of the present invention can also include: obtaining the second standard cell library corresponding to each die in the chip to be signed off, each standard cell in the second standard cell library has its own 2D process angle timing parameters, and the 2D process angle timing parameters include: the average delay of each standard cell under 2D conditions and the local standard deviation of the delay of the standard cell under 2D conditions; according to the average delay of each standard cell under 2D conditions, determine the average delay of the standard cell under the 3D process angle to obtain a first average delay, and according to the local standard deviation of the delay of each standard cell under 2D conditions, determine the standard deviation of the delay of the standard cell under the 3D process angle to obtain a first standard deviation; configure each of the first average delays and each of the first standard deviations to the second standard cell library to form the first standard cell library.

[0042] That is to say, in this embodiment, the 3D process corner timing parameters of each standard cell in the first standard cell library can be obtained based on the 2D process corner timing parameters of the standard cell. The 2D process corner timing parameters can specifically include: the average delay of each standard cell under 2D conditions and the local standard deviation of the delay of the standard cell under 2D conditions.

[0043] The average delay here may refer to the average value of any delay parameter of the standard cell, such as the average value of the arrival time of the signal from point A of the standard cell to point B of the standard cell, the average value of the establishment time of the signal at point B of the standard cell, or the average value of the retention time of the signal at point B of the standard cell, etc. Optionally, the 2D process angle may include multiple types, such as FF process angle, TT process angle, SS process angle, etc. The average delay may have different values ​​under different process angles, for example, the average delay under the FF process angle may be relatively small, while the average delay under the SS process angle may be relatively large.

[0044] In a specific implementation, determining the average delay of the standard unit at the 3-dimensional process angle according to the average delay of each standard unit under 2-dimensional conditions, and obtaining the first average delay may include: determining the average delay of the standard unit at the 3-dimensional process angle according to the average delay of each standard unit at the typical process angle under 2-dimensional conditions, and obtaining the first average delay. That is to say, in an embodiment of the present invention, the average delay of the typical process angle under 2-dimensional conditions can be used as the average delay under the 3-dimensional process angle. For example, in one example, in the standard unit A1, the average delay of the arrival time from point P1 to point P2 at the typical process angle under 2-dimensional conditions is 56 nanoseconds, then it can be determined that the average delay of the arrival time of the standard unit A1 from point P1 to point P2 at the 3-dimensional process angle is also 56 nanoseconds.

[0045] In this embodiment, the average value of typical process corners of the standard cell under 2D conditions is used as the average delay of the standard cell under 3D process corners, but the embodiments of the present invention are not limited thereto. In other embodiments of the present invention, the average delay of the standard cell at the 3D process corner can also be determined based on the average delay of other process corners of the standard cell under 2D conditions as needed. For example, in one example, the average delay t3 of the standard cell at the 3D process corner can also be determined based on the average delay t1 of the FF process corner and / or the average delay t2 of the SS process corner of the standard cell under 2D conditions (for example, t3=(t1+t2) / 2). The embodiments of the present invention are not limited thereto.

[0046] The above introduces the average delay. The following will continue to introduce the local standard deviation of the delay.

[0047] In an embodiment of the present invention, the local standard deviation of the delay may refer to the standard deviation of any delay parameter of the standard cell, such as the standard deviation of the arrival time of the signal from point A to point B, the standard deviation of the establishment time of the signal at point A, etc. In one example, according to the local standard deviation of the delay of each standard cell under the 2D condition, the standard deviation of the delay of the standard cell under the 3D process angle is determined, and obtaining the first standard deviation may include: determining the total standard deviation of the delay of each device in each die in the chip to be signed and the local standard deviation of the delay of the device through the device model provided by the wafer factory or through simulation; determining the standard deviation expansion coefficient of the device according to the total standard deviation of the delay of each device and the local standard deviation of the delay of the device; determining the standard deviation of the delay of the standard cell under the 3D process angle according to the local standard deviation of the delay of each standard cell under the 2D condition and the standard deviation expansion coefficient of the device corresponding to the standard cell, and obtaining the first standard deviation.

[0048] In one embodiment of the present invention, the device model provided by the foundry may be a spice model. In the chip to be signed, various devices in each die have their own corresponding device models, and the total standard deviation and local standard deviation of the delay of the corresponding device can be determined according to the device model. In another embodiment of the present invention, various devices in the die may also be simulated to determine the total standard deviation and local standard deviation of the delay of each device.

[0049] Furthermore, the standard deviation expansion coefficient of the device can be determined based on the total standard deviation of the delay of each of the devices and the local standard deviation of the delay of the device. In one example, the standard deviation expansion coefficient of each device can be equal to the ratio of the total standard deviation of the delay of the device to the local standard deviation of the delay of the device; based on this, the first standard deviation of each standard unit can be equal to the product of the local standard deviation of the delay of the standard unit under 2D conditions and the standard deviation expansion coefficient of the device corresponding to the standard unit. Exemplarily, the relationship between the delay standard deviation (i.e., the first standard deviation), the total standard deviation of the device delay, and the local standard deviation of the device delay under the 3D process angle can be as follows: Figure 2 As shown in the figure, TT is the delay under the typical process corner, FF is the delay under the fast N fast P process corner, and SS is the delay under the slow N slow P process corner. Figure 2 It can be seen that after the ellipse representing the local standard deviation of the device delay is enlarged by a certain multiple (the enlargement multiple is determined by the standard deviation expansion coefficient), the ellipse representing the delay standard deviation under the 3D process angle is obtained.

[0050] For example, in one embodiment of the present invention, according to the device model provided by the wafer factory, for the inverter inv1 in the grain, the total standard deviation of the transmission delay from the input end to the output end is a, and the local standard deviation is b, then the standard deviation expansion coefficient of the transmission delay from the input end to the output end of the inverter inv1 is k=a / b. Based on this, the first standard deviation of the standard unit corresponding to the inverter inv1 can be equal to the product (k×c) of the local standard deviation of the delay of the standard unit under 2D conditions (for example, c) and the standard deviation expansion coefficient of the device corresponding to the standard unit (for example, k), that is, the first standard deviation is equal to k×c.

[0051] After obtaining the first average delay and the first standard deviation, the first average value and the first standard deviation can be added to the standard cell corresponding to the second standard cell library, thereby forming a first standard cell library. Based on this, in step S11, the first standard cell library corresponding to each die in the chip to be signed off can be obtained, and further in step S12, the first standard cell library can be used to perform timing sign-off on the chip to be signed off.

[0052] In one embodiment of the present invention, the first standard cell library is used to perform timing sign-off on the chip to be signed, that is, the timing parameters in the first standard cell library are used to calculate whether the delay parameters of each path in the chip to be signed are within a preset parameter range. Each path may include one or more standard cells, and the delay parameters of each path may be determined by the delay parameters of each standard cell on the path.

[0053] In one example, each path in the chip to be signed off may include a section inside a die and a section between dies, and the delay parameter of the path may be obtained based on the delay parameters of these two sections.

[0054] Specifically, in one embodiment of the present invention, using the first standard cell library to perform timing sign-off on the chip to be signed off may include: determining the delay parameters of a first section of the target path in the chip to be signed off based on the first standard cell library, and determining the delay parameters of a second section of the target path based on a metal wire delay model, wherein the first section is the portion of the target path located inside each grain, and the second section is the portion of the target path located between adjacent grains; determining the delay parameters of the target path based on the delay parameters of the first section and the delay parameters of the second section; and determining whether the target path is signed off based on whether the delay parameters of the target path are within a preset parameter range.

[0055] The target path may be any path in the chip to be signed that needs to be signed for timing. The target path may involve all the grains in the chip to be signed, or may only involve a part of the grains in the chip to be signed, and the embodiments of the present invention are not limited to this. For example, in one example, the chip to be signed may include grain die1, grain die2, and grain die3, and the target path 1 may run through die1, die2, and die3, that is, the target path 1 involves 3 grains in the chip to be signed, and the target path 2 may run through die1 and die2, that is, the target path 2 involves 2 grains in the chip to be signed.

[0056] In the case where the target path involves two or more dies in the chip to be signed, the target path may include two sections, namely a first section and a second section, wherein the first section may refer to the portion of the target path located inside each die, for example, the portion of the target path located in die1 is one first section, and the portion located in die2 is another first section; the second section may refer to the portion of the target path located between adjacent dies, for example, the portion interconnecting die1 and die2.

[0057] In one embodiment of the present invention, when the target path is signed for timing, the first section and the second section can respectively calculate the delay parameters in different ways. Specifically, since the first section refers to the portion of the target path located inside each crystal grain, the delay parameters of the first section can be calculated based on the standard cells in the first standard cell library corresponding to the crystal grain; since the second section refers to the portion of the target path between adjacent crystal grains, and the delay of this part of the path is mostly caused by the resistance and capacitance of the metal wire, the delay parameters of the second section can be calculated based on the metal wire delay model.

[0058] After obtaining the delay parameters of the first section and the delay parameters of the second section, the delay parameters of the target path can be determined according to the delay parameters of the first section and the delay parameters of the second section. Specifically, in one embodiment of the present invention, the delay parameters of the first section may include the average delay of the first section and the standard deviation of the delay of the first section; the delay parameters of the second section may include the average delay of the second section and the standard deviation of the delay of the second section; based on this, determining the delay parameters of the target path according to the delay parameters of the first section and the delay parameters of the second section may specifically include: adding the average delay of each of the first sections and the average delay of each of the second sections to obtain the average delay of the target path; adding the sum of the squares of the standard deviations of the delays of each of the first sections and the sum of the squares of the standard deviations of the delays of each of the second sections, taking the arithmetic square root of the sum, and obtaining the standard deviation of the delay of the target path.

[0059] For example, in one embodiment of the present invention, the chip to be signed includes die0 and die1, and die0 and die1 are 3D integrated by hybrid bonding or the like to obtain the chip to be signed. Figure 3 As shown, when signing the chip to be signed, the corresponding first standard cell library can be linked to the die0 and the die1 respectively to obtain the netlist, design constraints, parasitic parameters and other information of the path to be signed in the die0 and the die1. For the path to be signed between the inter-die interconnection between the die0 and the die1, the corresponding standard delay format file can be obtained. Furthermore, the delay parameters of each standard cell in the path to be signed in the die0 and the die1 and the delay parameters of the path to be signed between the inter-die interconnection can be obtained, wherein each delay parameter is a delay parameter suitable for a 3D integrated chip obtained after the aforementioned coefficient processing, and then the timing analysis of the chip to be signed can be performed.

[0060] The following compares the signing method provided by the embodiment of the present invention with the signing method in the prior art.

[0061] Existing technical solutions

[0062] The chip to be signed is composed of three dies stacked together. The voltage and temperature conditions of the three dies are consistent and the clocks across the dies are synchronized.

[0063] TTG delay = 100ps (picosecond), FFG delay = 85ps, SSG delay = 115ps; Localvariation sigma = 5ps.

[0064] Among them, TTG delay is the average arrival time of the target path section located in each die under the typical process angle; FFG delay is the average arrival time of the target path section located in each die under the fast N fast P process angle; SSG delay is the average arrival time of the target path section located in each die under the slow N slow P process angle.

[0065] Using a solution combining global corner and local variation, if the global corners of the three dies in the chip to be signed off are all typical corners (TTG), then the global corner combination of the three dies is TTG+TTG+TTG. Under this combination of corners, the timing parameters are as follows:

[0066] Path arrival mean=delay_die0+delay_die1 + delay_die2 =100+100+100=300 (ps)

[0067] Path arrival sigma = ≈8.5ps

[0068] Path arrival mean is the average arrival time of the target path in the chip to be signed off (i.e., passing through the three dies of the chip to be signed off), and Path arrival sigma is the standard deviation of the arrival time of the target path in the chip to be signed off.

[0069] Similarly, the timing parameters of the three dies under other process corner combinations can be calculated, as shown in Table 1.

[0070]

[0071] As can be seen from Table 1, the process corner combinations of the three dies can include 3×3×3=27, that is, the number of process corners for sign-off is 27. For the three dies in various process corner combinations, the minimum path arrival time allowed under 3 times the standard deviation occurs in the FFG+FFG+FFG process corner combination, specifically 255-8.5×3=229.5 (see the × in Table 1), and the maximum path arrival time allowed under 3 times the standard deviation occurs in the SSG+SSG+SSG process corner combination, specifically 345+8.5×3=370.5 (see the × in Table 1). The difference between the two is 370.5-229.5=141, which covers a large range, but the probability of occurrence of actual extreme scenarios is very low, so signing in this way will be pessimistic.

[0072] Solutions of the embodiments of the present invention

[0073] In one embodiment of the present invention, the chip to be signed can be signed based on the 3D process angle. In this sign-off scenario, the sign-off process angle combination of each die corresponding to the 3D process angle is a combination of TTG+TTG+TTG. Therefore, the number of sign-off process angle combinations is 1, which is much smaller than the 27 sign-off process angle condition combinations in the prior art, thereby effectively reducing the complexity of the 3D integrated chip timing sign-off.

[0074] Optionally, during the sign-off, if only the average delay and standard deviation of the target path within the die are considered, and the average delay and standard deviation of the delay of the target path between the die are not considered, the standard deviation of the delay of the target path in each die and under the 3D process angle (i.e., the standard deviation of the delay of each first section in the target path) can be determined based on the standard deviation of the delay of each standard unit in each die in the chip to be signed off under the 3D process angle (e.g., the standard deviation of the arrival time). For example, the standard deviation of the delay of the target path in each die and under the 3D process angle is 10.

[0075] Then, Path arrival mean=delay_die0+delay_die1 + delay_die2 =100+100+100=300 (ps)

[0076] Path arrival sigma = ≈17 (ps)

[0077] Path arrival mean is the average arrival time of the target path in the chip to be signed off (i.e., passing through the three dies of the chip to be signed off), and Path arrival sigma is the standard deviation of the arrival time of the target path in the chip to be signed off.

[0078] It can be seen that the minimum target path arrival time allowed under 3 times the standard deviation is 300-17×3=249, and the maximum target path arrival time allowed under 3 times the standard deviation is 300+17×3=351. The difference between the two is 351-249=102ps, which is much smaller than 141 in the prior art solution. Therefore, pessimism can be effectively reduced. The timing parameters can be specifically shown in Table 2.

[0079]

[0080] In another embodiment of the present invention, if the average delay and standard deviation of the delay of the target path between the dies are considered, in addition to determining the average delay and standard deviation of the delay of the first section as in the above embodiment, the average delay and standard deviation of the delay of the portion of the target path between the dies in the chip to be signed off (i.e., the average delay and standard deviation of the delay of each second section of the target path) can be further determined. For example, in one example, the average delay of the portion of the target path between the dies is 10, and the standard deviation of the delay is 5.

[0081] The following conclusions are drawn:

[0082] Path arrival mean=delay_die0+delay_0-1+delay_die1+delay_1-2+ delay_die2

[0083] =100+10+100+10+100=320 (ps)

[0084] Path arrival sigma = ≈18.7 (ps)

[0085] The timing sign-off method provided by the embodiment of the present invention is described in detail below through a specific embodiment.

[0086] like Figure 4 As shown, the timing sign-off method provided by the embodiment of the present invention may include:

[0087] S201. Obtain a second standard cell library corresponding to each die in the chip to be signed, where each standard cell in the second standard cell library has its own 2D process corner timing parameters, and the 2D process corner timing parameters include: an average delay of each standard cell under 2D conditions and a local standard deviation of the delay of the standard cell under 2D conditions.

[0088] S202 , determining the average delay of each standard cell under a 3D process corner according to the average delay of a typical process corner under a 2D condition, and obtaining a first average delay.

[0089] S203 , determining the total standard deviation of the delay of each device in each die in the chip to be signed off and the local standard deviation of the delay of the device through a device model provided by the wafer factory or through simulation.

[0090] S204 , determining a standard deviation expansion coefficient of each device according to the total standard deviation of the delay of the device and the local standard deviation of the delay of the device.

[0091] S205 , determining the standard deviation of the delay of each standard cell under a 3D process angle according to the local standard deviation of the delay of each standard cell under a 2D condition and the standard deviation expansion coefficient of the device corresponding to the standard cell, to obtain a first standard deviation.

[0092] S206 , configuring each first average delay and each first standard deviation to a second standard cell library to form a first standard cell library.

[0093] S207. Determine a delay parameter of a first section of a target path in the chip to be signed based on the first standard cell library, and determine a delay parameter of a second section of the target path based on a metal line delay model, wherein the first section is a portion of the target path located inside each grain, and the second section is a portion of the target path located between adjacent grains.

[0094] S208: Determine the delay parameter of the target path according to the delay parameter of the first section and the delay parameter of the second section.

[0095] Exemplarily, the average delay of each first section and the average delay of each second section can be added to obtain the average delay of the target path, and the sum of the squares of the standard deviations of the delays of each first section and the sum of the squares of the standard deviations of the delays of each second section can be added, and the square root of the sum is calculated to obtain the standard deviation of the delay of the target path.

[0096] S209: Determine whether the target path is approved based on whether the delay parameter of the target path is within a preset parameter range.

[0097] In a second aspect, an embodiment of the present invention provides a timing sign-off apparatus, which can effectively reduce the pessimism and complexity of timing sign-off of a 3D integrated chip.

[0098] like Figure 5 As shown, an embodiment of the present invention further provides a timing sign-off device, comprising:

[0099] A first acquisition unit 31 is used to acquire a first standard cell library corresponding to each die in the chip to be signed off, each standard cell in the first standard cell library has its own 3D process angle timing parameter, and the 3D process angle timing parameter includes an average delay of each standard cell under the 3D process angle and a standard deviation of the delay of the standard cell under the 3D process angle; wherein the chip to be signed off is obtained by 3D integration of at least two die;

[0100] The sign-off unit 32 is used to perform a timing sign-off on the chip to be signed off by using the first standard cell library.

[0101] The timing sign-off device provided by the embodiment of the present invention can obtain the first standard cell library corresponding to each die in the chip to be signed off, and use the first standard cell library to perform timing sign-off on the chip to be signed off. Since the chip to be signed off is obtained by 3D integration of at least two die, and each standard cell in the first standard cell library corresponding to each die has its own 3D process angle timing parameter, and the 3D process angle timing parameter includes the average delay of each standard cell under the 3D process angle and the standard deviation of the delay of the standard cell under the 3D process angle, therefore, when performing timing sign-off on the chip to be signed off, the 3D process angle timing parameter of each standard cell can be directly used for timing sign-off, and since the 3D process angle timing parameter is a timing parameter under a process angle specially customized for the 3D integration situation, it can be closer to the 3D integration application scenario, without using the 2D sign-off process angle of each die for various combinations as in the prior art, resulting in overly pessimistic and complex sign-off, thereby effectively reducing the pessimism and complexity of the timing sign-off of the 3D integrated chip.

[0102] In one implementation, the timing sign-off apparatus provided by the embodiment of the present invention may further include:

[0103] A second acquisition unit is used to acquire a second standard cell library corresponding to each die in the chip to be signed before acquiring the first standard cell library corresponding to each die in the chip to be signed, wherein each standard cell in the second standard cell library has its own 2D process angle timing parameter, and the 2D process angle timing parameter includes: an average delay of each standard cell under 2D conditions and a local standard deviation of the delay of the standard cell under 2D conditions;

[0104] A determination unit, configured to determine the average delay of each standard cell under the 3D process angle according to the average delay of each standard cell under the 2D condition, to obtain a first average delay, and to determine the standard deviation of the delay of each standard cell under the 3D process angle according to the local standard deviation of the delay of each standard cell under the 2D condition, to obtain a first standard deviation;

[0105] A configuration unit is used to configure each of the first average delays and each of the first standard deviations to the second standard cell library to form the first standard cell library.

[0106] In one embodiment, the determining unit includes a first determining module, configured to determine the average delay of each standard cell under the 3D process angle according to the average delay of a typical process angle under 2D conditions, to obtain the first average delay.

[0107] In one embodiment, the determining unit includes a second determining module, configured to:

[0108] Determine the total standard deviation of the delay of each device in each die in the chip to be signed off and the local standard deviation of the delay of the device through a device model provided by a wafer factory or through simulation;

[0109] Determining a standard deviation expansion coefficient of each device according to a total standard deviation of the delay of the device and a local standard deviation of the delay of the device;

[0110] According to the local standard deviation of the delay of each standard cell under 2D conditions and the standard deviation expansion coefficient of the device corresponding to the standard cell, the standard deviation of the delay of the standard cell under the 3D process angle is determined to obtain the first standard deviation.

[0111] In one embodiment, the standard deviation expansion coefficient of each of the devices is equal to the ratio of the total standard deviation of the delay of the device to the local standard deviation of the delay of the device; the first standard deviation of each of the standard units is equal to the product of the local standard deviation of the delay of the standard unit under 2D conditions and the standard deviation expansion coefficient of the device corresponding to the standard unit.

[0112] In one implementation, the sign-off unit 31 includes:

[0113] a third determination module, configured to determine a delay parameter of a first section of a target path in the chip to be signed off based on the first standard cell library, and to determine a delay parameter of a second section of the target path based on a metal line delay model, wherein the first section is a portion of the target path located inside each crystal grain, and the second section is a portion of the target path located between adjacent crystal grains;

[0114] a fourth determining module, configured to determine a delay parameter of the target path according to the delay parameter of the first section and the delay parameter of the second section;

[0115] The fifth determination module is used to determine whether the target path is approved according to whether the delay parameter of the target path is within a preset parameter range.

[0116] In one embodiment, the delay parameters of the first section include the average delay of the first section and the standard deviation of the delay of the first section; the delay parameters of the second section include the average delay of the second section and the standard deviation of the delay of the second section; the fourth determination module is specifically used to: add the average delay of each of the first sections and the average delay of each of the second sections to obtain the average delay of the target path; add the sum of the squares of the standard deviations of the delays of each of the first sections and the sum of the squares of the standard deviations of the delays of each of the second sections, and take the arithmetic square root of the sum to obtain the standard deviation of the delay of the target path.

[0117] In a third aspect, an embodiment of the present invention further provides an electronic device that can effectively reduce the pessimism and complexity of timing sign-off of a 3D integrated chip.

[0118] like Figure 6 As shown, the electronic device provided by the embodiment of the present invention may include: a processor 51 and a memory 52, wherein the processor 51 is electrically connected to the memory 52; the memory 52 is used to store executable program codes; the processor 51 runs a program corresponding to the executable program code by reading the executable program code stored in the memory 52, so as to implement any one of the timing sign-off methods provided by the embodiment of the present invention.

[0119] The specific execution process of the above steps by the processor 51 and the steps further executed by the processor 51 by running the executable program code can be found in the description of the above embodiment, which will not be repeated here.

[0120] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, which stores one or more programs, and the one or more programs can be executed by one or more processors to implement any one of the timing sign-off methods provided in the aforementioned embodiments, thereby also achieving the corresponding technical effects, which have been described in detail above and will not be repeated here.

[0121] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0122] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0123] In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0124] For the convenience of description, the above device is described by dividing the functions into various units / modules. Of course, when implementing the present invention, the functions of each unit / module can be implemented in the same or multiple software and / or hardware.

[0125] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0126] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A timing sign-off method, characterized in that: include: Obtaining a first standard cell library corresponding to each die in the chip to be signed off, wherein each standard cell in the first standard cell library has its own 3D process angle timing parameter, and the 3D process angle timing parameter includes an average delay of each standard cell under the 3D process angle and a standard deviation of the delay of the standard cell under the 3D process angle; wherein the chip to be signed off is obtained by 3D integration of at least two die; The first standard cell library is used to perform timing sign-off on the chip to be signed off.

2. The method according to claim 1, characterized in that Before obtaining the first standard cell library corresponding to each die in the chip to be signed, the method further includes: Acquire a second standard cell library corresponding to each die in the chip to be signed, wherein each standard cell in the second standard cell library has its own 2D process corner timing parameter, and the 2D process corner timing parameter includes: an average delay of each standard cell under 2D conditions and a local standard deviation of the delay of the standard cell under 2D conditions; According to the average delay of each of the standard cells under the 2D condition, the average delay of the standard cell under the 3D process angle is determined to obtain a first average delay, and according to the local standard deviation of the delay of each of the standard cells under the 2D condition, the standard deviation of the delay of the standard cell under the 3D process angle is determined to obtain a first standard deviation; The first average delays and the first standard deviations are configured to the second standard cell library to form the first standard cell library.

3. The method according to claim 2, characterized in that Determining the average delay of each standard unit under the 3D process angle according to the average delay of each standard unit under the 2D condition to obtain the first average delay includes: According to the average delay of each of the standard cells at a typical process corner under a 2D condition, the average delay of the standard cell at the 3D process corner is determined to obtain the first average delay.

4. The method according to claim 2, characterized in that: Determining the standard deviation of the delay of each standard unit under the 3D process angle according to the local standard deviation of the delay of each standard unit under the 2D condition to obtain the first standard deviation includes: Determine the total standard deviation of the delay of each device in each die in the chip to be signed off and the local standard deviation of the delay of the device through a device model provided by a wafer factory or through simulation; Determining a standard deviation expansion coefficient of each device according to a total standard deviation of the delay of the device and a local standard deviation of the delay of the device; According to the local standard deviation of the delay of each standard cell under 2D conditions and the standard deviation expansion coefficient of the device corresponding to the standard cell, the standard deviation of the delay of the standard cell under the 3D process angle is determined to obtain the first standard deviation.

5. The method according to claim 4, characterized in that The standard deviation expansion coefficient of each device is equal to the ratio of the total standard deviation of the delay of the device to the local standard deviation of the delay of the device; The first standard deviation of each of the standard cells is equal to the product of the local standard deviation of the delay of the standard cell under 2-dimensional conditions and the standard deviation expansion coefficient of the device corresponding to the standard cell.

6. The method according to any one of claims 1 to 5, characterized in that The performing timing sign-off on the chip to be signed off by using the first standard cell library comprises: Determine a delay parameter of a first section of a target path in the chip to be signed off based on the first standard cell library, and determine a delay parameter of a second section of the target path based on a metal line delay model, wherein the first section is a portion of the target path located inside each die, and the second section is a portion of the target path located between adjacent die; Determining the delay parameter of the target path according to the delay parameter of the first section and the delay parameter of the second section; Whether the target path is approved is determined according to whether the delay parameter of the target path is within a preset parameter range.

7. The method according to claim 6, characterized in that The delay parameter of the first section includes an average delay of the first section and a standard deviation of the delay of the first section; the delay parameter of the second section includes an average delay of the second section and a standard deviation of the delay of the second section; The determining the delay parameter of the target path according to the delay parameter of the first section and the delay parameter of the second section includes: Adding the average delay of each of the first sections and the average delay of each of the second sections to obtain the average delay of the target path; The sum of the squares of the standard deviations of the delays of the first sections and the sum of the squares of the standard deviations of the delays of the second sections are added, and the arithmetic square root of the sum is calculated to obtain the standard deviation of the delay of the target path.

8. A timing sign-off device, characterized in that: include: A first acquisition unit is used to acquire a first standard cell library corresponding to each die in the chip to be signed off, each standard cell in the first standard cell library has its own 3D process angle timing parameter, and the 3D process angle timing parameter includes an average delay of each standard cell under the 3D process angle and a standard deviation of the delay of the standard cell under the 3D process angle; wherein the chip to be signed off is obtained by 3D integration of at least two die; A sign-off unit is used to perform a timing sign-off on the chip to be signed by using the first standard cell library.

9. The device according to claim 8, characterized in that Also includes A second acquisition unit is used to acquire a second standard cell library corresponding to each die in the chip to be signed before acquiring the first standard cell library corresponding to each die in the chip to be signed, wherein each standard cell in the second standard cell library has its own 2D process angle timing parameter, and the 2D process angle timing parameter includes: an average delay of each standard cell under 2D conditions and a local standard deviation of the delay of the standard cell under 2D conditions; A determination unit, configured to determine the average delay of each standard cell under the 3D process angle according to the average delay of each standard cell under the 2D condition, to obtain a first average delay, and to determine the standard deviation of the delay of each standard cell under the 3D process angle according to the local standard deviation of the delay of each standard cell under the 2D condition, to obtain a first standard deviation; A configuration unit is used to configure each of the first average delays and each of the first standard deviations to the second standard cell library to form the first standard cell library.

10. The device according to claim 9, characterized in that The determining unit comprises a first determining module, which is used to determine the average delay of the standard cell under the 3D process angle according to the average delay of each standard cell under the typical process angle under the 2D condition, so as to obtain the first average delay.

11. The device according to claim 9, characterized in that The determining unit includes a second determining module, configured to: Determine the total standard deviation of the delay of each device in each die in the chip to be signed off and the local standard deviation of the delay of the device through a device model provided by a wafer factory or through simulation; Determining a standard deviation expansion coefficient of each device according to a total standard deviation of the delay of the device and a local standard deviation of the delay of the device; According to the local standard deviation of the delay of each standard cell under 2D conditions and the standard deviation expansion coefficient of the device corresponding to the standard cell, the standard deviation of the delay of the standard cell under the 3D process angle is determined to obtain the first standard deviation.

12. The device according to claim 11, characterized in that The standard deviation expansion coefficient of each device is equal to the ratio of the total standard deviation of the delay of the device to the local standard deviation of the delay of the device; The first standard deviation of each of the standard cells is equal to the product of the local standard deviation of the delay of the standard cell under 2-dimensional conditions and the standard deviation expansion coefficient of the device corresponding to the standard cell.

13. The device according to any one of claims 8 to 12, characterized in that The sign-off unit comprises: a third determination module, configured to determine a delay parameter of a first section of a target path in the chip to be signed off based on the first standard cell library, and to determine a delay parameter of a second section of the target path based on a metal line delay model, wherein the first section is a portion of the target path located inside each crystal grain, and the second section is a portion of the target path located between adjacent crystal grains; a fourth determining module, configured to determine a delay parameter of the target path according to the delay parameter of the first section and the delay parameter of the second section; The fifth determination module is used to determine whether the target path is approved according to whether the delay parameter of the target path is within a preset parameter range.

14. The device according to claim 13, characterized in that The delay parameter of the first section includes an average delay of the first section and a standard deviation of the delay of the first section; the delay parameter of the second section includes an average delay of the second section and a standard deviation of the delay of the second section; The fourth determining module is specifically used for: Adding the average delay of each of the first sections and the average delay of each of the second sections to obtain the average delay of the target path; The sum of the squares of the standard deviations of the delays of the first sections and the sum of the squares of the standard deviations of the delays of the second sections are added, and the arithmetic square root of the sum is calculated to obtain the standard deviation of the delay of the target path.

15. An electronic device, characterized in that: The electronic device includes: a processor and a memory, wherein the processor is electrically connected to the memory; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to implement the timing sign-off method described in any one of claims 1 to 7.

16. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the timing signoff method according to any one of claims 1 to 7.

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