Non-binary CDAC layout structure and design method for reducing parasitic parameters thereof
By adopting a non-binary CDAC layout structure and virtual capacitor design in the capacitance array of SAR ADC, crosstalk and signal integrity problems caused by parasitic capacitance are solved, and higher accuracy and performance are achieved.
Patent Information
- Application Number
- CN202411560243.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-04
- Publication Date
- 2025-02-25
AI Technical Summary
In SAR ADCs, common capacitor arrays are prone to generate parasitic capacitances, resulting in crosstalk, EMI and signal integrity problems, and the prior art is difficult to effectively reduce these parasitic parameters.
A non-binary CDAC layout structure is proposed. By setting a low-weight distribution area and a high-weight distribution area in the capacitor array, and adding virtual capacitors around it, a capacitor array is formed to reduce the parasitic parameters caused by traces.
It effectively reduces the parasitic parameters between traces, improves the matching accuracy of the capacitor array, meets the requirements for capacitance array accuracy in SAR ADC, and improves overall accuracy and performance.
Smart Images
Figure CN119514469A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuit layout design, and in particular to a non-binary CDAC layout structure and a design method for reducing parasitic parameters thereof. Background Art
[0002] In SAR ADC, capacitor array is a key component. The main function of capacitor array is to convert analog signal into digital signal through sampling and successive approximation process of input analog signal.
[0003] The working principle of the capacitor array is based on the principle of charge redistribution. In the sampling stage, the input analog signal is loaded onto the capacitor array, and the capacitor array stores a charge proportional to the input signal. In the successive approximation stage, by controlling the connection state of each capacitor in the capacitor array, the size of the input analog signal is gradually approximated, and the corresponding digital output is finally determined.
[0004] The capacitor array is composed of multiple capacitors, which can provide a larger total capacitance value, thereby reducing the charge loss during the sampling process. At the same time, by reasonably designing the structure and layout of the capacitor array, the matching between capacitors can be improved, thereby improving the conversion accuracy of the ADC. In common SAR ADCs, parasitic capacitance is easy to generate, especially in high-frequency circuit boards. Parasitic capacitance is easy to cause crosstalk, EMI, signal integrity and other problems, and special treatment is required to reduce its impact. Because it can be seen from this that how to design a capacitor array with low parasitic parameters and matching is particularly important. Summary of the invention
[0005] The present invention aims to solve the technical problems existing in the prior art, and in particular innovatively proposes a non-binary CDAC layout structure and a design method for reducing parasitic parameters, which can effectively reduce parasitics between traces, improve the accuracy of capacitor array matching, and meet the accuracy requirements for capacitor arrays in SAR ADC.
[0006] In order to achieve the above object, the present invention provides a non-binary CDAC layout structure, including a low-weight distribution area and high-weight distribution areas located on the upper and lower sides of the low-weight distribution area, wherein the low-weight distribution area is used to set capacitors with lower weights, and the high-weight distribution area is used to set capacitors with higher weights, and a capacitor array is formed by the capacitors set in the low-weight distribution area and the high-weight distribution area, and a circle of virtual capacitors is set around the capacitor array;
[0007] The unit capacitors in the low-weight distribution area are arranged in an even number of rows, and are arranged horizontally outward from the center point of the capacitor array in order from small to large according to the capacitor weights. The unit capacitors on each weight are symmetrically arranged along the horizontal center line of the capacitor array. If the number of unit capacitors on a certain weight is an odd number, a virtual capacitor is added so that the unit capacitor of the weight and the added virtual capacitor are symmetrically distributed along the horizontal center line of the capacitor array.
[0008] Capacitors with higher weights are set in sequence from small to large according to the capacitance weight, and unit capacitors with the same weight among all capacitors with higher weights are distributed symmetrically in two high-weight distribution areas with the center point of the capacitor array as the origin. When setting capacitors with higher weights, they are set from the side close to the low-weight distribution area to the side away from the low-weight distribution area.
[0009] In the above scheme: the unit capacitor is a mom capacitor.
[0010] In the above solution: the virtual capacitors of adjacent layers are connected to the metal plates on both sides of the unit capacitors adjacent to the virtual capacitors through connecting wires for routing.
[0011] In the above solution: the metal plate connected by the connecting wire is the metal plate of the unit capacitor far away from the upper and lower plates.
[0012] In the above scheme: the upper plates of all unit capacitors are arranged correspondingly to the upper plates, and the lower plates are arranged correspondingly to the lower plates.
[0013] In the above solution: the size and capacitance of the virtual capacitor are all consistent with the size and capacitance of the unit capacitor.
[0014] The present invention also provides a non-binary CDAC layout structure design method for reducing parasitic parameters, comprising the following steps:
[0015] S1: Determine the total number of capacitors, the number of rows and the number of columns of the capacitor array;
[0016] S1-1: Determine the total number of capacitors according to the specific functional requirements of the circuit, and determine the total number of capacitors by calculating the series and parallel relationships of the capacitors and the weight distribution of the capacitors;
[0017] S1-2: Calculate the number of rows of the capacitor array using the following formula:
[0018] NL=round{(C N ) 0.5 / 2}
[0019] Where NL is the number of columns in the capacitor array, C N is the total number of capacitors in the capacitor array, and round{·} is rounded;
[0020] S1-3: Calculate the number of columns of the capacitor array using the following formula:
[0021] NM=round(C N / NL)
[0022] Where NM is the number of rows of the capacitor array, and round(·) is rounding;
[0023] S2: layout of capacitor array;
[0024] S2-1: Determine the center point of the capacitor array, and divide the capacitors into capacitors with higher weights and capacitors with lower weights according to the size of each capacitor bit;
[0025] S2-2: Arrange capacitors with lower weights;
[0026] S2-3: Arrange capacitors with relatively high weights;
[0027] S2-4: Adjust the distribution of the upper and lower plates of the unit capacitor so that the upper plate of the unit capacitor in each row corresponds to the upper plate, and the lower plate corresponds to the lower plate;
[0028] S2-5: Add virtual capacitors around the capacitor array;
[0029] S3: wiring the capacitor array; when wiring the upper and lower plates, they are both connected to the center of the capacitor plates through metal wires and then led out from one side of the plates;
[0030] S4: Extract parasitic parameters through the PEX tool, simulate the capacitor array, and adjust the layout and routing of the capacitor array.
[0031] In the above scheme: step S2-3 includes:
[0032] S2-2-1: Assume that the even-numbered rows in the center of the capacitor array are the distribution range of capacitors with lower weights;
[0033] S2-2-2: Arrange the capacitors in order from small to large capacitance weights;
[0034] S2-2-3: The unit capacitance of each bit weight is symmetrically distributed along the horizontal center line of the capacitor array, and is also symmetrically distributed along the vertical center line of the capacitor array;
[0035] S2-2-4: When the number of unit capacitors on a certain weight is an odd number, a virtual capacitor is added at the missing position.
[0036] In the above scheme: step S2-3 includes:
[0037] S2-3-1: Assume that the upper and lower sides of the distribution range of capacitors with relatively low weights are both the distribution ranges of capacitors with relatively high weights;
[0038] S2-3-2: Arrange the unit capacitors in order from small to large according to the capacitance weight;
[0039] S2-3-3: The unit capacitance of each bit weight is distributed symmetrically with the center point of the capacitor array as the origin.
[0040] In summary, the beneficial effects of the present invention are: it is possible to reduce unnecessary parasitic parameters caused by wiring on the layout as much as possible, thereby reducing capacitor mismatch and improving the overall accuracy and performance of the SAR ADC. It can effectively reduce parasitics between routings, improve the accuracy of capacitor array matching, and meet the accuracy requirements for capacitor arrays in SAR ADC. At the same time, it is also possible to quickly determine the formula for the number of rows and columns to plan the area of the capacitor array in advance and improve efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0041] Figure 1 It is a schematic diagram of a capacitor array with a non-binary CDAC layout structure of the present invention.
[0042] Figure 2 Schematic diagram of a virtual capacitor of the present invention. DETAILED DESCRIPTION
[0043] The present invention will be further described below by way of embodiments and in conjunction with the accompanying drawings:
[0044] like Figure 1 , 2 As shown, a non-binary CDAC layout structure includes a low-weight distribution area and high-weight distribution areas located on the upper and lower sides of the low-weight distribution area. The low-weight distribution area is used to set capacitors with lower weights, and the high-weight distribution area is used to set capacitors with higher weights, and a capacitor array is formed by the capacitors set in the low-weight distribution area and the high-weight distribution area. A circle of virtual capacitors 2 is set around the capacitor array.
[0045] The unit capacitors 1 in the low-weight distribution area are arranged in an even number of rows, and are arranged horizontally outward from the center point of the capacitor array in order from small to large according to the capacitor weight. The unit capacitors 1 on each weight are symmetrically arranged along the horizontal center line of the capacitor array. If the number of unit capacitors 1 on a certain weight is an odd number, a virtual capacitor 2 is added so that the unit capacitors 1 of the weight and the added virtual capacitors 2 are symmetrically distributed along the horizontal center line of the capacitor array.
[0046] The capacitors with higher weights are set in sequence from small to large according to the capacitance weights, and the unit capacitors 1 with the same weight in all the capacitors with higher weights are distributed symmetrically in two high-weight distribution areas with the center point of the capacitor array as the origin. When setting the capacitors with higher weights, they are set from the side close to the low-weight distribution area to the side away from the low-weight distribution area.
[0047] The unit capacitor 1 is a mom capacitor. The virtual capacitors 2 of adjacent layers are connected to the metal plates on both sides of the unit capacitor 1 adjacent to the virtual capacitor 2 through the connecting wire 3. The metal plate connected by the connecting wire 3 is the metal plate of the unit capacitor 1 away from the upper and lower plates.
[0048] The upper plates of all unit capacitors 1 are arranged correspondingly to each other, and the lower plates are arranged correspondingly to each other. The size and capacitance of the virtual capacitor 2 are all consistent with the size and capacitance of the unit capacitor 1.
[0049] The present invention also provides a non-binary CDAC layout structure design method for reducing parasitic parameters, comprising the following steps:
[0050] S1: Determine the total number of capacitors, the number of rows and the number of columns of the capacitor array;
[0051] S1-1: Determine the total number of capacitors according to the specific functional requirements of the circuit, and determine the total number of capacitors by calculating the series and parallel relationships of the capacitors and the weight distribution of the capacitors;
[0052] S1-2: Calculate the number of rows of the capacitor array using the following formula:
[0053] NL=round{(C N ) 0.5 / 2}
[0054] Where NL is the number of columns in the capacitor array, C N is the total number of capacitors in the capacitor array, and round{·} is rounded;
[0055] S1-3: Calculate the number of columns of the capacitor array using the following formula:
[0056] NM=round(C N / NL)
[0057] Where NM is the number of rows of the capacitor array, and round(·) is rounding.
[0058] According to the above formula, the number of columns of the capacitor array should be 11, but because virtual capacitors 2 are added in the actual capacitor layout, the number of capacitor units in the capacitor array excluding the virtual capacitors 2 around is greater than the total number of actual unit capacitors 1. Therefore, the number of rows and columns of the capacitor array in the actual layout will change slightly.
[0059] Taking a 10-bit SAR ADC as an example, the number of columns of the non-binary capacitor array is 10, which contains a total of 4-bit weighted unit capacitors 1. The number of rows of the non-binary capacitor array is 52.
[0060] S2: layout of capacitor array;
[0061] S2-1: Determine the center point of the capacitor array, and divide the capacitors into capacitors with higher weights and capacitors with lower weights according to the size of each capacitor bit;
[0062] S2-2: Arrange capacitors with lower weights;
[0063] S2-2-1: Assume that the even-numbered rows in the center of the capacitor array are the distribution range of capacitors with lower weights;
[0064] S2-2-2: Arrange the capacitors in order from small to large capacitance weights;
[0065] S2-2-3: The unit capacitance 1 of each weight is symmetrically distributed along the horizontal center line of the capacitor array, and is also symmetrically distributed along the vertical center line of the capacitor array;
[0066] S2-2-4: When the number of unit capacitors 1 on a certain weight is an odd number, a virtual capacitor 2 is added at the missing position to fill the position, thereby reducing the mismatch of the capacitor array;
[0067] S2-3: Arrange capacitors with relatively high weights;
[0068] S2-3-1: Assume that the upper and lower sides of the distribution range of capacitors with relatively low weights are both the distribution ranges of capacitors with relatively high weights;
[0069] S2-3-2: Arrange the unit capacitors 1 in order from small to large according to the capacitance weight;
[0070] S2-3-3: The unit capacitance 1 on each weight is distributed symmetrically with the center point of the capacitor array as the origin;
[0071] S2-4: Adjust the distribution of the upper and lower plates of the unit capacitor 1; the upper plate of the unit capacitor 1 in each row corresponds to the upper plate setting, and the lower plate corresponds to the lower plate setting;
[0072] S2-5: Add virtual capacitor 2 around the capacitor array;
[0073] Taking the center of the capacitor array as the origin, for capacitors with relatively low weights, try to make the distribution symmetrical along the horizontal line of the center of the capacitor array. However, since it is a non-binary capacitor array, the number of unit capacitors 1 on each weight is not completely even. When there are odd numbers of unit capacitors 1, add virtual capacitors 2 on the corresponding side of the axis to reduce the mismatch of the capacitor array. For capacitors with high weights, they can be centrally symmetrical about the origin. The distribution of the upper and lower plates of the capacitor can be distributed according to the upper plate corresponding to the upper plate of each row of capacitors, and the lower plate corresponding to the lower plate. During wiring, the parasitic effect of the routing of the upper plate on the routing of the lower plate can be reduced.
[0074] Among them, Figure 1 The capacitor array shown is used as an example to illustrate that C0, C1, C2, C3, and C4 are the bits with lower weights in the capacitor array. In the layout of the capacitor array, the positions are in the upper and lower rows of the horizontal line at the center of the capacitor array. For non-binary capacitor arrays, when the number of unit capacitors 1 of C2 and C4 is not all even, when the axis is symmetrical on the horizontal line of the capacitor array origin, a virtual capacitor 2 should be added on the other side to reduce the mismatch of capacitor matching.
[0075] For capacitors with higher weights, C5 is distributed in the second row above and below the center horizontal line of the capacitor array, located on one side of the row number of the capacitor array, and the symmetrical capacitors are on the other side of the row number symmetrical to it. C6 is a capacitor with higher weights, and its distribution is consistent with C5. It continues to distribute the remaining positions of a row of C5, and the remaining unit capacitors 1 of C6 continue to be distributed at one end of the other row, and the same is true for the symmetrical capacitors.
[0076] The capacitors with higher weights C7 are also distributed as described above, arranged in order from the front of the capacitor weight to the back.
[0077] S3: wiring the capacitor array; when wiring the upper and lower plates, they are connected to the center of the capacitor plates through metal wires and then led out from one side.
[0078] Since the upper plate of the capacitor is uniformly connected to the charge sampling, and the lower plate of the capacitor is weightedly connected to the capacitor switch, the upper and lower plates need to be wired separately. When wiring the upper and lower plates, they are connected to the center of the capacitor plates through metal wires and then led out from one side.
[0079] After all weighted capacitors are laid out, virtual capacitors 2 are placed in the remaining spaces and around the capacitor array. The size and capacitance of virtual capacitors 2 are consistent with those of unit capacitors 1, thereby ensuring the consistency of the surrounding environment of the capacitor array.
[0080] The distribution of the upper and lower plates is also symmetrically distributed along the horizontal line in the center of the capacitor array. Capacitors C0, C1, C2, C3, and C4 are opposite to the lower plates of the capacitors, and the other side of the capacitor is the upper plate. C0, C1, C2, C3, and C4 are opposite to capacitors C5 and C6, which are the upper plates of the capacitors.
[0081] The unit capacitor 1 of the technical solution is a mom capacitor. Regarding the wiring of the virtual capacitor 2, the wiring of the virtual capacitor 2 to the ground will cause parasitic capacitance to the wiring between the capacitor arrays, resulting in the charge carried by the weight on a certain bit being filled in the parasitic capacitance between the virtual capacitor 2 wiring, thereby reducing the original calculated weight.
[0082] When the virtual capacitors 2 are routed to each other, the metal attached to the mom capacitor can be used for vertical connection, wherein the metal is selected to be a metal layer away from the upper and lower plate connections of the capacitor. The parasitic capacitance value generated by the weights at the capacitor array position can be effectively reduced, thereby improving the accuracy of the SAR ADC. That is, the virtual capacitors 2 are connected to the metal attached to the mom capacitor through the connecting wire 3 to achieve vertical connection, and when connecting, the mom capacitor is selected to be away from the metal layer of the upper and lower plate connections.
[0083] S4: Extract parasitic parameters through the PEX tool, simulate the capacitor array, and adjust the layout and routing of the capacitor array.
Claims
1. A non-binary CDAC layout structure, characterized in that: It comprises a low-weight distribution area and high-weight distribution areas located on the upper and lower sides of the low-weight distribution area, wherein the low-weight distribution area is used to set capacitors with lower weights, and the high-weight distribution area is used to set capacitors with higher weights, and a capacitor array is formed by the capacitors set in the low-weight distribution area and the high-weight distribution area, and a circle of virtual capacitors (2) is set around the capacitor array; The unit capacitors (1) in the low-weight distribution area are arranged in an even number of rows, and are arranged horizontally outward from the center point of the capacitor array in order from small to large according to the capacitor weights. The unit capacitors (1) on each bit weight are symmetrically arranged along the horizontal center line of the capacitor array. If the number of unit capacitors (1) on a certain weight is an odd number, a virtual capacitor (2) is added so that the unit capacitors (1) of the weight and the added virtual capacitors (2) are symmetrically distributed along the horizontal center line of the capacitor array. The capacitors with higher weights are arranged in order from small to large according to the capacitance weights, and the unit capacitors (1) with the same weight among all the capacitors with higher weights are centrally symmetrically distributed in two high-weight distribution areas with the center point of the capacitor array as the origin. When setting the capacitors with higher weights, they are arranged from the side close to the low-weight distribution area to the side away from the low-weight distribution area.
2. A non-binary CDAC layout structure according to claim 1, characterized in that: The unit capacitor (1) is a mom capacitor.
3. A non-binary CDAC layout structure according to claim 2, characterized in that: Virtual capacitors (2) in adjacent layers are connected to metal plates on both sides of unit capacitors (1) adjacent to the virtual capacitors (2) via connecting wires (3) for routing.
4. A non-binary CDAC layout structure according to claim 3, characterized in that: The metal plate connected to the connecting line (3) is a metal plate of the unit capacitor (1) that is far away from the upper and lower plates.
5. A non-binary CDAC layout structure according to claim 1, characterized in that: The upper plates of all unit capacitors (1) are arranged correspondingly to each other, and the lower plates are arranged correspondingly to each other.
6. A non-binary CDAC layout structure according to claim 1, characterized in that: The size and capacitance of the virtual capacitor (2) are consistent with the size and capacitance of the unit capacitor (1).
7. A non-binary CDAC layout structure design method for reducing parasitic parameters, characterized in that: The following steps are involved: S1: Determine the total number of capacitors, the number of rows and the number of columns of the capacitor array; S1-1: Determine the total number of capacitors according to the specific functional requirements of the circuit, and determine the total number of capacitors by calculating the series and parallel relationships of the capacitors and the weight distribution of the capacitors; S1-2: Calculate the number of rows of the capacitor array using the following formula: NL=round{(C N ) 0.5 / 2} Where NL is the number of columns in the capacitor array, C N is the total number of capacitors in the capacitor array, and round{·} is rounded; S1-3: Calculate the number of columns of the capacitor array using the following formula: NM=round(C N / NL) Where NM is the number of rows of the capacitor array, and round(·) is rounding; S2: layout of capacitor array; S2-1: Determine the center point of the capacitor array, and divide the capacitors into capacitors with higher weights and capacitors with lower weights according to the size of each capacitor bit; S2-2: Arrange capacitors with lower weights; S2-3: Arrange capacitors with relatively high weights; S2-4: adjusting the distribution of the upper and lower plates of the unit capacitor (1) so that the upper plate of the unit capacitor (1) in each row is arranged correspondingly to the upper plate, and the lower plate is arranged correspondingly to the lower plate; S2-5: Add virtual capacitors (2) around the capacitor array; S3: wiring the capacitor array; when wiring the upper and lower plates, they are both connected to the center of the capacitor plates through metal wires and then led out from one side of the plates; S4: Extract parasitic parameters through the PEX tool, simulate the capacitor array, and adjust the layout and routing of the capacitor array.
8. The non-binary CDAC layout structure design method for reducing parasitic parameters according to claim 7, characterized in that: Step S2-3 includes: S2-2-1: Assume that the even-numbered rows in the center of the capacitor array are the distribution range of capacitors with lower weights; S2-2-2: Arrange the capacitors in order from small to large capacitance weights; S2-2-3: The unit capacitance (1) on each bit weight is symmetrically distributed along the horizontal center line of the capacitor array, and is also symmetrically distributed along the vertical center line of the capacitor array; S2-2-4: When the number of unit capacitors (1) on a certain weight is an odd number, a virtual capacitor (2) is added at the missing position.
9. The non-binary CDAC layout structure design method for reducing parasitic parameters according to claim 7, characterized in that: Step S2-3 includes: S2-3-1: Assume that the upper and lower sides of the distribution range of capacitors with relatively low weights are both the distribution ranges of capacitors with relatively high weights; S2-3-2: Arrange the unit capacitors in order from small to large according to the capacitance weight (1); S2-3-3: The unit capacitance (1) of each bit weight is distributed symmetrically with the center point of the capacitor array as the origin.