Method and system for acquiring pre-emphasis parameter and equalization parameter of chip

Abstract

The invention discloses a method and a system for acquiring a pre-emphasis parameter and an equalization parameter of a chip. The method comprises the following steps: acquiring a target design factor of a to-be-designed chip; based on the target design factor, obtaining a target pre-emphasis parameter and an equalization parameter matched with the target design factor by querying a parameter screening model; wherein the incidence relation between the design factor and the pre-emphasis parameter as well as the pre-emphasis parameter and the equilibrium parameter is recorded in the parameter screening model.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of cloud terminal communication technology, and in particular to a method and system for obtaining pre-emphasis parameters and equalization parameters of a chip. Background Art

[0002] As the service rates of communication products become higher and higher, the high-frequency components of the high-speed serializer / deserializer (serdes) signal will be lost after being attenuated through the product channel. Pre-emphasis parameter compensation and equalization parameter compensation are performed at the transmitting and receiving ends of the chip in the product to compensate for the high-frequency components attenuated in the product channel.

[0003] The debugging or traversal of the pre-emphasis parameters and equalization parameters of the chip in the prior art has the following problems: first, it can only be applied to specific chips, for example, the chip is required to support reading eye diagrams or the chip manual specifies the corresponding relationship between parameters and losses; second, only one of the pre-emphasis parameters of the chip's transmitter or the equalization parameters of the receiver can be traversed, and the transmitter and receiver of the channel cannot be covered, resulting in the inability to guarantee complete compensation of the high-frequency components lost after the high-speed signal passes through the channel; third, the pre-emphasis parameters and equalization parameters of the traversed chip have not been verified by stress testing, and it is impossible to guarantee that these parameters are optimal, and they cannot be applied to other product chips in the same scenario, resulting in the need to traverse each product chip, and the reliability of the pre-emphasis parameters and equalization parameters will be affected due to the different capabilities and traversal configurations of different testers. Therefore, how to improve the efficiency and accuracy of obtaining the pre-emphasis parameters and equalization parameters of the chip is a problem that needs to be solved at present. Summary of the invention

[0004] The embodiments of the present application provide a method and system for obtaining pre-emphasis parameters and equalization parameters of a chip, which can solve the problem of how to improve the efficiency and accuracy of obtaining pre-emphasis parameters and equalization parameters of the chip.

[0005] In order to solve the above technical problems, this application is implemented as follows:

[0006] In a first aspect, a method for obtaining pre-emphasis parameters and equalization parameters of a chip is provided, comprising: obtaining target design factors of a chip to be designed; based on the target design factors, obtaining target pre-emphasis parameters and equalization parameters matching the target design factors by querying a parameter screening model; wherein the parameter screening model records the association between the design factors and the pre-emphasis parameters and equalization parameters.

[0007] In a second aspect, a system for acquiring pre-emphasis parameters and equalization parameters of a chip is provided, comprising: a first acquisition module, used to acquire target design factors of the chip to be designed; a second acquisition module, used to acquire target pre-emphasis parameters and equalization parameters matching the target design factors by querying a parameter screening model based on the target design factors; wherein the parameter screening model records the association between the design factors and the pre-emphasis parameters and equalization parameters.

[0008] In a third aspect, an electronic device is provided, comprising a processor and a memory, wherein the memory stores programs or instructions that can be run on the processor, and when the program or instructions are executed by the processor, the steps of the method for obtaining pre-emphasis parameters and equalization parameters of the chip as described in the first aspect are implemented.

[0009] In a fourth aspect, a readable storage medium is provided, on which a program or instruction is stored. When the program or instruction is executed by a processor, the steps of the method for obtaining pre-emphasis parameters and equalization parameters of the chip as described in the first aspect are implemented.

[0010] The technical solution provided by this application may have the following beneficial effects:

[0011] In an embodiment of the present application, by obtaining the target design factor of the chip to be designed, and then based on the target design factor, querying the parameter screening model that records the correlation between the design factor and the pre-emphasis parameter and the equalization parameter, the target pre-emphasis parameter and the equalization parameter that match the target design factor are obtained, thereby achieving rapid acquisition of accurate target pre-emphasis parameters and equalization parameters, and applying the target pre-emphasis parameters and the equalization parameters to the design of the chip without repeated debugging, thereby improving the efficiency and accuracy of obtaining the pre-emphasis parameters and the equalization parameters of the chip.

[0012] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0014] Figure 1 A schematic flow chart of a method for obtaining pre-emphasis parameters and equalization parameters of a chip provided by an exemplary embodiment of the present application is shown;

[0015] Figure 2a A schematic flow chart of a method for obtaining pre-emphasis parameters and equalization parameters of another chip provided by an exemplary embodiment of the present application is shown;

[0016] Figure 2b A schematic flow chart of a method for obtaining pre-emphasis parameters and equalization parameters of another chip provided by an exemplary embodiment of the present application is shown;

[0017] Figure 2c A schematic flow chart of a method for obtaining pre-emphasis parameters and equalization parameters of another chip provided by an exemplary embodiment of the present application is shown;

[0018] Figure 3 A schematic diagram of the structure of a system for obtaining pre-emphasis parameters and equalization parameters of a chip provided by an exemplary embodiment of the present application is shown;

[0019] Figure 4 A schematic diagram of a chip docking scenario provided by an exemplary embodiment of the present application is shown;

[0020] Figure 5 A schematic diagram showing another chip docking scenario provided by an exemplary embodiment of the present application is shown;

[0021] Figure 6 A schematic diagram showing another chip docking scenario provided by an exemplary embodiment of the present application is shown;

[0022] Figure 7 A schematic diagram showing another chip docking scenario provided by an exemplary embodiment of the present application is shown;

[0023] Figure 8 A schematic diagram of the structure of another chip pre-emphasis parameter and equalization parameter acquisition system provided by an exemplary embodiment of the present application is shown;

[0024] Fig. 9 A schematic diagram of a process of traversing parameters of a chip docking scenario provided by an exemplary embodiment of the present application is shown;

[0025] Fig.10 A schematic diagram of a process of traversing parameters in another chip docking scenario provided by an exemplary embodiment of the present application is shown;

[0026] Fig.11 A schematic diagram of a process of traversing parameters in another chip docking scenario provided by an exemplary embodiment of the present application is shown;

[0027] Fig.12 A schematic diagram of a process of traversing parameters in another chip docking scenario provided by an exemplary embodiment of the present application is shown;

[0028] Fig.13 A schematic structural diagram of an electronic device provided by an exemplary embodiment of the present application is shown. DETAILED DESCRIPTION

[0029] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0030] Figure 1 A schematic diagram showing a flow chart of a method for obtaining pre-emphasis parameters and equalization parameters of a chip provided by an exemplary embodiment of the present application is shown. Figure 1 , the method may include the following steps:

[0031] Step 102, obtaining target design factors of the chip to be designed;

[0032] The target design factors may include at least one of the following: docking scenario, chip code, rate, board material, channel insertion loss, and fault occurrence frequency.

[0033] Step 104, based on the target design factor, obtaining a target pre-emphasis parameter and an equalization parameter matching the target design factor by querying a parameter screening model;

[0034] Among them, the correlation between the design factors and the pre-emphasis parameters and the equalization parameters is recorded in the parameter screening model.

[0035] Optionally, the design factors may include at least one of the following: docking scenario, chip code, rate, board material, channel insertion loss, and fault occurrence frequency.

[0036] In an embodiment of the present application, by obtaining the target design factor of the chip to be designed, and then based on the target design factor, querying the parameter screening model that records the correlation between the design factor and the pre-emphasis parameter and the equalization parameter, the target pre-emphasis parameter and the equalization parameter that match the target design factor are obtained, thereby achieving rapid acquisition of accurate target pre-emphasis parameters and equalization parameters, and applying the target pre-emphasis parameters and the equalization parameters to the design of the chip without repeated debugging, thereby improving the efficiency and accuracy of obtaining the pre-emphasis parameters and the equalization parameters of the chip.

[0037] In one implementation, the above parameter screening model also records the verification passing level of each association relationship.

[0038] The verification pass level indicates whether each pre-emphasis parameter and equalization parameter has passed verification, and the verification pass level of the pre-emphasis parameter and equalization parameter that have passed verification is higher than the verification pass level of the pre-emphasis parameter and equalization parameter that have not passed verification.

[0039] In one implementation, the above-mentioned step 104 may include: when a plurality of target pre-emphasis parameters and equalization parameters matching the target design factors are queried by querying the parameter screening model, selecting the target pre-emphasis parameters and equalization parameters having the highest verification passing level from the plurality of target pre-emphasis parameters and equalization parameters.

[0040] Among them, according to the target design factors, such as at least one of the docking scenario, chip code, rate, board material, channel insertion loss, and fault occurrence frequency, the parameter screening model is queried, and there may be a situation where multiple target pre-emphasis parameters and equalization parameters matching the target design factor are queried. At this time, the multiple target pre-emphasis parameters and equalization parameters matching the target design factor can be further screened through the gears through the verification of each association relationship recorded in the parameter screening model, and the target pre-emphasis parameters and equalization parameters with the highest gear that have passed the verification are selected, so that more accurate target pre-emphasis parameters and equalization parameters can be obtained.

[0041] Figure 2a FIG. 1 shows a flow chart of a method for obtaining pre-emphasis parameters and equalization parameters of another chip provided by an exemplary embodiment of the present application in an implementation manner, see Figure 2a , the method may include the following steps:

[0042] Step 202: Obtain target design factors of the chip to be designed.

[0043] Step 204: Based on the target design factor, obtain the target pre-emphasis parameter and equalization parameter matching the target design factor by querying the parameter screening model; wherein the parameter screening model records the association between the design factor and the pre-emphasis parameter and the equalization parameter.

[0044] Step 206: Obtain application results of the chip product designed according to the target pre-emphasis parameters and equalization parameters.

[0045] Step 208: According to the application result, the target pre-emphasis parameters and equalization parameters corresponding to the target design factors in the parameter screening model are optimized.

[0046] In an embodiment of the present application, after querying a parameter screening model based on the target design factors of the chip to be designed and obtaining the target pre-emphasis parameters and equalization parameters that match the target design factors, the chip is designed according to the target pre-emphasis parameters and equalization parameters, and then the application results of the chip product designed according to the target pre-emphasis parameters and equalization parameters are obtained. By judging the application results, the target pre-emphasis parameters and equalization parameters used for the chip design in the parameter screening model are optimized, so that the pre-emphasis parameters and equalization parameters in the parameter screening model can be continuously updated and optimized to improve the accuracy of the pre-emphasis parameters and equalization parameters.

[0047] Figure 2b A schematic diagram of a process for obtaining pre-emphasis parameters and equalization parameters of another chip provided by an exemplary embodiment of the present application is shown in one implementation. Before obtaining the target pre-emphasis parameters and equalization parameters matching the target design factors by querying the parameter screening model based on the target design factors, refer to Figure 2b The method for obtaining the pre-emphasis parameters and equalization parameters of the above chip may further include the following steps:

[0048] Step 210, obtaining a plurality of sample data, wherein the sample data includes: sample design factors and sample pre-emphasis parameters and equalization parameters corresponding to the sample design factors;

[0049] Step 220, dividing the plurality of sample data into a plurality of types according to the sample design factors of each of the sample data;

[0050] Among them, the sample design factors include at least one of the following: docking scenario, chip code, rate, board material, channel insertion loss, and fault occurrence frequency.

[0051] For example, (1) it can be classified according to the docking scenario, which can be divided into four scenarios: "chip docking optical module scenario", "chip docking behind the backplane scenario", "chip docking chip scenario within the board", and "chip docking chip scenario between boards". (2) The sample data in each docking scenario can be classified according to the rate, which can be divided into 1.25Gbps, 2.5Gbps, 5Gbps, 10Gbps, 12.5Gbps, etc. (3) It can be further classified according to the board material, which can be divided into FR4, Z2, Z4, Z6, Z7, Z8, etc.

[0052] Step 230, according to the verification factors corresponding to the sample data of each type, determine the verification pass level corresponding to each type, wherein the verification factors include at least one of the following: verification scenario, number of verification samples, and verification time.

[0053] For example, verification scenarios can be divided into reliability verification (48 hours of temperature cycle, 24 hours of high temperature, 24 hours of low temperature, 24 hours of high temperature and high humidity), production line verification (high temperature aging), and engineering verification (actual environments in various countries around the world); the number of verification samples can be divided into a small number of samples (less than 50 pieces), a small batch of samples (50 to 500 pieces), and a large batch of samples (greater than 500 pieces); the verification duration can be divided into 7 days, 1 month, 3 months, 1 year, 3 years, 5 years, 10 years, etc.

[0054] Step 240 , the sample design factors, sample pre-emphasis parameters and equalization parameters corresponding to each of the types, and the verification are stored by associating the gears to obtain the parameter screening model.

[0055] In an embodiment of the present application, by classifying and iterating the acquired multiple sample data, the sample design factors, sample pre-emphasis parameters and equalization parameters are determined, and the correlation relationship between the gears is verified to obtain a parameter screening model, so that the target design factors of the chip to be designed can be obtained, and the target pre-emphasis parameters and equalization parameters matching the target design factors can be determined from the parameter screening model according to the target design factors, so that the chip can be designed according to the target pre-emphasis parameters and equalization parameters.

[0056] In one implementation, the above step 210 of acquiring a plurality of sample data may include:

[0057] Step 1, obtaining first pre-emphasis parameters and equalization parameters that have been traversed by multiple chip products in various docking scenarios;

[0058] Step 2, verifying the first pre-emphasis parameter and the equalization parameter based on at least one of the verification factors;

[0059] Among them, verification factors may include a reliability environment of standard specifications.

[0060] Step 3: taking the first pre-emphasis parameter and equalization parameter that have passed verification and the design factors corresponding to the first pre-emphasis parameter and equalization parameter that have passed verification as the sample data.

[0061] In an embodiment of the present application, the first pre-emphasis parameters and equalization parameters corresponding to the currently existing multiple chip products are verified based on at least one verification factor. Only the first pre-emphasis parameters and equalization parameters that pass the verification can be used as sample data. Since the first pre-emphasis parameters and equalization parameters already have designed chip products, the design factors corresponding to the first pre-emphasis parameters and equalization parameters can also be obtained. When the design factors also pass the verification, the first pre-emphasis parameters and equalization parameters and the design factors corresponding to the first pre-emphasis parameters and equalization parameters are used as sample data for training, thereby ensuring the quality of the parameter screening model.

[0062] Figure 2c FIG. 1 is a flow chart of a method for obtaining pre-emphasis parameters and equalization parameters of another chip provided by an exemplary embodiment of the present application in an implementation manner. Figure 2c , the method may include:

[0063] Step 210, obtaining a plurality of sample data, wherein the sample data includes: sample design factors and sample pre-emphasis parameters and equalization parameters corresponding to the sample design factors;

[0064] Step 220, dividing the plurality of sample data into a plurality of types according to the sample design factors of each of the sample data;

[0065] Step 230, determining the verification pass level corresponding to each type according to the verification factors corresponding to the sample data of each type, wherein the verification factors include at least one of the following: verification scenario, number of verification samples, and verification duration;

[0066] Step 240, storing the sample design factors, sample pre-emphasis parameters and equalization parameters corresponding to each type, and the verification by gear association, to obtain the parameter screening model;

[0067] Step 241, according to the screening condition, by querying the parameter screening model, obtaining the second pre-emphasis parameter and the equalization parameter matching the screening condition;

[0068] The screening conditions may include at least one of the following: docking scenario, chip code, rate, board material, channel insertion loss, and fault occurrence frequency.

[0069] Step 242: Obtain application results of a chip product corresponding to the second pre-emphasis parameters and equalization parameters.

[0070] Step 243: Optimize the second pre-emphasis parameter and the equalization parameter corresponding to the screening condition in the parameter screening model according to the application result.

[0071] Wherein, when the application result indicates normal, the verification pass level corresponding to the screening condition and the second pre-emphasis parameter and the equalization parameter in the parameter screening model is raised.

[0072] When the application result indicates an abnormality, the second pre-emphasis parameter and the equalization parameter corresponding to the screening condition are adjusted, and after the adjusted second pre-emphasis parameter and the equalization parameter are verified, the adjusted second pre-emphasis parameter and the equalization parameter are used to update the second pre-emphasis parameter and the equalization parameter in the parameter screening model.

[0073] In an embodiment of the present application, after obtaining a parameter screening model by training the acquired sample data, it is necessary to further evaluate the pre-emphasis parameters and equalization parameters in the parameter screening model. The parameter screening model can be queried according to the screening conditions to obtain second pre-emphasis parameters and equalization parameters that match the screening conditions. After designing a chip product according to the second pre-emphasis parameters and equalization parameters, an application result is obtained, the application result is judged, and then the second pre-emphasis parameters and equalization parameters used for the chip design in the parameter screening model are optimized according to the application result. When the application result indicates normal, the verification pass level corresponding to the screening conditions and the second pre-emphasis parameters and equalization parameters in the parameter screening model is increased; when the application result indicates abnormal, the second pre-emphasis parameters and equalization parameters are adjusted and verified again. After the verification passes, the adjusted second pre-emphasis parameters and equalization parameters are used to update the original second pre-emphasis parameters and equalization parameters in the parameter screening model, so that the pre-emphasis parameters and equalization parameters in the parameter screening model can be continuously updated and optimized to improve the accuracy of the pre-emphasis parameters and equalization parameters.

[0074] Figure 3 It is a structural diagram of a system for acquiring pre-emphasis parameters and equalization parameters of a chip provided by an exemplary embodiment of the present application. The system includes a parameter adjustment module 31, an intelligent module 32, an application module 33 and a design module 34.

[0075] Among them, the parameter adjustment module 31 is used to traverse the pre-emphasis parameters and the equalization parameters, and send the pre-emphasis parameters and the equalization parameters to the intelligent module; the intelligent module 32 is used to obtain the target pre-emphasis parameters and the equalization parameters that match the target design factors by querying the parameter screening model based on the target design factors; the application module 33 is used to obtain the application results of the chip product designed according to the target pre-emphasis parameters and the equalization parameters; the design module 34 is used to design according to the target pre-emphasis parameters and the equalization parameters; wherein the parameter screening model records the association between the design factors and the pre-emphasis parameters and the equalization parameters.

[0076] Optionally, the design factors include at least one of the following: docking scenario, chip code, rate, board material, channel insertion loss, and fault occurrence frequency.

[0077] In one implementation, the above-mentioned intelligent module 32 may include an input unit, a training unit, a storage unit and a query unit; wherein the input unit is used to receive the pre-emphasis parameters and equalization parameters sent by the parameter adjustment module; the training unit is used to train the pre-emphasis parameters and equalization parameters; the storage unit is used to store the trained pre-emphasis parameters and equalization parameters in the parameter screening model; the query unit is used to obtain the target pre-emphasis parameters and equalization parameters matching the target design factors from the parameter screening model based on the target design factors.

[0078] In one implementation, the above-mentioned parameter screening model also records the verification passing level of each of the association relationships.

[0079] In one implementation, the above-mentioned intelligent module 32 can be used to select the target pre-emphasis parameters and equalization parameters with the highest verification level from the multiple target pre-emphasis parameters and equalization parameters when multiple target pre-emphasis parameters and equalization parameters matching the target design factors are queried by querying the parameter screening model.

[0080] In one implementation, the input unit in the above-mentioned intelligent module 32 can be used to obtain multiple sample data, wherein the sample data include: sample design factors and sample pre-emphasis parameters and equalization parameters corresponding to the sample design factors; the training unit of the above-mentioned intelligent module 32 can be used to divide the multiple sample data into multiple types according to the sample design factors of each of the sample data; according to the verification factors corresponding to the sample data of each type, determine the verification pass level corresponding to each of the types, wherein the verification factors include at least one of the following: verification scenario, number of verification samples, and verification time; the storage unit of the above-mentioned intelligent module 32 can be used to associate and store the sample design factors, sample pre-emphasis parameters and equalization parameters, and verification pass level corresponding to each of the types to obtain the parameter screening model.

[0081] In one implementation, the above-mentioned parameter adjustment module 31 is also used to optimize the target pre-emphasis parameters and equalization parameters corresponding to the target design factors in the parameter screening model when the application result indicates an abnormality. Wherein, when the application result indicates an abnormality, the target pre-emphasis parameters and equalization parameters corresponding to the target design factors are adjusted, and after the adjusted target pre-emphasis parameters and equalization parameters are verified, the adjusted target pre-emphasis parameters and equalization parameters are used to update the target pre-emphasis parameters and equalization parameters in the parameter screening model, so as to optimize the target pre-emphasis parameters and equalization parameters corresponding to the target design factors in the parameter screening model.

[0082] In one implementation, the intelligent module 32 is also used to optimize the target pre-emphasis parameters and equalization parameters corresponding to the target design factors in the parameter screening model when the application result indicates normal. Wherein, when the application result indicates normal, the target pre-emphasis parameters and equalization parameters corresponding to the target design factors in the parameter screening model are optimized by improving the verification pass level corresponding to the target design factors and the target pre-emphasis parameters and equalization parameters in the parameter screening model.

[0083] Figure 4 It is a schematic diagram of a chip docking scenario provided by an exemplary embodiment of the present application, wherein the chip docking scenario is specifically a chip docking optical module scenario, which is generally used in a business board. On this board, one ASIC chip may be connected to multiple optical modules, which are sorted and named Module_1, Module_2, ..., Module_n respectively.

[0084] Figure 5 It is a schematic diagram of another chip docking scenario provided by an exemplary embodiment of the present application, wherein the chip docking scenario is specifically a chip-under-backplane docking chip scenario, the scenario includes single board 1 and single board 2, single board 1 and single board 2 are respectively inserted into the corresponding positions of single board 1 and single board 2 in the backplane through connectors, and some connectors are mainly distributed on the backplane for interconnecting signals between different single boards, and the chip names on single board 1 and single board 2 are ASIC_1 and ASIC_2 respectively, and the number of serdes between the two chips is n+1, and their names are serdes 0, serdes 1, ..., serdes n, abbreviated as serdes<0...n>. The number of single boards in the entire backplane system varies according to different products, and is described in this application by two single boards, but is not limited to 2.

[0085] Figure 61 is a schematic diagram of another chip docking scenario provided by an exemplary embodiment of the present application, wherein the chip docking scenario is specifically a chip-to-chip scenario within a board, and the scenario shows the interconnection scenario of two chips within a single board. The number of serdes between chip ASIC_3 and chip ASIC_4 is m+1, and their names are serdes 0, serdes 1, ..., serdesm, abbreviated as serdes<0...m>.

[0086] Figure 7 It is a schematic diagram of another chip docking scenario provided by an exemplary embodiment of the present application, wherein the chip docking scenario is specifically an inter-board chip docking chip scenario, which shows that a single board is divided into a daughter board (single board_S) and a mother board (single board_M), and the daughter board and the mother board are interconnected through an inter-board connector, and the number of serdes between the chip ASIC_5 on the daughter board and the chip ASIC_6 on the mother board is p+1, and their names are serdes 0, serdes 1, ..., serdes p, abbreviated as serdes<0...p>.

[0087] Figure 8 It is a structural diagram of a system for acquiring pre-emphasis parameters and equalization parameters of another chip provided by an exemplary embodiment of the present application, the system including a parameter adjustment module 81, an input module 82, a training module 83, a storage module 84, a query module 85, an application module 86, and a design module 87.

[0088] The parameter adjustment module 81 is used to traverse the pre-emphasis parameters and equalization parameters of the chip docking scenario, and selects the corresponding parameter adjustment or parameter traversal method according to the above-mentioned four chip docking scenarios to adjust the parameters or traverse the parameters. Figures 9 to 12 A flow chart of traversing parameters for the above-mentioned four chip docking scenarios is shown, and appropriate pre-emphasis parameters and equalization parameters are selected according to the parameter adjustment results or traversal results; and the pre-emphasis parameters and equalization parameters for verifying the corresponding chip docking scenarios are verified using a standard reliability environment. If the verification fails, it is necessary to continue adjusting the parameters or traversing the parameters, and verify after outputting appropriate parameters again. If the verification passes, the "entry module" can be used to enter the parameters.

[0089] Among them, Fig. 9 As shown in the figure, the traversal parameters from the chip transmitter to the optical module receiver in the chip-to-optical module scenario include the following steps:

[0090] Step 901: Count the insertion loss values ​​from the chip ball solder joint position to the optical module connector position in the direction from the chip transmitting end to the optical module receiving end, and classify them into n1 levels such as insertion loss 1, insertion loss 2, ..., insertion loss n1, where n1 ≥ 1, and select one link channel for each level of insertion loss value as the link to be tested.

[0091] Step 902: Select the i-th link to start testing until n1 tests are completed, where i = 1, 2, ... n1.

[0092] Step 903: Determine the equalization parameters of the i-th link; the chip board is interconnected with the oscilloscope through a test fixture, and the oscilloscope is used to simulate the optical module. At this time, the pre-emphasis parameter of the chip transmitter is set to the default value, and then the equalization parameters in the oscilloscope are traversed. Read the eye height and eye width under each equalization parameter, and select the equalization parameter corresponding to the maximum eye height * eye width, which is the optimal equalization parameter of the optical module.

[0093] Step 904: determine the pre-emphasis parameter of the i-th link; set the equalization parameter of the oscilloscope to the optimal equalization parameter, then traverse the pre-emphasis parameter near the default pre-emphasis parameter of the chip transmitter, read the eye height and eye width of different pre-emphasis parameters, and determine that the pre-emphasis parameter when the eye height * eye width is the largest is the optimal pre-emphasis parameter.

[0094] Step 905: Compare the pre-emphasis parameters and equalization parameters corresponding to the n1 links; if the n1 pre-emphasis parameters are not much different from the equalization parameters, the same parameter can be selected as the parameter of the n1 insertion loss gears; if the n1 pre-emphasis parameters are significantly different from the equalization parameters, the links with smaller parameter differences can be combined to use the same parameter, and the links with larger parameter differences can be set with different parameters.

[0095] like Fig.10 As shown in the figure, the traversal parameters from the optical module transmitter to the chip receiver in the chip-to-optical module scenario include the following steps:

[0096] Step 1001: Count the insertion loss values ​​from the chip ball solder joint position to the optical module connector position in the direction from the optical module transmitting end to the chip receiving end, and classify them into n2 levels such as insertion loss 1, insertion loss 2, ..., insertion loss n2, where n2 ≥ 1, and select one link channel as the link to be tested for each level of insertion loss value.

[0097] Step 1002: Simulate channel insertion loss; the optical module is interconnected with the oscilloscope through a fixture and the insertion loss of the interconnected channel is modified to simulate the actual insertion loss value of the optical module docking chip, and then a code stream is sent to the optical module receiving end through a signal generator, which is looped back to the optical module transmitting end through the optical fiber of the optical port of the optical module, and then the eye height and eye width are displayed on the oscilloscope through the simulated channel.

[0098] Step 1003: Simulate the i-th insertion loss value to start testing until the n2 insertion loss value tests are completed.

[0099] Step 1004: determine the pre-emphasis parameter of the i-th link; traverse the pre-emphasis parameters of the optical module transmitter, read the eye height and eye width on the oscilloscope, and select the pre-emphasis parameter corresponding to the maximum eye height * eye width as the optimal parameter.

[0100] Step 1005: Compare the pre-emphasis parameters corresponding to the n2 links; if the n2 pre-emphasis parameters are not very different, the same parameter can be selected as the parameter of the n2 insertion loss gears; if the n2 pre-emphasis parameters are very different, the links with smaller parameter differences can be combined to use the same parameter, and the links with larger parameter differences can be set with different parameters; at this time, since the chip receiving end is adaptive, there is no need to traverse the equalization parameters.

[0101] like Fig.11 As shown, the traversal parameters from the A chip transmitter to the B chip receiver in the chip-under-backplane-to-chip scenario, the intra-board chip-to-chip scenario, and the inter-board chip-to-chip scenario include the following steps:

[0102] Step 1101: Count the insertion loss values ​​from the ball solder joint position of chip A to the ball solder joint position of chip B in the direction from the transmitting end of chip A to the receiving end of chip B, and classify them into n3 levels such as insertion loss 1, insertion loss 2, ..., insertion loss n3, where n3 ≥ 1, and select one link channel for each level of insertion loss value as the link to be tested.

[0103] Step 1102: traverse n3 links; determine the combination of pre-emphasis parameters of the A chip transmitter, set the range, step size and scanning time of each parameter in the pre-emphasis parameter in the script, and then configure the pre-emphasis parameters of the n3 links in turn. At this time, the parameters configured for the n3 links are the same each time, and then the B chip adapts and reads the indicators of the B chip receiver and records them in the background log. When the set pre-emphasis parameters are traversed, the log is exported.

[0104] Step 1103: Confirm the pre-emphasis parameters; sort out the relationship diagram between the pre-emphasis parameters and indicators of the n3 links according to the log, and output the optimal pre-emphasis parameters of the n3 links. Compare the optimal pre-emphasis parameters of the n3 links. If the n3 pre-emphasis parameters are not very different, the same parameter can be selected as the parameter of the n3 insertion loss gears; if the n3 pre-emphasis parameters are very different, the links with smaller parameter differences can be combined to use the same parameter, and the links with larger parameter differences can be set with different parameters; at this time, since the chip receiving end is adaptive, there is no need to set the equalization parameters.

[0105] like Fig.12 As shown, the traversal parameters from the B chip transmitter to the A chip receiver in the chip-under-backplane-to-chip scenario, the chip-in-board-to-chip scenario, and the chip-between-board-to-chip scenario include the following steps:

[0106] Step 1201: Count the insertion loss values ​​from the ball solder joint position of chip B to the ball solder joint position of chip A in the direction from the transmitting end of chip B to the receiving end of chip A, and classify them into n4 levels such as insertion loss 1, insertion loss 2, ..., insertion loss n4, where n4 ≥ 1, and select one link channel as the link to be tested for each level of insertion loss value.

[0107] Step 1202: traverse n4 links; determine the combination of pre-emphasis parameters of the B chip transmitter, set the range, step size and scanning time of each parameter in the pre-emphasis parameter in the script, and then configure the pre-emphasis parameters of the n4 links in turn. At this time, the parameters configured for the n4 links are the same each time, and then the A chip adapts and reads the indicators of the A chip receiver and records them in the background log. When the set pre-emphasis parameters are traversed, the log is exported.

[0108] Step 1203: Confirm the pre-emphasis parameters; sort out the relationship diagram between the pre-emphasis parameters and indicators of the n4 links according to the log, and output the optimal pre-emphasis parameters of the n4 links. Compare the optimal pre-emphasis parameters of the n4 links. If the n4 pre-emphasis parameters are not very different, the same parameter can be selected as the parameter of the n4 insertion loss gears; if the n4 pre-emphasis parameters are very different, the links with smaller parameter differences can be combined to use the same parameter, and the links with larger parameter differences can be set with different winter numbers; at this time, since the chip receiving end is adaptive, there is no need to set the equalization parameters.

[0109] The input module 82 is used to input three parts of parameter data. The first part is the pre-emphasis parameters and equalization parameters related to the chip docking scenario of the current chip product after review; the second part is the pre-emphasis parameters and equalization parameters in the new chip product; and the third part is the pre-emphasis parameters and equalization parameters verified by the application module 86.

[0110] The training module 83 is used to train the data entered by the input module 82, including classification and iteration. Since there are a lot of parameter data, they can be classified in the following ways: first, they are classified according to four scenarios, namely, "chip docking optical module scenario", "chip docking scenario behind the backplane", "chip docking scenario within the board", and "chip docking scenario between boards". The chip code in each chip docking scenario is clearly defined; secondly, each chip docking scenario is classified according to the rate, including but not limited to 1.25Gbps, 2.5Gbps, 5Gbps, 10Gbps, 12.5Gbps, 25Gbps, 26Gbps, 28Gbps, 53Gbps, 56Gbps, 58Gbps, 106Gbps, 112Gbps, 224Gbps, etc.; thirdly, the PCB board grade used in chip product design is classified, including FR4, Z2, Z4, Z6, Z7, Z8, etc.; finally, the chip docking scenarios with the same code are classified according to the channel insertion loss value, for example, they are classified from large to small according to the channel insertion loss. Iterating parameter data includes real-time updating of the entered parameters according to the "entry time" and "verification pass level". The "entry time" is based on the fact that if it is the first time to enter a new chip docking scenario, the parameters entered at this time are the latest parameters. For parameters that are not entered for the first time, in principle, the parameters entered for the last time are the latest state, but the previous parameters will not be overwritten, because it is uncertain whether the latest parameters at this time are necessarily the optimal parameters for long-term verification, and they may be iterated at any time; the "verification pass level" is based on the actual verification scenario. , the number of verification samples, the verification time, etc., among which "verification scenario" can be divided into reliability verification (temperature cycle for 48 hours, high temperature for 24 hours, low temperature for 24 hours, high temperature and high humidity for 24 hours), production line verification (high temperature aging), engineering verification (actual environment of various countries in the world), "number of verification samples" can be divided into a small number of samples (less than 50 pieces), small batch samples (50 to 500 pieces), and large batch samples (greater than 500 pieces), and "duration" can be divided into 7 days, 1 month, 3 months, 1 year, 3 years, 5 years, 10 years, etc.

[0111] The storage module 84 is used to store the parameter data trained by the training module 83, so that the query module 85 can query according to the query conditions.

[0112] The query module 85 is used to query whether there are corresponding pre-emphasis parameters and equalization parameters in the storage module 84 according to the chip docking scenario, rate, chip code, board material, channel insertion loss and other information. If yes, it enters the application module 86 to directly apply this parameter. If not, it enters the parameter adjustment module 81 to traverse the parameters.

[0113] The application module 86 is used to apply the parameters queried by the query module 85 and verify the application results of the parameters. If a problem is found with the parameter, it is necessary to enter the parameter adjustment module 81 to traverse the parameters. If no problem is found with the parameter, it is necessary to enter the entry module 82 to re-enter the verification information of the parameter, and then iterate the parameter through the training module 83.

[0114] The design module 87 is used to apply the parameters queried by the query module 85 to the chip product, so as to obtain the required parameters for product design without traversing or debugging the parameters. This module retrieves qualified parameters in the query module 85 according to the chip docking scenario, rate and other retrieval conditions, and then constrains the product design according to the board material and insertion loss value corresponding to this parameter, to ensure that the board material of the chip docking channel is at the same level and the insertion loss value is at the same level. The board material level is divided into: FR4, Z2, Z4, Z6, Z7, Z8, etc.; the insertion loss value can be divided into levels according to a fixed value, and the specific value can be divided according to each chip docking scenario. For example, with 3dB as a level, the insertion loss level of the channel is divided into 0~3dB, 3~6dB, 6~9dB, 9~12dB, 12~15dB, 15~18dB, etc.

[0115] In an exemplary embodiment, an electronic device is further provided, the electronic device being used to execute the above-mentioned method for obtaining the pre-emphasis parameters and the equalization parameters of the chip. Fig.13 A schematic diagram of the structure of an electronic device for implementing each embodiment of the present application. The electronic device may have relatively large differences due to different configurations or performances, and may include a processor (processor) 1301, a communication interface (CommunicationsInterface) 1302, a memory (memory) 1303 and a communication bus 1304, wherein the processor 1301, the communication interface 1302, and the memory 1303 communicate with each other through the communication bus 1304. The processor 1301 can call a computer program stored in the memory 1303 and can be run on the processor 1301 to execute all or part of the steps of the embodiment of the method for obtaining the pre-emphasis parameters and equalization parameters of the above-mentioned chip, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0116] The above electronic device structure does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently. For example, the input unit may include a graphics processing unit (GPU) and a microphone, and the display unit may be configured with a display panel in the form of a liquid crystal display, an organic light emitting diode, etc. The user input unit includes a touch panel and at least one of other input devices. The touch panel is also called a touch screen. Other input devices may include, but are not limited to, a physical keyboard, function keys (such as volume control buttons, switch buttons, etc.), a trackball, a mouse, and a joystick, which will not be repeated here.

[0117] The memory can be used to store software programs and various data. The memory may mainly include a first storage area for storing programs or instructions and a second storage area for storing data, wherein the first storage area may store an operating system, an application program or instructions required for at least one function (such as a sound playback function, an image playback function, etc.), etc. In addition, the memory may include a volatile memory or a non-volatile memory, or the memory may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. Volatile memory can be random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM) and direct memory bus random access memory (DRRAM).

[0118] The processor may include one or more processing units; optionally, the processor integrates an application processor and a modem processor, wherein the application processor mainly processes operations related to the operating system, user interface, and application programs, and the modem processor mainly processes wireless communication signals, such as a baseband processor. It is understandable that the modem processor may not be integrated into the processor.

[0119] In an exemplary embodiment, a readable storage medium is also provided, in which at least one computer program is stored, and the computer program is loaded and executed by a processor to implement all or part of the steps in the method for obtaining the pre-emphasis parameters and equalization parameters of the above chip. For example, the readable storage medium can be a read-only memory (ROM), a random access memory (RAM), a compact disc (CD-ROM), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0120] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the claims.

[0121] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A method for obtaining pre-emphasis parameters and equalization parameters of a chip, characterized in that: include: Obtain target design factors of the chip to be designed; Based on the target design factor, obtaining target pre-emphasis parameters and equalization parameters matching the target design factor by querying a parameter screening model; The parameter screening model records the correlation between the design factors and the pre-emphasis parameters and the equalization parameters.

2. The method according to claim 1, characterized in that The design factors include at least one of the following: docking scenario, chip code, rate, board material, channel insertion loss, and fault occurrence frequency.

3. The method according to claim 1, characterized in that The parameter screening model also records the verification passing level of each of the association relationships.

4. The method according to claim 3, characterized in that Based on the target design factor, a target pre-emphasis parameter and an equalization parameter matching the target design factor are obtained by querying a parameter screening model, including: When a plurality of target pre-emphasis parameters and equalization parameters matching the target design factor are found by querying the parameter screening model, the target pre-emphasis parameters and equalization parameters having the highest verification passing level are selected from the plurality of target pre-emphasis parameters and equalization parameters.

5. The method according to claim 1, characterized in that After acquiring the target pre-emphasis parameters and equalization parameters matching the target design factors, the method further includes: Obtaining application results of a chip product designed according to the target pre-emphasis parameters and equalization parameters; According to the application result, the target pre-emphasis parameters and equalization parameters corresponding to the target design factors in the parameter screening model are optimized.

6. The method according to any one of claims 1 to 5, characterized in that: Before acquiring the target pre-emphasis parameters and equalization parameters matching the target design factors by querying the parameter screening model based on the target design factors, the method further includes: Acquire a plurality of sample data, wherein the sample data includes: sample design factors and sample pre-emphasis parameters and equalization parameters corresponding to the sample design factors; According to the sample design factors of each of the sample data, the plurality of sample data are divided into a plurality of types; Determine the verification pass level corresponding to each type according to the verification factors corresponding to the sample data of each type, wherein the verification factors include at least one of the following: verification scenario, number of verification samples, and verification duration; The sample design factors, sample pre-emphasis parameters and equalization parameters corresponding to each of the types, and the verification are stored in association with the gear position to obtain the parameter screening model.

7. The method according to claim 6, characterized in that The obtaining of a plurality of sample data comprises: Obtaining first pre-emphasis parameters and equalization parameters that have been traversed by multiple chip products in various docking scenarios; Verifying the first pre-emphasis parameter and the equalization parameter based on at least one of the verification factors; The first pre-emphasis parameter and equalization parameter that have passed verification and the design factors corresponding to the first pre-emphasis parameter and equalization parameter that have passed verification are used as the sample data.

8. The method according to claim 6, characterized in that After obtaining the parameter screening model, the method further includes: According to the screening condition, by querying the parameter screening model, obtaining the second pre-emphasis parameter and the equalization parameter matching the screening condition; Acquire application results of a chip product corresponding to the second pre-emphasis parameter and equalization parameter; According to the application result, the second pre-emphasis parameter and the equalization parameter corresponding to the screening condition in the parameter screening model are optimized.

9. The method according to claim 8, characterized in that According to the application result, optimizing the second pre-emphasis parameter and the equalization parameter corresponding to the screening condition in the parameter screening model includes: When the application result indicates that the result is normal, raising the verification pass level corresponding to the screening condition and the second pre-emphasis parameter and the equalization parameter in the parameter screening model; When the application result indicates an abnormality, the second pre-emphasis parameter and the equalization parameter corresponding to the screening condition are adjusted, and after the adjusted second pre-emphasis parameter and the equalization parameter are verified, the adjusted second pre-emphasis parameter and the equalization parameter are used to update the second pre-emphasis parameter and the equalization parameter in the parameter screening model.

10. The method according to claim 8 or 9, characterized in that: The screening condition includes at least one of the following: docking scenario, chip code, rate, board material, channel insertion loss, and fault occurrence frequency.

11. A system for obtaining pre-emphasis parameters and equalization parameters of a chip, characterized in that: include: Parameter adjustment module, intelligent module, application module and design module; among them, The parameter adjustment module is used to traverse the pre-emphasis parameters and the equalization parameters, and send the pre-emphasis parameters and the equalization parameters to the intelligent module; The intelligent module is used to obtain target pre-emphasis parameters and equalization parameters matching the target design factors by querying parameter screening models based on the target design factors; The application module is used to obtain the application result of the chip product designed according to the target pre-emphasis parameters and equalization parameters; The design module is used to design according to the target pre-emphasis parameters and equalization parameters; The parameter screening model records the correlation between the design factors and the pre-emphasis parameters and the equalization parameters.

12. The system according to claim 11, characterized in that The intelligent module includes: an input unit, a training unit, a storage unit and a query unit; wherein, The input unit is used to receive the pre-emphasis parameters and equalization parameters sent by the parameter adjustment module; The training unit is used to train the pre-emphasis parameters and equalization parameters; The storage unit is used to store the association relationship between the design factors and the trained pre-emphasis parameters and equalization parameters to obtain the parameter screening model; The query unit is used for acquiring target pre-emphasis parameters and equalization parameters matching the target design factors from the parameter screening model based on the target design factors.

13. The system according to claim 11, characterized in that The parameter adjustment module is also used to optimize the target pre-emphasis parameters and equalization parameters corresponding to the target design factors in the parameter screening model when the application result indicates an abnormality.

14. The system according to claim 11, characterized in that The intelligent module is further configured to optimize the target pre-emphasis parameters and equalization parameters corresponding to the target design factors in the parameter screening model when the application result indicates that the application result is normal.

15. An electronic device, characterized in that: The electronic device includes a processor and a memory, the memory stores a program or instruction that can be run on the processor, and when the program or instruction is executed by the processor, the steps of the method for obtaining pre-emphasis parameters and equalization parameters of the chip as described in any one of claims 1 to 10 are implemented.

16. A readable storage medium, characterized in that: The readable storage medium stores a program or instruction, and when the program or instruction is executed by the processor, the steps of the method for obtaining pre-emphasis parameters and equalization parameters of the chip as described in any one of claims 1 to 10 are implemented.

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