Simulated annealing calculator based on floating gate transistor
Through a simulated annealing calculator based on floating gate transistors, combined with the parallel operation of probability bit units and the step-by-step cooling mechanism during the annealing process, the existing combination optimization problem solution is solved in terms of computational complexity and flexibility, and efficient solution to large-scale optimization problems and low-power applications are realized.
Patent Information
- Application Number
- CN202411553444.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-02
- Publication Date
- 2025-02-25
AI Technical Summary
Existing solutions to combinatorial optimization problems such as precision and approximation algorithms are insufficient in computational complexity and flexibility, and machine learning and deep learning methods have challenges in stability and parameter sensitivity.
An analog annealing calculator based on floating gate transistors is adopted, combined with the parallel operation of probability bit units and the gradual cooling mechanism during the annealing process, and through mechanisms such as state perturbation, digital-to-analog conversion and probability state acceptance, efficient solution to large-scale optimization problems is achieved.
It realizes efficient solution to large-scale optimization problems, especially suitable for low-power application scenarios such as large-scale combination optimization problems, machine learning and embedded systems, and improves computing efficiency and energy efficiency.
Smart Images
Figure CN119514706A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a simulated annealing calculator based on a floating gate transistor, and belongs to the field of integrated circuits. Background Art
[0002] Complex combinatorial optimization problems are a type of optimization problem that seeks extreme values in discrete states; these problems usually involve a limited solution space, and it is necessary to find a solution that minimizes or maximizes a certain objective function among these solutions. They are widely found in many fields, such as: computer science, artificial intelligence, logistics management, and communication networks.
[0003] Traditional methods for solving combinatorial optimization problems mainly include exact algorithms and approximate algorithms. Exact algorithms include branch-and-bound and dynamic programming. The principle of this type of method is to decompose the original problem into smaller problems and solve these sub-problems iteratively to obtain the global optimal solution. However, the calculation is relatively complex, lacks flexibility, and is only applicable to solving small-scale problems. Approximate algorithms include greedy algorithms and local search. This type of method cannot guarantee the optimal solution, but can only find an approximate solution within an acceptable time. It also has the disadvantages of being sensitive to parameters and having poor generalization ability.
[0004] In recent years, with the development of artificial intelligence technology, machine learning and deep learning methods have gradually been applied to solve combinatorial optimization problems, such as graph neural networks and deep reinforcement learning. The graph neural network method predicts the optimal solution or provides decision support by learning the structural characteristics of the graph, but the model required by this method is complex and has theoretical limitations. Deep reinforcement learning learns the decision-making process through interaction with the environment and gradually optimizes the decision-making strategy to achieve the goal; however, this method is very sensitive to changes in input data and has poor stability.
[0005] Compared with the above methods, simulated annealing is widely used because of its simple implementation, flexible parameters, wide application range and global search capability. The core idea of simulated annealing is to simulate the annealing process in physics, that is, random search at a high temperature, then gradually lower the temperature (annealing), perform local search at each temperature, and finally reach a stable state, that is, find the optimal solution to the problem. This method can jump out of the local optimum during the search process, thereby increasing the probability of finding the global optimal solution.
[0006] The probability bit unit is a new type of computing unit for solving optimization problems. It can be used to improve the simulated annealing algorithm. The simulated annealing algorithm based on the probability bit unit is called probability bit simulated annealing. The probability bit unit uses the superposition state and entanglement characteristics of quantum bits to realize parallel search of the solution space, and simulates the randomness of the system through the characteristics of natural fluctuations. However, the probability bit unit used for solving optimization problems mainly relies on spin electronics devices, such as magnetic tunnel junctions (MTJs). These devices usually control the state of the probability bit unit through thermal noise or spin polarization; however, thermal noise will have the problem of balancing thermal stability and noise-to-signal ratio and the problem of temperature dependence. The implementation of spin polarization will also be affected by temperature, and there is also the limitation of tunnel magnetoresistance; this design has certain limitations in the face of complex optimization problems and the flexibility of hardware implementation. Summary of the invention
[0007] In order to further improve computing efficiency and energy efficiency, the present invention combines the innovative design of floating gate transistors and probabilistic bit units to propose a new hardware implementation scheme. Floating gate transistors have good charge storage capacity and programmability, and can effectively control the electric field strength and charge distribution by adjusting the gate voltage and designing the dielectric layer. By combining the probabilistic output of the probabilistic bit unit and the gradual cooling mechanism during the annealing process, the system can quickly search in the solution space of the optimization problem and find the optimal solution by minimizing energy. The present invention is particularly suitable for low-power application scenarios such as large-scale combinatorial optimization problems, machine learning, and embedded systems.
[0008] The purpose of the present invention is to provide a simulated annealing calculator based on floating gate transistors, which can achieve efficient solution to large-scale optimization problems through innovative hardware architecture. The system relies on the parallel operation of each probability bit unit in the probability unit group, and generates probabilistic outputs through random signals generated by floating gate transistors combined with charge control of floating gate transistors. Through mechanisms such as state perturbation, digital-to-analog conversion and probabilistic state acceptance, the annealing calculator can complete complex optimization calculation tasks at the hardware level. The calculator includes: at least two probability unit groups and a data conversion module, wherein each probability unit group includes at least one probability bit unit, which functions to generate a probability output according to an input signal; the data conversion module includes a digital-to-analog converter (DAC) and a microcontroller (MCU), which is used to convert the analog input signal into a reference voltage of each probability bit unit, wherein the output of the probability bit unit is connected to the MCU digital input terminal, and the result is processed by the MCU to realize digital signal output.
[0009] Optionally, each probability bit unit includes a floating gate transistor, a source resistor, and an operational amplifier.
[0010] Optionally, the output of the probabilistic bit unit depends on the random floating gate charge inside the floating gate transistor, combined with the comparison of the input voltage Vin and the reference voltage Vref, to generate a probabilistic output Vout.
[0011] Optionally, the DAC module is connected to the probability bit unit input interface, and the analog input signal is synchronously sent to the probability bit unit through the SPI interface, and the input signal is adjusted in combination with the task.
[0012] Optionally, the output of the probability bit unit is a probabilistic voltage signal, and the microcontroller digitally outputs the signal and optimizes the subsequent disturbance process through a feedback mechanism.
[0013] Optionally, the calculator dynamically adjusts the probabilistic perturbation of the input signal through a gradual cooling annealing process and finds the global optimal solution through multiple iterations.
[0014] Optionally, the MCU has a training function. The main goal of the MCU training is to optimize the probability output of the probability bit unit by adjusting the input voltage, reference voltage and perturbation parameters, thereby improving the overall performance of the simulated annealing calculator. The purpose of training is to enable the system to dynamically adjust its state to adapt to different optimization tasks.
[0015] The present application also provides applications of the above floating gate transistor-based simulated annealing calculator in computational science, artificial intelligence, logistics management and communication networks.
[0016] The effective gain of the present invention is:
[0017] Through innovative hardware architecture, efficient solution of large-scale optimization problems is achieved. The present invention realizes efficient solution of large-scale optimization problems through innovative hardware architecture. The system relies on the parallel operation of multiple probability bit units, combined with the probabilistic output of the probability bit units and the gradual cooling mechanism during the annealing process, and generates probabilistic outputs through random signals generated by floating gate transistors combined with charge control of floating gate transistors. Through mechanisms such as state perturbation, digital-to-analog conversion, and probabilistic state acceptance, the annealing calculator can complete complex optimization calculation tasks at the hardware level; it is particularly suitable for low-power application scenarios such as large-scale combinatorial optimization problems, machine learning, and embedded systems. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0019] Figure 1is a schematic diagram of a simulated annealing calculator based on floating gate transistors composed of N probability unit groups;
[0020] Figure 2 It is a schematic diagram of the construction of a single probability bit unit in a simulated annealing calculator based on floating gate transistors;
[0021] Figure 3 It is a schematic diagram of an 8-bit multiplier of a simulated annealing calculator based on floating-gate transistors. DETAILED DESCRIPTION
[0022] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.
[0023] Embodiment 1:
[0024] This embodiment provides a simulated annealing calculator based on floating gate transistors, such as Figure 1 As shown, the analog annealing calculator based on floating gate transistors includes at least two probability unit groups and a data conversion module, each probability unit group includes at least one probability bit unit, and the probability bit unit is used to generate a probability output according to an input signal. The data conversion module includes a digital-to-analog converter (DAC) and a microcontroller (MCU), which are used to convert the analog input signal into a reference voltage of each probability bit unit, wherein the output of each probability bit unit is connected to the MCU digital input terminal, and the result is processed by the MCU to realize the digital signal output.
[0025] The structure of a single probability bit unit is as follows Figure 2 As shown, each probability bit unit includes a floating gate transistor, a source resistor and an operational amplifier, which is used to generate a probabilistic output according to an input signal and a random signal obtained by the floating gate transistor.
[0026] The output of the probabilistic bit cell depends on the random floating gate charge inside the floating gate transistor, combined with the comparison of the input voltage Vin and the reference voltage Vref, to generate a probabilistic output Vout.
[0027] The DAC module is connected to the input interface of the probability bit unit, and sends the analog input signal to the probability bit unit synchronously through the SPI interface, and adjusts the input signal in combination with the task.
[0028] The output of the probability bit unit is a probabilistic voltage signal, which is digitized and output by the microcontroller, and the subsequent disturbance process is optimized through a feedback mechanism.
[0029] The calculator dynamically adjusts the probabilistic perturbations of the input signal through a gradual cooling annealing process and finds the global optimal solution through multiple iterations.
[0030] MCU has a training function. The main goal of MCU training is to optimize the probability output of the probability bit unit by adjusting the input voltage, reference voltage and perturbation parameters, thereby improving the overall performance of the simulated annealing calculator. The purpose of training is to enable the system to dynamically adjust its state to adapt to different optimization tasks.
[0031] Multiple probability bit units in the probability unit group operate in parallel, and the random signal generated by the floating gate transistor is combined with the charge control of the random floating gate charge inside the floating gate transistor to generate a probability output; through mechanisms such as state perturbation, digital-to-analog conversion and probabilistic state acceptance, the annealing calculator can complete complex optimization calculation tasks at the hardware level.
[0032] Embodiment 2:
[0033] This embodiment provides an 8-bit multiplication operation of a simulated annealing calculator based on floating gate transistors, see Figure 3 The 8-bit multiplication operation includes two probability unit groups, each of which includes an 8-bit probability bit unit, which is used to generate a probability output according to the input signal. The data conversion module includes a digital-to-analog converter (DAC) and a microcontroller (MCU), which is used to convert the analog input signal into a reference voltage of each probability bit unit, wherein the output of the probability bit unit is connected to the MCU digital output terminal, and the result is processed by the MCU to realize the digital signal output.
[0034] The entire link optimization process is as follows:
[0035] Suppose there are two binary numbers A and B, which have n and m bits respectively, and their product P is expressed as:
[0036] P=A×B
[0037] Where A and B can be expressed as:
[0038]
[0039] a i (i=1,2,……n) represents the i-th digit of the binary number A, b j (j=1,2,...m) represents the jth bit of the binary number B; then the product P is the product and accumulation of all corresponding bits:
[0040]
[0041] In the probabilistic architecture, input values A and B are processed in parallel by multiple probabilistic bit units, and the multiplication result is obtained by state perturbation and accumulation.
[0042] In order to optimize the output of the multiplier, we first need to define an error function that measures the difference between the output result Pout and the target product Ptarget. The error function E can be expressed as:
[0043]
[0044] Where Pout is the current product output obtained by the probability bit unit calculator, and Ptarget is the true product of the input binary numbers A and B. The error function reflects the gap between the output and the expected result. The optimization goal is to minimize the error by adjusting the input voltage, disturbance intensity and other parameters of the probability bit unit.
[0045] The output of each probability bit unit is related to its input voltage Vin and reference voltage Vref. The probability output of the probability bit unit can be represented by the Sigmoid function:
[0046]
[0047] Where S is the output state (0 or 1) of the probabilistic bit unit, that is, a random signal generated according to the random floating gate charge inside the floating gate transistor, and Vin is the input voltage.
[0048] In order to reduce the error, the MCU can adjust the input voltage Vin and reference voltage Vref of each probability bit unit. By calculating the partial derivative of the error function with respect to the input voltage, we can obtain the updated formula for voltage adjustment:
[0049]
[0050] Among them, η is the learning rate, which is used to control the adjustment step size, is the gradient of the error function with respect to the input voltage.
[0051] The output state of the probability bit unit is affected by its internal random perturbation, and the perturbation intensity σ will affect the output stability of the probability. A larger perturbation intensity will increase the randomness of the system's output, while a smaller perturbation intensity will make the system more likely to fall into a local optimal solution.
[0052] The output of the system can be optimized by adjusting the perturbation intensity. During the annealing process, as the system temperature T decreases, the perturbation intensity should be gradually reduced so that the system converges. Therefore, the optimization formula for the perturbation intensity is:
[0053]
[0054] Among them, σ0 is the initial perturbation intensity, T is the current temperature, and T0 is the initial temperature.
[0055] The MCU can dynamically adjust the disturbance intensity by controlling the rate of decrease of the temperature T, so that the system can explore more solution spaces in the early stage and converge to the correct multiplication result in the later stage.
[0056] The system can adjust the input voltage and reference voltage of each probability bit unit based on the output feedback. Assuming that there is an error between the current output and the expected result, the MCU can adjust the reference voltage Vref through the feedback mechanism to make the probability output of the probability bit unit closer to the ideal state.
[0057] The update formula of the reference voltage is:
[0058] V ref (t+1)=V ref (t)+η(P out -P target )
[0059] Among them, V ref (t) is the reference voltage at the current moment, P target is the expected product value, P out It is the output result of the current probability bit unit.
[0060] In actual design, the output of the probability bit unit is usually accumulated to obtain the final multiplication result. For further optimization, a weight w can be assigned to the output of each probability bit unit. i , and dynamically adjust the weights to minimize the error.
[0061] The weight update can be achieved by gradient descent:
[0062]
[0063] Among them, w i (t) is the weight value at the current moment, is the gradient of the error function with respect to the weights.
[0064] In summary, the optimization process of MCU can be described as dynamically adjusting the input voltage, reference voltage, perturbation strength and weight by minimizing the error function to obtain accurate multiplication output. Through the above operations, MCU can gradually adjust the input voltage, reference voltage, perturbation strength and weight of the probability bit unit to optimize the performance of the entire multiplier. During the annealing process, MCU can dynamically adjust these parameters according to the output feedback, so that the system gradually converges to the global optimal solution in complex optimization tasks, and finally achieves accurate multiplication results.
[0065] Some steps in the embodiments of the present invention may be implemented using software, and the corresponding software program may be stored in a readable storage medium, such as a CD or a hard disk.
[0066] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims
1. A simulated annealing calculator based on floating gate transistors, characterized in that: The simulated annealing calculator includes at least two probability unit groups and a data conversion module, each probability unit group includes at least one probability bit unit, and the probability bit unit includes a floating gate transistor, a source resistor and an operational amplifier; the probability bit unit is used to generate a probability output according to an input signal and a random floating gate charge inside the floating gate transistor; The data conversion module includes a microcontroller and a digital-to-analog converter, which is used to convert an analog input signal into a reference voltage of each probability bit unit.
2. The simulated annealing calculator according to claim 1, characterized in that: In the probability bit unit, the drain terminal of the floating gate transistor is connected to the voltage Vdd, the gate terminal is connected to the input voltage Vin, the source terminal is grounded through the source resistor, and the source terminal is also connected to the non-inverting input terminal of the operational amplifier, the inverting input terminal of the operational amplifier is connected to the reference voltage Vref, and the output terminal of the operational amplifier serves as the output Vout of the probability bit unit; The output end of the microcontroller is connected to the input end of the digital-to-analog converter through a serial peripheral interface.
3. The floating gate transistor-based simulated annealing calculator according to claim 2, characterized in that: The simulated annealing calculator dynamically adjusts the probabilistic disturbance of the input signal through a gradually cooling annealing process and finds the global optimal solution through multiple iterations.
4. The floating gate transistor-based simulated annealing calculator according to claim 3, characterized in that: The microcontroller dynamically adjusts the disturbance intensity by controlling the decreasing rate of the temperature T. The optimization formula of the disturbance intensity of the probabilistic disturbance is: Among them, σ0 is the initial perturbation intensity, T is the current temperature, and T0 is the initial temperature.
5. The floating gate transistor-based simulated annealing calculator according to claim 4, characterized in that: The microcontroller adjusts the input voltage and reference voltage of each probability bit unit through the output of each probability bit unit so that the probability output of the probability bit unit is closer to an ideal state.
6. The floating gate transistor-based simulated annealing calculator according to claim 5, characterized in that: The updating formula of the reference voltage is: V ref (t+1)=V ref (t)+η(P out -P target ) Among them, V ref (t) is the reference voltage at the current moment, P target is the expected calculated value, P out is the output result of the current probability bit unit, and η is the learning rate.
7. The floating gate transistor-based simulated annealing calculator according to claim 6, characterized in that: The microcontroller assigns a weight w to the output of each probability bit unit. i , and dynamically adjust the weights to minimize the error function, which is 8. The floating gate transistor-based simulated annealing calculator according to claim 7, characterized in that: Weight w i The update is achieved through gradient descent, momentum method, AdaGrad and other methods.
9. Application of the simulated annealing calculator based on floating gate transistors as described in any one of claims 1 to 8 in computational science, artificial intelligence, logistics management and communication networks.