Display panel and display device

Abstract

The invention provides a display panel and a display device. The display panel comprises a plurality of binding terminals located in the binding area, the binding terminals in the binding area are divided into a plurality of units, and the binding terminals in the same unit are divided into a first terminal group, a second terminal group, a third terminal group and a fourth terminal group; the first terminal group, the second terminal group, the third terminal group and the fourth terminal group respectively comprise a plurality of binding terminals, the binding terminals of the first terminal group, the second terminal group and the third terminal group are configured to be bound with output terminals of a test chip, and the binding terminals of the fourth terminal group are configured to be bound with input terminals of the test chip; in the same unit, the second terminal set is located on the side, away from the display area, of the first terminal set, the fourth terminal set is located on the side, away from the display area, of the second terminal set, and the third terminal set is located on the side, away from the display area, of the second terminal set and the side, close to the display area, of the fourth terminal set. The narrow bezel of the display panel can be realized.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, consumers have an increasingly strong demand for display panels with narrow borders. A test chip is provided in the border area of ​​the display panel, and the test circuit on the test chip is used to detect related defects such as short circuit or open circuit of the display panel to improve the yield of the display panel. The test circuit includes multiple rows of switching transistors, which occupy a large space in the border area. If a narrow border is to be achieved, one way to achieve it is to reduce the space occupied by the switching transistor and further reduce the size of the test chip. One solution adopted in the related art is to adjust the process to reduce the size of the switching transistor to ensure that the same number of switching transistors are placed in the limited space after the border is reduced, but the process adjustment will increase the difficulty of the process and even reduce the output yield. Summary of the invention

[0003] In view of the shortcomings of the related art, the present application proposes a display panel and a display device to solve the problem in the related art of how to place a constant number and constant size of switching transistors in a limited space while reducing the size of a test chip.

[0004] An embodiment of the present application provides a display panel, the display panel comprising a display area and a non-display area located at least on one side of the display area; the non-display area comprises a binding area located on one side of the display area;

[0005] The display panel includes a plurality of binding terminals located in the binding area, the plurality of binding terminals in the binding area are divided into a plurality of units, each unit includes a plurality of binding terminals, and the binding terminals of each unit are bound to a test chip; the binding terminals of the same unit are divided into a first terminal group, a second terminal group, a third terminal group and a fourth terminal group; the first terminal group, the second terminal group, the third terminal group and the fourth terminal group respectively include a plurality of binding terminals, the binding terminals of the first terminal group, the second terminal group and the third terminal group are configured to be bound to the output terminals of the test chip, and the binding terminals of the fourth terminal group are configured to be bound to the input terminals of the test chip;

[0006] In the same unit, the second terminal group is located on the side of the first terminal group away from the display area, the fourth terminal group is located on the side of the second terminal group away from the display area, the third terminal group is located on the side of the second terminal group away from the display area and on the side of the fourth terminal group close to the display area; the direction from the display area to the binding area is the first direction, and the binding terminals of the first terminal group and the binding terminals of the second terminal group are arranged along a second direction intersecting with the first direction.

[0007] In some embodiments, in the same unit, the first terminal group, the second terminal group, and the third terminal group are arranged in a direction from the display area to the binding area.

[0008] In some embodiments, a distance between the third terminal group and the second terminal group is smaller than a distance between the third terminal group and the fourth terminal group.

[0009] In some embodiments, the binding area includes a first side and a second side opposite to each other in the second direction; in a unit adjacent to the first side, the binding terminals of the third terminal group are located on a side of the area of ​​the second terminal group facing the first side, away from the display area; and / or, in a unit adjacent to the second side, the binding terminals of the third terminal group are located on a side of the area of ​​the second terminal group facing the second side, away from the display area.

[0010] In some embodiments, the third terminal group includes at least two sub-terminal groups arranged along the second direction, and each of the sub-terminal groups includes a plurality of binding terminals arranged along the first direction.

[0011] The present embodiment further provides a display device, comprising the aforementioned display panel and a test chip located in a binding area of ​​the display panel, wherein the test chip is provided with a test circuit, wherein the test circuit comprises a plurality of electrically connected switch transistors, wherein each of the switch transistors is respectively configured to be connected to an output terminal of the corresponding test chip, wherein the width of the switch transistor is T, the width of a line connected to the switch transistor is W, the minimum distance between the central axes of two adjacent lines is S, and the distance in the second direction between the geometric center of the binding terminal of the first terminal group and the geometric center of the binding terminal adjacent to the binding terminal and located in the second terminal group is p 1 ,

[0012] In some embodiments, the multiple switching transistors of the same test circuit include a first switching transistor group and a second switching transistor group, the multiple switching transistors in the first switching transistor group and the multiple switching transistors in the second switching transistor group are alternately distributed in the second direction, and the switching transistors in the first switching transistor group and the switching transistors adjacent to them in the second switching transistor group are staggered in the first direction; in the same unit, when the first terminal group, the second terminal group and the third terminal group are arranged in the direction from the display area to the binding area, the multiple binding terminals in the first terminal group, the second terminal group and the third terminal group are alternately distributed in the second direction, and the binding terminals in the first terminal group and the binding terminals adjacent to them in the second terminal group are staggered in the first direction, the binding terminals in the second terminal group and the binding terminals adjacent to them in the third terminal group are staggered in the first direction, and each of the switching transistors is respectively connected to the corresponding binding terminal.

[0013] In some embodiments, the binding terminals of the third terminal group are arranged along a second direction intersecting the first direction, the orthographic projections of the plurality of switch transistors on the surface of the display panel facing the test chip are all located between the third terminal group and the fourth terminal group, the plurality of switch transistors in the first switch transistor group and the plurality of switch transistors in the second switch transistor group are all arranged along the second direction intersecting the first direction; the geometric center of the binding terminal of the second terminal group is adjacent to the binding terminal and is located at a distance p in the second direction from the geometric center of the binding terminal of the third terminal group. 2 ,

[0014] In some embodiments, the plurality of switch transistors are disposed on a side of the fourth terminal group close to the display area.

[0015] In some embodiments, the binding area includes a first side and a second side opposite to each other in the second direction, and in a unit adjacent to the first side, when the binding terminal of the third terminal group is located on a side of an area of ​​the second terminal group facing the first side away from the display area, the first orthographic projections of the plurality of switch transistors connected to the binding terminals of the first terminal group and the second terminal group on the surface of the display panel facing the test chip are all located between the second terminal group and the fourth terminal group, and the second orthographic projections of the plurality of switch transistors connected to the binding terminals of the third terminal group on the surface are located in an area of ​​the first orthographic projection facing the first side and away from the display area;

[0016] And / or, the binding area includes a first side and a second side opposite to each other in the second direction, and in a unit adjacent to the second side, the binding terminal of the third terminal group is located on a side of the area of ​​the second terminal group facing the second side and away from the display area; the first orthographic projections of the multiple switching transistors connected to the binding terminals of the first terminal group and the second terminal group on the surface of the display panel facing the test chip are all located between the second terminal group and the fourth terminal group, and the second orthographic projections of the multiple switching transistors connected to the binding terminals of the third terminal group on the surface are located in the area of ​​the first orthographic projection facing the second side and away from the display area.

[0017] In some embodiments, the third terminal group includes a first sub-terminal group and a second sub-terminal group arranged along the second direction, and the first sub-terminal group and the second sub-terminal group both include a plurality of binding terminals arranged along the first direction; the plurality of binding terminals in the first sub-terminal group and the plurality of binding terminals in the second sub-terminal group are alternately distributed in the first direction, and the binding terminals in the first sub-terminal group and the binding terminals adjacent thereto in the second sub-terminal group are staggered in the second direction; the geometric center of the binding terminal of the first sub-terminal group is at a distance p from the geometric center of the binding terminal adjacent to the binding terminal and located in the second sub-terminal group in the first direction. 3 ,

[0018] In some embodiments, an orthographic projection of the third terminal group on the first side of the bonding area at least partially overlaps with an orthographic projection of the fourth terminal group on the first side of the bonding area.

[0019] The beneficial effects of this application include:

[0020] In the present embodiment, the binding terminals bound to the output terminals of the test chip in each unit are arranged as a first terminal group, a second terminal group and a third terminal group, and the third terminal group is located on the side of the second terminal group away from the display area and on the side of the fourth terminal group close to the display area. Compared with the scheme of arranging only one terminal group or two terminal groups, under the premise that the number of binding terminals bound to the output terminals of the test chip remains unchanged, the number of binding terminals in the first terminal group and the second terminal group can be reduced, and the distance p in the second direction between the geometric center of the binding terminal in the first terminal group and the geometric center of the binding terminal adjacent to the binding terminal and located in the second terminal group can be increased. Furthermore, the arrangement mode of the switching transistors on the test chip can be changed accordingly, and the density of the arrangement of the switching transistors can be increased, so that the switching transistors with the same number and size can be arranged on a smaller test chip, thereby further reducing the layout area of ​​the binding area of ​​the display panel, which is conducive to the narrow frame of the display panel.

[0021] Additional aspects and advantages of the present application will be partially given in the following description, which will become apparent from the following description, or will be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0023] Figure 1 Shown is a schematic diagram of an exemplary structure of a display panel;

[0024] Figure 2 Shown is a schematic diagram of the layout structure of a binding area of ​​a display panel / display device provided by an exemplary embodiment of the present application;

[0025] Figure 3 Shown is a schematic diagram of the layout structure of a binding area of ​​a display panel / display device provided by an exemplary embodiment of the present application;

[0026] Figure 4 Shown is a schematic diagram of the layout structure of a binding area of ​​a display panel / display device provided by an exemplary embodiment of the present application;

[0027] Figure 5 Shown Figure 4 A diagram comparing the layout structure diagram of the enlarged layout at A in the middle with the layout structure diagram of a display panel provided by an exemplary embodiment;

[0028] Figure 6 The figure shows a comparison of the layout structure data of a display panel of a related art and an exemplary embodiment of the present application.

[0029] In the figure: 100-binding terminal; 10-first terminal group; 20-second terminal group; 30-third terminal group; 31-first sub-terminal group; 32-second sub-terminal group; 40-fourth terminal group; 200-switching transistor; 50-first switching transistor group; 60-second switching transistor group; 1-first scanning signal binding unit; 2-data signal binding unit; 3-second scanning signal binding unit; AA-display area; NA-non-display area; BA-binding area; L 1 - First side; L 2 - Second side. DETAILED DESCRIPTION

[0030] The display panel and the display device in the embodiments of the present application are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the features in the following embodiments can complement or be combined with each other.

[0031] The present application provides a display panel, combined with Figures 1 to 5 As shown, Figure 1 FIG. 1 is a schematic diagram of the layout structure of the display panel. Figures 2 to 4 FIG. 1 is a schematic diagram showing the layout structure of the binding area BA of the display panel in several exemplary embodiments provided in the present application. Figure 5 Shown Figure 4 The enlarged structural diagram at A in the figure is compared with the schematic diagram of the layout structure of the display panel provided by an exemplary embodiment. Figure 1 As shown, the display panel includes a display area AA and a non-display area NA located at least on one side of the display area AA; the non-display area NA includes a binding area BA located on one side of the display area AA; Figure 2 As shown, the display panel includes a plurality of binding terminals 100 located in the binding area BA, the plurality of binding terminals 100 of the binding area BA are divided into a plurality of units, each unit includes a plurality of binding terminals 100, and the binding terminals 100 of each unit are bound to a test chip; the binding terminals 100 of the same unit are divided into a first terminal group 10, a second terminal group 20, a third terminal group 30 and a fourth terminal group 40; the first terminal group 10, the second terminal group 20, the third terminal group 30 and the fourth terminal group 40 respectively include a plurality of binding terminals 100, and the binding terminals 100 of the first terminal group 10, the second terminal group 20 and the third terminal group 30 are configured to be bound to the test chip. The output terminals of the test chip are bound, and the binding terminals 100 of the fourth terminal group 40 are configured to be bound to the input terminals of the test chip; in the same unit, the second terminal group 20 is located on the side of the first terminal group 10 away from the display area AA, the fourth terminal group 40 is located on the side of the second terminal group 20 away from the display area AA, and the third terminal group 30 is located on the side of the second terminal group 20 away from the display area AA and on the side of the fourth terminal group 40 close to the display area AA; the direction from the display area AA to the binding area BA is the first direction y, and the binding terminals 100 of the first terminal group 10 and the binding terminals 100 of the second terminal group 20 are arranged along the second direction x intersecting with the first direction y.

[0032] In the present embodiment, the binding terminals bound to the output terminals of the test chip in each unit are arranged as a first terminal group 10, a second terminal group 20 and a third terminal group 30, and the third terminal group 30 is located on the side of the second terminal group 20 away from the display area AA and on the side of the fourth terminal group 40 close to the display area AA. Compared with the scheme of arranging only one terminal group or two terminal groups, under the premise that the number of binding terminals bound to the output terminals of the test chip remains unchanged, the number of binding terminals 100 in the first terminal group and the second terminal group can be reduced, so that the distance p between the geometric center of the binding terminal 100 in the first terminal group 10 and the geometric center of the binding terminal 100 adjacent to the binding terminal 100 and located in the second terminal group 20 in the second direction x can be increased, and further, the arrangement mode of the switching transistor 200 on the test chip can be changed accordingly, and the density of the arrangement of the switching transistor 200 can be improved, so that the switching transistor 200 with the same number and size can be arranged on a smaller test chip, thereby further reducing the layout area of ​​the display panel binding area BA, which is conducive to the narrow frame of the display panel.

[0033] For example, in this embodiment, by increasing p, the arrangement of the switch transistors 200 on the test chip can be further changed. Figure 5 As shown, the arrangement of three adjacent switch transistors 200 in different rows in three rows in an exemplary embodiment of the related art is improved to the arrangement of two adjacent switch transistors 200 in different rows in two rows in this embodiment. Thus, the length occupied by the switch transistors 200 in the first direction y can be reduced without changing the size of the switch transistors 200 themselves and the line width and line spacing of the routing lines connected to the switch transistors 200. Moreover, since the density of the switch transistors 200 increases, when the same number of switch transistors 200 are arranged, the length occupied by the switch transistors 200 in the second direction x changes less overall. Furthermore, the length of the test chip in the first direction y is reduced, which is conducive to the narrow frame of the display panel.

[0034] In one example, if Figure 6 The following table shows the structural parameter comparison between the related art and an exemplary embodiment of the present application. Figure 5As shown, the width T of the switch transistor 200 remains unchanged at 14μm; the line width W connected to the switch transistor 200 remains unchanged at 16μm; and the line spacing S remains unchanged at 5μm. The distance p between the geometric center of the binding terminal 100 in the first terminal group 10 and the geometric center of the binding terminal 100 adjacent to the binding terminal 100 and located in the second terminal group 20 in the second direction x increases from 14μm in the related art to 15μm, the arrangement of the switch transistor 200 changes from 3 rows to 2 rows, and the length of the test chip in the first direction y decreases from 333μm to 220μm, and the length in the first direction y decreases by 113μm. It can be seen that the length of the test chip in the first direction y decreases significantly. At the same time, the length of the switch transistor 200 in the second direction x increases from 84μm to 90μm, and it can be seen that the length of the switch transistor 200 as a whole in the second direction x increases less, and the size in the second direction x is less affected. In summary, by increasing p, the size of the test chip can be reduced, and the overall narrow frame of the display panel can be further improved.

[0035] In some embodiments, Figure 2 As shown, the multiple binding terminals 100 of the binding area BA are divided into a first scan signal binding unit 1, a data signal binding unit 2 and a second scan signal binding unit 3, each unit includes multiple binding terminals 100, and the binding terminals 100 of each unit are respectively bound to the corresponding test chip. The binding terminals of the first terminal group 10, the second terminal group 20 and the third terminal group 30 in the first scan signal binding unit 1 and the second scan signal binding unit 3 are connected to the scan line on the side close to the display area AA, and the side away from the display area AA is used to connect to the corresponding switch transistor 200 in the test circuit on the test chip for circuit testing. The first terminal group 10, the second terminal group 20 and the third terminal group 30 in the data signal binding unit 2 are connected to the data line on the side close to the display area AA, and the side away from the display area AA is used to connect to the corresponding switch transistor 200 in the test circuit on the test chip for circuit testing.

[0036] In some embodiments, the switching transistor 200 connected to the binding terminal 100 in the first scan signal binding unit 1 is connected to the gate drive signal line (GO), the switching transistor 200 connected to the binding terminal 100 in the second scan signal binding unit 3 is connected to the gate enable signal line (GE), and the switching transistor 200 connected to the binding terminal 100 in the data signal binding unit 2 is connected to the data output signal line (DO) and the timing control signal line (DE).

[0037] In some embodiments, the display panel may be an electronic paper display panel, an LCD (liquid crystal display), or an OLED (organic light emitting diode).

[0038] In some embodiments, the binding terminals 100 of the first terminal group 10 and the binding terminals 100 of the second terminal group 20 are arranged at intervals along the second direction x.

[0039] In some embodiments, the lengths of the binding terminals 100 in the first terminal group 10 and / or the second terminal group 20 in the first direction y are the same. In other embodiments, the lengths of the binding terminals 100 in the first terminal group 10 and / or the second terminal group 20 in the first direction y are different.

[0040] In some embodiments, the lengths of the binding terminals 100 in the first terminal group 10 and / or the second terminal group 20 in the second direction x are the same. In other embodiments, the lengths of the binding terminals 100 in the first terminal group 10 and / or the second terminal group 20 in the second direction x are different.

[0041] In some embodiments, each binding terminal 100 in the first terminal group 10 and / or the second terminal group 20 is a binding pad.

[0042] In some embodiments, the projection shape of the orthographic projection of each binding terminal 100 in the first terminal group 10 and / or the second terminal group 20 on the display panel is a rectangle.

[0043] In some embodiments, Figure 2 As shown, in the same unit, the first terminal group 10, the second terminal group 20 and the third terminal group 30 are arranged in a direction from the display area AA to the binding area BA.

[0044] In this embodiment, a first terminal group 10, a second terminal group 20 and a third terminal group 30 are arranged in sequence along the same direction in each unit, so the arrangement of the first terminal group 10, the second terminal group 20 and the third terminal group 30 is relatively regular, and the arrangement of the wiring connected to the multiple binding terminals 100 in the first terminal group 10, the second terminal group 20 and the third terminal group 30 is relatively consistent, which is more convenient for wiring and binding with the test chip, avoiding signal crosstalk caused by wiring overlap.

[0045] In some embodiments, considering that the provision of the third terminal group 30 will increase the area occupied by the binding terminal 100 in the first direction y, it is possible to consider reducing the length L of the binding terminal 100 in the first terminal group 10 and the second terminal group 20 in the first direction y. At the same time, in order to ensure the binding contact area requirements of the chip binding terminal 100, the width W of the binding terminal 100 in the first terminal group 10 and the second terminal group 20 in the second direction x can be further increased to keep the area of ​​the binding terminal 100 approximately unchanged.

[0046] In some examples, such as Figure 2As shown, the area range of the binding terminal 100 in this embodiment is: 1125 μm 2 ≤W*L≤1300μm 2 ; The value ranges of W and L are: W≥13μm, 70μm≤L≤75μm.

[0047] In some embodiments, Figure 2 As shown, the distance between the geometric center of the binding terminal 100 in the first terminal group 10 and the geometric center of the binding terminal 100 adjacent to the binding terminal 100 and located in the second terminal group 20 in the second direction x is p 1 , 15μm≤p 1 ≤16μm.

[0048] In some embodiments, the distance between the geometric center of the binding terminal 100 in the second terminal group 20 and the geometric center of the binding terminal 100 adjacent to the binding terminal 100 and located in the third terminal group 30 in the second direction x is p. 2 , 15μm≤p 2 ≤16μm.

[0049] In some embodiments, the distance between the third terminal set 30 and the second terminal set 20 is smaller than the distance between the third terminal set 30 and the fourth terminal set 40 .

[0050] In this embodiment, the switching transistor 200 can be arranged between the third terminal group 30 and the fourth terminal group 40, so that the third terminal group 30, the second terminal group 20 and the first terminal group 10 are all located on the side of the switching transistor 200 close to the display area AA so that the binding terminal 100 is directly connected to the switching transistor 200, which is convenient for designing straight lines without bending, saving wiring space, and improving the space utilization of the binding area BA of the display panel.

[0051] In some embodiments, multiple binding terminals 100 of the same unit also include a fifth terminal group (not shown in the figure) located on the side of the third terminal group 30 close to the fourth terminal group 40, so as to further increase the spacing between adjacent binding terminals 100 to flexibly set the arrangement of the switching transistor 200.

[0052] In some embodiments, Figure 3 As shown, the bonding area BA includes first sides L opposite to each other in the second direction x. 1 and the second side L 2 ; and the first side L 1 In the adjacent units, the binding terminals 100 of the third terminal group 30 are located on the second terminal group 20 toward the first side L 1 The area is away from the side of the display area AA; and / or, the area is away from the second side L 2In the adjacent units, the binding terminals 100 of the third terminal group 30 are located on the second terminal group 20 toward the second side L 2 The area is away from the side of the display area AA.

[0053] In this embodiment, the multiple binding terminals 100 of the third terminal group 30 are located in the side space, which can avoid the third terminal group 30 occupying the space on the side of the second terminal group 20 away from the display area AA, and can further avoid the space occupied by the third terminal group 30 increasing the overall length of the multiple binding terminals 100 in the first direction y. Therefore, the space of the non-display area NA can be fully utilized while improving the narrow frame degree of the display panel.

[0054] In addition, in this embodiment, the first side L 1 In the adjacent units, the binding terminals 100 of the third terminal group 30 are located on the second terminal group 20 toward the first side L 1 The area is away from the display area AA. So that the binding terminals 100 in the third terminal group 30 and the binding terminals 100 in the second terminal group 20 are respectively connected to the switch transistor 200 through straight lines, wherein the multiple binding terminals 100 in the second terminal group 20 can be connected to the switch transistor 200 on the test chip through the lines extending along the first direction y, and the multiple binding terminals 100 in the third terminal group 30 can be connected to the switch transistor 200 on the test chip through the lines extending along the second direction x. Similarly, with the second side L 2 In the adjacent units, the binding terminals 100 of the third terminal group 30 are located on the second terminal group 20 toward the second side L 2 When the area is away from the side of the display area AA, the same beneficial effect is achieved. No further details will be given here.

[0055] In some embodiments, the bonding area BA includes first sides L opposite to each other in the second direction x. The bonding area BA includes first sides L opposite to each other in the second direction x. 1 and the second side L 2 ; and the first side L 1 In the adjacent units, the binding terminals 100 of the third terminal group 30 are located on the second terminal group 20 toward the first side L 1 The area is away from the side of the display area AA.

[0056] In some embodiments, the bonding area BA includes first sides L opposite to each other in the second direction x. The bonding area BA includes first sides L opposite to each other in the second direction x. 1 and the second side L 2 ; and the second side L 2 In the adjacent units, the binding terminals 100 of the third terminal group 30 are located on the second terminal group 20 toward the second side L 2 The area is away from the side of the display area AA.

[0057] In some embodiments, Figure 3 As shown, the bonding area BA includes first sides L opposite to each other in the second direction x. 1 and the second side L 2 ; and the first side L 1 In the adjacent units, the binding terminals 100 of the third terminal group 30 are located on the second terminal group 20 toward the first side L 1 The area of ​​the display area AA is away from the second side L 2 In the adjacent units, the binding terminals 100 of the third terminal group 30 are located on the second terminal group 20 toward the second side L 2 The area is away from the side of the display area AA.

[0058] In some embodiments, the third terminal group 30 includes at least two sub-terminal groups arranged along the second direction x, and each sub-terminal group includes a plurality of binding terminals 100 arranged along the first direction y. This embodiment can be adapted to when the test chip is bound to the binding area BA, the test chip is provided with a plurality of switch transistors 200, and the plurality of sub-terminal groups arranged along the second direction x in the third terminal group 30 can be respectively connected to the respective groups of switch transistors 200.

[0059] In some embodiments, Figure 3 As shown, the third terminal group 30 includes a first sub-terminal group 31 and a second sub-terminal group 32 arranged along the second direction x, and the test chip bound to the binding area BA is provided with two groups of staggered switching transistors 200, and the multiple binding terminals 100 in the first sub-terminal group 31 are respectively connected to one group of switching transistors 200, and the multiple binding terminals 100 in the second sub-terminal group 32 are respectively connected to the remaining group of switching transistors 200.

[0060] Based on the same inventive concept, this embodiment also provides a display device, such as Figure 2 As shown, the display panel and the test chip located on the binding area BA of the display panel are included. The test chip is provided with a test circuit. The test circuit includes a plurality of electrically connected switch transistors 200. Each switch transistor 200 is respectively configured to be connected to an output terminal of the corresponding test chip. The width of the switch transistor 200 is T. The width of the line connected to the switch transistor 200 is W. The minimum distance between the central axes of two adjacent lines is S. The geometric center of the binding terminal 100 of the first terminal group 10 is adjacent to the binding terminal 100 and located in the second terminal group 20. The distance in the second direction x is p 1 ,

[0061] In this embodiment, by setting p 1The value range of is used to realize that the arrangement of the switch transistors 200 is as compact as possible to reduce the length occupied by the multiple switch transistors 200 in the first direction y, thereby reducing the size of the test chip to improve the narrow frame degree of the display panel.

[0062] In one example, the width T of the switch transistor 200 is 14 μm, the line width W of the line connected to the switch transistor 200 is 6 μm, the line spacing S is 5 μm, and the p 1 ≥15μm.

[0063] In some embodiments, Figure 2 As shown, multiple switch transistors 200 of the same test circuit include a first switch transistor group 50 and a second switch transistor group 60, and the multiple switch transistors 200 in the first switch transistor group 50 and the multiple switch transistors 200 in the second switch transistor group 60 are alternately distributed in the second direction x; and the switch transistors 200 in the first switch transistor group 50 and the switch transistors 200 adjacent thereto in the second switch transistor group 60 are staggered in the first direction y; in the same unit, when the first terminal group 10, the second terminal group 20 and the third terminal group 30 are arranged in the direction from the display area to the binding area, the multiple binding terminals in the first terminal group 10, the second terminal group 20 and the third terminal group 30 are alternately distributed in the second direction x, and the binding terminals 100 in the first terminal group 10 and the binding terminals 100 adjacent thereto in the second terminal group 20 are staggered in the first direction y, and the binding terminals in the second terminal group 20 and the binding terminals 100 adjacent thereto in the third terminal group 30 are staggered in the first direction y, and each switch transistor 200 is respectively connected to the corresponding binding terminal 100.

[0064] In this embodiment, the multiple switch transistors 200 in the first switch transistor group 50 and the second switch transistor group 60 are alternately staggered and distributed, and the multiple binding terminals 100 in the first terminal group 10, the second terminal group 20 and the third terminal group 30 can be arranged more compactly to fully utilize the space of the test chip. Thus, the size of the test chip can be reduced, and the degree of narrow frame of the display panel can be further improved.

[0065] In some embodiments, the plurality of switch transistors 200 are disposed on a side of the fourth terminal group 40 close to the display area AA.

[0066] In this embodiment, the switch transistor 200 can be connected to the first terminal group 10, the second terminal group 20, and the third terminal group 30 through wiring extending along the first direction y, and the arrangement is compact, which is conducive to narrowing the frame of the display panel.

[0067] In some embodiments, Figure 2As shown, the binding terminals 100 of the third terminal group 30 are arranged along the second direction x intersecting with the first direction y, the orthographic projections of the plurality of switch transistors 200 on the surface of the display panel facing the test chip are all located between the third terminal group 30 and the fourth terminal group 40, the plurality of switch transistors 200 in the first switch transistor group 50 and the plurality of switch transistors 200 in the second switch transistor group 60 are all arranged along the second direction x intersecting with the first direction y; the geometric center of the binding terminal 100 of the second terminal group 20 is adjacent to the binding terminal 100 and is located at a distance p from the geometric center of the binding terminal 100 of the third terminal group 30 in the second direction x. 2 , Similar to the above embodiment, in this embodiment, by increasing p 2 The arrangement of the switch transistor 200 can be flexibly adjusted to improve the compactness of the switch transistor 200, thereby reducing the size of the test chip and improving the narrow frame degree of the display panel.

[0068] In some embodiments, Figure 3 As shown, the bonding area BA includes first sides L opposite to each other in the second direction x. 1 and the second side L 2 ; and with the first side L 1 In the adjacent units, the binding terminals 100 of the third terminal group 30 are located on the second terminal group 20 toward the first side L 1 When the area is away from the side of the display area AA, the first orthographic projections of the plurality of switch transistors 200 connected to the binding terminals 100 of the first terminal group 10 and the second terminal group 20 on the surface of the display panel facing the test chip are all located between the second terminal group 20 and the fourth terminal group 40, and the second orthographic projections of the plurality of switch transistors 200 connected to the binding terminals 100 of the third terminal group 30 on the surface of the display panel facing the test chip are located at the side of the first orthographic projection facing the first side L 1 The area is away from the display area AA;

[0069] And / or, the bonding area BA includes first sides L opposite to each other in the second direction x. 1 and the second side L 2 ; and the second side L 2 In the adjacent units, the binding terminals 100 of the third terminal group 30 are located on the second terminal group 20 toward the second side L 2When the area is away from the side of the display area AA, the first orthographic projections of the plurality of switch transistors 200 connected to the binding terminals 100 of the first terminal group 10 and the second terminal group 20 on the surface of the display panel facing the test chip are all located between the second terminal group 20 and the fourth terminal group 40, and the second orthographic projections of the plurality of switch transistors 200 connected to the binding terminals 100 of the third terminal group 30 on the surface of the display panel facing the test chip are located on the side of the first orthographic projection facing the second side L 2 The area is away from the side of the display area AA.

[0070] In this embodiment, the multiple switching transistors 200 connected to the binding terminals 100 of the first terminal group 10 and the second terminal group 20 can be connected to the multiple binding terminals 100 in the first terminal group 10 and the second terminal group 20 through the routing extending along the first direction y, and the multiple switching transistors 200 connected to the binding terminals 100 of the third terminal group 30 can be connected to the multiple binding terminals 100 in the third terminal group 30 through the routing extending along the second direction x. Therefore, the switching transistors 200 and the binding terminals 100 can be connected through shorter routings, which can simplify the wiring process and save wiring costs.

[0071] In some embodiments, the bonding area BA includes first sides L opposite to each other in the second direction x. 1 and the second side L 2 ; and with the first side L 1 In the adjacent units, the binding terminals 100 of the third terminal group 30 are located on the second terminal group 20 toward the first side L 1 When the area is away from the side of the display area AA, the first orthographic projections of the plurality of switch transistors 200 connected to the binding terminals 100 of the first terminal group 10 and the second terminal group 20 on the surface of the display panel facing the test chip are all located between the second terminal group 20 and the fourth terminal group 40, and the second orthographic projections of the plurality of switch transistors 200 connected to the binding terminals 100 of the third terminal group 30 on the surface of the display panel facing the test chip are located at the side of the first orthographic projection facing the first side L 1 area and away from one side of the display area AA.

[0072] In some embodiments, the bonding area BA includes first sides L opposite to each other in the second direction x. 1 and the second side L 2 ; and the second side L 2 In the adjacent units, the binding terminals 100 of the third terminal group 30 are located on the second terminal group 20 toward the second side L 2When the area is away from the side of the display area AA, the first orthographic projections of the plurality of switch transistors 200 connected to the binding terminals 100 of the first terminal group 10 and the second terminal group 20 on the surface of the display panel facing the test chip are all located between the second terminal group 20 and the fourth terminal group 40, and the second orthographic projections of the plurality of switch transistors 200 connected to the binding terminals 100 of the third terminal group 30 on the surface of the display panel facing the test chip are located on the side of the first orthographic projection facing the second side L 2 The area is away from the side of the display area AA.

[0073] In some embodiments, the bonding area BA includes first sides L opposite to each other in the second direction x. 1 and the second side L 2 ; and with the first side L 1 In the adjacent units, the binding terminals 100 of the third terminal group 30 are located on the second terminal group 20 toward the first side L 1 When the area is away from the side of the display area AA, the first orthographic projections of the plurality of switch transistors 200 connected to the binding terminals 100 of the first terminal group 10 and the second terminal group 20 on the surface of the display panel facing the test chip are all located between the second terminal group 20 and the fourth terminal group 40, and the second orthographic projections of the plurality of switch transistors 200 connected to the binding terminals 100 of the third terminal group 30 on the surface of the display panel facing the test chip are located at the side of the first orthographic projection facing the first side L 1 The binding area BA includes a first side L opposite to the second direction x. 1 and the second side L 2 ; and the second side L 2 In the adjacent units, the binding terminals 100 of the third terminal group 30 are located on the second terminal group 20 toward the second side L 2 When the area is away from the side of the display area AA, the first orthographic projections of the plurality of switch transistors 200 connected to the binding terminals 100 of the first terminal group 10 and the second terminal group 20 on the surface of the display panel facing the test chip are all located between the second terminal group 20 and the fourth terminal group 40, and the second orthographic projections of the plurality of switch transistors 200 connected to the binding terminals 100 of the third terminal group 30 on the surface of the display panel facing the test chip are located on the side of the first orthographic projection facing the second side L 2 The area is away from the side of the display area AA.

[0074] In some embodiments, Figure 3As shown, the third terminal group 30 includes a first sub-terminal group 31 and a second sub-terminal group 32 arranged along the second direction x, and the first sub-terminal group 31 and the second sub-terminal group 32 both include a plurality of binding terminals 100 arranged along the first direction y; the plurality of binding terminals 100 in the first sub-terminal group 31 and the plurality of binding terminals 100 in the second sub-terminal group 32 are alternately distributed in the first direction y, and the binding terminals 100 in the first sub-terminal group 31 and the binding terminals 100 adjacent thereto in the second sub-terminal group 32 are staggered in the second direction; the geometric center of the binding terminal 100 of the first sub-terminal group 31 is at a distance p from the geometric center of the binding terminal 100 adjacent to the binding terminal 100 and located in the second sub-terminal group 32 in the first direction y. 3 ,

[0075] Similar to the aforementioned embodiment, in this embodiment, by increasing p, the arrangement of the plurality of switch transistors 200 in the second switch transistor section 202 located in the side space can be adjusted to make the arrangement of the switch transistors 200 more compact, avoid occupying too much layout space, and leave more space for arranging other devices.

[0076] In some embodiments, the third terminal group 30 is disposed at the first side L of the bonding area BA. 1 The orthographic projection of the fourth terminal group 40 is at the first side L of the bonding area BA 1 The orthographic projections of at least partially overlap. This can make the layout space of the third terminal group 30 and the fourth terminal group 40 more compact, fully utilize the space of the display panel binding area BA, shorten the wiring, and save wiring costs.

[0077] In some embodiments, Figure 4 As shown, in this embodiment, the third terminal group 30 can be simultaneously disposed between the second terminal group 20 and the fourth terminal group 40 and in the side space of the second terminal group 20, and its beneficial effects are the same as those of the aforementioned embodiments, which will not be repeated here.

[0078] It should be noted that the terms "first", "second", "third", and "fourth" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first", "second", "third", and "fourth" may explicitly or implicitly include one or more of the feature. In the description of this application, unless otherwise specified, "multiple" means two or more.

Claims

1. A display panel, characterized in that: The display panel includes a display area and a non-display area located at least on one side of the display area; the non-display area includes a binding area located on one side of the display area; The display panel includes a plurality of binding terminals located in the binding area, the plurality of binding terminals in the binding area are divided into a plurality of units, each unit includes a plurality of binding terminals, and the binding terminals of each unit are bound to a test chip; The binding terminals of the same unit are divided into a first terminal group, a second terminal group, a third terminal group and a fourth terminal group; the first terminal group, the second terminal group, the third terminal group and the fourth terminal group respectively include a plurality of binding terminals, the binding terminals of the first terminal group, the second terminal group and the third terminal group are configured to be bound to the output terminals of the test chip, and the binding terminals of the fourth terminal group are configured to be bound to the input terminals of the test chip; In the same unit, the second terminal group is located on the side of the first terminal group away from the display area, the fourth terminal group is located on the side of the second terminal group away from the display area, the third terminal group is located on the side of the second terminal group away from the display area and on the side of the fourth terminal group close to the display area; the direction from the display area to the binding area is the first direction, and the binding terminals of the first terminal group and the binding terminals of the second terminal group are arranged along a second direction intersecting with the first direction.

2. The display panel according to claim 1, characterized in that: In the same unit, the first terminal group, the second terminal group and the third terminal group are arranged in a direction from the display area to the binding area.

3. The display panel according to claim 2, characterized in that: A distance between the third terminal group and the second terminal group is smaller than a distance between the third terminal group and the fourth terminal group.

4. The display panel according to claim 1, characterized in that: The binding area includes a first side and a second side opposite to each other in the second direction; in a unit adjacent to the first side, the binding terminals of the third terminal group are located on a side of the area of ​​the second terminal group facing the first side, away from the display area; and / or, in a unit adjacent to the second side, the binding terminals of the third terminal group are located on a side of the area of ​​the second terminal group facing the second side, away from the display area.

5. The display panel according to claim 4, characterized in that: The third terminal group includes at least two sub-terminal groups arranged along the second direction, and each of the sub-terminal groups includes a plurality of binding terminals arranged along the first direction.

6. A display device, comprising a display panel as claimed in any one of claims 1 to 5 and a test chip located in a binding area of ​​the display panel, the test chip being provided with a test circuit, the test circuit comprising a plurality of electrically connected switch transistors, each of the switch transistors being respectively configured to be connected to an output terminal of the corresponding test chip, the width of the switch transistor being T, the width of a trace connected to the switch transistor being W, the minimum distance between the central axes of two adjacent traces being S, the distance in the second direction between the geometric center of the binding terminal of the first terminal group and the geometric center of the binding terminal adjacent to the binding terminal and located in the second terminal group being p1, 7. The display device according to claim 6, characterized in that: The multiple switching transistors of the same test circuit include a first switching transistor group and a second switching transistor group, the multiple switching transistors in the first switching transistor group and the multiple switching transistors in the second switching transistor group are alternately distributed in the second direction, and the switching transistors in the first switching transistor group and the switching transistors adjacent to them in the second switching transistor group are staggered in the first direction; in the same unit, when the first terminal group, the second terminal group and the third terminal group are arranged in the direction from the display area to the binding area, the multiple binding terminals in the first terminal group, the second terminal group and the third terminal group are alternately distributed in the second direction, and the binding terminals in the first terminal group and the binding terminals adjacent to them in the second terminal group are staggered in the first direction, the binding terminals in the second terminal group and the binding terminals adjacent to them in the third terminal group are staggered in the first direction, and each of the switching transistors is respectively connected to the corresponding binding terminal.

8. The display device according to claim 7, characterized in that: The binding terminals of the third terminal group are arranged along a second direction intersecting the first direction, the orthographic projections of the plurality of switch transistors on the surface of the display panel facing the test chip are all located between the third terminal group and the fourth terminal group, the plurality of switch transistors in the first switch transistor group and the plurality of switch transistors in the second switch transistor group are all arranged along the second direction intersecting the first direction; the geometric center of the binding terminal of the second terminal group is adjacent to the binding terminal and is located at a distance p2 from the geometric center of the binding terminal of the third terminal group in the second direction, 9. The display device according to claim 6, characterized in that: The plurality of switch transistors are disposed on a side of the fourth terminal group close to the display area.

10. The display device according to claim 6, characterized in that: The binding area includes a first side and a second side opposite to each other in the second direction, and in a unit adjacent to the first side, when the binding terminal of the third terminal group is located on a side of an area of ​​the second terminal group facing the first side away from the display area, the first orthographic projections of the plurality of switch transistors connected to the binding terminals of the first terminal group and the second terminal group on the surface of the display panel facing the test chip are all located between the second terminal group and the fourth terminal group, and the second orthographic projections of the plurality of switch transistors connected to the binding terminals of the third terminal group on the surface are located in an area of ​​the first orthographic projection facing the first side and away from the display area; And / or, the binding area includes a first side and a second side opposite to each other in the second direction, and in a unit adjacent to the second side, the binding terminal of the third terminal group is located on a side of the area of ​​the second terminal group facing the second side and away from the display area; the first orthographic projections of the multiple switching transistors connected to the binding terminals of the first terminal group and the second terminal group on the surface of the display panel facing the test chip are all located between the second terminal group and the fourth terminal group, and the second orthographic projections of the multiple switching transistors connected to the binding terminals of the third terminal group on the surface are located in the area of ​​the first orthographic projection facing the second side and away from the display area.

11. The display device according to claim 10, characterized in that: The third terminal group includes a first sub-terminal group and a second sub-terminal group arranged along the second direction, and the first sub-terminal group and the second sub-terminal group both include a plurality of binding terminals arranged along the first direction; the plurality of binding terminals in the first sub-terminal group and the plurality of binding terminals in the second sub-terminal group are alternately distributed in the first direction, and the binding terminals in the first sub-terminal group and the binding terminals adjacent thereto in the second sub-terminal group are staggeredly arranged in the second direction; the geometric center of the binding terminal of the first sub-terminal group is at a distance p3 from the geometric center of the binding terminal adjacent to the binding terminal and located in the second sub-terminal group in the first direction, 12. The display device according to claim 10, characterized in that: An orthographic projection of the third terminal group on the first side of the bonding area at least partially overlaps with an orthographic projection of the fourth terminal group on the first side of the bonding area.

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