Memory circuit
By designing the differential structure of M+1-bit memory cells in the memory circuit and using a sensitive amplifier array for differential reading, the problem of low memory cell utilization is solved, and a storage product design with high data retention ability and reliability is realized.
Patent Information
- Application Number
- CN202311076264.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-24
- Publication Date
- 2025-02-25
AI Technical Summary
When existing memory circuits improve data retention capabilities and reliability, the utilization rate of memory cells is low, resulting in a weak position in area competitiveness.
A memory circuit is designed, in which each row of memory cells includes an M+1 bit memory cell. The first M bit memory cell that normally stores M bit data is stored together with the M+1 bit memory cell and is carried out through a sensitive amplifier array. Differential reading ensures the stability and reliability of the read window.
It effectively improves data retention capabilities and the reliability of storage products, while improving the utilization rate of storage units, realizing a more optimized design of storage products.
Smart Images
Figure CN119517121A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to memory technology, and in particular to a memory circuit. Background Art
[0002] Conventional non-volatile memory cells (including Flash, EEPROM, EPROM, etc.) store data in the form of charges stored in floating gates or charge trapping layers. Charge leakage over time will eventually lead to the loss of stored data, so data retention is one of the important indicators of memory cell performance. Data retention is not only affected by the memory cell structure and manufacturing process, but also by the storage / reading method and circuit. When the memory cell selection and manufacturing process are fixed, improving data retention from the perspective of data storage / reading method and circuit design has become an important breakthrough direction for non-volatile memory products (IP) to enter the automotive market.
[0003] In the prior art, a reading circuit that compares the saturation current of a memory cell with a reference current is as follows: Figure 1 As shown. In the read cycle, the read address and the reference address will be selected and precharged to the same potential. Due to the difference between the storage cell current and the reference current iref, the potential difference between the nodes will be caused after the discharge cycle. The difference in potential is input into the sense amplifier as a differential signal to read the data stored in the storage cell. Here, it is defined that the "0" cell (0 storage cell) current is large and the "1" cell (1 storage cell) current is small. When the reference current iref is between the "0" cell (0 storage cell) current and the "1" cell (1 storage cell) current, after discharge, the "1" cell (1 storage cell) current node potential is lower than the reference current node potential. When one end of the storage cell (cell) is used as the positive feedback amplifier "+" input, the Bit SA ((bit sense amplifier, bit sense amplifier)) gives a read result of "0"; otherwise, it reads "1".
[0004] When all the memory cells in the memory array store data, a certain statistical distribution of the memory cell current is formed. Each memory cell needs a separate read circuit to read out. Therefore, considering the external conditions such as temperature and power supply voltage, usually (for example, in the form of commonly used 32-bit readout) the reference current corresponding to the read circuit also has a certain distribution. Figure 2 As shown, when the storage product is used, the current window for reading data is defined as read "0" margin (window) and read "1" margin (window).
[0005] In actual use, the reference current iref is fine-tuned to balance the read "0" margin (window) and the read "1" margin (window) to achieve the most stable data readout effect. However, this storage / reading method has inherent weaknesses. Since the storage product (IP) application requires that all storage cells (cells) are guaranteed to be read correctly, the read "0" margin (window) and the read "1" margin (window) are both determined by the weakest storage cell (cell) in the statistical distribution of the storage cell (cell) current, which ultimately leads to a smaller read window (margin).
[0006] In addition, the leakage of written data along with the charge will cause the change of the current distribution of the storage cell, such as Figure 3 As shown in the figure. Since the "0" cell (0 storage unit) current and the "1" cell (1 storage unit) current are not symmetrical, the optimal current for distinguishing the "0" cell (0 storage unit) current and the "1" cell (1 storage unit) current will drift with the change of writing time, while the reference current iref does not change with time, further resulting in a reduction in the read window. Similarly, changes in temperature and power supply voltage will also introduce the same type of read window loss.
[0007] Figure 1 The disadvantages of the read circuit structure shown in the figure are mainly two points. First, to ensure the correct reading of the entire array, the read window is determined by the tail bit of the storage cell distribution; second, the read window loss is caused by comparing the storage cell current that changes with time / temperature / power supply voltage with a relatively constant reference current. A solution in the prior art is as follows Figure 4 As shown, data is stored and read using a differential pair, adjacent differential storage cells store opposite numbers, and when reading, the nodes of the differential storage cells are introduced into a sensitive amplifier for comparison.
[0008] Figure 4 The reading circuit for comparing the currents of the differential storage cells shown in the figure has the working principle of the differential storage cell as follows: when writing data, in the form of a differential pair, "0" cell / "1" cell is defined as storing data "0", and "1" cell / "0" cell is defined as storing data "1". During the reading process, since the discharge current of the "0" cell is greater than that of the "1" cell, when comparing the data, the potential on the "0" cell side is low, so the differential combination of "0" cell / "1" cell reads "0", and conversely, the differential combination of "1" cell / "0" cell reads "1".
[0009] The structure of differential storage cells can effectively increase the read window and improve the data retention parameters of the memory. The main reason is that after writing opposite values to adjacent storage cells, the read window (margin) is determined by the current difference between the "0" cell and the "1" cell. In theory, Figure 1 The structure shown in the figure has more than doubled. In fact, considering that the process conditions of adjacent memory cells are more similar, such as Figure 5 As shown in the figure, when the current of the "0" cell is at a relatively small position in the distribution, the current of the adjacent "1" cell is also likely to be relatively small. Therefore, the final comparison result is much greater than the readout circuit of the reference current comparison. In addition, since the differential data is stored in adjacent storage units (cells), the leakage of charge over time often only produces common-mode signal changes, such as Figure 6 As shown, it does not affect the differential signal and has little impact on the reading result.
[0010] In summary, the reading circuit that compares the currents of differential storage cells can effectively improve data retention and the reliability of storage products. However, the only disadvantage is that since each two adjacent storage cells store one bit of data, the utilization rate of the storage cells is greatly reduced, making the flash storage products (flash IP) with differential storage cell structures at a disadvantage in terms of area competitiveness. Summary of the invention
[0011] The technical problem to be solved by the present invention is to provide a memory circuit which can effectively improve the data retention capability, improve the reliability of storage products, and improve the utilization rate of storage units.
[0012] In order to solve the above technical problems, the present invention provides a memory circuit, which includes a memory cell array and a sense amplifier:
[0013] The storage cell array comprises N rows of storage cells, where N is a positive integer;
[0014] Each row of storage cells includes M+1 storage cells, wherein the first to M-th storage cells normally store M-bit data, and the M+1-th storage cell stores the opposite data of the i-th storage cell, where M is a positive integer, and i is a positive integer less than or equal to M;
[0015] The sense amplifier array comprises N rows of sense amplifiers;
[0016] Each row of sense amplifiers includes M sense amplifiers, each sense amplifier having a differential input port for reading stored data;
[0017] For the M sense amplifiers in the same row, a positive input terminal of the i-th sense amplifier is connected to the output terminal of the i-th storage unit, and a negative input terminal of the i-th sense amplifier is connected to the output terminal of the M+1-th storage unit; two positive input terminals of the j-th sense amplifier are both connected to the output terminal of the j-th storage unit, and two negative input terminals of the j-th sense amplifier are respectively connected to the output terminal of the M+1-th storage unit and the output terminal of the i-th storage unit, where j is a positive integer less than or equal to M and not equal to i.
[0018] Preferably, in the same row of M sense amplifiers, both positive input terminals of the i-th sense amplifier are connected to the output terminal of the i-th storage unit, and both negative input terminals of the i-th sense amplifier are connected to the output terminal of the M+1-th storage unit and the output terminal of the i-th storage unit respectively.
[0019] Preferably, the memory cell is a non-volatile memory cell storing charges in a floating gate or a charge trapping layer.
[0020] Preferably, the storage unit is Flash, EEPROM or EPROM.
[0021] Preferably, the memory circuit further includes an auxiliary circuit;
[0022] The auxiliary circuit is used to select the storage unit, connect the storage unit with the sense amplifier, and connect the sense amplifier with the readout circuit.
[0023] Preferably, the auxiliary circuit includes a plurality of transmission gate circuits, a digital logic circuit and a driving circuit.
[0024] Preferably, M is 2, 3, 4, 8, 16, 32 or 64.
[0025] Preferably, the sense amplifier circuit includes a first PMOS tube P1, a second PMOS tube P2, a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a fourth NMOS tube N4, a fifth NMOS tube N5 and a sixth NMOS tube N6;
[0026] The source terminals of the first PMOS transistor P1 and the second PMOS transistor P2 are connected to the working voltage VDD;
[0027] The drain terminal of the first PMOS transistor P1 is connected to the drain terminal of the first NMOS transistor N1, the gate terminal of the second PMOS transistor P2 and the gate terminal of the second NMOS transistor N2;
[0028] The drain terminal of the second PMOS transistor P2 is connected to the drain terminal of the second NMOS transistor N2, the gate terminal of the first PMOS transistor P1 and the gate terminal of the first NMOS transistor N1, and serves as a data output terminal of the sensitive amplifier circuit;
[0029] The source terminal of the first NMOS tube N1 is connected to the drain terminal of the third NMOS tube N3 and the drain terminal of the fifth NMOS tube N5;
[0030] The source terminal of the second NMOS tube N2 is connected to the drain terminal of the fourth NMOS tube N4 and the drain terminal of the sixth NMOS tube N6;
[0031] The gate end of the third NMOS transistor N3 and the gate end of the fifth NMOS transistor N5 serve as two positive input ends of the sense amplifier;
[0032] The drain terminal of the fourth NMOS tube N4 and the drain terminal of the sixth NMOS tube N6 serve as two negative input terminals of the sense amplifier;
[0033] The source terminal of the third NMOS transistor N3 , the source terminal of the fifth NMOS transistor N5 , the source terminal of the fourth NMOS transistor N4 , and the source terminal of the sixth NMOS transistor N6 are connected to the common ground terminal VSS.
[0034] Preferably, the first PMOS transistor P1 , the second PMOS transistor P2 , the first NMOS transistor N1 , the second NMOS transistor N2 , the third NMOS transistor N3 , the fourth NMOS transistor N4 , the fifth NMOS transistor N5 and the sixth NMOS transistor N6 are all field effect transistors.
[0035] Preferably, the third NMOS transistor N3 , the fourth NMOS transistor N4 , the fifth NMOS transistor N5 and the sixth NMOS transistor N6 have the same size.
[0036] The memory circuit of the present invention stores / reads M data in M+1 memory cells, retaining the reading method of comparing the currents of neighboring memory cells with each other in a differential structure. Since the currents of neighboring "0" memory cells and "1" memory cells are both smaller or larger when distributed, a larger reading window (margin) can be guaranteed. Fig.11 As shown. Fig.12As shown, the leakage of charge generated over time often only produces a change in the common-mode signal, which can avoid the loss of the reading window (margin) caused by the reference current iref of the reference current type circuit not changing with the state of the storage unit, thereby retaining the high reliability advantage of the differential storage unit structure with a large reading window (margin). The memory circuit of the present invention, its sensitive amplifier array retains the reading method of the current of the adjacent storage units of the differential structure to compare the read current, and largely inherits the advantages of the differential storage unit, that is, a large reading window, excellent data retention parameters, and high reliability of the storage product; at the same time, the utilization rate of the storage unit is M / M+1, and when the value of M increases, the utilization rate of the storage unit can be close to 100%, which improves the utilization rate of the storage unit. According to the positioning of the storage product, a balance can be found between reliability and area, and a suitable M value can be selected to balance the two opposing factors of the reading window and the storage product area, which can effectively improve the data retention ability (data retention), improve the reliability of the storage product, and improve the utilization rate of the storage unit (cell), so as to achieve a more optimized design of the storage product. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0038] Figure 1 The invention discloses a comparison reading circuit for a storage unit current and a reference current iref;
[0039] Figure 2 yes Figure 1 a read circuit, a current distribution of a memory cell after initial writing and a reference current distribution;
[0040] Figure 3 yes Figure 1 A read circuit stores a current distribution of a memory cell after charge leakage and a reference current distribution over time;
[0041] Figure 4 It is an existing reading circuit for comparing the currents of differential storage cells with each other;
[0042] Figure 5 yes Figure 4 Current distribution of a memory cell after initial writing by a read circuit;
[0043] Figure 6 yes Figure 4The read circuit stores the current distribution of a memory cell after charge leakage over time;
[0044] Figure 7 is a storage state diagram of a row of storage cells in one embodiment of a memory circuit of the present invention;
[0045] Figure 8 yes Figure 7 A row of memory cells corresponding to a row of sense amplifiers reading state diagram is shown;
[0046] Fig. 9 is another row storage unit storage state diagram of an embodiment of the memory circuit of the present invention;
[0047] Fig.10 yes Fig. 9 Another row of memory cells corresponding to another row of sense amplifiers reading state diagram shown;
[0048] Fig.11 yes Figure 7 , Fig. 9 The current distribution of a memory cell after the initial writing of the reading circuit shown;
[0049] Fig.12 yes Figure 7 , Fig. 9 The reading circuit shown, stores the current distribution of a single-bit memory cell after charge leakage over time;
[0050] Fig.13 FIG. 4 is a circuit diagram of a sense amplifier according to an embodiment of a memory circuit of the present invention. DETAILED DESCRIPTION
[0051] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0052] The words "first", "second" and similar terms used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprises" and similar terms mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative position relationships. When the absolute position of the object being described changes, the relative position relationship may also change accordingly.
[0053] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.
[0054] Embodiment 1
[0055] A memory circuit includes a memory cell array and a sense amplifier:
[0056] The storage cell array comprises N rows of storage cells, where N is a positive integer;
[0057] like Figure 7 , Fig. 9 As shown, each row of storage cells includes M+1 storage cells, wherein the first to M-th storage cells normally store M-bit data, and the M+1-th storage cell stores the opposite data of the i-th storage cell, where M is a positive integer, and i is a positive integer less than or equal to M;
[0058] The sense amplifier array comprises N rows of sense amplifiers;
[0059] like Figure 8 , Fig.10 As shown, each row of sense amplifiers includes M sense amplifiers, each sense amplifier having a differential input port for reading stored data;
[0060] For the M sense amplifiers in the same row, a positive input terminal of the i-th sense amplifier is connected to the output terminal of the i-th storage unit, and a negative input terminal of the i-th sense amplifier is connected to the output terminal of the M+1-th storage unit; two positive input terminals of the j-th sense amplifier are both connected to the output terminal of the j-th storage unit, and two negative input terminals of the j-th sense amplifier are respectively connected to the output terminal of the M+1-th storage unit and the output terminal of the i-th storage unit, where j is a positive integer less than or equal to M and not equal to i.
[0061] The M+1th storage unit may be located at any position in the storage unit row.
[0062] Take M=3 as an example, that is, 3 data are stored in 4 storage units.
[0063] like Figure 7 , Figure 8 , Fig. 9 , Fig.10 As shown, define 3-bit input data din <0> ,din <1> ,din <2> ; 3-bit output dout <0> ,dout <1> ,dout <2> ; 4 storage units (cell) are bits <0> ,bitb <0> ,bit <1> ,bit <2> .
[0064] The storage rule is that data din <0> Stored in the form of a differential pair (opposite storage states) in bit <0> and bitb <0> Among them, din <1> ,din <2> Conventional storage in bit <1> ,bit <2> middle, Figure 7 , Fig. 9 As shown; when reading, Figure 8 , Fig.10 As shown, dout <0> Using differential reading, compare bit <0> and bitb <0> The storage cell current gives the read result; dout <1> The reading still uses the differential input method. The special point is that the "+" end of the differential input is 2-bit <1> Potential sampling, the "-" end of the differential input is bit <0> With bitb <0> Superposition of terminal potential sampling; dout <2> Reading method is the same as dout <1> .
[0065] When M=3, a row of four storage cells stores 3 bits of data, with a total of 8 storage / read states as shown in the following table:
[0066]
[0067] Take "000" and "111" as examples. Figure 7 As shown, the data storage states in a row of four-bit storage cells are arranged as "0100", as shown in Figure 8 As shown, the read data is "000"; Fig. 9 As shown, the data storage states in a row of four-bit storage cells are arranged as "1011", as Fig.10 As shown, the read data is "111".
[0068] The readout principle is as follows, dout <0> The readout principle is exactly the same as that of differential flash storage products (flash IP). <0> / bitb <0> When storing "0" / "1" respectively, bit <0> Current is greater than bitb <0> , after discharge bit <0> The node potential is lower than bitb <0> Node potential, according to the positive feedback amplification principle of the sensitive amplifier (SA), dout <0> The output result is "0", otherwise, the output result is "1".
[0069] From dout <1> to dout <m-1>The reading method is the same as that of the other cell current comparison principle, in which the sensitive amplifier samples the bit potential circuit as shown in Figure 8 , Fig.10 As shown. <1> When the storage state is "0", the "+" end of the differential input is a potential sample of 2 "0". <0> / bitb <0> According to the storage rules, the values must be opposite. The "-" end of the differential input must be the potential sampling of "0" and "1". At this time, the equivalent "+" end input potential is lower than the "-" end, dout <1> The output result is "0"; when bit <1> When the storage state is "1", the "+" input is 2-way "1" potential sampling, and the "-" input is constant "0" and "1" potential sampling. At this time, the equivalent "+" input potential is higher than the "-" end, dout <1> The output result is "1".
[0070] When bit <1> When the storage state is "0", the "+" end of the differential input is a potential sample of 2 "0". <0> / bitb <0> According to the storage rules, the values must be opposite. The potential of the differential input "0" and "1" is sampled. At this time, the equivalent "+" input potential is lower than the "-" end, dout <1> The output result is "0";
[0071] When bit <1> When the storage state is "1", the "+" end of the differential input is a potential sample of 2 "1" channels. <0> / bitb <0> According to the storage rules, the values must be opposite. The "-" end of the differential input must be the potential sampling of "0" and "1". At this time, the equivalent "+" end input potential is higher than the "-" end, dout <1> The output result is "1".
[0072] bit <2> to bit <m-1>The storage / reading method is the same as above.
[0073] In the memory circuit of the first embodiment, M bits of data are stored in the M+1-bit storage cells of the same row, wherein the M-bit storage cells store M bits of normal data, and the M+1-th storage cell stores the opposite data of the i-th storage cell; when reading the storage data in the storage cells of the corresponding row, the M sensitive amplifiers of the same row compare the currents of the i-th storage cell and the M+1-th storage cell storing the opposite data for differential reading, and read out the i-th storage data; the currents of the remaining other M-1-bit storage cells are compared with the average of the currents of the two storage cells storing the opposite data for differential reading, which is defined as reading 1 or 0.
[0074] In the memory circuit of the first embodiment, the sense amplifier array stores / reads M data in M+1 memory cells, and retains the reading method of comparing the currents of neighboring memory cells of the differential structure with each other. Since the currents of the neighboring "0" memory cells and "1" memory cells are both smaller or larger when distributed, a larger reading window (margin) can be guaranteed. Fig.11 As shown. Fig.12 As shown, the leakage of charge generated over time often only produces a common-mode signal change, which can avoid the loss of the read window (margin) caused by the reference current iref of the reference current type circuit not changing with the state of the storage unit, thereby retaining the high reliability advantage of the differential storage unit structure with a large read window (margin). The memory circuit of the first embodiment, its sensitive amplifier array retains the reading method of the current of the adjacent storage units of the differential structure to compare the read current, and largely inherits the advantages of the differential storage unit, that is, a large read window, excellent data retention parameters, and high reliability of the storage product; at the same time, the utilization rate of the storage unit is M / M+1, and when the value of M increases, the utilization rate of the storage unit can be close to 100%, which improves the utilization rate of the storage unit. According to the positioning of the storage product, a balance can be found between reliability and area, and a suitable M value can be selected to balance the two opposing factors of the read window and the storage product area, which can effectively improve the data retention ability (data retention), improve the reliability of the storage product, and improve the utilization rate of the storage unit (cell), so as to achieve a more optimized design of the storage product.
[0075] Usually, storage products are composed of peripheral circuits and storage cells. As the capacity increases, the storage area gradually dominates. Referring to storage products with conventional structures, when the capacity is greater than 256KB, the area of using 2 storage cells to store 1 bit of data is more than 1.8 times the area of the reference structure; the area of using 4 storage cells to store 3 bits of data is about 1.25 times the area of the reference structure; the area of using 8 storage cells to store 7 bits of data is about 1.13 times the area of the reference structure. It is obvious that as M increases, the structure of M+1 storage cells storing M bit data greatly improves the area utilization of storage products.
[0076] Embodiment 2
[0077] Based on the memory circuit of the first embodiment, in the same row of M sense amplifiers, the two positive input terminals of the i-th sense amplifier are both connected to the output terminal of the i-th storage unit, and the two negative input terminals of the i-th sense amplifier are respectively connected to the output terminal of the M+1-th storage unit and the output terminal of the i-th storage unit.
[0078] Preferably, the memory cell is a non-volatile memory cell storing charges in a floating gate or a charge trapping layer.
[0079] Preferably, the storage unit is Flash, EEPROM, EPROM, etc.
[0080] Preferably, the memory circuit further includes an auxiliary circuit;
[0081] The auxiliary circuit is used to select the storage unit, connect the storage unit with the sense amplifier, and connect the sense amplifier with the readout circuit.
[0082] Preferably, the auxiliary circuit includes a plurality of transmission gate circuits, a digital logic circuit and a driving circuit.
[0083] Preferably, M is 2, 3, 4, 8, 16, 32, 64, etc.
[0084] Embodiment 3
[0085] Based on the memory circuit of the first embodiment, Fig.13 As shown, the sense amplifier circuit includes a first PMOS tube P1, a second PMOS tube P2, a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a fourth NMOS tube N4, a fifth NMOS tube N5 and a sixth NMOS tube N6;
[0086] The source terminals of the first PMOS transistor P1 and the second PMOS transistor P2 are connected to the working voltage VDD;
[0087] The drain terminal of the first PMOS transistor P1 is connected to the drain terminal of the first NMOS transistor N1, the gate terminal of the second PMOS transistor P2 and the gate terminal of the second NMOS transistor N2;
[0088] The drain terminal of the second PMOS transistor P2 is connected to the drain terminal of the second NMOS transistor N2, the gate terminal of the first PMOS transistor P1 and the gate terminal of the first NMOS transistor N1, and serves as a sensitive amplifier circuit to read the data output terminal OUT;
[0089] The source terminal of the first NMOS tube N1 is connected to the drain terminal of the third NMOS tube N3 and the drain terminal of the fifth NMOS tube N5;
[0090] The source terminal of the second NMOS tube N2 is connected to the drain terminal of the fourth NMOS tube N4 and the drain terminal of the sixth NMOS tube N6;
[0091] The gate end of the third NMOS transistor N3 and the gate end of the fifth NMOS transistor N5 serve as two positive input ends of the sense amplifier;
[0092] The drain terminal of the fourth NMOS tube N4 and the drain terminal of the sixth NMOS tube N6 serve as two negative input terminals of the sense amplifier;
[0093] The source terminal of the third NMOS transistor N3 , the source terminal of the fifth NMOS transistor N5 , the source terminal of the fourth NMOS transistor N4 , and the source terminal of the sixth NMOS transistor N6 are connected to the common ground terminal VSS.
[0094] Preferably, the first PMOS transistor P1 , the second PMOS transistor P2 , the first NMOS transistor N1 , the second NMOS transistor N2 , the third NMOS transistor N3 , the fourth NMOS transistor N4 , the fifth NMOS transistor N5 and the sixth NMOS transistor N6 are all field effect transistors.
[0095] Preferably, the third NMOS transistor N3 , the fourth NMOS transistor N4 , the fifth NMOS transistor N5 and the sixth NMOS transistor N6 have the same size.
[0096] In the memory circuit of the third embodiment, the "+" end of the differential input of the sensitive amplifier circuit is for sampling the potential of the output end of two paths from the same storage unit, and the input circuit includes two N-type field effect transistors, the third NMOS tube N3 and the fifth NMOS tube N5; the "-" end of the differential input of the sensitive amplifier circuit is for sampling the potential of the output end of two differential storage units with known differential storage, and the input circuit includes two N-type field effect transistors, the fourth NMOS tube N4 and the sixth NMOS tube N6. After sampling, the positive feedback amplification structure composed of the upper first NMOS tube N1 and the third NMOS tube N3 and the first PMOS tube P1 and the second PMOS tube P2 amplifies the output digital "0" or "1" result.
[0097] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.
Claims
1. A memory circuit, characterized in that: The memory circuit includes a memory cell array and a sense amplifier: The storage cell array comprises N rows of storage cells, where N is a positive integer; Each row of storage cells includes M+1 storage cells, wherein the first to M-th storage cells normally store M-bit data, and the M+1-th storage cell stores the opposite data of the i-th storage cell, where M is a positive integer, and i is a positive integer less than or equal to M; The sense amplifier array comprises N rows of sense amplifiers; Each row of sense amplifiers includes M sense amplifiers, each sense amplifier having a differential input port for reading stored data; For the M sense amplifiers in the same row, a positive input terminal of the i-th sense amplifier is connected to the output terminal of the i-th storage unit, and a negative input terminal of the i-th sense amplifier is connected to the output terminal of the M+1-th storage unit; two positive input terminals of the j-th sense amplifier are both connected to the output terminal of the j-th storage unit, and two negative input terminals of the j-th sense amplifier are respectively connected to the output terminal of the M+1-th storage unit and the output terminal of the i-th storage unit, where j is a positive integer less than or equal to M and not equal to i.
2. The memory circuit according to claim 1, wherein: For the M sense amplifiers in the same row, the two positive input terminals of the ith sense amplifier are connected to the output terminal of the ith storage unit, and the two negative input terminals of the ith sense amplifier are connected to the output terminal of the M+1th storage unit and the output terminal of the ith storage unit respectively.
3. The memory circuit according to claim 1, wherein: The memory cell is a non-volatile memory cell that stores charges in a floating gate or a charge trapping layer.
4. The memory circuit according to claim 1, wherein: The storage unit is Flash, EEPROM or EPROM.
5. The memory circuit according to claim 1, wherein: The memory circuit also includes an auxiliary circuit; The auxiliary circuit is used to select the storage unit, connect the storage unit with the sense amplifier, and connect the sense amplifier with the readout circuit.
6. The memory circuit according to claim 1, wherein: The auxiliary circuit includes a plurality of transmission gate circuits, a digital logic circuit and a driving circuit.
7. The memory circuit according to claim 1, wherein: M is 2, 3, 4, 8, 16, 32, or 64.
8. The memory circuit according to claim 1, wherein: The sensitive amplifier circuit comprises a first PMOS tube (P1), a second PMOS tube (P2), a first NMOS tube (N1), a second NMOS tube (N2), a third NMOS tube (N3), a fourth NMOS tube (N4), a fifth NMOS tube (N5) and a sixth NMOS tube (N6); A source terminal operating voltage (VDD) of the first PMOS transistor (P1) and the second PMOS transistor (P2); The drain end of the first PMOS tube (P1) is connected to the drain end of the first NMOS tube (N1), the gate end of the second PMOS tube (P2) and the gate end of the second NMOS tube (N2); The drain end of the second PMOS tube (P2) is connected to the drain end of the second NMOS tube (N2), the gate end of the first PMOS tube (P1) and the gate end of the first NMOS tube (N1), and serves as a data output end of the sensitive amplifier circuit; The source end of the first NMOS tube (N1) is connected to the drain end of the third NMOS tube (N3) and the drain end of the fifth NMOS tube (N5); The source end of the second NMOS tube (N2) is connected to the drain end of the fourth NMOS tube (N4) and the drain end of the sixth NMOS tube (N6); The gate end of the third NMOS tube (N3) and the gate end of the fifth NMOS tube (N5) serve as two positive input ends of the sensitive amplifier; The drain end of the fourth NMOS tube (N4) and the drain end of the sixth NMOS tube (N6) serve as two negative input ends of the sensitive amplifier; The source end of the third NMOS tube (N3), the source end of the fifth NMOS tube (N5), the source end of the fourth NMOS tube (N4) and the source end of the sixth NMOS tube (N6) are connected to a common ground end (VSS).
9. The memory circuit according to claim 8, wherein: The first PMOS transistor (P1), the second PMOS transistor (P2), the first NMOS transistor (N1), the second NMOS transistor (N2), the third NMOS transistor (N3), the fourth NMOS transistor (N4), the fifth NMOS transistor (N5) and the sixth NMOS transistor (N6) are all field effect transistors.
10. The memory circuit according to claim 9, characterized in that The third NMOS tube (N3), the fourth NMOS tube (N4), the fifth NMOS tube (N5) and the sixth NMOS tube (N6) have the same size.