Method for manufacturing semiconductor device

Abstract

The invention provides a method for manufacturing a semiconductor device. In accordance with some embodiments, a first device wafer is bonded to a first carrier through wafer-on-wafer bonding, and an additional device wafer may be subsequently bonded to the first device wafer. The support wafer is then bonded to the topmost device wafer, and then the first wafer is removed. The bonded wafer structures may then be singulated into individual semiconductor device packages. By means of the wafer-on-wafer bonding process, the manufacturing cost and the cycle time can be reduced.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor device. Background Art

[0002] As the integration level of integrated circuits increases, semiconductor devices are no longer all integrated circuits formed in the same die, but more and more device dies are bonded together to form a package, in which device dies with different functions can work together to realize system functions. Summary of the invention

[0003] The present disclosure is directed to a method for manufacturing a semiconductor device, comprising: bonding a first device chip to a first supporting chip; bonding a second device chip to the first device chip; bonding a second supporting chip to the second device chip after bonding the second device chip to the first device chip, wherein the second supporting chip has a larger area than the first device chip and the second device chip in a top view; and performing a singulation process on the first device chip, the second device chip, and the second supporting chip to form a singulated semiconductor package.

[0004] In some embodiments, the present disclosure provides another method for manufacturing a semiconductor device, comprising: utilizing a first bonding layer of a first chip to bond a plurality of device dies to the first chip; depositing an insulating material on the first chip, wherein the insulating material surrounds each of the plurality of device dies and encapsulates the first chip; forming a second bonding layer above the exposed surfaces of the plurality of device dies and above the insulating material; bonding the first device chip to the second bonding layer opposite to the plurality of device dies; after bonding the first device chip to the second bonding layer, performing a first edge trimming process on the first device chip, the insulating material, and the first chip; and performing a singulation process on the first device chip and the insulating material between each of the plurality of device dies.

[0005] In some embodiments, the present disclosure provides another method for manufacturing a semiconductor device, comprising: bonding a first device chip to a first carrier chip, the first device chip having a first area in a top view; bonding a second device chip to the first device chip opposite to the first carrier chip, the second device chip having the first area in the top view; bonding a third device chip to the second device chip opposite to the first device chip, the third device chip having the first area in the top view; performing an edge trimming process, wherein after the edge trimming process, a recess of the first carrier chip has side walls that are coplanar with side walls of the first device chip, the second device chip, and the third device chip; after performing the edge trimming process, bonding a second carrier chip to the third device chip opposite to the second device chip; and after bonding the second carrier chip, removing the first carrier chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure can be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, various features are not drawn to scale. In fact, for the sake of clarity of discussion, the size of various features can be increased or decreased arbitrarily.

[0007] Figures 1 to 6 Various stages of a wafer-on-wafer bonding process and forming a package are shown in accordance with some embodiments.

[0008] Figures 7 to 12 A die-on-wafer bonding process and formation of a package are shown in accordance with some embodiments.

[0009] Figure 13 to Figure 14 Additional wafer devices are shown bonded to the wafer structure on the wafer to form a semiconductor package. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or on a second feature in the following description may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat figure numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself dictate the relationship between the various embodiments and / or configurations discussed.

[0011] Additionally, for convenience of description, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein to describe the relationship of one component or feature to another component or feature, as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0012] Wafer on wafer on wafer and chip on wafer on wafer on wafer structures and methods for forming the same are provided. According to some embodiments, a first device wafer is bonded to a first carrier via wafer-on-wafer bonding, and then another device wafer may be bonded to the first device wafer. A support wafer is then bonded to the topmost device wafer, and then the first wafer may be removed. The bonded wafer structure may then be segmented into separate semiconductor device packages. Through the wafer-on-wafer bonding process, manufacturing costs and cycle times may be reduced. The embodiments discussed herein will provide examples of the subject matter of the present disclosure that may be implemented or used, and those of ordinary skill in the art will readily appreciate that modifications may be made within the intended scope of different embodiments. In the various views and illustrative embodiments, the same reference numerals are used to indicate the same components. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0013] Figures 1 to 6 The first semiconductor package 600 ( Figure 6 ) is shown in the embodiment. In this embodiment, the first semiconductor package 600 is formed by various processing steps of directly bonding one or more device wafers to a first device wafer (e.g., a tier-1 device wafer, tier-1 refers to the first structure bonded to a carrier wafer) using a support and carrier wafer during the processing steps. Multiple device wafers are bonded to another device wafer using a support and carrier wafer to form a wafer-on-wafer-on-wafer (WoWoW) structure, which can then be divided into individual semiconductor packages (e.g., the first semiconductor package 600).

[0014] refer to Figure 1 , forming a wafer 10. According to some embodiments, the wafer 10 is a carrier without active devices (such as transistors) and passive devices, and thus may be referred to as a carrier 10 hereinafter. The carrier 10 may have a circular top view shape, Figure 1An edge portion of the wafer 10 is shown. According to some embodiments, the carrier 10 includes a substrate 12. The substrate 12 may be a blank substrate. In one embodiment, the substrate 12 may be a semiconductor substrate, such as a silicon substrate. In some embodiments, the substrate 12 may include other semiconductor materials, such as silicon germanium, carbon-doped silicon, or the like. The substrate 12 may be a bulk substrate, or may have a layered structure, for example, including a silicon substrate and a silicon germanium layer above the silicon substrate. In other embodiments, the substrate 12 may also be formed of other materials, for example, ceramics, glass, silicate glass, or the like may also be used. According to some embodiments, the entire substrate 12 is formed of a homogeneous material, wherein there is no other material different from the homogeneous material. For example, the substrate 12 may be formed of silicon (doped or undoped), and there are no metal regions, dielectric regions, etc.

[0015] In another embodiment, wafer 10 is a device wafer including active devices (e.g., transistors) and / or passive devices (e.g., capacitors, resistors, inductors, and / or the like) therein. When wafer 10 is a device wafer, wafer 10 may be an unsawn wafer including a semiconductor substrate extending continuously to all device dies in the wafer, or may be a reconstituted wafer including discrete device dies encapsulated in an encapsulation (e.g., a molding compound or an inorganic gap-fill region).

[0016] In one embodiment, the bonding layer 14 is deposited or otherwise formed on the substrate 12. According to some embodiments, the bonding layer 14 is formed of or includes a dielectric material, which may be a silicon-based dielectric material, such as silicon oxide (SiO2), SiN, SiON, SiOCN, SiC, SiCN, or the like or a combination thereof. According to some embodiments, the bonding layer 14 is formed using high density plasma chemical vapor deposition (HDPCVD), plasma enhanced chemical vapor deposition (PECVD), chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), or the like.

[0017] According to some embodiments, the bonding layer 14 is in physical contact with the substrate 12. According to another embodiment, the carrier 10 includes a plurality of layers (not shown) between the bonding layer 14 and the substrate 12. For example, there may be an oxide-based layer formed of an oxide-based material (which may also be silicon oxide-based), such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), or the like. There may also be a nitride-based layer formed of or including silicon nitride, silicon oxynitride (SiON), or the like. According to some embodiments, the layer between the substrate 12 and the bonding layer 14 may be formed using PECVD, CVD, LPCVD, ALD, or the like. An alignment mark (not shown) may also be formed between the bonding layer 14 and the substrate 12. The alignment mark may be formed as a metal plug, which may be formed through a damascene process.

[0018] Figure 1 Further shown is a first device wafer 30 attached to the carrier 10. In an embodiment, the first device wafer 30 may be an unsawn wafer. According to some embodiments, the first device wafer 30 includes a substrate 32 and integrated circuit devices (not separately shown) at a surface of the substrate 32. Examples of integrated circuit devices may include complementary metal oxide semiconductor (CMOS) transistors, resistors, capacitors, diodes, and / or the like.

[0019] According to some embodiments, the through-hole 36 is formed to extend from the front side (shown as the bottom side) into the substrate 32. According to other embodiments, the through-hole is not formed at this stage, and the through-hole 36 is formed in a subsequent process. In some embodiments, the substrate 32 may be a semiconductor substrate, such as a silicon substrate. According to other embodiments, the substrate 32 may include other semiconductor materials, such as silicon germanium, carbon-doped silicon, or the like. The substrate 32 may be a bulk substrate, or may have a layered structure, for example, including a silicon substrate and a silicon germanium layer above the silicon substrate. In one embodiment, the substrate 32 may be formed of the same material as the substrate 12 in the carrier 10, so that in the subsequent packaging process, the warpage caused by the mismatch of the coefficient of thermal expansion (CTE) value between the carrier 10 and the first device wafer 30 is reduced.

[0020] According to some embodiments, the first device chip 30 includes device dies, which may include logic dies, memory dies, input-output dies, integrated passive devices (IPDs), or the like, or a combination thereof. For example, the logic device die in the first device chip 30 may be a central processing unit (CPU) die, a graphics processing unit (GPU) die, a mobile application die, a micro control unit (MCU) die, a baseband (BB) die, an application processor (AP) die, or the like. The memory die in the first device chip 30 may include a static random access memory (SRAM) die, a dynamic random access memory (DRAM) die, or the like. The first device chip 30 may be a simple device chip including a semiconductor substrate extending continuously throughout the first device chip 30, or may be a reconstructed chip including device dies packaged therein, wherein the device dies may be integrated into a system.

[0021] According to some embodiments, a front side inline structure 38 is formed on the front side of substrate 32. Front side inline structure 38 may include a plurality of dielectric layers 40 and conductive features (not separately shown) within the plurality of dielectric layers 40. In an embodiment, the plurality of dielectric layers 40 may include dielectric structures such as interlayer dielectrics (ILDs), intermetallic dielectrics (IMDs), non-low dielectric constant (low-k) passivation layers, polymer layers, and / or the like. One such dielectric layer may be a dielectric layer formed on the bottom surface of substrate 32 (e.g., Figure 1 ) is deposited or otherwise formed on a passivation layer (not shown separately). In one embodiment, a metal pad 44 (e.g., an aluminum pad) can be embedded in the passivation layer, wherein the bottom surface of the metal pad 44 is coplanar with the bottom surface of the passivation layer. Other dielectric layers can be formed between the passivation layer and the substrate 32, for example, an ILD or an IMD, and can further include additional conductive features. In addition, a dielectric bonding layer (not shown separately) can be part of the plurality of dielectric layers 40 as the outermost dielectric layer. In one embodiment, the dielectric bonding layer can function in a similar manner to the bonding layer 14 and be formed of similar materials. The dielectric bonding layer can be in physical contact with the sidewalls of the substrate 32 and be the outermost dielectric layer of the plurality of dielectric layers 40 for use in subsequent bonding.

[0022] In one embodiment, the front-side interconnect structure 38 also includes additional conductive features in the plurality of dielectric layers 40. The conductive features may include contact plugs, metal lines and metal pads (e.g., metal pads 44), metal vias (e.g., vias 36), and / or the like. The contact plugs may be formed of tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multiple layers thereof. Each of the metal lines and metal vias may include a diffusion barrier layer and a copper-containing metal material located on the diffusion barrier layer. The diffusion barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like.

[0023] According to some embodiments, metal pads 44 are formed in the plurality of dielectric layers 40. Metal pads 44 may be formed of or include aluminum, copper, nickel, titanium, palladium, or the like, or alloys thereof. According to some embodiments, metal pads 44 are in the passivation layer. According to some embodiments, a polymer layer (which may be polyimide, polybenzoxazole (PBO) or the like) may be formed, wherein metal pads 44 are located in the polymer layer.

[0024] In one embodiment, the first device wafer 30 is bonded to the carrier 10 by wafer-on-wafer bonding. A surface dielectric layer among the plurality of dielectric layers 40 (e.g., dielectric bonding layer) is bonded to the bonding layer 14 by fusion bonding. In one embodiment, the fusion bonding forms Si-O-Si bonds to connect the surface dielectric layer among the plurality of dielectric layers 40 (e.g., dielectric bonding layer) to the bonding layer 14.

[0025] exist Figure 1 , edge seal layer 48 is dispensed into the edge gap between substrate 12 and substrate 32, which may be above dielectric layer 40. According to some embodiments, edge seal layer 48 is formed of or includes a polymer, which may be polyimide, PBO, or the like. Edge seal layer 48 may be dispensed in a flowable form and may then be hardened and solidified. Additionally, edge seal layer 48 may be dispensed as a ring that completely surrounds front inline structure 38.

[0026] See also Figure 2, a first wafer edge trimming process 200 is performed to form a recess 50, which forms a recess ring along the periphery of the carrier 10 and the first device wafer 30. A back side planarization process 250 is then performed from the back side of the first device wafer 30, and the substrate 32 is thinned. The back side planarization process 250 can be performed by a chemical mechanical polishing (CMP) process, a mechanical polishing process, a grinding process, etc. In one embodiment, during the back side planarization process 250, the edge sealing layer 48 ( Figure 2 The back surface planarization process 250 may be performed until the through-hole 36 is exposed.

[0027] Further after the backside planarization process 250, in one embodiment, a portion of the substrate 32 may be further removed to form a recess (not shown separately). The recess may be formed so that the through-hole 36 protrudes from the substrate 32. The recess may then be filled with an isolation layer (not shown separately). According to some embodiments, the recess is formed in the substrate 32 using an etching process that selectively etches the substrate 32 without significantly etching the through-hole 36. In some embodiments, an isolation material may be formed in the recess in which the isolation layer is formed. The isolation layer may be formed of a dielectric material. The dielectric material may be an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), tetraethoxysilane (TEOS)-based oxide, or the like, which may be formed by an appropriate deposition process such as CVD, ALD, or the like. Other suitable dielectric materials may also be used, such as low-temperature polyimide materials, polybenzoxazole (PBO), encapsulants, combinations thereof, or the like. The isolation layer may isolate the through-hole 36 from the substrate 32 of the first device wafer 30. Furthermore, in one embodiment, another planarization process may be performed on the dielectric material of the isolation layer to remove excess material from the isolation layer until the top surface of the through hole 36 is fully exposed through the isolation layer. In this embodiment, the planarization process may be any suitable planarization process, such as a CMP process, a grinding process, or the like, or a combination thereof.

[0028] In one embodiment, the first wafer edge trimming process 200 may cause the carrier 10 to have a first thickness Th1 in the recess 50, while a portion of the substrate 12 remains below the recess 50. The first thickness Th1 may be in the range of 5 μm to 350 μm. In addition, the front side inline structure 38 may be formed to have a second thickness Th2. The second thickness Th2 may be in the range of 0.1 μm to 30 μm. After the back side planarization process 250 and any subsequent planarization processes, the substrate 32 may be formed to a third thickness Th3. The third thickness Th3 may be in the range of 0.1 μm to 200 μm. In one embodiment, the resulting first device wafer 30 may have a fourth thickness Th4. The fourth thickness Th4 may be in the range of 0.2 μm to 230 μm.

[0029] refer to Figure 3 , the second device wafer 300 is attached to the first device wafer 30 using the first bonding layer 350. In one embodiment, the first bonding layer 350 is formed on the back side of the first device wafer 30. In one embodiment, the first bonding layer 350 may include a dielectric layer 352 and a first bonding pad 354 within the dielectric layer 352. In some embodiments, the first bonding pad 354 may include a conductive material, such as copper or the like. Some first bonding pads 354 may be physically and electrically coupled to the through-hole 36. In one embodiment, the dielectric layer 352 may include a silicon-containing dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or the like, or a combination thereof. In one embodiment, the dielectric layer 352 may be deposited using an appropriate deposition process, such as CVD, PVD, ALD, HDPCVD, the like, or a combination thereof. Optionally, a planarization step may then be performed to flatten the top surface of the first bonding layer 350 so that the first bonding layer 350 has a high flatness. Other materials and formation methods are also possible.

[0030] According to some embodiments, a first bonding pad 354 may be formed over the isolation layer and the through-hole 36 before forming the dielectric layer 352. As an example, in order to form the first bonding pad 354, a seed layer (not shown separately) may be formed over the through-hole 36 and the substrate 32. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer including a plurality of sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer on the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is then formed on the seed layer and patterned. The photoresist may be formed by spin coating or the like, and may be exposed for patterning. The pattern of the photoresist corresponds to the first bonding pad 354. An opening is formed through the patterning of the photoresist to expose the seed layer. A conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating or the like. The conductive material may include a metal, such as copper, titanium, tungsten, aluminum, or the like. Then, the photoresist and the portion of the seed layer on which the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma or the like. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portion of the seed layer and the conductive material form the first bonding pad 354. In addition, the dielectric layer 352 can be formed by spin coating, lamination, CVD, the like, or a combination thereof after the first bonding pad 354 is formed, and the dielectric layer 352 can then be planarized to expose the first bonding pad 354.

[0031] According to another embodiment, the dielectric layer 352 is formed before the first bonding pad 354. The dielectric layer 352 can be formed over the substrate 32 by spin coating, lamination, CVD, the like, or a combination thereof. The first bonding pad 354 can then be formed in the dielectric layer 352 by forming a recess (not shown separately) in the dielectric layer 352 (e.g., etching, milling, laser technology, the like, or a combination thereof). A thin barrier layer (not shown separately) can be conformally deposited in the recess, for example, by CVD, ALD, PVD, thermal oxidation, a combination thereof, or the like. The barrier layer can be formed of an oxide, a nitride, a carbide, a combination thereof, or the like. A conductive material can be deposited over the barrier layer and in the recess. The conductive material can be formed by an electrochemical plating process, CVD, ALD, PVD, the like, or a combination thereof. Examples of conductive materials include copper, tungsten, aluminum, silver, gold, a combination thereof, or the like. Excess conductive material and barrier layer may then be removed from the surface of dielectric layer 352 , for example, by a planarization process (eg, CMP process). The remaining portion of the barrier layer and conductive material in the recess forms a first bonding pad 354 .

[0032] Figure 3It is further shown that the second device wafer 300 is attached to the first device wafer 30 using the first bonding layer 350. In an embodiment, the second device wafer 300 may be an unsawn wafer. According to some embodiments, the second device wafer 300 includes a substrate 322, an integrated circuit device (not shown separately) at a surface of the substrate 322, and a front-side inline structure 328. In an embodiment, the integrated circuit device may include a complementary metal oxide semiconductor (CMOS), a transistor, a resistor, a capacitor, a diode, and / or the like. In an embodiment, the front-side inline structure 328 is formed on the front side of the substrate 322. The front-side inline structure 328 may include a plurality of dielectric layers 340, such as an interlayer dielectric (ILD), an intermetallic dielectric (IMD), a non-low-k passivation layer, a polymer layer, and / or the like. According to some exemplary embodiments, the ILD is formed of silicon oxide, PSG, BSG, BPSG, FSG, or the like, or includes silicon oxide, PSG, BSG, BPSG, FSG, or the like. The IMD layer may be formed of a low-k dielectric material having a dielectric constant (k value) lower than about 3.0. For example, the IMD layer may include a carbon-containing low-k dielectric material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), and the like.

[0033] In one embodiment, the front-side interconnect structure 328 also includes a conductive feature in the dielectric layer. The conductive feature may include a contact plug, a metal line, a metal pad, a metal via, and / or the like, for example, a metal pad 344. The contact plug may be formed of tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multiple layers thereof. Each of the metal line and the metal via may include a copper-containing metal material on a diffusion barrier layer and on the diffusion barrier layer. The diffusion barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like.

[0034] According to some embodiments, metal pads 344 are formed in the plurality of dielectric layers 340. Metal pads 344 may be formed of or include aluminum, copper, nickel, titanium, palladium, or the like, or alloys thereof. According to some embodiments, metal pads 344 are in the passivation layer. According to some embodiments, a polymer layer (which may be polyimide, polybenzoxazole (PBO), or the like) may be formed, wherein metal pads 344 are located in the polymer layer. In one embodiment, metal pads 344 are formed and may be subsequently processed so that metal pads 344 have an exposed surface at the outer surface of dielectric layer 340.

[0035] In addition, the second device wafer 300 can be attached to the first device wafer 30 by bonding the features of the front side interconnect structure 328 to the first bonding layer 350. In some embodiments, bonding the first device wafer 30 to the second device wafer 300 includes performing dielectric-to-dielectric and metal-to-metal bonding processes between the first bonding layer 350 and the features of the front side interconnect structure 328 (e.g., the dielectric layer 340 and the metal pad 344). In some embodiments, the dielectric-to-dielectric bonding process forms a direct bond (e.g., a fusion bond, such as an oxide-to-oxide bond) between the dielectric layer 352 and the dielectric layer 340. In addition, the metal-to-metal bonding process can directly bond the first bonding pad 354 of the first bonding layer 350 to the metal pad 344 of the front side interconnect structure 328 through direct metal-to-metal bonding. Therefore, the electrical connection between the first device wafer 30 and the second device wafer 300 can be provided through the physical connection of the first bonding pad 354 to the metal pad 344.

[0036] The dielectric-to-dielectric bonding process may begin by applying a surface treatment to one or both of dielectric layer 352 and dielectric layer 340 to promote dielectric-to-dielectric bonds (e.g., oxide-to-oxide bonds) between dielectric layer 352 and dielectric layer 340. The surface treatment may include a plasma treatment. The plasma treatment may be performed in a vacuum environment. After the plasma treatment, the surface treatment may also include a cleaning process (e.g., rinsing with deionized water or the like), which may be applied to either or both of dielectric layer 352 and dielectric layer 340.

[0037] The dielectric-to-dielectric and metal-to-metal bonding process may then proceed to align the first bonding pad 354 with the metal pad 344. Next, the dielectric-to-dielectric and metal-to-metal bonding process includes a pre-bonding step during which the second device wafer 300 is contacted with the first bonding layer 350. The pre-bonding may be performed at room temperature (e.g., between about 21° C. and about 25° C.). The dielectric-to-dielectric and metal-to-metal bonding process proceeds to perform an anneal at a temperature between, for example, about 150° C. and about 400° C. for a duration between about 0.5 hours and about 3 hours, such that the first bonding pad 354 (e.g., copper) and the metal pad 344 (e.g., copper) interdiffuse with each other, thereby forming a direct metal-to-metal bond.

[0038] After bonding the second device wafer 300 to the first device wafer 30, in some embodiments, a second wafer edge trimming process can be performed. The second wafer edge trimming process can trim the edges of the second device wafer 300 and the first device wafer 30. In some embodiments, the second wafer edge trimming process causes the edges of the second device wafer 300 and the first device wafer 30 to be planar.

[0039] In one embodiment, the front-side inline structure 328 of the second device wafer 300 is formed to a fifth thickness Th5. The fifth thickness may be in the range of 0.1 μm to 30 μm. In addition, the substrate 322 may have a sixth thickness Th6. The sixth thickness Th6 may be in the range of 0.1 μm to 775 μm. In this embodiment, the second device wafer 300 may have a seventh thickness Th7. The seventh thickness Th7 may be in the range of 0.2 μm to 805 μm.

[0040] Furthermore, it should be noted that the process of attaching the second device wafer 300 to the first device wafer 30 can be repeated to form a stack of any number of device wafers as desired ( Fig.13 and 14 ). The device wafers may be electrically connected to each other through metallization lines and vias contained within the device wafers. Additionally, in one embodiment, each device wafer (e.g., first device wafer 30, second device wafer 300, etc.) has an area in a top view that is equal to or substantially equal to the area of ​​another device wafer.

[0041] refer to Figure 4 According to some embodiments, a support substrate 88 is attached to the substrate 322 on the back side of the second device wafer 300. In some embodiments, the support substrate 88 is in the form of a wafer and is therefore also referred to as a support wafer. The support substrate 88 can be bonded to the substrate 322. According to some embodiments, a bonding layer 92 is preformed on the support substrate 88, for example, through a thermal oxidation process or a deposition process, and a structure including the bonding layer 92 and the support substrate 88 is bonded to the substrate 322.

[0042] In one embodiment, the bonding layer 92 may be a silicon-containing dielectric layer formed of or containing SiO2, SiN, SiC, SiON, or the like. The deposition process may include LPCVD, PECVD, PVD, ALD, PEALD, or the like. The support substrate 88 may be formed of a material having a high thermal conductivity. According to some embodiments, the support substrate 88 is a silicon substrate, however another type of substrate may be used, such as another semiconductor substrate, a dielectric substrate, a metal substrate, or the like. The entire support substrate 88 may be formed of a homogeneous material. For example, the support substrate 88 may not contain active and passive devices, metal lines, dielectric layers, and the like. The bonding of the bonding layer 92 to the substrate 322 may include fusion bonding.

[0043] According to some embodiments, after the bonding process, the support substrate 88 is thinned, for example, by a mechanical grinding process or a CMP process, so that the thickness of the support substrate 88 is reduced to an appropriate value. In one embodiment, the support substrate 88 is thinned so that the support substrate 88 is thick enough to support subsequent grinding and is not too thick. According to some embodiments, the support substrate 88 is not thinned.

[0044] See also Figure 5 After the second device wafer 300 is bonded to the first device wafer 30, Figure 4 The intermediate wafer obtained on the wafer structure shown is turned over, as shown in FIG. Figure 5 As shown. It should be noted that the wafer-on-wafer structure is formed without any insulating or gap filling material. In one embodiment, the carrier 10 can be removed by a planarization process, such as a mechanical grinding process, a CMP process, the like, or a combination thereof. In one embodiment, a singulation process 500 can be performed along the dicing street 508. The singulation process 500 can be a sawing process, a trimming process, or the like. However, any suitable singulation process can be performed to produce the first semiconductor package 600 ( Figure 5 Not shown in, but shown in Figure 6 In addition, in one embodiment, the integrated circuit devices in the first device wafer 30 and the integrated circuit devices in the second device wafer 300 are aligned to form functional circuits between the first device wafer 30 and the second device wafer 300 after the singulation process 500 in the resulting first semiconductor package 600.

[0045] See also Figure 6 , the singulation process 500 forms a first semiconductor package 600. In an embodiment, the first semiconductor package includes a carrier substrate 688, a first semiconductor device 630, and a second semiconductor device 650. In an embodiment, as a result of the singulation process 500, the carrier substrate 688 is formed from a portion of the support substrate 88. As a result of the singulation process 500, the first semiconductor device 630 can be formed from a portion of the first device wafer 30. As a result of the singulation process 500, the second semiconductor device 650 can be formed from a portion of the second device wafer 300. In an embodiment, the sidewalls of the carrier substrate 688, the sidewalls of the first semiconductor device 630, and the sidewalls of the second semiconductor device 650 can be substantially flush with each other (within process variations) as a result of the singulation process 500.

[0046] Figures 1 to 6The advantages of the embodiments discussed in are achieved by reducing cost and cycle time. By directly bonding the first device wafer 30 to the second device wafer 300 (and possibly subsequent additional device wafers), multiple semiconductor packages can be formed from the WoWoW structure after the singulation process 500 without the need for separate die preparation and gap fill processes associated with bonding separate chips to form such 3DIC packages. The reduction in separate die preparation and gap fill processes reduces cost and manufacturing cycle time.

[0047] Figures 7 to 12 A second semiconductor package 1200 ( Fig.12 1 . In this embodiment, the second semiconductor package 1200 is formed by various processing steps of directly bonding one or more device wafers to a plurality of Tier 1 semiconductor dies (Tier 1 refers to the first structure bonded to the carrier wafer) using a support and carrier wafer during the processing steps. Bonding the one or more device wafers to the plurality of semiconductor dies using a support and carrier wafer produces a chip-on-wafer-on-wafer (CoWoW) structure, which can then be singulated into individual semiconductor packages (e.g., the second semiconductor package 1200).

[0048] refer to Figure 7 According to some embodiments, a plurality of device dies 62 are bonded to a wafer 710. In one embodiment, the wafer 710 is a carrier having no active devices (eg, transistors) and passive devices therein, and thus may be referred to as a carrier 710 hereinafter. The carrier 710 may have a circular top view shape, Figure 7 An edge portion of the wafer 710 is shown. According to some embodiments, the carrier 710 includes a substrate 712. The substrate 712 may be a blank substrate. In one embodiment, the substrate 712 may be a semiconductor substrate, such as a silicon substrate. In some embodiments, the substrate 712 may include other semiconductor materials, such as silicon germanium, carbon-doped silicon, or the like. The substrate 712 may be a bulk substrate, or may have a layered structure, for example, including a silicon substrate and a silicon germanium layer on the silicon substrate. In some embodiments, the substrate 712 may be formed of other materials, for example, ceramics, glass, silicate glass, or the like may also be used. According to some embodiments, the entire substrate 712 is formed of a homogeneous material, wherein there is no other material different from the homogeneous material. For example, the substrate 712 may be formed of silicon (doped or undoped) and wherein there are no metal regions, dielectric regions, etc.

[0049] In another embodiment, wafer 710 is a device wafer including active devices (e.g., transistors) and / or passive devices (e.g., capacitors, resistors, inductors, and / or the like) therein. When wafer 710 is a device wafer, wafer 710 may be an unsawn wafer including a semiconductor substrate extending continuously across all device dies in the wafer, or may be a reconstructed wafer including discrete device dies encapsulated in an encapsulation (e.g., a molding compound or an inorganic gap-fill region).

[0050] In one embodiment, the bonding layer 714 is deposited on the substrate 712. According to some embodiments, the bonding layer 714 is formed of or includes a dielectric material, which may be a silicon-based dielectric material, such as silicon oxide (SiO2), SiN, SiON, SiOCN, SiC, SiCN, or the like, or a combination thereof. According to some embodiments, the bonding layer 714 is formed using high density plasma chemical vapor deposition (HDPCVD), plasma enhanced chemical vapor deposition (PECVD), chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), or the like.

[0051] According to some embodiments, the bonding layer 714 is in physical contact with the substrate 712. According to some embodiments, the carrier 710 includes a plurality of layers (not shown) between the bonding layer 714 and the substrate 712. For example, there may be an oxide-based layer formed of an oxide-based material (which may also be silicon oxide-based), such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), or the like. There may also be a nitride-based layer formed of or including silicon nitride, silicon oxynitride (SiON), or the like. According to some embodiments, the layer between the substrate 712 and the bonding layer 714 may be formed using PECVD, CVD, LPCVD, ALD, or the like. An alignment mark (not shown) may also be formed between the bonding layer 714 and the substrate 712. The alignment mark may be formed as a metal plug, which may be formed through a damascene process.

[0052] In one embodiment, the plurality of device dies 62 may each include a substrate 64, an integrated circuit (not shown separately) at a surface of the substrate 64, an interconnect structure 68 (which includes a dielectric layer 70 and a conductive feature (not shown separately)), and a through-substrate via (TSV) 736. In one embodiment, the substrate 64 is formed in a similar manner and from a similar material as the substrate 32 described above, and may be further formed to a thickness that is the same as the thickness of the substrate 32. The plurality of device dies 62 may include logic dies, memory dies, input-output dies, or the like. For example, the logic device die may be a central processing unit (CPU) die, a graphics processing unit (GPU) die, a mobile application die, a microcontroller unit (MCU) die, a baseband (BB) die, an application processor (AP) die, or the like. The memory die may include a static random access memory (SRAM) die, a dynamic random access memory (DRAM) die, or the like.

[0053] Substrate 64 may be a silicon substrate. Dielectric layer 70 may include a passivation layer (not shown separately) on the surface of substrate 64, a dielectric bonding layer (not shown separately) as the outermost dielectric layer of dielectric layer 70, and an additional dielectric layer (not shown separately) between the passivation layer and the dielectric bonding layer. In one embodiment, dielectric layer 70 may be formed of similar materials and similar processes to form a structure similar to the plurality of dielectric layers 40 discussed above. However, any suitable materials and processes may be used to form dielectric layer 70. Conductive features may include contact plugs, metal lines, metal pads (e.g., metal pads 744), metal vias (e.g., TSV 736), and / or the like. The conductive features of inline structure 68 may be formed in a manner similar to the conductive features of front-side inline structure 38 discussed above and by similar processes, including the same thickness as front-side inline structure 38. However, any suitable materials and processes may be used to form the conductive features of inline structure 68. For example, the contact plug may be formed of tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multilayers thereof. Each of the metal line and the metal via may include a diffusion barrier layer and a copper-containing metal material on the diffusion barrier layer. The diffusion barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like.

[0054] According to some embodiments, metal pad 744 can be formed in the passivation layer of dielectric layer 70 in a similar manner as discussed above with respect to metal pad 44. The metal pad can be formed of or include aluminum, copper, nickel, titanium, palladium, or the like, or alloys thereof. According to some embodiments, the metal pad is in the passivation layer. According to an alternative embodiment, a polymer layer (which can be polyimide, polybenzoxazole (PBO), or the like) can be formed, wherein the metal pad is located in the polymer layer.

[0055] In one embodiment, the plurality of device dies 62 may be bonded to the carrier 710 via dielectric-to-dielectric bonding. A surface dielectric layer (e.g., a dielectric bonding layer) in the dielectric layer 70 is bonded to the bonding layer 714 via fusion bonding. In one embodiment, the fusion bonding forms Si-O-Si bonds to connect the surface dielectric layer in the dielectric layer 70 to the bonding layer 714.

[0056] refer to Figure 8 , showing a gap filling process for forming a gap filling layer / region 78 over a plurality of device dies 62 ( Figure 7 Only a single device die 62 is shown for clarity, and one or more device dies 62 are fully intended to be included within the scope of this discussion). In one embodiment, the gap fill layer 78 includes an adhesion layer 74 and a dielectric layer 76 on and in contact with the adhesion layer 74. The adhesion layer 74 may be deposited using a conformal deposition process such as ALD, CVD, the like, or a combination thereof. Thus, the adhesion layer 74 may be a conformal layer, for example, where the thickness of the horizontal portion and the thickness of the vertical portion are substantially equal to each other (e.g., with a variation of 20% or less). The adhesion layer 74 is formed of a dielectric material that has good adhesion to the sidewalls in the plurality of device dies 62 and the top surface in the bonding layer 714. According to some embodiments, the adhesion layer 74 is formed of or includes a nitride-containing material, such as silicon nitride.

[0057] In some embodiments, dielectric layer 76 is formed of a material different from that of adhesion layer 74. According to some embodiments, dielectric layer 76 is formed of or includes silicon oxide, although other dielectric materials such as silicon carbide, silicon oxynitride, silicon oxynitride carbon, or the like may also be used. Dielectric layer 76 may be a non-conformal layer having different thicknesses in horizontal and vertical portions, or may be a conformal layer.

[0058] Figure 8 Also shown is the formation of a second bonding layer 800 over the plurality of device dies 62 after the planarization process. In one embodiment, the planarization process may be performed to remove excess portions of the gap fill layer 78 over the plurality of device dies 62 such that the top surface of the substrate 64 is exposed. The planarization process may further thin the substrate 64 to expose the TSVs 736 within the substrate 64. The planarization process may be a CMP process, a grinding process, a polishing process, the like, or a combination thereof.

[0059] After the planarization process, in one embodiment, a portion of the substrate 64 may be further removed to form a recess (not shown separately). The recess may be formed so that the TSV 736 protrudes from the substrate 64. The recess may then be filled with the isolation layer 802. According to some embodiments, a recess is formed in the substrate 64 using an etching process, and the etching process selectively etches the substrate 64 without significantly etching the TSV 736. In some embodiments, an isolation material may be formed in the recess in which the isolation layer 802 is formed. The isolation layer 802 may be formed of a dielectric material. The dielectric material may be an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), tetraethoxysilane (TEOS)-based oxide or the like, which may be formed by an appropriate deposition process such as CVD, ALD or the like. Other suitable dielectric materials may also be used, such as low-temperature polyimide materials, polybenzoxazole (PBO), encapsulation, combinations thereof or the like. The isolation layer 802 may isolate the TSV 736 from the substrate 64 of the plurality of device dies 62 .

[0060] After forming the isolation layer 802, a second bonding layer 800 may be formed above the top surface of the gap filling layer 78 and above the isolation layer 802. In one embodiment, the second bonding layer 800 may include a dielectric layer 804 and a second bonding pad 806 embedded in the dielectric layer 804. In some embodiments, the second bonding pad 806 may include a conductive material, such as copper or the like. Some second bonding pads 806 may be physically and electrically coupled to the TSV 736. In one embodiment, the dielectric layer 804 may include a silicon-containing dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride or the like, and the dielectric layer 804 may be deposited using an appropriate deposition process, such as CVD, PVD, ALD, HDPCVD, a combination of these or the like. Optionally, a planarization step may then be performed to level the top surface of the second bonding layer 800 so that the second bonding layer 800 has a high flatness. Other materials and formation methods are also possible. In addition, the second bonding layer 800 may be formed in a similar manner to that discussed above with respect to the first bonding layer 350.

[0061] refer to Fig. 9, the third device wafer 900 is attached to the plurality of device dies 62 over the gap fill layer 78. In an embodiment, the third device wafer 900 may be an unsawn wafer. According to some embodiments, the third device wafer 900 includes a substrate 922, an integrated circuit device (not shown separately) at a surface of the substrate 922, and a front-side inline structure 928. In an embodiment, the integrated circuit device may include a complementary metal oxide semiconductor (CMOS), a transistor, a resistor, a capacitor, a diode, and / or the like. In an embodiment, the front-side inline structure 928 is formed on the front side of the substrate 922. The front-side inline structure 928 may include a plurality of dielectric layers 940, such as an interlayer dielectric (ILD), an intermetallic dielectric (IMD), a non-low-k passivation layer, a polymer layer, and / or the like. According to some exemplary embodiments, the ILD is formed of silicon oxide, PSG, BSG, BPSG, FSG, or the like, or includes silicon oxide, PSG, BSG, BPSG, FSG, or the like. The IMD layer may be formed of a low-k dielectric material having a dielectric constant value (k value) less than about 3.0. For example, the IMD layer may include a carbon-containing low-k dielectric material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), or the like.

[0062] In one embodiment, the front side inline structure 928 also includes conductive features (not separately shown) in the plurality of dielectric layers 940. The conductive features may include contact plugs, metal lines, metal pads, metal vias, and / or the like, such as metal pads 944. In one embodiment, the plurality of dielectric layers 940 and the conductive features within the plurality of dielectric layers 940 may be formed in a manner similar to the plurality of dielectric layers 340 and the conductive features contained within the plurality of dielectric layers 340 described above. However, any suitable materials and processes may be utilized to form the plurality of dielectric layers 940 and the conductive features therein.

[0063] According to some embodiments, metal pad 944 is formed in dielectric layer 940. Metal pad 944 may be formed of or include aluminum, copper, nickel, titanium, palladium, or the like, or an alloy thereof. According to some embodiments, metal pad 944 is in the passivation layer. According to some embodiments, a polymer layer (which may be polyimide, polybenzoxazole (PBO), or the like) may be formed, wherein metal pad 944 is located in the polymer layer. In one embodiment, metal pad 944 is formed and may be subsequently processed so that metal pad 944 has an exposed surface at the outer surface of dielectric layer 940.

[0064] In addition, the third device wafer 900 can be attached to the plurality of device dies 62 by bonding features in the front side interconnect structure 928 to the second bonding layer 800. In some embodiments, the bonding of the third device wafer 900 includes dielectric-to-dielectric and metal-to-metal bonding processes between the second bonding layer 800 and features (e.g., dielectric layer 940 and metal pad 944) of the front side interconnect structure 928. In some embodiments, the dielectric-to-dielectric bonding process forms a direct bond (e.g., a fusion bond, such as an oxide-to-oxide bond) between the dielectric layer 804 and the dielectric layer 940. In addition, the metal-to-metal bonding process can directly bond the second bonding pad 806 of the second bonding layer 800 to the metal pad 944 of the front side interconnect structure 928 through direct metal-to-metal bonding. Thus, electrical connections between the plurality of device dies 62 and the third device wafer 900 can be provided through physical connections of the second bonding pad 806 to the metal pad 944.

[0065] The dielectric-to-dielectric bonding process may begin by applying a surface treatment to one or both of the dielectric layer 804 and the dielectric layer 940 to promote a dielectric-to-dielectric bond (e.g., oxide-to-oxide bond) between the dielectric layer 804 and the dielectric layer 940. The surface treatment may include a plasma treatment. The plasma treatment may be performed in a vacuum environment. After the plasma treatment, the surface treatment may also include a cleaning process (e.g., rinsing with deionized water or the like), which may be applied to either or both of the dielectric layer 804 and the dielectric layer 940.

[0066] The dielectric-to-dielectric and metal-to-metal bonding process may then proceed to align the second bonding pad 806 with the metal pad 944. Next, the dielectric-to-dielectric and metal-to-metal bonding process includes a pre-bonding step during which the third device wafer 900 is contacted with the second bonding layer 800. The pre-bonding may be performed at room temperature (e.g., between about 21° C. and about 25° C.). The dielectric-to-dielectric and metal-to-metal bonding process proceeds to perform an anneal at a temperature between, for example, about 150° C. and about 400° C. for a duration between about 0.5 hours and about 3 hours, such that the second bonding pad 806 (e.g., copper) and the metal pad 944 (e.g., copper) interdiffuse with each other, thereby forming a direct metal-to-metal bond.

[0067] refer to Fig.10 , a wafer edge trimming process is performed to form a recess 1050, which forms a recess ring around the carrier 710, the plurality of device dies 62 surrounded by the gap fill layer 78, and the third device wafer 900. A backside planarization process may then be performed from the backside of the third device wafer 900, and the substrate 922 may be thinned. The backside planarization process may be performed by a CMP process, a mechanical polishing process, a grinding process, or the like.

[0068] In addition, after the wafer edge trimming process, according to some embodiments, a support substrate 1088 is attached to the substrate 922 on the back side of the third device wafer 900. In some embodiments, the support substrate 1088 is in the form of a wafer, and is therefore also referred to as a support wafer. The support substrate 1088 may be bonded to the substrate 922. According to some embodiments, a bonding layer 1092 is preformed on the support substrate 1088, for example, through a thermal oxidation process or a deposition process, and a structure including the bonding layer 1092 and the support substrate 1088 is bonded to the substrate 922.

[0069] In one embodiment, the bonding layer 1092 may be a silicon-containing dielectric layer formed of SiO2, SiN, SiC, SiON, or the like, or including SiO2, SiN, SiC, SiON, or the like. The deposition process may include LPCVD, PECVD, PVD, ALD, PEALD, or the like. The support substrate 1088 may be formed of a material having a high thermal conductivity. According to some embodiments, the support substrate 1088 is a silicon substrate, however another type of substrate may be used, such as another semiconductor substrate, a dielectric substrate, a metal substrate, or the like. The entire support substrate 1088 may be formed of a homogeneous material. For example, the support substrate 1088 may not contain active and passive devices, metal lines, dielectric layers, and the like therein. The bonding of the bonding layer 1092 to the substrate 922 may include fusion bonding.

[0070] According to some embodiments, after the bonding process, the support substrate 1088 is thinned, for example, in a mechanical grinding process or a CMP process, so that the thickness of the support substrate 1088 is reduced to an appropriate value. In one embodiment, the support substrate 1088 is thinned so that the support substrate 1088 is thick enough to support subsequent grinding and is not too thick. According to some embodiments, the support substrate 1088 is not thinned.

[0071] refer to Fig.11 After the third device wafer 900 is bonded to the plurality of device dies 62, Fig.10 The intermediate structure of the chip on the resulting wafer is flipped, as shown Fig.11 In one embodiment, the carrier 710 may be removed by a planarization process, such as a mechanical grinding process, a CMP process, the like, or a combination thereof. In one embodiment, a singulation process 1100 may be performed along the scribe line 1108. The singulation process 1100 may be a sawing process, a trimming process, or the like. However, any suitable singulation process may be performed to produce the second semiconductor package 1200 ( Fig.11 Not shown in, but shown in Fig.12 middle).

[0072] refer to Fig.12, the singulation process 1100 forms a second semiconductor package 1200. In one embodiment, the second semiconductor package 1200 includes a carrier substrate 1288, a third semiconductor device 1230, and a fourth semiconductor device 1250. In one embodiment, as a result of the singulation process 1100, the carrier substrate 1288 is formed from a portion of the support substrate 1088. As a result of the singulation process 1100, the third semiconductor device 1230 can be formed from individual device dies 62 surrounded by singulated portions of the gap fill layer 78. As a result of the singulation process 1100, the fourth semiconductor device 1250 can be formed from a portion of the third device wafer 900.

[0073] See also Fig.13 , showing that another device wafer (eg, fourth device wafer 1300) is bonded to Figure 3 1. In this embodiment, fourth device wafer 1300 is bonded to second device wafer 300 in a manner similar to how second device wafer 300 is bonded to first device wafer 30. Figures 4 to 6 Prior to the processing steps performed in , an additional device wafer (e.g., fourth device wafer 1300) may be bonded to Figure 3 The structure shown. In one embodiment, the third bonding layer 1350 can be formed in a similar manner and from similar materials as the first bonding layer 350, wherein the dielectric layer 1352 and the third bonding pad 1354 can be formed in a similar manner and from similar materials as discussed above with respect to the dielectric layer 352 and the first bonding pad 354. The conductive features of the inline structure 1328 of the fourth device wafer 1300 can be formed in a similar manner and by a similar process as the conductive features of the front-side inline structure 38 discussed above, including the same thickness as the front-side inline structure 38. However, any suitable materials and processes can be used to form the conductive features of the inline structure 1328. The conductive features can be formed in the dielectric layer 1340, for example, in a similar manner as the dielectric layer 340, and the dielectric layer 1340 can be a structure similar to the dielectric layer 340. Similarly, the metal pad 1344 can be formed in the dielectric layer 1340 in a manner similar to the metal pad 344 in the dielectric layer 340. Additionally, substrate 1322 may be formed in a similar manner and from similar materials as substrate 322, including similar structures contained within substrate 1322. Then, Fig.13 The intermediate structure shown can be continued as follows Figures 4 to 5 Similar process steps as described above, resulting in Fig.14 A third semiconductor package 1400 is shown.

[0074] refer to Fig.14 , a third semiconductor package 1400 is shown after the singulation process, similar to the above reference Figure 5 In one embodiment, after the singulation process, the first semiconductor device 630, the second semiconductor device 650, the fifth semiconductor device 1450 and the carrier substrate 688 are formed by the first device wafer 30, the second device wafer 300, the fourth device wafer 1300 and the support substrate 88, respectively. In one embodiment, the third semiconductor package 1400 includes the first semiconductor device 630, the second semiconductor device 650, the fifth semiconductor device 1450 and the support substrate 688.

[0075] Embodiments of the present disclosure achieve benefits. By directly bonding device wafer to device wafer (e.g., bonding first device wafer 30 to second device wafer 300), the cost and cycle time of manufacturing are reduced by eliminating the need to use a gap fill process when forming a semiconductor package. Combining wafer-on-wafer processing with chip-on-wafer bonding can improve the reliability of the manufacturing process of integrated circuits.

[0076] According to one embodiment, a method includes bonding a first device wafer to a first support wafer, bonding a second device wafer to the first device wafer, bonding the second support wafer to the second device wafer after bonding the second device wafer to the first device wafer, wherein the second support wafer has a larger area than the first device wafer and the second device wafer in a top view, and performing a singulation process on the first device wafer, the second device wafer, and the second support wafer to form a singulated semiconductor package. In one embodiment, the singulated semiconductor package is formed without utilizing a gap filling process. In one embodiment, bonding the first device wafer to the first support wafer includes forming a fusion bond. In one embodiment, it further includes removing the first support wafer before performing the singulation process. In one embodiment, removing the first support wafer includes performing chemical mechanical polishing. In one embodiment, it further includes performing a thinning process on the second support wafer before performing the singulation process. In one embodiment, it further includes performing a first edge trimming process on the first support wafer and the first device wafer before bonding the second device wafer to the first device wafer. In one embodiment, it further includes performing a second edge trimming process on the second device wafer after bonding the second device wafer to the first device wafer. In one embodiment, the singulation process is a sawing process.

[0077] According to an embodiment, a method includes bonding a plurality of device dies to a first wafer using a first bonding layer of the first wafer, depositing an insulating material over the first wafer, wherein the insulating material surrounds each of the plurality of device dies and encapsulates the first wafer, forming a second bonding layer over exposed surfaces of the plurality of device dies and over the insulating material, bonding the first device wafer to the second bonding layer opposite the plurality of device dies, performing a first edge trimming process on the first device wafer, the insulating material, and the first wafer after bonding the first device wafer to the second bonding layer, and performing a singulation process through the first device wafer and through the insulating material between each of the plurality of device dies. In an embodiment, further comprising bonding a second device wafer to the first device wafer opposite the plurality of device dies. In an embodiment, further comprising performing a second edge trimming process on the second device wafer. In an embodiment, further comprising bonding a second wafer to the first device wafer opposite the plurality of device dies, and removing the first wafer before performing the singulation process. In an embodiment, the insulating material includes an adhesive layer formed of a first dielectric material and a dielectric layer formed of a second dielectric material on the adhesive layer, the second dielectric material being different from the first dielectric material. In one embodiment, the singulation process is performed along scribe lines that pass through insulating materials between the plurality of device dies. In one embodiment, the plurality of device dies include logic dies.

[0078] According to one embodiment, a method for manufacturing a semiconductor device includes bonding a first device wafer to a first carrier wafer, the first device wafer having a first area in a top view, bonding a second device wafer to the first device wafer opposite to the first carrier wafer, the second device wafer having the first area in a top view. Bonding a third device wafer to a second device wafer opposite to the first device wafer, the third device wafer having the first area in a top view, performing an edge trimming process, wherein after the edge trimming process, a recess of the first carrier has a sidewall coplanar with the sidewalls of the first device wafer, the second device wafer, and the third device wafer, bonding the second carrier wafer to the third device wafer opposite to the second device wafer after performing the edge trimming process, and after bonding the second carrier wafer, removing the first carrier wafer. In one embodiment, it also includes performing a singulation process on the first device wafer, the second device wafer, the third device wafer, and the second carrier wafer. In one embodiment, the second carrier wafer includes a homogeneous substrate, the outer surface of which is covered by a dielectric bonding layer. In one embodiment, bonding the second carrier wafer includes forming a fusion bond between the dielectric bonding layer and the dielectric layer of the third device wafer.

[0079] The foregoing overview features and embodiments enable those skilled in the art to better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: bonding the first device wafer to the first support wafer; bonding a second device wafer to the first device wafer; bonding a second support wafer to the second device wafer after bonding the second device wafer to the first device wafer, wherein the second support wafer has a larger area than the first device wafer and the second device wafer in a top view; as well as A singulation process is performed on the first device wafer, the second device wafer, and the second support wafer to form singulated semiconductor packages.

2. The method according to claim 1, characterized in that The singulated semiconductor package is formed without using a gap-fill process.

3. The method according to claim 2, characterized in that Bonding the first device wafer to the first support wafer includes forming a fusion bond.

4. The method according to claim 3, characterized in that Also included is removing the first support wafer before performing the singulation process.

5. A method for manufacturing a semiconductor device, characterized in that: include: bonding a plurality of device dies to the first wafer using a first bonding layer of the first wafer; depositing an insulating material over the first wafer, wherein the insulating material surrounds each of the plurality of device dies and encapsulates the first wafer; forming a second bonding layer over the exposed surfaces of the plurality of device dies and over the insulating material; bonding a first device wafer to the second bonding layer opposite the plurality of device dies; After bonding the first device wafer to the second bonding layer, performing a first edge trimming process on the first device wafer, the insulating material, and the first wafer; and A singulation process is performed on the first device wafer and the insulating material between each of the plurality of device dies.

6. The method according to claim 5, characterized in that Also included is bonding a second device wafer to the first device wafer opposite the plurality of device dies.

7. The method according to claim 6, characterized in that Also included is performing a second edge trimming process on the second device wafer.

8. A method for manufacturing a semiconductor device, characterized in that: include: bonding a first device wafer to a first carrier wafer, the first device wafer having a first area in top view; bonding a second device wafer to the first device wafer opposite the first carrier wafer, the second device wafer having the first region in the top view; bonding a third device wafer to the second device wafer opposite to the first device wafer, the third device wafer having the first region in the top view; performing an edge trimming process, wherein after the edge trimming process, the recess of the first carrier wafer has sidewalls that are coplanar with sidewalls of the first device wafer, the second device wafer, and the third device wafer; After performing the edge trimming process, bonding a second carrier wafer to the third device wafer opposite to the second device wafer; as well as After bonding the second carrier wafer, the first carrier wafer is removed.

9. The method according to claim 8, characterized in that The second carrier wafer includes a homogeneous substrate having an outer surface covered by a dielectric bonding layer.

10. The method according to claim 9, characterized in that Bonding the second carrier wafer includes forming a fusion bond between the dielectric bonding layer and a dielectric layer of the third device wafer.

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