Self-adaptive zero-crossing comparator capable of sampling off-chip inductive current change rate

Abstract

The invention belongs to the technical field of integrated circuits, and relates to a self-adaptive zero-crossing comparator capable of sampling off-chip inductive current change rate for a synchronous rectification DC-DC converter, and the self-adaptive zero-crossing comparator specifically comprises a biasing circuit, an inductive current sampling circuit, a clamping operational amplifier and a zero-crossing comparator. The bias circuit provides bias current for other modules, the inductive current sampling circuit samples SW voltage of the synchronous rectification DC-DC converter, calculates inductive current and converts the inductive current into output voltage SENSOR, the clamping operational amplifier and the zero-crossing comparator output control signals ZCDOUT, and a zero-crossing detection line can be automatically adjusted according to a sampling result of an off-chip inductive current change rate. The self-adaptive zero-crossing comparator has the beneficial effects that the provided self-adaptive zero-crossing comparator can automatically adjust the overturning threshold according to the off-chip inductor current change rate, so that the efficiency of the synchronous rectification DC-DC converter in a light-load DCM working mode in different application scenes is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to an adaptive zero-crossing comparator (Adaptive Zero Current Detector, AZCD) circuit for a synchronous rectification DC-DC converter capable of sampling an off-chip inductor current change rate. Background Art

[0002] The synchronous rectification DC-DC converter is a power management circuit with the advantages of low conduction loss and high efficiency. In order to meet the requirements of different load currents, the synchronous rectification DC-DC converter often uses discontinuous conduction mode (DCM) to improve efficiency when the load is light, that is, when the upper power tube is turned off and the lower power tube is turned on, the change of the inductor current is detected. When the inductor current drops to zero, the upper and lower power tubes are turned off through logic control. The zero-crossing comparator is the key to realize this control mode.

[0003] However, there is a transmission line delay t between the time when the zero-crossing comparator detects that the inductor current drops to zero and triggers the lower power tube shutdown signal and the lower power tube shuts down. delay This delay will cause an error between the inductor current and the zero-crossing detection line when the lower power tube is actually turned off, causing the inductor to reverse and affecting the overall efficiency of the chip. Traditional zero-crossing comparators often reduce errors by reducing transmission line delays or controlling offset voltages to flip the comparator in advance. However, since the current error is affected by off-chip inductance and output voltage, the above methods cannot cover all application scenarios of synchronous rectification DC-DC converters. Summary of the invention

[0004] The present invention aims to solve the above problem and proposes an adaptive zero-crossing comparator capable of sampling the rate of change of the off-chip inductor current.

[0005] To achieve the above object, the present invention adopts the following technical solution:

[0006] An adaptive zero-crossing comparator capable of sampling the rate of change of an off-chip inductor current comprises a bias circuit, an inductor current sampling circuit, a clamping operational amplifier and a zero-crossing comparator. The invention is characterized in that the adaptive zero-crossing comparator can sample the rate of change of the off-chip inductor current when the lower power tube is turned on, and automatically adjust the zero-crossing detection threshold according to the sampling result, so as to reduce the current detection error, so as to improve the efficiency of the synchronous rectification DC-DC converter in the light-load DCM working mode in different application scenarios.

[0007] The bias circuit adopts a common bias circuit structure to provide bias current for the subsequent inductor current sampling circuit, clamping operational amplifier, and zero-crossing comparator.

[0008] The clamping operational amplifier adopts a common operational amplifier structure, with its positive input connected to the output voltage V3 of the inductor current sampling circuit, its negative input connected to the zero-crossing comparator input voltage V4, and its output generating V X And input to the zero-crossing comparator.

[0009] The inductor current sampling circuit includes a first current mirror PMOS tube M P1 , the second current mirror PMOS tube M P2 , the third feedback PMOS tube M P3 , the first source follower NMOS tube M N1 , the second current mirror NMOS tube M N2 , the third current mirror NMOS tube M N3 , a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4. The first current mirror PMOS tube M P1 and the second current mirror PMOS tube M P2 The current mirror structure is formed, and its source is connected to the power supply V CC , M P1 The drain electrode is connected to the positive electrode of the first resistor R1 and the first source follower NMOS tube M N1 The gate is connected to generate voltage V1 and input to the zero-crossing comparator, M N1 The drain and the negative terminal of R1 are both grounded, M N1 Source connection output SENSOR signal, M P2 The gate and drain are short-circuited, and the third feedback PMOS tube M is connected at the same time. P3 Source. Second current mirror NMOS tube M N2 and the third current mirror NMOS tube M N3 The current mirror structure is formed, and both drains are connected to the bias current I Bias1 , M N2 The gate and drain are short-circuited, and the source is connected to the positive electrode of the second resistor R2 and M P3 The drain generates voltage V2, and the negative electrode of R2 is connected to the SW input signal. N3 The source is connected in series with the third resistor R3 and the fourth resistor R4, a voltage V3 is generated between the cathode of R3 and the anode of R4, and the cathode of R4 is grounded.

[0010] The zero-crossing comparator includes a fourth current mirror PMOS tube M P4 , the fifth current mirror PMOS tube M P5 , the sixth feedback PMOS tube M P6 , the seventh current mirror PMOS tube M P7 , the eighth current mirror PMOS tube M P8 , the fourth current mirror NMOS tube M N4 , the fifth current mirror NMOS tube M N5, the sixth input NMOS pair tube M N6 , the seventh NMOS input pair transistor M N7 , a fifth resistor R5, a sixth resistor R6, and a compensation resistor R S and compensation capacitor C S . M P4 and M P5 The current mirror structure is formed, and the source of the two tubes is connected to the power supply V CC , M P4 The gate and drain are short-circuited, and the sixth feedback PMOS tube M is connected at the same time. P6 Source, M P6 The gate is connected to the clamped op amp output, generating a voltage V X , the drain is connected to the negative input terminal of the clamping operational amplifier and the positive electrode of the fifth resistor R5, generating a voltage V4, and the negative electrode of R5 is grounded. P5 The drain is connected to the positive electrode of the sixth resistor R6, generating a voltage V Det . M N4 and M N5 The current mirror structure is formed, the source of the two tubes is grounded, M N4 The gate and drain are short-circuited, and the bias current I Bias3 , M N5 Drain connection M N6 , M N7 Source. The seventh current mirror PMOS tube M P7 and the eighth current mirror PMOS tube M P8 The current mirror structure is formed, and the source of the two tubes is connected to the power supply V CC , M P7 The gate and drain are short-circuited and connected to M N6 Drain, M P8 Drain connection M N7 Drain and zero-crossing comparator output signal ZCD OUT The sixth input NMOS pair tube M N6 and the seventh NMOS input pair transistor M N7 Form an input differential pair, M N6 Gate connection voltage V Det , M N7 The gate is connected to the voltage V1. The compensation resistor R S With compensation capacitor C S Series connection, C S Positive connection voltage V1, R S Negative connection voltage V4, C S Negative electrode and R S The positive electrode generates a voltage V S .

[0011] The beneficial effect of the present invention is that the adaptive zero-crossing comparator proposed in the present invention can automatically adjust the flip threshold according to the change rate of the off-chip inductor current, thereby improving the efficiency of the synchronous rectification DC-DC converter in the light-load DCM working mode in different application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 The overall block diagram of the adaptive zero-crossing comparator proposed by the present invention;

[0013] Figure 2 This is a structural diagram of the inductor current sampling proposed by the present invention;

[0014] Figure 3 It is a structural diagram of the zero-crossing comparator proposed by the present invention;

[0015] Figure 4 This is a waveform diagram of key nodes of the adaptive zero-crossing comparator proposed in the present invention. DETAILED DESCRIPTION

[0016] like Figure 1 As shown, an adaptive zero-crossing comparator capable of detecting the rate of change of an off-chip inductor current specifically includes a bias circuit, an inductor current sampling circuit, a clamping operational amplifier, and a zero-crossing comparator. The characteristic is that the rate of change of the off-chip inductor current can be sampled, and the zero-crossing detection line is automatically adjusted according to the sampling result, thereby reducing the zero-crossing detection error and improving the efficiency of the synchronous rectification DC-DC converter in the light-load DCM working mode in different application scenarios.

[0017] The bias circuit provides bias current for the subsequent inductor current sampling circuit, clamping operational amplifier, and zero-crossing comparator.

[0018] The input end of the inductor current sampling circuit is connected to the switch node SW of the synchronous rectification DC-DC converter, and the SW voltage is converted into a voltage signal proportional to the inductor current and output to the zero-crossing comparator. Specifically, the inductor current sampling circuit includes a first current mirror PMOS tube M P1 , the second current mirror PMOS tube M P2 , the third feedback PMOS tube M P3 , the first source follower NMOS tube M N1 , the second current mirror NMOS tube M N2 , the third current mirror NMOS tube M N3 , a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4. The first current mirror PMOS tube M P1 and the second current mirror PMOS tube M P2 The current mirror structure is formed, and its source is connected to the power supply V CC , M P1The drain electrode is connected to the positive electrode of the first resistor R1 and the first source follower NMOS tube M N1 The gate is connected to generate voltage V1 and input to the zero-crossing comparator, M N1 The drain and the negative terminal of R1 are both grounded, M N1 Source connection output SENSOR signal, M P2 The gate and drain are short-circuited, and the third feedback PMOS tube M is connected at the same time. P3 Source. Second current mirror NMOS tube M N2 and the third current mirror NMOS tube M N3 The current mirror structure is formed, and both drains are connected to the bias current I Bias1 , M N2 The gate and drain are short-circuited, and the source is connected to the positive electrode of the second resistor R2 and M P3 The drain generates voltage V2, and the negative electrode of R2 is connected to the SW input signal. N3 The source is connected in series with the third resistor R3 and the fourth resistor R4, a voltage V3 is generated between the cathode of R3 and the anode of R4, and the cathode of R4 is grounded.

[0019] like Figure 2 As shown, M N3 The bias current in the branch drops on the resistor string R3 and R4 to generate a voltage. N2 , M N3 , M P3 The image after clamping of the current mirror feedback loop is M N2 The source voltage is V2, R2 converts V2 into current I1, and flows through M N2 The bias current of the branch I Bias1 Make a difference and get the detection current I Sensor , the detection current can be expressed as:

[0020]

[0021] M P1 , M P2 The current mirror I Sensor Like M P1 The voltage V1 is obtained by dropping on the resistor R1. V1 passes through the source follower M N1 , is converted into the output voltage signal SENSOR. When the upper power tube of the synchronous rectification DC-DC converter is turned off and the lower power tube is turned on, I Sensor , V1 and the output voltage SENSOR are inversely proportional to the inductor current.

[0022] The positive input terminal V+ of the clamping operational amplifier is connected to the output voltage V3 of the inductor current sampling circuit, and the negative input terminal V- outputs the voltage V4 to the zero-crossing comparator, and clamps V4 to V3. The output terminal generates a voltage V XAnd it is input to the zero-crossing comparator, and together with the zero-crossing comparator forms a negative feedback loop.

[0023] The input terminal of the zero-crossing comparator is connected to the output voltage V1 of the inductor current sampling circuit, the negative input terminal voltage V4 of the clamping operational amplifier and the output terminal voltage V X , output zero-crossing comparison signal ZCD OUT Specifically, the zero-crossing comparator includes a fourth current mirror PMOS tube M P4 , the fifth current mirror PMOS tube M P5 , the sixth feedback PMOS tube M P6 , the seventh current mirror PMOS tube M P7 , the eighth current mirror PMOS tube M P8 , the fourth current mirror NMOS tube M N4 , the fifth current mirror NMOS tube M N5 , the sixth input NMOS pair tube M N6 , the seventh NMOS input pair transistor M N7 , a fifth resistor R5, a sixth resistor R6, and a compensation resistor R S and compensation capacitor C S . M P4 and M P5 The current mirror structure is formed, and the source of the two tubes is connected to the power supply V CC , M P4 The gate and drain are short-circuited, and the sixth feedback PMOS tube M is connected at the same time. P6 Source, M P6 The gate is connected to the clamped op amp output, generating a voltage V X , the drain is connected to the negative input terminal of the clamping operational amplifier and the positive electrode of the fifth resistor R5, generating a voltage V4, and the negative electrode of R5 is grounded. P5 The drain is connected to the positive electrode of the sixth resistor R6, generating a voltage V Det . M N4 and M N5 The current mirror structure is formed, the source of the two tubes is grounded, M N4 The gate and drain are short-circuited, and the bias current I Bias3 , M N5 Drain connection M N6 , M N7 Source. The seventh current mirror PMOS tube M P7 and the eighth current mirror PMOS tube M P8 The current mirror structure is formed, and the source of the two tubes is connected to the power supply V CC , M P7 The gate and drain are short-circuited and connected to M N6 Drain, M P8 Drain connection M N7 Drain and zero-crossing comparator output signal ZCD OUTThe sixth input NMOS pair tube M N6 and the seventh NMOS input pair transistor M N7 Form an input differential pair, M N6 Gate connection voltage V Det , M N7 The gate is connected to the voltage V1. The compensation resistor R S With compensation capacitor C S Series connection, C S Positive connection voltage V1, R S Negative connection voltage V4, C S Negative electrode and R S The positive electrode generates a voltage V S .

[0024] like Figure 3 As shown, the voltage V4 at the negative input of the clamping operational amplifier drops to the positive input of the resistor R5, generating a current I2. The output voltage V1 of the inductor current sampling circuit is connected to C S Positive input terminal, landed at C S , R S The current I generated in the series path RC ; Clamp the voltage V at the output of the operational amplifier X Connect M P6 The gate generates a current I Detector , the three currents satisfy the relationship:

[0025]

[0026] I Detector By M P4 , M P5 The current mirror image formed by the resistor R6 generates a voltage V Det , and input to M N6 The gate current I2 is constant, while V1 is proportional to the inductor current. When the upper power tube of the synchronous rectifier DC-DC converter is turned on and the lower power tube is turned off, the inductor current decreases linearly in the time domain. dV1 / dt and I RC are inversely proportional to the inductor current change rate di / dt, so I Detector and V Det Proportional to the rate of change of inductor current. M N7 The gate is connected to a voltage V1 that is proportional to the inductor current and V Det Comparison generates zero-crossing comparison output signal ZCD OUT .

[0027] In summary, the zero-crossing comparator flip threshold V Det It will change linearly with the inductor current change rate di / dt. Since the synchronous rectification DC-DC converter is turned on when the upper power tube is turned on, the inductor current change rate is equal to the output voltage VOUT and the ratio of the off-chip inductance L, so the adaptive zero-crossing comparator can be based on the output voltage V in the synchronous rectification DC-DC converter application environment. OUT And the off-chip inductor L, calculate the inductor current change rate, and then automatically modify the inductor current zero-crossing detection line to achieve adaptive zero-crossing comparison.

[0028] like Figure 4 As shown in Figure 1, (a) and (b) correspond to the two cases where the synchronous rectification DC-DC converter operates at a low inductor current change rate and a high inductor current change rate when the power tube switching cycle, input voltage, transmission line delay and other parameters are the same. In (a), the inductor current zero-crossing detection line is I L_th(a) , compared with I in (b) L_th(b) Closer to the zero current line, when the inductor current drops to I L_th(a) When the adaptive zero-crossing comparator outputs a signal ZCD OUT Turn high, after the transmission line delay t delay After that, the power tube is turned off, and the inductor current just drops to zero. In (b), due to the high rate of change of the inductor current, the inductor current zero-crossing detection line is automatically raised to I L_th(b) , compared to I L_th(a) Away from the zero current line, when the inductor current drops to I L_th(b) When the adaptive zero-crossing comparator outputs a signal ZCD OUT Turn high, after the same transmission line delay t delay After that, the lower power tube is turned off. In (b), due to the high rate of change of the inductor current, the same t delay The inductor current decreases during the time period (a), but compared to I L_th(a) Higher I L_th(b) This difference is just made up to ensure that the inductor current is still zero when the lower power tube is turned off, thereby realizing adaptive zero-crossing comparison.

Claims

1. An adaptive zero-crossing comparator capable of sampling the rate of change of an off-chip inductor current, characterized in that: It includes a bias circuit, an inductor current sampling circuit, a clamping operational amplifier and a zero-crossing comparator; The bias circuit is used to provide bias current for the inductor current sampling circuit, the clamping operational amplifier, and the zero-crossing comparator; The positive input terminal of the clamp operational amplifier is connected to the output voltage V3 of the inductor current sampling circuit, the negative input terminal is connected to the input voltage V4 of the zero-crossing comparator, and the output terminal generates a voltage V X And input to the zero-crossing comparator. The inductor current sampling circuit includes a first current mirror PMOS tube M P1 , the second current mirror PMOS tube M P2 , the third feedback PMOS tube M P3 , the first source follower NMOS tube M N1 , the second current mirror NMOS tube M N2 , the third current mirror NMOS tube M N3 , a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4; a first current mirror PMOS tube M P1 and the second current mirror PMOS tube M P2 The current mirror structure is formed, and its source is connected to the power supply V CC , the first current mirror PMOS tube M P1 The drain electrode is connected to the positive electrode of the first resistor R1 and the first source follower NMOS tube M N1 The gate is connected to generate a voltage V1 and input it to the zero-crossing comparator; the first source follower NMOS tube M N1 The drain and the negative electrode of the first resistor R1 are both grounded, and the first source follower NMOS tube M N1 The source outputs the SENSOR signal, and the second current mirror PMOS tube M P2 The gate and drain are short-circuited, and the third feedback PMOS tube M is connected at the same time. P3 Source: Second current mirror NMOS tube M N2 and the third current mirror NMOS tube M N3 The current mirror structure is formed, and both drains are connected to the bias current I Bias1 ; The second current mirror NMOS tube M N2 The gate and drain are short-circuited, and the source is connected to the positive electrode of the second resistor R2 and the third feedback PMOS tube M P3 The drain generates a voltage V2; the cathode of the second resistor R2 is connected to the SW input signal; the third current mirror NMOS tube M N3 The source is connected in series with the third resistor R3 and the fourth resistor R4, a voltage V3 is generated between the cathode of the third resistor R3 and the anode of the fourth resistor R4, and the cathode of the fourth resistor R4 is grounded; The zero-crossing comparator includes a fourth current mirror PMOS tube M P4 , the fifth current mirror PMOS tube M P5 , the sixth feedback PMOS tube M P6 , the seventh current mirror PMOS tube M P7 , the eighth current mirror PMOS tube M P8 , the fourth current mirror NMOS tube M N4 , the fifth current mirror NMOS tube M N5 , the sixth input NMOS pair tube M N6 , the seventh NMOS input pair transistor M N7 , a fifth resistor R5, a sixth resistor R6, and a compensation resistor R S and compensation capacitor C S ; The fourth current mirror PMOS tube M P4 and the fifth current mirror PMOS tube M P5 The current mirror structure is formed, and the source of the two tubes is connected to the power supply V CC ; The fourth current mirror PMOS tube M P4 The gate and drain are short-circuited, and the sixth feedback PMOS tube M is connected at the same time. P6 Source, sixth feedback PMOS tube M P6 The gate is connected to the clamped op amp output, generating a voltage V X , the sixth feedback PMOS tube M P6 The drain is connected to the negative input terminal of the clamp operational amplifier and the positive electrode of the fifth resistor R5 to generate a voltage V4; the negative electrode of the fifth resistor R5 is grounded; the fifth current mirror PMOS tube M P5 The drain is connected to the positive electrode of the sixth resistor R6, generating a voltage V Det ; The fourth current mirror NMOS tube M N4 and the fifth current mirror NMOS tube M N5 The current mirror structure is formed, the source of the two tubes is grounded, and the fourth current mirror NMOS tube M N4 The gate and drain are short-circuited, and the bias current I Bias3 , the fifth current mirror NMOS tube M N5 The drain is connected to the sixth input NMOS pair transistor M N6 The source and the seventh NMOS input pair transistor M N7 Source: seventh current mirror PMOS tube M P7 and the eighth current mirror PMOS tube M P8 The current mirror structure is formed, and the source of the two tubes is connected to the power supply V CC , the seventh current mirror PMOS tube M P7 The gate and drain are short-circuited, and the sixth input NMOS pair is connected. N6 Drain: The eighth current mirror PMOS tube M P8 The drain is connected to the seventh NMOS input pair transistor M N7 Drain and zero-crossing comparator output signal ZCD OUT ; The sixth input NMOS pair tube M N6 and the seventh NMOS input pair transistor M N7 Form an input differential pair, M N6 Gate connection voltage V Det , the seventh NMOS input pair tube M N7 Gate connection voltage V1; compensation resistor R S With compensation capacitor C S Series connection, compensation capacitor C S Positive connection voltage V1, compensation resistor R S Negative connection voltage V4, compensation capacitor C S Negative electrode and compensation resistor R S The positive electrode generates a voltage V S ; The adaptive zero-crossing comparator is based on the output voltage V in the application environment of the synchronous rectification DC-DC converter. OUT and the off-chip inductor L, calculate the inductor current change rate di / dt, and then automatically modify the inductor current zero-crossing detection line to achieve adaptive zero-crossing comparison.

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