High-resistance-state upper tube electric leakage processing circuit of H bridge

Abstract

The invention provides an H-bridge high-resistance-state upper tube electric leakage processing circuit which comprises two half-bridge driving assemblies, and each half-bridge driving assembly comprises a comparator connected with one H-bridge output end of an H-bridge circuit and an enabling control circuit connected with the enabling end of the comparator. The enabling control circuit is set to send a signal for switching the comparator into a comparison state when detecting that the H-bridge circuit is switched into a high-resistance state; when the comparator enters a comparison state and the voltage of the output end of the H bridge is higher than the power supply voltage, a comparison result signal of the comparator is used for starting the upper PMOS tube connected with the output end of the H bridge, and otherwise, the comparison result signal enables the upper PMOS tube to maintain a conventional working mode. According to the circuit, the output end voltage of the H bridge and the power supply voltage are compared in a high-resistance state, and the upper tube is controlled to be turned on and turned off according to a comparison result, so that the problem of electric leakage caused by conduction of a parasitic PNP device in the upper tube in the high-resistance state is solved.

Description

Technical Field

[0001] The invention belongs to the field of H-bridge circuits, and in particular relates to a high-impedance upper tube leakage processing circuit of an H-bridge, which is used to solve the upper tube leakage problem of the H-bridge circuit in a high-impedance state. Background Art

[0002] Figure 1 FIG. 1 shows a circuit diagram of an H-bridge circuit in the prior art, wherein the H-bridge circuit is used to drive a motor. Figure 1 As shown, the drain connection of the two pairs of power tubes is respectively used as the first H-bridge output terminal OUTA1 and the second H-bridge output terminal OUTB1 and is respectively connected to the two sides of the motor 109. The first H-bridge output terminal OUTA1 and the second H-bridge output terminal OUTB1 are used to drive the motor 109 from both sides. It should be noted that when the H-bridge circuit is working, the upper and lower pairs of MOS switch tubes on the same side of the motor 109 are not allowed to be turned on at the same time, because if they are turned on at the same time, it is equivalent to a path between the power supply and the ground, and a large current will flow directly from the power supply through the pair of switch tubes to the ground, which will cause the switch tubes to burn out. During normal operation, it is assumed that the upper left PMOS tube 101 on the left side of the motor 109 and the lower right NMOS tube 104 on the right side are turned on. This is called the forward drive mode. The current flows as shown by the black dotted line from the power supply voltage VDD → the upper left PMOS tube 101 → the first H-bridge output terminal OUTA1 → the motor 109 → the second H-bridge output terminal OUTB1 → the lower right NMOS tube 104 → the ground. Conversely, the upper right PMOS tube 102 on the right side of the motor 109 and the lower left NMOS tube 103 on the left side are turned on. The current flows from the power supply → the upper right PMOS tube 102 → the second H-bridge output terminal OUT B1 → the motor 109 → the first H-bridge output terminal OUTA1 → the lower left NMOS tube 103 → the ground. This is the reverse drive mode. The switching action between these two drive modes is called commutation.

[0003] During the forward and reverse switching process, a high impedance state is inevitable (turning off the four MOS tubes of the H bridge) due to external configuration and other reasons. If there is no leakage treatment circuit for the upper tube, the parasitic body diode will continue to flow. When the H bridge switches from forward drive to high impedance, the upper left PMOS tube, the lower right PMOS tube are turned on, the upper right PMOS is turned off, and the lower left NMOS tube is turned off to a high impedance state where all switch tubes are turned off. The inside of the DC motor can be equivalent to an inductor, that is, an inductive load. In the high-impedance state, since the inductance current of the motor cannot change suddenly, the current direction of the motor load 109 cannot change suddenly when it is from the first H-bridge output terminal OUTA1 to the second H-bridge output terminal OUTB1, and the current maintains the original direction of flow. The current direction changes from the original upper left PMOS tube 101 to the motor 109 and then through the lower right PMOS tube 104 (the direction of the black arrow) to the body diode 107 of the lower left NMOS tube 103 through the motor 109 and then to the body diode 106 of the upper right PMOS tube 102 (the direction of the red solid arrow). This phenomenon is called body diode freewheeling. Summary of the invention

[0004] The object of the present invention is to provide a high-impedance upper tube leakage processing circuit of an H-bridge to solve the upper tube leakage problem when the H-bridge circuit is in a high-impedance state.

[0005] In order to achieve the above-mentioned object, the present invention provides a high-impedance upper tube leakage processing circuit of an H-bridge, comprising two half-bridge driving components, each of which comprises a comparator connected to one of the H-bridge output terminals of the H-bridge circuit, and an enable control circuit connected to the enable terminal of the comparator; the enable control circuit is configured to send a signal to switch the comparator to a comparison state when detecting that the H-bridge circuit is switched to a high-impedance state; the comparator is configured to, when entering the comparison state, when the voltage at the H-bridge output terminal is higher than the power supply voltage, the comparison result signal of the comparator is used to turn on the upper PMOS tube connected to the H-bridge output terminal, otherwise, the comparison result signal enables the upper PMOS tube to maintain a normal working mode.

[0006] The enable control circuit is configured to send a signal to switch the comparator to a failure output state when the H-bridge circuit switches from a high impedance state to other states; when entering the failure output state, the comparison result signal output by the comparator enables the upper PMOS tube to maintain a normal working mode.

[0007] The enable control circuit is connected to a timing circuit, and the counting circuit is configured to count the number of times the comparator outputs a high level. When the count value reaches a preset count, the enable control circuit is driven to send a signal to switch the comparator to a disabled output state.

[0008] The preset count is 4-16.

[0009] When the comparison result signal is at a high level, it is used to turn on the upper PMOS tube connected to the output end of the H-bridge, and when the comparison result signal is at a low level, it is used to maintain the upper PMOS tube in a normal working mode.

[0010] The comparator is connected to the gate of the upper PMOS tube through a gate voltage logic control circuit. The gate voltage logic control circuit is configured to send a signal to turn on the upper PMOS tube when the comparison result signal of the comparator is used to turn on the upper PMOS tube connected to the output end of the H-bridge, and restore the normal working mode when the comparison result signal of the comparator causes the upper PMOS tube to maintain the normal working mode.

[0011] The comparator is connected to the gate of the upper PMOS tube through a driving circuit, and the driving circuit is used to generate a driving signal.

[0012] The driving circuit is a half-bridge driving circuit, and the two output ends of the half-bridge driving circuit are respectively connected to the gates of the upper PMOS tube and the lower NMOS tube connected to the H-bridge output end; or, each half-bridge driving component also includes a second driving circuit, and the second driving circuit is connected to the gate of the lower NMOS tube connected to the H-bridge output end.

[0013] When the comparison result signal is used to turn on the upper PMOS tube connected to the output end of the H-bridge, the turn-on time of the upper PMOS tube is the minimum time for the drive circuit itself to drive the upper PMOS tube to turn on.

[0014] The comparator is a single-sided hysteresis comparator with an upper threshold and a lower threshold.

[0015] The high-impedance upper tube leakage processing circuit of the H-bridge of the present invention compares the output terminal voltage of the H-bridge with the power supply voltage in the high-impedance state, and controls the opening and closing of the upper tube according to the comparison result of the output terminal voltage of the H-bridge and the power supply voltage, thereby solving the problem that when the H-bridge enters the high-impedance state, the upper tube has a voltage higher than VDD due to the conduction of the parasitic PNP device inside the upper PMOS tube to generate leakage current, thereby causing leakage, abnormal function, burning of the switch tube, power supply voltage fluctuation and other problems; and the counting circuit is designed not to turn on the PMOS tube after a preset count, so as to weaken the power supply voltage fluctuation, avoid the comparator turning high again due to the presence of capacitive coupling, and reopen the PMOS tube, resulting in a periodic cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a typical circuit diagram of an H-bridge circuit;

[0017] Figure 2 Yes Figure 1A cross-sectional view of the upper right PMOS tube and the lower right power tube of the H-bridge circuit shown;

[0018] Figure 3 is a circuit block diagram of a high-impedance upper tube leakage processing circuit of an H-bridge according to an embodiment of the present invention;

[0019] Figure 4 It is a waveform timing diagram of input and output signals of a comparator of a high-impedance upper tube leakage processing circuit of an H-bridge of the present invention.

[0020] Figure 5 It is a waveform timing diagram of the H-bridge output end and the power tube gate voltage of the high-resistance upper tube leakage processing circuit of the H-bridge of the present invention. DETAILED DESCRIPTION

[0021] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings.

[0022] The high-impedance upper tube leakage processing circuit of the H-bridge of the present invention is used to solve the upper tube leakage problem of the H-bridge circuit 100 when it is in a high-impedance state, thereby avoiding the parasitic PNP transistor being turned on to cause leakage, abnormal function, switch tube burning, power supply voltage fluctuation and other problems.

[0023] The specific structure of the H-bridge circuit 100 is as follows Figure 1 As shown, it includes a first H-bridge output terminal OUTA1 and a second H-bridge output terminal OUTB1 for connecting the two sides of the motor 109, an upper left PMOS tube 101 and a lower left NMOS tube 103 whose drain terminals are connected to the first H-bridge output terminal OUTA1, and an upper right PMOS tube 102 and a lower right NMOS tube 104 whose drain terminals are connected to the second H-bridge output terminal OUTB1. The sources of the upper left PMOS tube 101 and the upper right PMOS tube 102 are both connected to the power supply voltage VDD, and the sources of the lower left NMOS tube 103 and the lower right NMOS tube 104 are both grounded GND. Therefore, the turning on of the upper left PMOS tube 101, the lower left NMOS tube 103, the upper right PMOS tube 102, and the lower right NMOS tube 104 are all controlled by the voltages of their gates Gp1, Gn1, Gp2, and Gn2. For a PMOS tube, pulling up the gate voltage is a turn-off action, also called pull-up, and pulling down the voltage is a turn-on action, also called pull-down; for an NMOS tube, on the contrary, pulling up the gate voltage (pulling up) is a turn-on action, and pulling down the gate voltage (pulling down) is a turn-off action. The upper left PMOS tube 101, the lower left NMOS tube 103, the upper right PMOS tube 102, and the lower right NMOS tube 104 have a first parasitic body diode 105, a third parasitic body diode 107, a second parasitic body diode 106, and a fourth parasitic body diode 108, respectively.

[0024] The working modes of the motor 109 include a forward driving mode and a reverse driving mode. When the H-bridge is in the forward driving mode, the upper left PMOS tube 101 on the left side of the motor 109 and the lower right NMOS tube 104 on the right side are turned on, and the current flows as shown by the black dotted line from the power supply voltage VDD→upper left PMOS tube 101→first H-bridge output terminal OUTA1→motor 109→second H-bridge output terminal OUTB1→lower right NMOS tube 104→ground, which is defined as forward rotation. In the reverse driving mode, the upper right PMOS tube 102 on the right side of the motor 109 and the lower left NMOS tube 103 on the left side are turned on, and the current flows from the power supply→upper right PMOS tube 102→second H-bridge output terminal OUT B1→motor 109→first H-bridge output terminal OUTA1→lower left NMOS tube 103→ground, which is defined as reverse rotation.

[0025] In the process of forward switching and reverse switching, it is necessary to switch to a high impedance state in which both switch tubes are closed. In the high impedance state, since the inductance current of the motor cannot suddenly change through the motor, the current direction is still OUTA1→OUTB1. The left half bridge passes through the parasitic body diode 107, and the right half bridge passes through the second parasitic body diode 106. The current direction changes from the original upper left PMOS tube 101 to the motor 109 and then passes through the lower right PMOS tube 104 (black arrow direction) to the body diode 107 of the lower left NMOS tube 103 through the motor 109 and then flows to the body diode 106 of the upper right PMOS tube 102 (red solid arrow direction). This phenomenon is called body diode freewheeling.

[0026] At this time, it is equivalent to the external circuit injecting current into the second H-bridge output terminal OUTB1, which will cause the voltage at the OUTB1 terminal to be higher than the power supply voltage VDD, and the voltage is about VDD+0.7V.

[0027] like Figure 2 As shown, at this time, the drain terminal D of the upper right PMOS tube 102 and its N well NWH are forward biased, and minority carriers are injected into the N well of the upper right PMOS tube 102. In the upper right PMOS tube 102, the minority carriers are holes, and the majority carriers are electrons. Therefore, most of the injected holes will recombine with the electrons in the N well, but some holes will diffuse to the area of ​​the P-type substrate PSUB, so that the parasitic PNP triode from the drain terminal D (which connects the P-type semiconductor P+) of the upper right PMOS tube 102 to the N well NWH is turned on, resulting in leakage. When the high voltage at the second H-bridge output terminal OUTB1 reaches a certain level, the parasitic PNP triode from the drain terminal D (P+) of the PMOS inside the chip to the N well NWH is turned on, thereby causing leakage, abnormal function, burning of the switch tube, power supply voltage fluctuation and other problems.

[0028] For the present invention, it is necessary to avoid the leakage of the body diode of the upper tube to achieve freewheeling, thereby avoiding the parasitic PNP device inside the PMOS power tube to generate leakage current, thereby causing leakage, abnormal function, burning of the switch tube, power supply voltage fluctuation and other problems.

[0029] Figure 3 FIG. 1 is a circuit block diagram of a high-impedance upper tube leakage processing circuit of an H-bridge according to an embodiment of the present invention. Figure 3 As shown, the high-impedance upper tube leakage processing circuit of the H-bridge includes two symmetrical half-bridge driving components, namely a left half-bridge driving component and a right half-bridge driving component.

[0030] Among them, the left half-bridge driving component includes a first comparator 201, a first gate voltage logic control circuit 203 and a left half-bridge driving circuit 204 which are connected in sequence from the first H-bridge output terminal OUTA1 of the H-bridge circuit 100, and the two output terminals of the left half-bridge driving circuit 204 are respectively connected to the gates of the upper left PMOS tube 101 and the lower left NMOS tube 103.

[0031] In this embodiment, the non-inverting input terminal of the first comparator 201 is connected to the first H-bridge output terminal OUTA1 , and the inverting input terminal is connected to the power supply voltage VDD.

[0032] The output end of the first comparator 201 is connected to the first gate voltage logic control circuit 203 and the first counting circuit 205 at the same time, the first counting circuit 205 is connected to the first enable control circuit 206, and the first enable control circuit 206 is connected to the enable end of the first comparator 201. Therefore, the first comparator 201 outputs the comparison result signal to the first gate voltage logic control circuit 203 and the first counting circuit 205 at the same time.

[0033] The first counting circuit 205 is configured to count the number of times the first comparator 201 outputs a high level, and when the count value reaches a preset count, the first enabling control circuit 206 is driven to send a signal to switch the first comparator 201 to a disabled output state.

[0034] In this embodiment, the preset count is 8. In other embodiments, the preset count may be 4, 8, or 16; the preset count range may also be any value between 4 and 16.

[0035] In addition, the first enable control circuit 206 is configured to send a signal to switch the first comparator 201 to a disabled output state when the H-bridge circuit switches from a high-impedance state to other states; and is configured to send a signal to switch the first comparator 201 to a comparison state when it is detected that the H-bridge circuit switches to a high-impedance state.

[0036] In other embodiments, the first counting circuit 205 can be omitted. When the first enabling control circuit 206 is omitted, the first enabling control circuit 206 is configured to send a signal to switch the first comparator 201 to a failed output state when the H-bridge circuit switches from a high-impedance state to other states; and is configured to send a signal to switch the first comparator 201 to a comparison state when it is detected that the H-bridge circuit switches to a high-impedance state.

[0037] In this embodiment, the signal sent by the first enable control circuit 206 to switch the first comparator 201 to the disabled output state is a continuous low level, and the signal sent by the first enable control circuit 206 to switch the first comparator 201 to the comparison state is a continuous high level.

[0038] In this embodiment, the first enable control circuit 206 determines whether to enter the high impedance state by detecting the logic input signal (i.e., the logic input signal of the gate logic control circuit) input to the first gate logic control circuit 203 and the second gate logic control circuit 303. Therefore, when the H-bridge circuit is in the high impedance state, the first H-bridge output terminal OUTA1 transmits its voltage to the non-inverting input terminal of the first comparator 201.

[0039] The first comparator 201 is configured to compare the voltage of the first H-bridge output terminal OUTA1 and the power supply voltage VDD when entering the comparison state. When the voltage of the first H-bridge output terminal OUTA1 is higher than the power supply voltage VDD, the comparison result signal 202 of the first comparator 201 is used to turn on the upper left PMOS tube 101 of the H-bridge circuit (in this embodiment, it is a high level), otherwise, the comparison result signal 202 is a low level; when entering the failure output state, the comparison result signal 202 output by the first comparator 201 is a low level.

[0040] The first gate voltage logic control circuit 203 is configured to send a signal to turn on the upper left PMOS tube 101 and turn off the lower left NMOS tube 103 when the comparison result signal 202 of the first comparator 201 is at a high level; when the comparison result signal 202 of the first comparator 201 is at a low level, restore the normal working mode, for example, send a signal to turn off the upper left PMOS tube 101 and the lower left NMOS tube 103 in a high impedance state. The left half-bridge driving circuit 204 generates a corresponding driving signal according to the signal sent by the first gate voltage logic control circuit 203.

[0041] When the comparison result signal 202 is at a high level, the turn-on time of the upper left PMOS tube 101 is the minimum time for the left half-bridge driving circuit 204 to drive the upper left PMOS tube 101 to turn on, preferably about 150ns. In other embodiments, the turn-on time can be adjusted as needed.

[0042] Therefore, when the H-bridge is in high impedance state, the two ends of the comparator compare the voltage at the output of the H-bridge with the power supply voltage VDD. When the voltage at the output of the H-bridge is greater than the power supply voltage VDD, the comparator outputs a signal to turn on the upper tube. That is, when the H-bridge is in high impedance state, when the voltage at either of the H-bridge output terminals OUTA1 and OUTB1 is higher than the power supply voltage, the PMOS tube on the corresponding side is turned on to prevent excessive current from passing through the parasitic PNP transistor, causing chip damage or degradation.

[0043] When the voltage at the first H-bridge output terminal OUTA1 is higher than the VDD voltage and the count value of the first counting circuit 205 has not reached the preset count, the comparison result signal 202 of the first comparator 201 is output as a high level, and the first gate voltage logic control circuit 203 outputs a signal of turning on the upper tube and turning off the lower tube to the left half-bridge driving circuit 204. If the voltage at the first H-bridge output terminal OUTA1 is lower than the VDD voltage, or the count value of the first counting circuit 205 has reached the preset count, the comparison result signal 202 of the first comparator 201 is all low level, and the first gate voltage logic control circuit 203 returns to the normal working mode, for example, outputting a signal to keep the upper tube and the lower tube turned off in a high impedance state.

[0044] The power tube on the left side of the H-bridge is controlled to be turned on or off by the left half-bridge driving circuit 204 and the logic control circuit 203 when it does not enter the high-impedance state. When it enters the high-impedance state and the comparison result signal of the first comparator is at a low level, the upper tube and the lower tube are kept closed to be consistent with the normal working mode. When it enters the high-impedance state and the comparison result signal of the first comparator is at a high level, it is transmitted to the gate voltage logic control circuit. The gate voltage logic control circuit changes the logic that originally controls the upper tube (such as the upper left PMOS tube 101) to be at a high level to a low level, so that the upper tube is turned on briefly, so that it quickly discharges the current in the motor and realizes freewheeling, so as to solve the problem of leakage of the upper tube when the H-bridge is in the high-impedance state, and avoid the conduction of the parasitic PNP device inside the upper tube. Specifically, when the PMOS is turned on, the current passes through the channel of the PMOS tube, and the emitter of the parasitic PNP triode from the drain end D (P+) of the PMOS tube to the N well NWH does not reach its turn-on voltage, which will not cause the conduction of the parasitic PNP device inside the upper tube.

[0045] After the freewheeling is completed, the voltage at the output end of the H-bridge will be lower than the H-bridge power supply voltage. At this time, the gate voltage logic control circuit returns to the original logic, pulling the gate voltage of the upper tube from 0V to 5V (that is, turning it into an off state), presenting a state in which all power tubes are turned off in the original high-impedance state.

[0046] In order to prevent the comparison result signal output by the comparator from turning high again after all power tubes are turned off due to parasitic coupling of capacitors, generating self-oscillation, repeatedly reopening the PMOS power tube, forming a cycle, and affecting the operation of the circuit, the circuit of the present invention is designed with a counting circuit. When entering the high-impedance state, the comparator only compares the voltage at the output end of the H-bridge with the power supply voltage VDD for a preset number of times (8 times in this embodiment). After the counting circuit reads the preset number of times, it will output a low level to the enable control circuit of the comparator to pull the comparator output low. In this way, the comparator will continue to output a constant low level when receiving the low level of the enable control circuit, and will no longer compare the voltage at the output end of the H-bridge with the power supply voltage VDD. After the H-bridge switches to a state other than the high-impedance state, the comparator enters a failed output state and does not detect the voltage at the output of the H-bridge and the power supply voltage VDD; when the H-bridge enters the high-impedance state again, the comparator enable control circuit will jump to a high level, causing the comparator to enter a comparison state, and the comparator can compare the voltage at the output of the H-bridge with the power supply voltage VDD normally, and continue to compare the preset count number of times.

[0047] like Figure 4 As shown, VDD represents the power supply voltage, VP represents the voltage at the positive input terminal of the comparator, Vcp represents the output signal of the comparator, and EN_comp represents the signal at the enable terminal of the comparator. Figure 4 It shows that when a high level is detected, after 8 rising edges, the comparator enable signal EN_comp becomes a low level, and at this time, the output signal Vcp of the comparator continues to be low.

[0048] Combine the following Figure 5 The logic timing waveforms shown in the figure illustrate the changes in the input, output and gate voltage of the power tube during the whole process, so as to show how the present invention solves the problem of leakage of the upper tube when the H bridge is in high impedance state. When the H bridge is controlled to switch from forward rotation to high impedance state, the output voltage waveforms of the first H bridge output terminal OUTA1 and the second H bridge output terminal OUTB1 are as follows: Figure 5 As shown. When rotating forward, the first H-bridge output terminal OUTA1 outputs a high level, and the second H-bridge output terminal OUTB1 outputs a low level, corresponding to the gate voltage driving circuit controlling the H-bridge power tube, the gate voltage of the upper left PMOS tube 101 is low, the gate voltage of the upper right PMOS tube 102 is high, the gate voltage of the lower left NMOS tube 103 is low, and the gate voltage of the upper right PMOS tube 102 is high. When switching to a high-impedance state, because the current of the motor cannot change suddenly, the current will continue to flow in the original direction, from the third parasitic body diode 107 of the lower left NMOS tube 103 through the motor 109 and then through the second parasitic body diode 106 of the PMOS power tube 102 to the power supply.

[0049] At this time, if the circuit of the present invention is not used, the on-resistance of the second parasitic body diode 106 is relatively large, generally higher than the on-resistance of the switch tube, so when the current flows in the direction of the power supply voltage VDD, a voltage higher than the power supply voltage VDD will be generated. Therefore, the body diode freewheeling will cause the second H-bridge output terminal OUTB1 to generate a voltage higher than the power supply voltage VDD (such as Figure 5 505 in FIG), at this time, the gate voltage of the upper left PMOS power tube 102 on the side of the second H-bridge output terminal OUTB1 is high level (as shown in FIG. Figure 5 508), is in the off state, so a large leakage current will occur.

[0050] If the circuit structure of the present invention is adopted, when the voltage of the second H-bridge output terminal OUTB1 is detected to be higher than the power supply voltage VDD during freewheeling, the upper right PMOS power tube 102 will be turned on for a short time, and the gate voltage Gp2 of the upper right PMOS power tube 102 will be pulled to Figure 5 The low level shown in 507 can quickly attenuate the current in the motor, so that the voltage of the second H-bridge output terminal OUTB1 is as follows Figure 5 The gate voltage Gn2 of the lower right NMOS power tube 104 is shown as Figure 5 shown.

[0051] In this embodiment, the first comparator 201 is a single-sided hysteresis comparator with dual threshold values ​​to implement a comparator hysteresis function.

[0052] The unilateral hysteresis comparator is a comparator with hysteresis loop transmission characteristics, which can also be understood as a single-limit comparator with positive feedback. By introducing positive feedback design inside the single-limit comparator, a unilateral hysteresis comparator with dual threshold values ​​is formed. In addition, positive feedback can also speed up the comparator and make it respond quickly.

[0053] The unilateral hysteresis comparator with dual threshold values ​​has two threshold voltages, namely the upper threshold and the lower threshold. In this circuit, the upper threshold is VDD+30mV and the lower threshold is VDD. When the input signal changes from large to small, the output will jump to a specific state (such as a low level) when the input signal is smaller than the lower threshold. When the input signal changes from small to large, the output will jump to another state (such as a high level) when the input signal is larger than the upper threshold. Between the two threshold voltages, the output remains unchanged.

[0054] This hysteresis comparison setting of the comparator avoids the situation of being locked in the state of turning on the upper tube. Specifically, the detection trigger voltage (upper threshold) VDD+30mV can detect the event of overcurrent through the body diode of high resistance in time, and the recovery voltage (lower threshold) is VDD, which is to detect the end of freewheeling and return to high resistance. The recovery voltage (lower threshold) is not designed to be VDD-30mV. This bilateral hysteresis is because it may be locked in the state of turning on the upper tube. Because the leakage turns on the upper tube, the lowest voltage of the upper tube is approximately equal to VDD.

[0055] For the power tube on the right side of the H-bridge and the right half-bridge driving component, since their structure and working mode are completely symmetrical with the power tube on the left side of the H-bridge and the left half-bridge driving component, the working process is the same.

[0056] The right half-bridge driving component includes a second comparator 301, a second gate voltage logic control circuit 303 and a right half-bridge driving circuit 304 which are sequentially connected to the second H-bridge output terminal OUTB1 of the H-bridge circuit 100, and the two output terminals of the right half-bridge driving circuit 304 are respectively connected to the upper right PMOS tube 102 and the lower right NMOS tube 104.

[0057] The output terminal of the second comparator 301 is connected to the second gate voltage logic control circuit 303 and the second counting circuit 305 . The second counting circuit 305 is connected to the second enable control circuit 306 . The second enable control circuit 306 is connected to the enable terminal of the second comparator 301 .

[0058] The upper left PMOS tube 101 and the upper right PMOS tube 102 are completely the same upper PMOS tubes; the lower left NMOS tube and the lower right NMOS tube are completely the same lower NMOS tubes.

[0059] The first comparator 201 and the second comparator 301 are exactly the same comparators, the first gate voltage logic control circuit 203 and the second gate voltage logic control circuit 303 are exactly the same gate voltage logic control circuits, and the left half-bridge driving circuit 204 and the right half-bridge driving circuit 304 are exactly the same half-bridge driving circuits. The first counting circuit 205 and the second counting circuit 305 are exactly the same counting circuits. The first enabling control circuit 206 and the second enabling control circuit 306 are exactly the same enabling control circuits.

[0060] In summary, the high-impedance upper tube leakage processing circuit of the H-bridge of the present invention compares the output terminal voltage and the power supply voltage of the H-bridge in the high-impedance state, and controls the opening and closing of the upper tube according to the output terminal voltage and the power supply voltage of the H-bridge, thereby solving the problem that when the H-bridge enters the high-impedance state, the upper tube has a voltage higher than VDD due to the conduction of the parasitic PNP device inside the PMOS tube to generate leakage current, thereby causing leakage, abnormal function, burning of the switch tube, power supply voltage fluctuation and other problems; and, the counting circuit is designed not to turn on the PMOS tube after a preset count, so as to weaken the power supply voltage fluctuation, and avoid the capacitor coupling that may cause the comparator to turn high again, reopen the PMOS tube, and cause a periodic cycle.

[0061] It should be noted that the present invention has been described in detail according to its specific embodiments. However, various modifications and changes can still be made around this idea without departing from the spirit and scope of the present invention. For example, it is possible to choose to control the upper tube or the lower tube separately or simultaneously, that is, each of the left half-bridge driving circuit and the right half-bridge driving circuit can be replaced by two driving circuits, each driving circuit only drives one of the upper PMOS tube and the lower PMOS tube, and only the driving circuit connected to the upper PMOS tube needs to be connected to the corresponding comparator to avoid leakage; or, it is applied to different H-bridge structures to change its conventional working mode, and it only needs to ensure that the comparator works in the high-impedance state to drive the upper tube to turn on; or, the gate voltage logic control circuit can be omitted, and the comparison result signal output by the comparator is directly used to control the drive, etc. These changes all belong to the disclosure and protection scope of the present invention. Therefore, the specification and drawings should be regarded as illustrative rather than restrictive, and all technical solutions and changes that do not deviate from the spirit and scope of the present invention should be covered in the protection scope of the patent of the present invention.

Claims

1. A high-impedance upper tube leakage processing circuit of an H-bridge, characterized in that: It comprises two half-bridge driving components, each of which comprises a comparator connected to one of the H-bridge output terminals of the H-bridge circuit, and an enable control circuit connected to the enable terminal of the comparator; The enabling control circuit is configured to send a signal to switch the comparator to a comparison state when detecting that the H-bridge circuit is switched to a high impedance state; The comparator is configured to, when entering a comparison state, when the voltage at the output end of the H-bridge is higher than the power supply voltage, the comparison result signal of the comparator is used to turn on the upper PMOS tube connected to the output end of the H-bridge; otherwise, the comparison result signal causes the upper PMOS tube to maintain a normal working mode.

2. The high-impedance upper tube leakage processing circuit of the H-bridge according to claim 1, characterized in that: The enable control circuit is configured to send a signal to switch the comparator to a failure output state when the H-bridge circuit switches from a high impedance state to other states; when entering the failure output state, the comparison result signal output by the comparator enables the upper PMOS tube to maintain a normal working mode.

3. The high-impedance upper tube leakage processing circuit of the H-bridge according to claim 1, characterized in that: The enable control circuit is connected to a timing circuit, and the counting circuit is configured to count the number of times the comparator outputs a high level. When the count value reaches a preset count, the enable control circuit is driven to send a signal to switch the comparator to a disabled output state.

4. The high-impedance upper tube leakage processing circuit of the H-bridge according to claim 3, characterized in that: The preset count is 4-16.

5. The high-impedance upper tube leakage processing circuit of the H-bridge according to claim 1, characterized in that: When the comparison result signal is at a high level, it is used to turn on the upper PMOS tube connected to the output end of the H-bridge, and when the comparison result signal is at a low level, it is used to maintain the upper PMOS tube in a normal working mode.

6. The high-impedance upper tube leakage processing circuit of the H-bridge according to claim 1, characterized in that: The comparator is connected to the gate of the upper PMOS tube through a gate voltage logic control circuit. The gate voltage logic control circuit is configured to send a signal to turn on the upper PMOS tube when the comparison result signal of the comparator is used to turn on the upper PMOS tube connected to the output end of the H-bridge, and restore the normal working mode when the comparison result signal of the comparator causes the upper PMOS tube to maintain the normal working mode.

7. The high-impedance upper tube leakage processing circuit of the H-bridge according to claim 1, characterized in that: The comparator is connected to the gate of the upper PMOS tube through a driving circuit, and the driving circuit is used to generate a driving signal.

8. The high-impedance upper tube leakage processing circuit of the H-bridge according to claim 7, characterized in that: The driving circuit is a half-bridge driving circuit, and the two output ends of the half-bridge driving circuit are respectively connected to the gates of the upper PMOS tube and the lower NMOS tube connected to the H-bridge output end; or Each half-bridge driving component also includes a second driving circuit, and the second driving circuit is connected to the gate of the lower NMOS tube connected to the output end of the H-bridge.

9. The high-impedance upper tube leakage processing circuit of the H-bridge according to claim 7, characterized in that: When the comparison result signal is used to turn on the upper PMOS tube connected to the output end of the H-bridge, the turn-on time of the upper PMOS tube is the minimum time for the drive circuit itself to drive the upper PMOS tube to turn on.

10. The high-impedance upper tube leakage processing circuit of the H-bridge according to claim 1, characterized in that: The comparator is a single-sided hysteresis comparator with an upper threshold and a lower threshold.

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