Parallel current-sharing digital closed-loop active driving system

Abstract

The invention relates to the technical field of driving circuits, in particular to a parallel current-sharing digital closed-loop active driving system, which comprises a switching tube circuit, a parallel current-sharing circuit and a parallel current-sharing circuit, the current sampling conditioning circuit obtains a switching voltage; the quiescent current identification circuit performs quiescent current identification; the dynamic current identification circuit carries out dynamic current identification; the static current-sharing closed-loop control circuit generates pulse width modulation waveforms with different duty ratios according to the static current; the dynamic current-sharing closed-loop control circuit generates pulse width modulation signals with different phases according to the dynamic current; the driving power supply adjusting circuit generates different driving voltages for the driving circuit according to the pulse width modulation waveforms with different duty ratios; the driving circuit outputs different driving voltages according to the pulse width modulation signals of different phases, and the driving voltages are used for controlling the switching current of the switching tube circuit to carry out closed-loop adjustment and dynamic and static current equalization. The problem that an existing driving circuit cannot meet parallel current sharing, steady-state current and rapid closed-loop adjustment at the same time is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of drive circuits, and in particular to a parallel current-sharing digital closed-loop active drive system. Background Art

[0002] SiC-based power electronic devices have higher rated voltage, lower on-resistance, and higher switching frequency. They are widely used in distributed energy, electric vehicles and other occasions. In order to adapt to higher power levels, many occasions require multiple SiC MOSFET switch tubes to work in parallel to improve current handling capabilities.

[0003] However, the mismatch of circuit parasitic parameters, the mismatch of parameters of the parallel devices themselves, and the mismatch of parameters of the drive circuit will affect the dynamic current of the parallel switch tube during the switching process and the steady-state current distribution when it is turned on; however, due to the increase in the switching frequency and switching speed of SiC MOSFET, the high drain-source voltage change rate and drain current change rate during the switching process act on the parasitic parameters generated by the device inside and the circuit layout, which will make the current imbalance of the parallel switch tube more serious; the current imbalance leads to the loss distribution and even heat distribution of the switch tube, reducing the reliability of the switch tube.

[0004] Among the existing active driving methods, some use analog control methods to achieve high-speed closed-loop control, but the design of the hardware circuit is relatively complex and not flexible enough, and the stability of the parameters is easily affected by the external environment such as temperature; others use digital control technologies such as CPLD and FPGA, but only focus on dynamic current balancing problems and do not pay attention to steady-state current problems. Summary of the invention

[0005] In view of the shortcomings of the existing circuits, the present invention aims to overcome the problem that the existing SiC MOSFET driving circuit cannot simultaneously meet the requirements of parallel current sharing, steady-state current, fast closed-loop regulation and adaptability to various parameter changes.

[0006] The technical solution adopted by the present invention is: a parallel current-sharing digital closed-loop active drive system comprising:

[0007] Switching tube circuit, current sampling and conditioning circuit, dynamic current identification circuit, static current identification circuit, static current sharing closed-loop control circuit, dynamic current sharing closed-loop control circuit, driving power supply regulation circuit and driving circuit; wherein,

[0008] The switch tube circuit is used to generate a switch current;

[0009] The current sampling and conditioning circuit performs voltage conditioning on the switch current to obtain the switch voltage;

[0010] The static current identification circuit performs static current identification on the discretized switch voltage;

[0011] The dynamic current identification circuit performs dynamic current identification on the discretized switch voltage;

[0012] The static current sharing closed-loop control circuit generates pulse width modulation waveforms with different duty ratios according to the static current;

[0013] The dynamic current sharing closed-loop control circuit generates pulse width modulation signals of different phases according to the dynamic current;

[0014] The driving power supply regulating circuit generates different driving voltages for the driving circuit according to the pulse width modulation waveforms with different duty ratios;

[0015] The driving circuit outputs different driving voltages according to the pulse width modulation signals of different phases, and uses the driving voltage to control the switching current of the switching tube circuit to perform closed-loop regulation and dynamic and static current balancing.

[0016] As a preferred embodiment of the present invention, the current sampling and conditioning circuit includes: a voltage isolation follower A 11 and A 21 、Operational amplifier A 12 and A 22 , resistor R 11 To R 13 , resistor R 21 To R 23 , A 11 The inverting input terminal is connected to the output terminal, A 11 The output terminal and R 12 The right end of the connection, R 12 The left end of A 12 The same-direction input terminal of A 12 The inverting input terminal is connected to R 13 , R 11 One end of the connection, R 13 The other end of A 12 The output terminal connection of 21 The inverting input terminal is connected to the output terminal, A 21 The output terminal and R 22 The right end of the connection, R 22 The left end of A 22 The same-direction input terminal of A 22 The inverting input terminal is connected to R 23 , R 21 One end of the connection, R 23 The other end of A 22 The output terminal is connected.

[0017] As a preferred embodiment of the present invention, the driving power supply regulating circuit includes: a switch tube QB1 , Q B2 , diodes D1, D2, inductors L1, L2, capacitors C1, C2, Q B1 The gate and source of D1 are connected in parallel, the negative electrode of D1 is connected to the left end of L1, the right end of L1 is connected to the upper end of C1, and the lower end of C1 is connected to the positive electrode of D1; Q B2 The gate and source of D2 are connected in parallel, the cathode of D2 is connected to the left end of L2, the right end of L2 is connected to the upper end of C2, and the lower end of C2 is connected to the positive electrode of D2.

[0018] As a preferred embodiment of the present invention, the driving circuit includes: a switch tube Q H1 , Q L1 , Q H2 , Q L2 , Q H1 The source and Q L1 The source connection, Q H1 The gate and Q L1 The gate connection of Q H2 The source and Q L2 The source connection, Q H2 The gate and Q L2 The gate connection.

[0019] As a preferred embodiment of the present invention, the switching tube circuit includes: switching tubes Q1, Q2, current sensors S1, S2, the source of Q1 is connected in series with S1, the source of Q2 is connected in series with S2, the drain of Q1 is connected to the drain of Q2, and the lower end of S1 is connected to the lower end of S2.

[0020] As a preferred embodiment of the present invention, the dynamic current identification circuit makes a judgment based on the discrete value of the current. When the discrete value of the current does not reach the steady-state current value threshold range, it is a dynamic current.

[0021] As a preferred embodiment of the present invention, the static current identification circuit makes a judgment based on the discrete value of the current. When the discrete value of the current is within the steady-state current value threshold range, it is a static current.

[0022] As a preferred embodiment of the present invention, the static current sharing closed-loop control circuit includes: k1,s and i k2,s The error signal e is obtained by subtracting s , through C s (s) adjustment, output duty cycle fine-tuning signal Δd, according to the initial duty cycle D, use HRPWM module to output pulse width modulation waveforms with duty cycles of D-Δd and D+Δd respectively.

[0023] As a preferred embodiment of the present invention, the dynamic current sharing closed-loop control circuit includes: k1,d and ik2,d The error signal e is obtained by subtracting d , through C d (s) adjustment, output phase difference signal The HRPWM module is used to output the initial pulse width modulation signal and the phase difference is The initial pulse width modulation signal.

[0024] Beneficial effects of the present invention:

[0025] 1. By detecting the source current of the parallel SiC MOSFET, a sampling and conditioning circuit, a DSP dynamic and static current identification and closed-loop control circuit are set up to output a control signal, change the high-level amplitude of the driving voltage and the phase difference of the switch tube driving signal, so as to achieve the balance of the parallel dynamic and static currents; this driving circuit can not only realize fast closed-loop regulation, improve the balance of dynamic and static currents when the SiC MOSFET switch tubes are connected in parallel, and improve the uneven heat distribution problem caused by current imbalance, but also improve the reliability of the switch tube, so that the SiC MOSFET can give full play to the characteristics of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a logic block diagram of the parallel current-sharing digital closed-loop active drive system of the present invention;

[0027] Figure 2 It is a circuit diagram of a parallel current-sharing digital closed-loop active drive system of the present invention;

[0028] Figure 3 It is a SiC MOSFET dual-tube parallel circuit model;

[0029] Figure 4 It is the dynamic current waveform of the two-tube parallel connection at the moment the two-tube parallel connection circuit is turned on. DETAILED DESCRIPTION

[0030] The present invention is further described below in conjunction with the accompanying drawings and embodiments. This figure is a simplified schematic diagram, which only illustrates the basic structure of the present invention in a schematic manner, and therefore it only shows the components related to the present invention.

[0031] like Figure 1 , 2 As shown in the figure, when two tubes are connected in parallel, the circuit of the switch tube and the typical waveform of the instantaneous current of the opening are shown in the figure. The modal analysis of each stage is as follows:

[0032] [t0, t1] stage:

[0033] At t0, the driving voltage v DR1 Turn on, gate-source voltage v GS1 It starts to rise under the action of the driving voltage, but has not yet reached the threshold voltage VTH , there is no current in the switch tube.

[0034] [t1, t2] stage:

[0035] As the gate-source voltage v GS1 The threshold voltage V TH1 The smaller switch tube Q1 reaches the turn-on condition first, and Q1 starts to conduct current first, while the switch tube Q2 remains off.

[0036] [t2, t3] stage:

[0037] Gate-source voltage v GS1 、v GS2 Continue to rise, the voltage across the gate and source of the switch tube Q2 also reaches the threshold voltage V TH2 And starts to conduct, the current of the main power circuit gradually switches to the switch tubes Q1 and Q2, and the drain-source voltage v DS The DC voltage V clamped by the diode in the main power circuit DC , the two tube currents i1 and i2 can be written as:

[0038] i1=g fs (v GS1 -V TH1 ) 2 (1)

[0039] i2=g fs (v GS2 -V TH2 ) 2 (2)

[0040] After the commutation is complete, this phase ends.

[0041] [t3, t4] stage:

[0042] The drain-source capacitance of the switch tube discharges, causing the current of the switch tube to peak. The drain-source voltages of the two tubes are the same, and the current between the drain and source can still be written as equations (2) and (3). The difference in the dynamic current of the two tubes Δi d for:

[0043] Δi d =g fs (v GS1 +v GS2 -V TH1 -V TH2 )(v GS1 -v GS2 -V TH1 +V TH2 ) (3)

[0044] Among them, g fs For transconductance.

[0045] Therefore, the imbalance of dynamic current is related to the gate-source voltage v GS and v GS Start rising time and start voltage V TH Related, and v GS The maximum value and the driving circuit waveform v DR Positive pressure V DRV The size of v GS The time difference of starting to rise and the phase difference of the two tube driving signals By adjusting the positive voltage V DRV The phase difference between the two tube drive signals The balance of parallel dynamic current can be improved.

[0046] [t4, t5] stage:

[0047] When the switch tube current reaches a steady state, the size of the static current is determined by the switch tube on-resistance. DS(on) for:

[0048]

[0049] Among them, L, W, μ n , C ox They are the inherent parameters of the SiC MOSFET tube channel length, width, electron mobility, gate oxide layer capacitance, etc., which are related to the manufacturing process of the switch tube and cannot be changed. Therefore, the static current can only be measured by v GS and V TH Regulation, while the turn-on voltage V TH It is not constant and will change due to the influence of temperature and negative pressure of the driving circuit. GS The maximum value of the driving circuit waveform v DR It is determined by the positive voltage amplitude of the driving circuit, so the effect of adjusting the parallel static current can be achieved by adjusting the positive voltage amplitude of the driving circuit.

[0050] The methods for parallel current sharing control of the above-mentioned SiC MOSFET in the prior art mainly include device pre-screening and parameter matching method, circuit or device package layout optimization method, passive current sharing method such as coupled inductor and active drive control method, etc.; the device pre-screening and parameter matching method cannot solve the problem of parallel uneven current caused by parameters such as circuit layout other than the device itself, and the circuit or device package layout optimization is not suitable for the situation where the circuit and device already exist and cannot be changed. Passive current sharing methods such as coupled inductor have limited regulating effect on steady-state current; among the existing active drive methods, one part adopts analog control method to achieve high-speed closed-loop control, and the design of hardware circuit is relatively complex and not flexible enough, and the stability of parameters is easily affected by the external temperature and other environment; the other part adopts digital control such as CPLD and FPGA, but only focuses on dynamic current balancing problem, not steady-state current.

[0051] The active driving method of the present invention solves the current imbalance problem caused by factors such as circuit parasitic parameter mismatch, parallel device parameter mismatch, and drive circuit parameter mismatch through active regulation, and improves the balance degree of dynamic current and steady-state current at the same time; the present invention adopts DSP digital control, realizes high-speed analog quantity acquisition and digital closed-loop control at the same time, and the hardware circuit is more compact.

[0052] like Figure 1 , 2 As shown, a parallel current-sharing digital closed-loop active drive system includes:

[0053] The parallel current sampling and conditioning circuit, DSP operation processing circuit, driving power supply regulating circuit and driving circuit have the following structural features: a current sampling circuit is set at the source of the parallel switch tube, the sampling result is sent to the conditioning circuit, and the sampling and conditioning result is sent to the high-precision ADC sampling module inside the DSP controller. The DSP identifies the dynamic and static currents and performs static current sharing closed-loop control calculation and dynamic current sharing closed-loop control calculation respectively; through the steady-state current closed-loop control calculation, a PWM wave with a variable duty cycle is output to control the switch tube of the driving power supply regulating Buck circuit. The output voltage of the Buck circuit is proportional to the duty cycle, thereby changing the high-level amplitude of the driving circuit; through the dynamic current closed-loop control calculation, a set of phase difference is output The PWM signal is sent to the driving circuit of the parallel switch tube to drive the gate of the parallel switch tube. The current sharing degree of the parallel switch tube is improved by real-time acquisition of each current and real-time calculation and correction output of DSP.

[0054] When the two tubes Q1 and Q2 are connected in parallel, the current sampling and conditioning circuit collects the current i1 and i2 of each switch tube by the current sensors S1 and S2 connected in series to the source of each parallel switch tube. The conditioning circuit of the current i1 includes a voltage isolation follower A 11、Operational amplifier A 12 And adjust the resistor R 11 , R 12 and R 13 The conditioning circuit of current i2 includes a voltage isolation follower A 21 、Operational amplifier A 22 And adjust the resistor R 21 , R 22 and R 23 The sampling results are conditioned to obtain voltages v1 and v2 to adapt to the voltage input range of 0 to 3.3V of the ADC conversion module in the DSP.

[0055] The DSP operation processing circuit includes an ADC sampling module, a dynamic current identification circuit, a static current identification circuit, a static current sharing closed-loop control circuit, and a dynamic current sharing closed-loop control circuit; the output voltages v1 and v2 of the sampling conditioning circuit are processed into discrete digital quantities I by the ADC sampling module. k1 and I k2 , the dynamic and static current identification circuit is used to distinguish between dynamic current and static current. If it is dynamic current, it is recorded as i k1,d and i k2,d If it is a static current, then the machine is i k1,s and i k2,s ; If it is the static current i k1,s and i k2,s , then it is sent to the static current sharing closed-loop control circuit, and i k1,s and i k2,s Subtract and calculate the error signal e s , through the PI controller C s (s) regulation, output duty cycle fine-tuning signal Δd, added to the initial duty cycle D, through the setting of HRPWM module inside DSP, output a set of pulse width modulation waveform PWM with duty cycle D-Δd DRV2 And the pulse width modulation waveform PWM with a duty cycle of D+Δd DRV1 , sent to the driving power supply regulation circuit; if it is a dynamic current i k1,d and i k2,d , then it is sent to the dynamic current sharing closed-loop control circuit to k1,d and i k2,d Subtract and calculate the error signal e d , through the PI controller C d (s) adjustment, output phase difference signal Through the setting of the HRPWM module inside the DSP, a set of initial pulse width modulation signals PWM1 and phase difference are output. The PWM2 signal of PWM1 and PWM2 are sent to the driving circuits of Q1 and Q2 respectively.

[0056] The driving power supply regulating circuit includes the driving power supply regulating circuit of the Q1 tube and the driving power supply regulating circuit of the Q2 tube. In the driving power supply regulating circuit of the Q1 tube, the switch tube Q B1 , diode D1, inductor L1, capacitor C1 form a Buck circuit, pulse width modulation waveform PWM DRV1 Control switch tube Q B1 The input of the Buck circuit is V in Constant, the output is V DRV1 The DC voltage is V according to the input-output characteristics of the Buck circuit. DRV1 The magnitude of the switch Q B1 The duty cycle D of the switch tube Q1 is proportional to the duty cycle D of the switch tube Q2. B2 , diode D2, inductor L2, capacitor C2 form a Buck circuit, pulse width modulation waveform PWM DRV2 Control switch tube Q B2 The input of the Buck circuit is V in Constant, the output is V DRV2 The DC voltage, output voltage V DRV2 With switch Q B1 The duty cycle D+Δd is proportional to the switching transistor Q2, providing an adjustable positive voltage power supply for the driving circuit of the switching tube Q2.

[0057] The driving circuit is composed of the driving circuit of Q1 tube and the driving circuit of Q2 tube; the driving circuit of Q1 tube is composed of the switching tube Q H1 and Q L1 Composed of V DRV1 Provides a positive voltage power supply with variable amplitude, V E Provide negative voltage power supply; the driving circuit of Q2 tube consists of switch tube Q H2 and Q L2 Composed of V DRV2 Provides a positive voltage power supply with variable amplitude, also by V E Provide negative voltage power supply; output v of driving circuit DR1 and v DR2 Used to drive the gates of parallel switching tubes Q1 and Q2 respectively.

[0058] DSP uses TI digital controller TMS320F28379D, the drive circuit uses driver chip IXDN609SI, the current sampling and conditioning circuit uses amplifier LTC6229, and the control parameter k of the control loop ps =0.19, k is =0.21, k pd =0.28, k id =0.15.

[0059] Q1 and Q2 are SiC MOSFET switch tubes connected in parallel. Current sensors S1 and S2 collect the current i1 and i2 of each switch tube. 11 For voltage isolation follower, A 12 For the operational amplifier, R 11 , R 12 and R 13 To adjust the resistance, A 21 For voltage isolation follower, A 22 For the operational amplifier, R 21 , R 22 and R 23 It is composed of adjustable resistors, v1 and v2 are the voltages obtained after conditioning the sampling results, and the voltage range is 0 to 3.3V.

[0060] I k1 and I k2 The output voltage v1 and v2 of the sampling and conditioning circuit are processed into discrete digital quantities by the ADC sampling module. k1,d and i k2,d is the dynamic current, i k1,s and i k2,s is the static current, e s for i k1,s and i k2,s The error signal, C s (s) is a PI controller, and the output Δd is the duty cycle fine-tuning signal, PWM DRV1 and PWM DRV2 HRPWM module outputs the pulse width modulation waveform, PWM DRV2 The duty cycle of PWM is D-Δd. DRV1 The duty cycle is D+Δd, where D is the initial duty cycle set by the switch tube; d for i k1,d and i k2,d The error signal, C d (s) is a PI controller, output is the phase difference signal, PWM1 and PWM2 are the pulse width modulation waveforms output by the HRPWM module, PWM1 is the pulse width modulation signal with an initial phase of 0, and PWM2 is the delayed phase of PWM1 The pulse width modulation signal waveform is output.

[0061] In the driving power supply regulation circuit, Q B1 is a switch tube, D1 is a diode, L1 is an inductor, and C1 is a capacitor, forming a Buck circuit. in is the input of the first Buck circuit, constant, V DRV1 is the DC voltage output by the Buck circuit, D+Δd is the switch Q B1 Duty cycle; Q B2is a switch tube, D2 is a diode, L2 is an inductor, and C2 is a capacitor, forming the second Buck circuit. DRV2 is the DC voltage output by the Buck circuit, and D-Δd is the switch Q B2 duty cycle.

[0062] In the driving circuit, Q H1 and Q L1 For the complementary conduction switch tube, V DRV1 is the positive voltage supply, V E is a negative voltage power supply; Q H2 and Q L2 It is also a complementary conduction switch tube, V DRV2 is the positive voltage power supply; v DR1 and v DR2 is the driving voltage signal applied to the gates of the switch tubes Q1 and Q2.

[0063] The current sensor S1 is connected in series in the source circuit of Q1, and the sampled current is connected to the voltage isolation follower A. 11 The non-inverting input terminal, A 11 The inverting input terminal is connected to the output, A 11 The output is connected through the resistor R 12 Connect to operational amplifier A 12 The non-inverting input terminal, A 12 The inverting input is connected to the 11 Ground, while A 12 The inverting input is connected through the resistor R 13 Connect A 12 Similarly, the current sensor S2 is connected in series in the source circuit of Q2, and the sampled current is connected to the voltage isolation follower A 21 The non-inverting input terminal, A 21 The inverting input terminal is connected to the output, A 21 The output is connected through the resistor R 22 Connect to operational amplifier A 22 The non-inverting input terminal, A 22 The inverting input is connected to the 21 Ground, while A 22 The inverting input is connected through the resistor R 23 Connect A 22 The output sampling results v1 and v2 are connected to the AD sampling port of DSP.

[0064] DSP converts v1 and v2 into discrete digital quantities I through AD conversion k1 and I k2 By storing and comparing the current change trend, I k1 and I k2 is the dynamic and static current; if it is a dynamic current, it is recorded as ik1,d and i k2,d If it is a static current, it is recorded as i k1,s and i k2,s ;change i k1,s and i s2,s The error signal e is obtained by subtracting s , sent to PI controller C s (s), output signal Δd; output pulse width modulation waveform PWM with a duty cycle of initial duty cycle D+Δd through DSP HRPWM module DRV1 , and the pulse width modulation waveform PWM with a duty cycle of D-Δd DRV2 ;change i k1,d and i k2,d The error signal e is obtained by subtracting d , sent to PI controller C d (s), output phase difference signal The HRPWM module of the DSP outputs the pulse width modulation signal PWM1 with an initial phase of 0, and delays the phase of PWM1 The pulse width modulation signal PWM2 is then output.

[0065] In the drive power regulation circuit, the PWM DRV1 Connect switch tube Q B1 The gate, Q B1 The drain terminal is connected to the input voltage V in The source is connected to the cathode of diode D1 and inductor L1, the other end of the inductor is connected to capacitor C1, the other end of C1 is connected to the anode of the diode and grounded, and the voltage at the connection point between inductor L1 and capacitor C1 is used as the output voltage V DRV1 ; Similarly, PWM DRV2 Connect switch tube Q B2 The gate, Q B2 The drain terminal is connected to the input voltage V in The source is connected to the cathode of diode D2 and inductor L2, the other end of the inductor is connected to capacitor C2, the other end of C2 is connected to the anode of the diode and grounded, and the voltage at the connection point between inductor L2 and capacitor C2 is used as the output voltage V DRV2 .

[0066] In the drive circuit, PWM1 is connected to Q H1 and Q L1 The gate, Q H1 and Q L1 The gate of Q H1 The drain is connected to the positive voltage supply V DRV1 , Q L1 The drain is connected to the negative voltage power supply V E , Q H1 The source and Q L1 The source of is connected, and the voltage at the connection point is used as the output vDR1 The gate of the switch tube Q1 is connected as the driving voltage; similarly, PWM2 is fed into Q H2 and Q L2 The gate, Q H2 and Q L2 The gate of Q H2 The drain is connected to the positive voltage supply V DRV2 , Q L2 The drain is connected to the negative voltage power supply V E , Q H2 The source and Q L2 The source of is connected, and the voltage at the connection point is used as the output v DR2 Connected to the gate of the switch tube Q2 as the driving voltage.

[0067] The DSP model is TMS320F28377, the switch tubes Q1 and Q2 are C3M0021120D, and the operational amplifier A 11 , A 12 , A 21 , A 22 The model is LTC6229, the adjustment resistor R 11 , R 12 and R 13 and R 21 , R 22 and R 23 The resistance of the switch tube Q is a high-precision resistor with a resistance of 1kΩ; B1 , Q B2 The model is SI4405, the model of diodes D1 and D2 is 1N5823, the inductance value of inductors L1 and L2 is 33μH, the capacitance value of capacitors C1 and C2 is 220μF, and the chip model used in the drive circuit is IXDN609SI.

[0068] Working principle:

[0069] Figure 3 In the driving circuit, when the two tubes Q1 and Q2 are connected in parallel, the current sampling and conditioning circuit collects the current i1 and i2 of each switch tube by the current sensors S1 and S2 connected in series to the source of each parallel switch tube. The conditioning circuit of the current i1 includes a voltage isolation follower A 11 、Operational amplifier A 12 , adjust the resistor R 11 , R 12 and R 13 The conditioning circuit of current i2 includes a voltage isolation follower A 21 、Operational amplifier A 22 And adjust the resistor R 21 , R 22 and R 23The sampling results are conditioned to obtain voltages v1 and v2 to adapt to the voltage input range of 0 to 3.3V of the ADC sampling module in the DSP operation processing circuit.

[0070] Among them, the voltage v1 is:

[0071]

[0072] To achieve impedance matching, R 12 Set to:

[0073]

[0074] Similarly, the voltage v2 is:

[0075]

[0076] To achieve impedance matching, R 22 Set to:

[0077]

[0078] The DSP operation processing circuit includes ADC sampling, dynamic current identification circuit, static current identification circuit, static current sharing closed-loop control circuit, and dynamic current sharing closed-loop control circuit;

[0079] The working process of the dynamic current identification circuit and the static current identification circuit is:

[0080] The current discrete value collected is used to distinguish whether it is dynamic current or static current. The current discrete value I k1 and I k2 The current collected before and after reaching the maximum value, that is, during the period before reaching the steady-state current value, is the dynamic current; and the current collected after the current rises to the maximum value and returns to the vicinity of the steady-state current value is the static current.

[0081] like Figure 4 As shown, at time t0, v DR When the driving signal voltage rises, the currents between t0 and t4 are dynamic currents. At t5, the currents i1 and i2 enter a steady-state current value of about 10A (between the steady-state current value threshold range 11A-9A), and the currents between t4 and t5 are static currents.

[0082] The static current sharing closed-loop control circuit and the dynamic current sharing closed-loop control circuit both use the DSP calculation module and the HRPWM module to configure the timer and register according to the calculation results and then output the PWM waveform.

[0083] The output voltages v1 and v2 of the current sampling and conditioning circuit are processed into discrete digital quantities I by the ADC sampling module. k1 and Ik2 , the dynamic current / static current identification circuit is used to distinguish whether it is dynamic current / static current; if it is dynamic current, it is recorded as i k1,d and i k2,d If it is a static current, it is recorded as i k1,s and i k2,s ; If it is the static current i k1,s and i k2,s , then it is sent to the static current sharing closed-loop control circuit, and i k1,s and i k2,s Subtract and calculate the error signal e s for:

[0084] e S =i k1,s -i k2,s (9)

[0085] Through the PI controller C s (s) regulation, output duty cycle fine-tuning signal Δd, and output a set of pulse width modulation waveform PWM with duty cycle D+Δd through DSP HRPWM module DRV1 , Pulse width modulation waveform PWM with duty cycle D-Δd DRV2 , sent to the drive power regulation circuit; where ru,

[0086]

[0087] Δd is:

[0088]

[0089] Δd is sent to the HRPWM high-precision pulse width modulation waveform output module of the DSP, and the duty cycle is configured through the timer of the HRPWM module and the register of the PWM module.

[0090] If the dynamic current i k1，d and i k2d , then it is sent to the dynamic current sharing closed-loop control circuit to k1d and i k2d Subtract and calculate the error signal e d :

[0091] e d =i k1,d -i k2,d (12)

[0092] Through the PI controller C d (s) adjustment, output phase difference The initial pulse width modulation signal PWM1 is delayed by a phase difference As the signal waveform of PWM2, the signals of PWM1 and PWM2 are sent to the driving circuits of Q1 and Q2 respectively.

[0093]

[0094] for:

[0095]

[0096] The HRPWM high-precision pulse width modulation waveform output module is sent to the DSP, and the phase can be configured through the timer of the HRPWM module and the register of the PWM module.

[0097] The driving power supply regulating circuit includes a driving power supply regulating circuit of the Q1 tube and a driving power supply regulating circuit of the Q2 tube; the driving power supply regulating circuit of the Q1 tube includes: a switch tube Q B1 , diode D1, inductor L1, capacitor C1 form the first Buck circuit, switch tube Q B1 The duty cycle is D+Δd, and the input of the first Buck circuit is V in Constant, the output is V DRV1 The DC voltage, output voltage V DRV1 With switch Q B1 The duty cycle D+Δd is proportional to the output voltage V DRV1 To provide an adjustable positive voltage power supply for the driving circuit of the switch tube Q1, we have:

[0098] V DRV1 =(D+Δd)·V in (15)

[0099] Similarly, the driving power supply regulation circuit of Q2 tube includes: switch tube Q B2 , diode D2, inductor L2, capacitor C2 form the second Buck circuit, switch tube Q B2 The duty cycle is D-Δd, and the input of the second Buck circuit is V in Constant, the output is V DRV2 The DC voltage, output voltage V DRV2 With switch Q B2 The duty cycle D-Δd is proportional to the output voltage V DRV2 To provide an adjustable positive voltage supply for the driving circuit of the switch tube Q2, we have:

[0100] V DRV2 =(D-Δd)·V in (16)

[0101] The driving circuit is composed of the driving circuit of Q1 tube and the driving circuit of Q2 tube. The driving circuit of Q1 tube is composed of the switching tube Q H1 and Q L2 Composed of VDRV1 Provides positive voltage supply, V E Provide negative voltage power supply; the driving circuit of Q2 tube consists of switch tube Q H2 and Q L2 Composed of V DRV2 Provides positive voltage supply, V E Provide negative voltage power supply; output v of driving circuit DR1 and v DR2 Used to drive the parallel switch tubes Q1 and Q2 respectively, v DR1 and v DR2 The maximum positive pressure is V DRV1 and V DRV2 , v DR1 and v DR2 The phase difference is The maximum value and phase difference of the driving signal are both adjustable, and closed-loop regulation is achieved. Therefore, by digitally closed-loop adjusting the high-level amplitude and phase difference of the driving waveform, the balance of the parallel current of the switching tube can be improved.

[0102] Based on the above ideal embodiments of the present invention, the relevant staff can make various changes and modifications without departing from the technical concept of the present invention through the above description. The technical scope of the present invention is not limited to the contents of the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A parallel current-sharing digital closed-loop active drive system, characterized in that: include: Switching tube circuit, current sampling and conditioning circuit, dynamic current identification circuit, static current identification circuit, static current sharing closed-loop control circuit, dynamic current sharing closed-loop control circuit, driving power supply regulation circuit and driving circuit; wherein, The switch tube circuit is used to generate a switching current; The current sampling and conditioning circuit performs voltage conditioning on the switch current to obtain the switch voltage; The static current identification circuit performs static current identification on the discretized switch voltage; The dynamic current identification circuit performs dynamic current identification on the discretized switch voltage; The static current sharing closed-loop control circuit generates pulse width modulation waveforms with different duty ratios according to the static current; The dynamic current sharing closed-loop control circuit generates pulse width modulation signals of different phases according to the dynamic current; The driving power supply regulating circuit generates different driving voltages for the driving circuit according to the pulse width modulation waveforms with different duty ratios; The driving circuit outputs different driving voltages according to the pulse width modulation signals of different phases, and uses the driving voltage to control the switching current of the switching tube circuit to perform closed-loop regulation and dynamic and static current balancing.

2. The parallel current-sharing digital closed-loop active drive system according to claim 1, characterized in that: The current sampling and conditioning circuit includes: voltage isolation follower A 11 , A 21 、Operational amplifier A 12 , A 22 , resistor R 11 To R 13 , resistor R 21 To R 23 , A 11 The inverting input terminal is connected to the output terminal, A 11 The output terminal and R 12 The right end of the connection, R 12 The left end of A 12 The same-direction input terminal of A 12 The inverting input terminal is connected to R 13 , R 11 One end of the connection, R 13 The other end of A 12 The output terminal connection of 21 The inverting input terminal is connected to the output terminal, A 21 The output terminal and R 22 The right end of the connection, R 22 The left end of A 22 The same-direction input terminal of A 22 The inverting input terminal is connected to R 23 , R 21 One end of the connection, R 23 The other end of A 22 The output terminal is connected.

3. The parallel current-sharing digital closed-loop active drive system according to claim 1, characterized in that: The driving power supply regulation circuit includes: switch tube Q B1 , Q B2 , diodes D1, D2, inductors L1, L2, capacitors C1, C2, Q B1 The gate and source of D1 are connected in parallel, the negative electrode of D1 is connected to the left end of L1, the right end of L1 is connected to the upper end of C1, and the lower end of C1 is connected to the positive electrode of D1; Q B2 The gate and source of D2 are connected in parallel, the cathode of D2 is connected to the left end of L2, the right end of L2 is connected to the upper end of C2, and the lower end of C2 is connected to the positive electrode of D2.

4. The parallel current-sharing digital closed-loop active drive system according to claim 1, characterized in that: The driving circuit includes: switch tube Q H1 , Q L1 , Q H2 , Q L2 , Q H1 The source and Q L1 The source connection, Q H1 The gate and Q L1 The gate connection of Q H2 The source and Q L2 The source connection, Q H2 The gate and Q L2 The gate connection.

5. The parallel current-sharing digital closed-loop active drive system according to claim 1, characterized in that: The switch tube circuit includes: switch tubes Q1, Q2, current sensors S1, S2, the source of Q1 is connected in series with S1, the source of Q2 is connected in series with S2, the drain of Q1 is connected to the drain of Q2, and the lower end of S1 is connected to the lower end of S2.

6. The parallel current-sharing digital closed-loop active drive system according to claim 1, characterized in that: The dynamic current identification circuit makes judgments based on the discrete value of the current. When the discrete value of the current does not reach the steady-state current value threshold range, it is a dynamic current.

7. The parallel current-sharing digital closed-loop active drive system according to claim 1, characterized in that: The static current identification circuit makes judgments based on the discrete value of the current. When the discrete value of the current is within the steady-state current value threshold range, it is a static current.

8. The parallel current-sharing digital closed-loop active drive system according to claim 1, characterized in that: The static current sharing closed-loop control circuit includes converting the static current i k1,s and i k2,s The error signal e is obtained by subtracting s , through C s (s) adjustment, output duty cycle fine-tuning signal Δd, according to the initial duty cycle D, use HRPWM module to output pulse width modulation waveforms with duty cycles of D-Δd and D+Δd respectively.

9. The parallel current-sharing digital closed-loop active drive system according to claim 1, characterized in that: The dynamic current sharing closed-loop control circuit includes converting the dynamic current i k1,d and i k2,d The error signal e is obtained by subtracting d , through C d (s) adjustment, output phase difference signal The HRPWM module is used to output the initial pulse width modulation signal and the phase difference is The initial pulse width modulation signal.

10. A computer readable medium storing computer program code, characterized in that: When the computer program code is executed by a processor, the parallel current-sharing digital closed-loop active drive system according to any one of claims 1 to 9 is implemented.

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