Charge amplifier structure and use method thereof

Abstract

The invention relates to the field of charge detection reading, and discloses a charge amplifier structure and a use method thereof, and the structure comprises an amplification unit which is used for receiving a to-be-identified charge signal outputted by a detector, and amplifying the received to-be-identified charge signal to obtain an amplified signal of the to-be-identified charge signal; the peak value sampling and holding circuit is used for collecting a peak value voltage signal of the amplification signal output by the amplification unit and storing the peak value voltage signal in a capacitor; the feedback circuit is used for feeding back the peak voltage signal acquired by the peak sampling and holding circuit to the reference voltage end of the amplification unit to form a new baseline of the amplification unit; and the reset signal unit is used for processing the amplification signal output by the amplification unit to obtain a trigger signal of the charge signal, and processing the trigger signal to obtain reset signals of the amplification unit and the peak value sampling and holding circuit. The problem that a traditional charge amplifier cannot continuously integrate charges with slow drifting speed and cannot continuously superpose collected charge peak values is solved.

Description

Technical Field

[0001] The present invention relates to the field of charge detection and readout technology, and in particular to a novel charge amplifier structure for reading out mainly by continuously integrating input charge and a method for using the same. Background Art

[0002] In nuclear detector applications, the main function of the detector is to detect radioactive materials and their physical properties by interacting with rays, particles or other radiation. These interactions will produce different types of signals in the sensitive materials of the detector, usually in the form of charges, which may be electron-hole pairs or ionic charges, depending on the material and working principle of the detector. For example, in semiconductor detectors, when particles pass through the material, electrons and holes are excited. Due to the high electron mobility of semiconductor materials, these charge carriers can drift quickly in the electric field, thereby generating signals with fast rise times, while in gas detectors, the interaction will produce charged slow-drifting ions and free electrons. These different types of charge signals reflect key information such as the energy and position of the particles and are the basis for subsequent signal processing. In the weak signals generated by the detector, since the number of charges generated by nuclear radiation is usually very small, the signal is easily interfered by noise, and direct processing of these signals will face significant challenges. At this time, the charge amplifier, especially the charge amplifier, plays a key role as the first checkpoint in the signal chain. Its main function is to convert the weak charge signal generated by the detector into a voltage signal that is easy to measure and process, while maintaining the integrity and accuracy of the signal as much as possible. The charge amplifier needs to have extremely high sensitivity and low noise characteristics to ensure that these important physical information can be accurately extracted and amplified, laying a solid foundation for subsequent signal analysis.

[0003] The signal widths of different nuclear detectors vary greatly, and the requirements for the integration time of the charge amplifier are different. The integration time of existing charge amplifiers does not exceed a few milliseconds, which cannot meet the needs of extremely slow charge signals, especially when integrating slowly drifting ion charges for a long time, there are many limitations. The existence of this problem seriously limits the reliability and applicability of charge amplifiers in high-precision nuclear detection applications. Based on this, the present invention proposes a new type of charge amplifier specifically for continuous integration of input charges. By introducing an adaptive feedback control mechanism, the charge amplifier can dynamically adjust the baseline of the charge amplifier according to the peak value of the collected signal, and realizes the function of continuously superimposing the collected charge peaks and self-resetting, thereby effectively solving the limitation that the integration time of existing charge sensitive amplifiers can only reach a few milliseconds. In addition, the new charge amplifier can not only accurately amplify instantaneous electron-hole pair signals, but also effectively process slower drifting ion signals. These technical improvements have greatly enhanced the ability of charge amplifiers to cope with different types of signals in nuclear detectors, so that the integrity and accuracy of the signal have been significantly improved. Summary of the invention

[0004] In view of the above problems, the purpose of the present invention is to provide a charge amplifier structure and a method of using the same, which effectively solves the difficulties that traditional charge amplifiers cannot continuously integrate charges with slow drift speeds and cannot continuously superimpose collected charge peaks.

[0005] To achieve the above object, the present invention adopts the following technical solution: a charge amplifier structure, which includes: an amplifying unit, used for receiving the charge signal to be identified output by the detector, and amplifying the received charge signal to be identified to obtain an amplified signal of the charge signal to be identified; A peak sampling and holding circuit is used to collect the peak voltage signal of the amplified signal output by the amplification unit and store it in a capacitor; A feedback circuit, used for feeding back the peak voltage signal collected by the peak sampling and holding circuit to the reference voltage terminal of the amplifying unit to form a new baseline of the amplifying unit; The reset signal unit is used to process the amplified signal output by the amplifying unit to obtain a trigger signal of the charge signal, and to process the trigger signal to obtain a reset signal of the amplifying unit and the peak sampling and holding circuit.

[0006] Furthermore, the amplifying unit includes a first amplifier AMP1, a feedback capacitor C f , feedback field effect transistor Q1, baseline holder and first reset switch S1; The detector output terminal is connected to the input terminal of the first amplifier AMP1, and the charge signal to be identified is input into the first amplifier AMP1. The input terminal of the first amplifier AMP1 is also connected to the feedback capacitor C fThe first end of the first amplifier AMP1 is connected to the drain of the feedback field effect tube Q1, the output end of the baseline holder and the first end of the first reset switch S1, and the output end of the first amplifier AMP1 is connected to the feedback capacitor C f The second end of the peak sampling and holding circuit, the source of the feedback field effect tube Q1, the input end of the baseline holder, the second end of the first reset switch S1, the input end of the peak sampling and holding circuit and the input end of the reset signal unit are connected.

[0007] Further, the peak sampling and holding circuit includes: a second amplifier AMP2, a diode, a first capacitor C1, a second reset switch S2 and a voltage buffer; A second amplifier AMP2, whose in-phase terminal is connected to the output terminal of the first amplifier AMP1 in the amplification unit, whose output terminal is connected to the anode of the diode, and whose cathode is connected to the inverting terminal of the second amplifier AMP2, so as to raise the voltage drop caused by the diode; The cathode of the diode is also connected to one end of the second reset switch S2, one end of the first capacitor C1 and the input end of the voltage buffer respectively, and the peak voltage is collected when the diode is turned on; The other end of the first capacitor C1 is connected in parallel with the other end of the second reset switch S2 and then grounded. The first capacitor C1 is used to store the collected peak voltage, and the second reset switch S2 is used to discharge the voltage stored in the first capacitor C1; The output end of the voltage buffer is connected to the feedback circuit and outputs a voltage signal for maintaining the signal output by the peak sampling and holding circuit and enhancing the driving capability of the circuit.

[0008] Furthermore, the second amplifier AMP2 adopts a two-stage operational amplifier or a folded cascode amplifier.

[0009] Further, the reset signal unit includes a comparator, an integration circuit and a monostable circuit; The non-inverting terminal of the comparator is used to receive the output signal of the amplification unit, the inverting terminal is provided with a threshold voltage by an off-chip DAC, and the output terminal of the comparator is connected to the input terminal of the monostable circuit and the input terminal of the integration circuit; The output end of the integration circuit is connected to the monostable circuit to output a voltage signal proportional to the pulse width of the trigger signal; The output signal of the monostable circuit is used for resetting the switches of the amplifying unit and the peak sampling and holding circuit.

[0010] Further, the monostable circuit includes a NOR gate NOR, an inverter INV, a second field effect transistor Q2 and a second capacitor C2; The first input end of the NOR gate NOR is connected to the output end of the comparator, the output end of the NOR gate NOR is connected to the second capacitor C2 and the input end of the inverter INV in sequence, and the second input end of the NOR gate NOR is connected in parallel with the output end of the inverter INV to serve as the output end of the monostable circuit; The gate of the second field effect transistor Q2 is connected to the output end of the integration circuit, the drain of the second field effect transistor Q2 is connected in parallel between the second capacitor C2 and the input end of the inverter INV, and the source is connected to the analog power supply.

[0011] Further, the baseline holder includes a third capacitor C3 and seven field effect transistors: a third field effect transistor Q3 to a ninth field effect transistor Q9; The third field effect transistor Q3 is a bias current source, a source of which is connected to the analog power supply AVDD, a gate receives a bias voltage Vbias, and a drain of the third field effect transistor Q3 is connected to the source of the fourth field effect transistor Q4 and the source of the fifth field effect transistor Q5; The source of the fourth field effect transistor Q4 and the source of the fifth field effect transistor Q5 are connected to form a differential pair, the gate of the fourth field effect transistor Q4 is used as the reference voltage terminal CSA_Vref of the baseline holder, and is connected to the output terminal of the feedback circuit, and the drain of the fourth field effect transistor Q4 is connected to the input terminal of the amplification unit; the gate of the fifth field effect transistor Q5 is used as the input terminal of the baseline holder and is connected to the output terminal of the amplification unit; The drain of the sixth field effect transistor Q6 is connected to the drain of the fourth field effect transistor Q4, the source is grounded, the gate is connected in parallel with one end of the third capacitor C3 and then connected to the drain of the fifth field effect transistor Q5, and the other end of the third capacitor C3 is grounded; The seventh to ninth field effect transistors Q7 - Q9 are connected as a current mirror, and the drain current of the fifth field effect transistor Q5 is integrated into the third capacitor C3 , and the generated voltage controls the gate of the sixth field effect transistor Q6 .

[0012] Furthermore, the feedback circuit is a resistor; one end of the resistor is connected to the output end of the peak sampling and holding circuit, and the other end is connected to the reference voltage end of the baseline holder.

[0013] Furthermore, the feedback circuit is a unit gain voltage buffer; the in-phase end of the unit gain voltage buffer is connected to the output end of the peak sampling and holding circuit, and the inverting end and the output end are connected to the reference voltage end of the baseline holder.

[0014] A method of using the charge amplifier structure, comprising: The charge signal to be identified output by the detector is transmitted to the amplification unit to obtain an amplified signal of the charge signal to be identified; The amplified signal is input into the peak sampling and holding circuit to obtain a peak voltage signal, and the peak voltage signal is fed back to the reference voltage terminal of the amplifying unit by the feedback circuit to form a new baseline of the amplifying unit; The amplified signal output by the amplifying unit is input into the reset signal unit to obtain the reset signal of the amplifying unit and the peak sampling and holding circuit.

[0015] The present invention adopts the above technical solution, which has the following advantages: 1. The present invention adopts feedback circuit, integration circuit and monostable circuit, which can adaptively adjust the integration time. The integration time range can be from tens of nanoseconds to several seconds, meeting the needs of physical experiments.

[0016] 2. The amplifier unit of the present invention is used to amplify the charge signal from the detector. The peak voltage signal collected by the peak sampling and holding circuit is fed back to the reference voltage terminal of the amplifier unit through the feedback circuit, which can collect and superimpose the peak value of the continuously integrated charge and generate amplitude information representing the energy. Then, the reset signal of the amplifier unit and the peak sampling and holding circuit is obtained through the reset signal unit. This effectively solves the problem that the traditional charge amplifier cannot continuously integrate the charge with a slow drift speed and cannot continuously superimpose the collected charge peaks. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a schematic diagram of the overall structure of the charge amplifier structure in an embodiment of the present invention; Figure 2 1 is a schematic diagram of the structure of a peak sampling and holding circuit in an embodiment of the present invention; Figure 3 is a schematic diagram of the structure of a reset signal unit in an embodiment of the present invention; Figure 4 is a schematic diagram of the structure of a baseline holder in an embodiment of the present invention; Figure 5 is a schematic diagram of the feedback circuit structure in an embodiment of the present invention; Figure 6 is a timing diagram of the readout operation in an embodiment of the present invention; Figure 7 It is a flow chart of the method of using the charge amplifier structure in an embodiment of the present invention. DETAILED DESCRIPTION

[0018] The charge amplifier is a key electronic device used in nuclear physics, particle physics, medical imaging and other radiation detection fields. Its main function is to amplify the weak charge signals output by detectors (such as semiconductor detectors, gas detectors, scintillators, etc.) so that subsequent electronic systems can process these signals more effectively. The charge signal generated by the detector after receiving radiation is usually very weak and not enough to be directly processed by the subsequent electronic system. The charge amplifier converts these weak charge signals into larger voltage signals through gain. The signal width of nuclear detectors varies greatly among different types of detectors, mainly depending on the working principle of the detector and how they respond to nuclear radiation. Therefore, the requirements for the integration time of the charge amplifier vary greatly. At the same time, the integration time of the charge amplifier cannot exceed a few milliseconds, which cannot meet the measurement of extremely slow signals represented by ion time projection chambers.

[0019] For example, a time projection chamber gas detector can simultaneously measure the three-dimensional position information and energy information of charged particles. It consists of a cylindrical chamber filled with a specific working gas. In the middle of the chamber, an electrode plate with negative high voltage is applied, and the two ends are closed with end caps. When a charged particle passes through this chamber, an ionization track is formed in the gas in the chamber to produce ionized electrons. These electrons drift toward the end caps under the impetus of the electric field force. By measuring the drift time and speed of the charge at the readout electronics located at the end caps, the position of the particle along the cylindrical direction can be determined. If the time projection chamber is filled with a non-electronegative gas, such as argon or helium, when the particles pass through the detector, they interact with the gas molecules to produce electron-ion pairs. Since the electrons are not quickly captured by the gas molecules, they can drift freely in the electric field, thus forming particle tracks, and the integration time of the charge signal is required to be in the microsecond range. If the time projection chamber uses an electronegative gas as the working medium, such as sulfur hexafluoride (SF6) or its mixture with noble gases, this type of TPC shows great potential in neutrinoless double beta decay experiments, such as NvDEx (neutrinoless double beta decay experiment), which uses the characteristics of electronegative gases to improve the performance of the detector. In electronegative gas TPCs, due to the affinity of electronegative gases for electrons, when charged particles interact with gas molecules and produce electrons, they will quickly combine with gas molecules to form negative ions. This characteristic enables electronegative gas TPCs to integrate charge signals for a long time, which is very useful for measuring low-energy particles or applications that require long-term integration. The time width of charge integration also reaches the order of hundreds of milliseconds to several seconds.

[0020] In order to meet the integration time requirements of different detector signals from tens of nanoseconds to several seconds, and to solve the limitation that the integration time of existing charge sensitive amplifiers can only reach the order of several milliseconds, the present invention proposes a charge amplifier structure and a method of using the same to support the integration time from tens of nanoseconds to several seconds, which includes: an amplifier unit for receiving a charge signal and amplifying the received charge signal to be identified to obtain an amplified signal of the charge signal to be identified; a peak sampling and holding circuit for collecting the peak signal of the amplifier unit and storing it in a capacitor; a feedback circuit for feeding back the peak voltage signal collected by the peak sampling and holding circuit to the reference voltage terminal of the amplifier unit to form a new baseline for the amplifier unit; a reset signal unit for processing the signal output by the amplifier unit to obtain a trigger signal of the charge signal, and processing the trigger signal to obtain a reset signal of the readout circuit. The present invention can be applied in the field of charge detection.

[0021] In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. Based on the described embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present invention.

[0022] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0023] In one embodiment of the present invention, a charge amplifier structure is provided. In this embodiment, Figure 1 As shown, the charge amplifier structure includes: an amplifying unit, used for receiving the charge signal to be identified output by the detector, and amplifying the received charge signal to be identified to obtain an amplified signal of the charge signal to be identified; A peak sampling and holding circuit is used to collect the peak voltage signal of the amplified signal output by the amplification unit and store it in a capacitor; A feedback circuit, used for feeding back the peak voltage signal collected by the peak sampling and holding circuit to the reference voltage terminal of the amplifying unit to form a new baseline of the amplifying unit; The reset signal unit is used to process the amplified signal output by the amplifying unit to obtain a trigger signal of the charge signal, and to process the trigger signal to obtain a reset signal of the amplifying unit and the peak sampling and holding circuit.

[0024] In the above embodiment, the amplifying unit includes a first amplifier AMP1, a feedback capacitor C f , a feedback field effect transistor Q1, a baseline holder and a first reset switch S1. The first amplifier AMP1 may be a single-ended folded common-source common-gate amplifier.

[0025] The detector output terminal is connected to the input terminal of the first amplifier AMP1, and the charge signal to be identified is input into the first amplifier AMP1. The input terminal of the first amplifier AMP1 is also connected to the feedback capacitor C f The first end of the first amplifier AMP1 is connected to the drain of the feedback field effect tube Q1, the output end of the baseline holder and the first end of the first reset switch S1, and the output end of the first amplifier AMP1 is connected to the feedback capacitor C f The second end of the peak sampling and holding circuit, the source of the feedback field effect tube Q1, the input end of the baseline holder, the second end of the first reset switch S1, the input end of the peak sampling and holding circuit and the input end of the reset signal unit are connected.

[0026] In this embodiment, the output end of the feedback circuit is connected to the reference voltage end CSA_Vref of the baseline holder; the reset signal output by the reset signal unit is respectively input to the first reset switch S1 of the amplifying unit and the switch of the peak sampling and holding circuit.

[0027] In the above embodiment, Figure 2 As shown, the peak sampling and holding circuit includes: a second amplifier AMP2, a diode, a first capacitor C1, a second reset switch S2 and a voltage buffer.

[0028] The second amplifier AMP2, whose in-phase terminal is connected to the output terminal of the first amplifier AMP1 in the amplification unit, the output terminal of the second amplifier AMP2 is connected to the positive electrode of the diode, and the negative electrode of the diode is connected to the inverting terminal of the second amplifier AMP2, so as to raise the voltage drop caused by the diode; in this embodiment, the second amplifier AMP2 is usually a two-stage operational amplifier or a folded common source and common gate amplifier; The cathode of the diode is also connected to one end of the second reset switch S2, one end of the first capacitor C1 and the input end of the voltage buffer respectively. The peak voltage is collected when the diode is turned on and is cut off after the collection. The other end of the first capacitor C1 is connected in parallel with the other end of the second reset switch S2 and then grounded. The first capacitor C1 is used to store the collected peak voltage, and the second reset switch S2 is used to discharge the voltage stored in the first capacitor C1. In this embodiment, the second reset switch S2 is usually an NMOS field effect transistor, and its gate is connected to a high level reset; The output end of the voltage buffer is connected to the feedback circuit and outputs a voltage signal for maintaining the signal output by the peak sampling and holding circuit and enhancing the driving capability of the circuit.

[0029] In the above embodiment, Figure 3 As shown, the reset signal unit includes a comparator, an integration circuit and a monostable circuit. The monostable circuit includes a NOR gate NOR, an inverter INV, a second field effect transistor Q2 and a second capacitor C2.

[0030] The non-inverting terminal of the comparator is used to receive the output signal of the amplification unit, the inverting terminal is provided with a threshold voltage by an off-chip DAC, and the output terminal of the comparator is connected to the input terminal of the monostable circuit and the input terminal of the integration circuit; The output end of the integration circuit is connected to the gate of the second field effect transistor Q2, and is used to output a voltage signal proportional to the pulse width of the trigger signal; The output signal of the monostable circuit is used for resetting the switches of the amplifying unit and the peak sampling and holding circuit.

[0031] Wherein, the first input end of the NOR gate NOR in the monostable circuit is connected to the output end of the comparator, the output end of the NOR gate NOR is connected to the second capacitor C2 and the input end of the inverter INV in sequence, and the second input end of the NOR gate NOR is connected in parallel with the output end of the inverter INV to serve as the output end of the monostable circuit; The drain of the second field effect transistor Q2 is connected in parallel between the second capacitor C2 and the input terminal of the inverter INV, and the source is connected to the analog power supply AVDD.

[0032] When in use, the equivalent resistor R of the second field effect tube Q2 and the second capacitor C2 constitute the time constant of the monostable circuit, which is used to determine the extended voltage control time of the reset signal. The gate of the second field effect tube Q2 receives the voltage signal output by the integration circuit to change the value of the equivalent resistor R in real time.

[0033] Although specific embodiments are described in the present invention, the present invention is not limited to these specific embodiments, and any other equivalent embodiments are within the protection scope of the present invention.

[0034] In the above embodiment, Figure 4 As shown, the baseline holder includes a third capacitor C3 and seven field effect transistors: a third field effect transistor Q3 to a ninth field effect transistor Q9.

[0035] The third field effect transistor Q3 is a bias current source, a source of which is connected to the analog power supply AVDD, a gate receives a bias voltage Vbias, and a drain of the third field effect transistor Q3 is connected to the source of the fourth field effect transistor Q4 and the source of the fifth field effect transistor Q5; The source of the fourth field effect transistor Q4 and the source of the fifth field effect transistor Q5 are connected to form a differential pair, the gate of the fourth field effect transistor Q4 is used as the reference voltage terminal CSA_Vref of the baseline holder, and is connected to the output terminal of the feedback circuit, and the drain of the fourth field effect transistor Q4 is connected to the input terminal of the amplification unit; the gate of the fifth field effect transistor Q5 is used as the input terminal of the baseline holder and is connected to the output terminal of the amplification unit; The drain of the sixth field effect transistor Q6 is connected to the drain of the fourth field effect transistor Q4, the source is grounded, the gate is connected in parallel with one end of the third capacitor C3 and then connected to the drain of the fifth field effect transistor Q5, and the other end of the third capacitor C3 is grounded; The seventh to ninth field effect transistors Q7 - Q9 are connected as a current mirror, and the drain current of the fifth field effect transistor Q5 is integrated into the third capacitor C3 , and the generated voltage controls the gate of the sixth field effect transistor Q6 .

[0036] When in use, the baseline holder can also compensate for the influence of the detector leakage current. When there is a voltage difference between the reference voltage terminal CSA_Vref and the output of the amplification unit, the channel current of the sixth field effect transistor Q6 will increase, thereby compensating for the leakage current of the detector and stabilizing the output baseline.

[0037] Although specific embodiments are described in the present invention, the present invention is not limited to these specific embodiments, and any other equivalent embodiments are within the protection scope of the present invention.

[0038] In the above embodiment, Figure 5 As shown in the figure, the feedback circuit can be implemented in two structural forms. The first feedback circuit is implemented with a resistor. One end of the resistor is connected to the output terminal Vout of the peak sampling and holding circuit, and the other end is connected to the reference voltage terminal CSA_Vref of the baseline holder. The resistor provides a stable feedback path in the feedback loop to help the baseline of the charge amplifier maintain an accurate peak voltage. In addition, the resistor can adjust the time constant of the circuit. Selecting a suitable resistance value can adjust the response speed and stability of the circuit.

[0039] like Figure 5 As shown, the second feedback circuit is implemented by a unit gain voltage buffer. The non-inverting terminal of the unit gain voltage buffer is connected to the output terminal Vout of the peak sampling and holding circuit, and the inverting terminal and the output terminal are connected to the reference voltage terminal CSA_Vref of the baseline holder.

[0040] Although specific embodiments are described in the present invention, the present invention is not limited to these specific embodiments, and any other equivalent embodiments are within the protection scope of the present invention.

[0041] In the above embodiments, Figure 6 As shown, the readout timing is: After the slowly drifting charge signal with different pulse widths is integrated to the first peak, the peak voltage is collected by the peak sampling and holding circuit of the subsequent stage and fed back to the reference voltage terminal of the amplifying unit to adjust the baseline in real time (the feedback time can be on the order of tens of nanoseconds). The peak sampling and holding circuit superimposes the second integrated charge peak collected on the basis of the collected first peak, and so on. Finally, the peak sampling and holding circuit continues to superimpose peak values ​​to obtain the energy information of the final slowly drifting charge.

[0042] The amplified signal output by the amplifying unit generates a trigger signal through a comparator, and then generates a reset signal for the amplifying unit and the peak sampling and holding circuit through a monostable circuit. The reset signal starts sampling when the falling edge arrives and resets when the rising edge arrives. Each reset signal can adaptively extend the voltage control time according to the trigger signal of different pulse width input signals.

[0043] The integrator generates a voltage signal proportional to the trigger signal pulse width and inputs it into the monostable circuit to change the extended voltage control time. In addition to the system self-reset function realized by the reset unit, the reset of the readout circuit can also be reset in real time by an external pulse signal.

[0044] In one embodiment of the present invention, a method for using a charge amplifier structure is provided, and the method is implemented based on the charge amplifier structure in the above embodiments. In this embodiment, Figure 7 As shown, the method of use includes the following steps: 1) transmitting the charge signal to be identified output by the detector to the amplification unit to obtain an amplified signal of the charge signal to be identified; 2) Input the amplified signal into the peak sampling and holding circuit to obtain the peak voltage signal, and the feedback circuit feeds the peak voltage signal back to the reference voltage terminal of the amplifying unit to form a new baseline of the amplifying unit; 3) The amplified signal output by the amplifying unit is input into the reset signal unit to obtain the reset signal of the amplifying unit and the peak sampling and holding circuit.

[0045] In the above embodiment, the amplifying unit includes a first amplifier AMP1, a feedback capacitor C f , feedback field effect transistor Q1, baseline holder and first reset switch S1; The detector output terminal is connected to the input terminal of the first amplifier AMP1, and the charge signal to be identified is input into the first amplifier AMP1. The input terminal of the first amplifier AMP1 is also connected to the feedback capacitor C f The first end of the first amplifier AMP1 is connected to the drain of the feedback field effect tube Q1, the output end of the baseline holder and the first end of the first reset switch S1, and the output end of the first amplifier AMP1 is connected to the feedback capacitor C fThe second end of the peak sampling and holding circuit, the source of the feedback field effect tube Q1, the input end of the baseline holder, the second end of the first reset switch S1, the input end of the peak sampling and holding circuit and the input end of the reset signal unit are connected.

[0046] In the above embodiment, the peak sampling and holding circuit includes: a second amplifier AMP2, a diode, a first capacitor C1, a second reset switch S2 and a voltage buffer; A second amplifier AMP2, whose in-phase terminal is connected to the output terminal of the first amplifier AMP1 in the amplification unit, whose output terminal is connected to the anode of the diode, and whose cathode is connected to the inverting terminal of the second amplifier AMP2, so as to raise the voltage drop caused by the diode; The cathode of the diode is also connected to one end of the second reset switch S2, one end of the first capacitor C1 and the input end of the voltage buffer respectively, and the peak voltage is collected when the diode is turned on; The other end of the first capacitor C1 is connected in parallel with the other end of the second reset switch S2 and then grounded. The first capacitor C1 is used to store the collected peak voltage, and the second reset switch S2 is used to discharge the voltage stored in the first capacitor C1; The output end of the voltage buffer is connected to the feedback circuit and outputs a voltage signal for maintaining the signal output by the peak sampling and holding circuit and enhancing the driving capability of the circuit.

[0047] In this embodiment, the second amplifier AMP2 is a two-stage operational amplifier or a folded cascode amplifier.

[0048] In the above embodiment, the reset signal unit includes a comparator, an integration circuit and a monostable circuit; The non-inverting terminal of the comparator is used to receive the output signal of the amplification unit, the inverting terminal is provided with a threshold voltage by an off-chip DAC, and the output terminal of the comparator is connected to the input terminal of the monostable circuit and the input terminal of the integration circuit; The output end of the integration circuit is connected to the monostable circuit to output a voltage signal proportional to the pulse width of the trigger signal; The output signal of the monostable circuit is used for resetting the switches of the amplifying unit and the peak sampling and holding circuit.

[0049] In this embodiment, the monostable circuit includes a NOR gate NOR, an inverter INV, a second field effect transistor Q2 and a second capacitor C2; The first input end of the NOR gate NOR is connected to the output end of the comparator, the output end of the NOR gate NOR is connected to the second capacitor C2 and the input end of the inverter INV in sequence, and the second input end of the NOR gate NOR is connected in parallel with the output end of the inverter INV to serve as the output end of the monostable circuit; The gate of the second field effect transistor Q2 is connected to the output end of the integration circuit, the drain of the second field effect transistor Q2 is connected in parallel between the second capacitor C2 and the input end of the inverter INV, and the source is connected to the analog power supply.

[0050] In the above embodiment, the baseline holder includes a third capacitor C3 and seven field effect transistors: a third field effect transistor Q3 to a ninth field effect transistor Q9; The third field effect transistor Q3 is a bias current source, a source of which is connected to the analog power supply AVDD, a gate receives a bias voltage Vbias, and a drain of the third field effect transistor Q3 is connected to the source of the fourth field effect transistor Q4 and the source of the fifth field effect transistor Q5; The source of the fourth field effect transistor Q4 and the source of the fifth field effect transistor Q5 are connected to form a differential pair, the gate of the fourth field effect transistor Q4 is used as the reference voltage terminal CSA_Vref of the baseline holder, and is connected to the output terminal of the feedback circuit, and the drain of the fourth field effect transistor Q4 is connected to the input terminal of the amplification unit; the gate of the fifth field effect transistor Q5 is used as the input terminal of the baseline holder and is connected to the output terminal of the amplification unit; The drain of the sixth field effect transistor Q6 is connected to the drain of the fourth field effect transistor Q4, the source is grounded, the gate is connected in parallel with one end of the third capacitor C3 and then connected to the drain of the fifth field effect transistor Q5, and the other end of the third capacitor C3 is grounded; The seventh to ninth field effect transistors Q7 - Q9 are connected as a current mirror, and the drain current of the fifth field effect transistor Q5 is integrated into the third capacitor C3 , and the generated voltage controls the gate of the sixth field effect transistor Q6 .

[0051] In the above embodiment, the feedback circuit is a resistor; one end of the resistor is connected to the output end of the peak sampling and holding circuit, and the other end is connected to the reference voltage end of the baseline holder.

[0052] In the above embodiment, the feedback circuit is a unit gain voltage buffer; the non-inverting end of the unit gain voltage buffer is connected to the output end of the peak sampling and holding circuit, and the inverting end and the output end are connected to the reference voltage end of the baseline holder.

[0053] The method of use provided in this embodiment is implemented based on the embodiments of the above-mentioned charge amplifier structures. Please refer to the above-mentioned embodiments for specific implementation methods and detailed contents, which will not be repeated here.

[0054] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A charge amplifier structure, characterized in that: include: an amplifying unit, used for receiving the charge signal to be identified output by the detector, and amplifying the received charge signal to be identified to obtain an amplified signal of the charge signal to be identified; A peak sampling and holding circuit is used to collect the peak voltage signal of the amplified signal output by the amplification unit and store it in a capacitor; A feedback circuit, used for feeding back the peak voltage signal collected by the peak sampling and holding circuit to the reference voltage terminal of the amplifying unit to form a new baseline of the amplifying unit; The reset signal unit is used to process the amplified signal output by the amplifying unit to obtain a trigger signal of the charge signal, and to process the trigger signal to obtain a reset signal of the amplifying unit and the peak sampling and holding circuit.

2. The charge amplifier structure according to claim 1, characterized in that: The amplifying unit includes a first amplifier AMP1, a feedback capacitor C f , feedback field effect transistor Q1, baseline holder and first reset switch S1; The detector output terminal is connected to the input terminal of the first amplifier AMP1, and the charge signal to be identified is input into the first amplifier AMP1. The input terminal of the first amplifier AMP1 is also connected to the feedback capacitor C f The first end of the first amplifier AMP1 is connected to the drain of the feedback field effect tube Q1, the output end of the baseline holder and the first end of the first reset switch S1, and the output end of the first amplifier AMP1 is connected to the feedback capacitor C f The second end of the peak sampling and holding circuit, the source of the feedback field effect tube Q1, the input end of the baseline holder, the second end of the first reset switch S1, the input end of the peak sampling and holding circuit and the input end of the reset signal unit are connected.

3. The charge amplifier structure according to claim 1, characterized in that: The peak sampling and holding circuit includes: a second amplifier AMP2, a diode, a first capacitor C1, a second reset switch S2 and a voltage buffer; A second amplifier AMP2, whose in-phase terminal is connected to the output terminal of the first amplifier AMP1 in the amplification unit, whose output terminal is connected to the anode of the diode, and whose cathode is connected to the inverting terminal of the second amplifier AMP2, so as to raise the voltage drop caused by the diode; The cathode of the diode is also connected to one end of the second reset switch S2, one end of the first capacitor C1 and the input end of the voltage buffer respectively, and the peak voltage is collected when the diode is turned on; The other end of the first capacitor C1 is connected in parallel with the other end of the second reset switch S2 and then grounded. The first capacitor C1 is used to store the collected peak voltage, and the second reset switch S2 is used to discharge the voltage stored in the first capacitor C1; The output end of the voltage buffer is connected to the feedback circuit and outputs a voltage signal for maintaining the signal output by the peak sampling and holding circuit and enhancing the driving capability of the circuit.

4. The charge amplifier structure according to claim 3, characterized in that: The second amplifier AMP2 is a two-stage operational amplifier or a folded common-source common-gate amplifier.

5. The charge amplifier structure according to claim 1, characterized in that: The reset signal unit includes a comparator, an integration circuit and a monostable circuit; The non-inverting terminal of the comparator is used to receive the output signal of the amplification unit, the inverting terminal is provided with a threshold voltage by an off-chip DAC, and the output terminal of the comparator is connected to the input terminal of the monostable circuit and the input terminal of the integration circuit; The output end of the integration circuit is connected to the monostable circuit to output a voltage signal proportional to the pulse width of the trigger signal; The output signal of the monostable circuit is used for resetting the switches of the amplifying unit and the peak sampling and holding circuit.

6. The charge amplifier structure according to claim 5, characterized in that: The monostable circuit includes a NOR gate NOR, an inverter INV, a second field effect transistor Q2 and a second capacitor C2; The first input end of the NOR gate NOR is connected to the output end of the comparator, the output end of the NOR gate NOR is connected to the second capacitor C2 and the input end of the inverter INV in sequence, and the second input end of the NOR gate NOR is connected in parallel with the output end of the inverter INV to serve as the output end of the monostable circuit; The gate of the second field effect transistor Q2 is connected to the output end of the integration circuit, the drain of the second field effect transistor Q2 is connected in parallel between the second capacitor C2 and the input end of the inverter INV, and the source is connected to the analog power supply.

7. The charge amplifier structure according to claim 1, characterized in that: The baseline holder includes a third capacitor C3 and seven field effect transistors: a third field effect transistor Q3 to a ninth field effect transistor Q9; The third field effect transistor Q3 is a bias current source, a source of which is connected to the analog power supply AVDD, a gate receives a bias voltage Vbias, and a drain of the third field effect transistor Q3 is connected to the source of the fourth field effect transistor Q4 and the source of the fifth field effect transistor Q5; The source of the fourth field effect transistor Q4 and the source of the fifth field effect transistor Q5 are connected to form a differential pair, the gate of the fourth field effect transistor Q4 is used as the reference voltage terminal CSA_Vref of the baseline holder, and is connected to the output terminal of the feedback circuit, and the drain of the fourth field effect transistor Q4 is connected to the input terminal of the amplification unit; the gate of the fifth field effect transistor Q5 is used as the input terminal of the baseline holder and is connected to the output terminal of the amplification unit; The drain of the sixth field effect transistor Q6 is connected to the drain of the fourth field effect transistor Q4, the source is grounded, the gate is connected in parallel with one end of the third capacitor C3 and then connected to the drain of the fifth field effect transistor Q5, and the other end of the third capacitor C3 is grounded; The seventh to ninth field effect transistors Q7 - Q9 are connected as a current mirror, and the drain current of the fifth field effect transistor Q5 is integrated into the third capacitor C3 , and the generated voltage controls the gate of the sixth field effect transistor Q6 .

8. The charge amplifier structure according to claim 1, characterized in that: The feedback circuit is a resistor; one end of the resistor is connected to the output end of the peak sampling and holding circuit, and the other end of the resistor is connected to the reference voltage end of the baseline holder.

9. The charge amplifier structure according to claim 1, characterized in that: The feedback circuit is a unit gain voltage buffer; the in-phase end of the unit gain voltage buffer is connected to the output end of the peak sampling and holding circuit, and the inverting end and the output end are connected to the reference voltage end of the baseline holder.

10. A method for using the charge amplifier structure according to any one of claims 1 to 9, characterized in that: include: The charge signal to be identified output by the detector is transmitted to the amplification unit to obtain an amplified signal of the charge signal to be identified; The amplified signal is input into the peak sampling and holding circuit to obtain a peak voltage signal, and the peak voltage signal is fed back to the reference voltage terminal of the amplifying unit by the feedback circuit to form a new baseline of the amplifying unit; The amplified signal output by the amplifying unit is input into the reset signal unit to obtain the reset signal of the amplifying unit and the peak sampling and holding circuit.

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