Digital-to-analog converter

Abstract

A digital-to-analog converter (DAC) for generating an analog output from a digital input includes a controller configured to generate a control signal based on the digital input; and a segment unit circuit including a plurality of segment units, the plurality of segment units being turned on or off based on a control signal, and the segment unit circuit being configured to generate an analog output based on outputs of the plurality of segment units, each first segment unit is configured to generate an output corresponding to each bit included in a first bit group of the digital input; a plurality of second segment units, each second segment unit configured to generate an output corresponding to each bit included in a second bit group of the digital input; and an additional segmentation unit configured to generate an output corresponding to a lowest bit among the bits included in the second bit group.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the priority of Korean Patent Application No. 10-2023-0110769 filed in the Korean Intellectual Property Office on August 23, 2023, and Korean Patent Application No. 10-2023-0186301 filed in the Korean Intellectual Property Office on December 19, 2023, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The disclosed embodiments relate to digital-to-analog converters (DACs), and more particularly, to analog-to-digital converters (DACs) for generating analog outputs from digital inputs. Background Art

[0004] Communication systems such as the fifth generation (5G) use orthogonal frequency division multiplexing (OFDM) for communication in both uplink and downlink, so very small data sizes can be used in each channel. Electronic devices in the communication system can use DACs to convert digital signals into analog signals and can output the analog signals.

[0005] The DAC can convert digital input into analog output. In this case, when the digital input of the DAC is small, even a small error in the process of converting the digital input into analog output may cause the linearity and dynamic range performance to degrade. Summary of the invention

[0006] According to some implementations of the present disclosure, a digital-to-analog converter (DAC) is provided, which can reduce errors that occur in the process of converting digital input to analog output.

[0007] According to some implementations, a DAC for generating an analog output from a digital input is provided, comprising: a controller configured to generate a control signal based on the digital input; and a segment unit circuit comprising a plurality of segment units, the plurality of segment units being turned on or off based on the control signal, and the segment unit circuit being configured to generate an analog output based on outputs of the plurality of segment units, wherein the plurality of segment units comprise: a plurality of first segment units, each of the first segment units being configured to generate an output corresponding to each bit included in a first bit group of the digital input; a plurality of second segment units, each of the second segment units being configured to generate an output corresponding to each bit included in a second bit group of the digital input; and an additional segment unit being configured to generate an output corresponding to the lowest bit among the bits included in the second bit group.

[0008] According to some implementations, a DAC for generating an analog output from a digital input is provided, comprising: a controller configured to generate a control signal based on the digital input; and a segment unit circuit comprising a plurality of segment units, the plurality of segment units being turned on or off based on the control signal, and the segment unit circuit being configured to generate an analog output based on outputs of the plurality of segment units, wherein the plurality of segment units comprise: a plurality of first segment units, each of the first segment units being configured to generate an output corresponding to each bit included in a first bit group of the digital input; a plurality of second segment units, each of the second segment units being configured to generate an output corresponding to each bit included in a second bit group of the digital input; a plurality of third segment units, each of the third segment units being configured to generate an output corresponding to each bit included in a third bit group of the digital input; and an additional segment unit being configured to generate an output corresponding to the lowest bit among the bits included in the second bit group.

[0009] According to some implementations, a method for operating a DAC is provided, the DAC being used to generate an analog output from a digital input, comprising: receiving a digital input; generating a control signal based on the digital input; and turning on or off a plurality of segment units based on the control signal, wherein the plurality of segment units comprise: a plurality of first segment units, each of the first segment units being configured to generate an output corresponding to each bit included in a first bit group of the digital input; a plurality of second segment units, each of the second segment units being configured to generate an output corresponding to each bit included in a second bit group of the digital input; and an additional segment unit being configured to generate an output corresponding to the lowest bit among the bits included in the second bit group. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The embodiments of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a block diagram illustrating an example of a communication device;

[0012] Figure 2 is a block diagram illustrating an example of a digital-to-analog converter (DAC);

[0013] Figure 3A is a circuit diagram showing an example of a segment unit circuit in which a digital input of a DAC is divided into two bit groups;

[0014] Figure 3B is shown with Figure 3A A diagram of the structure of a plurality of segment units corresponding to the segment unit circuit;

[0015] Figure 3C is shown with Figure 3AAn example table of a structure of a segment unit circuit wherein a digital input of a DAC corresponds to a state of a plurality of segment units;

[0016] Figure 4A is a circuit diagram showing an example of a segment unit circuit in which a digital input of a DAC is divided into two bit groups and a high bit is decoded by a thermometer code;

[0017] Figure 4B is shown with Figure 4A A diagram of the structure of a plurality of segment units corresponding to the segment unit circuit;

[0018] Figure 4C is shown with Figure 4A An example table of states of a plurality of segment units corresponding to digital inputs of a DAC of a segment unit circuit structure;

[0019] Figure 5A is a circuit diagram showing an example of a segment unit circuit in which a digital input of a DAC is divided into three bit groups and a high bit is decoded by a thermometer code;

[0020] Figure 5B is shown with Figure 5A A diagram of the structure of a plurality of segment units corresponding to the segment unit circuit;

[0021] Figure 5C is shown with Figure 5A An example table of states of a plurality of segment units corresponding to digital inputs of a DAC of a segment unit circuit structure;

[0022] Fig. 6A is a circuit diagram showing an example of a segment unit circuit in which a digital input of a DAC is divided into three bit groups and upper bits and middle bits are decoded by a thermometer code;

[0023] Figure 6B is shown with Fig. 6A A diagram of the structure of a plurality of segment units corresponding to the segment unit circuit;

[0024] Figure 6C is shown with Fig. 6A An example table of states of a plurality of segment units corresponding to digital inputs of a DAC of a segment unit circuit structure;

[0025] Figure 7 is a flow chart showing an example of a method of operation of a DAC;

[0026] Figure 8 is a flowchart illustrating an example of an operating method of a detection circuit of a DAC.

[0027] Fig. 9is a block diagram illustrating an example of an electronic device; and

[0028] Fig.10 is a diagram showing an example of a communication device including a DAC. DETAILED DESCRIPTION

[0029] Figure 1 is a block diagram showing a communication device. Figure 1 , the communication device 1 may include a processor 10 , a transmitter 20 and a receiver 30 .

[0030] In some implementations, the communication device 1 is a communication device capable of supporting fifth generation (5G) communication, long term evolution (LTE) communication, code division multiple access (CDMA) communication, global system for mobile communication (GSM) communication, wireless local area network (WLAN) communication, or next generation communication. However, the communication device 1 is not limited thereto, for example, in some implementations, the communication device 1 may include at least one of a smart phone, a tablet personal computer (PC), a mobile phone, a video phone, an e-book reader, a desktop computer, a laptop computer, a netbook computer, a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, a mobile medical device, a camera, or a wearable device (e.g., a head mounted device (HMD) (e.g., electronic glasses, electronic clothes, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch)).

[0031] In some implementations, the communication device 1 is a smart home appliance with an image display function. The smart home appliance may include, for example, at least one of a television, a digital video disc (DVD) player, an audio device, a refrigerator, an air conditioner, a cleaner, an oven, a microwave oven, a washing machine, an air purifier, a set-top box, a TV box (e.g., Samsung HomeSync, Apple TV, or Google TV), a game console, an electronic dictionary, an electronic key, a camera, or an electronic photo frame.

[0032] In some implementations, the communication device 1 includes at least one of various medical devices (e.g., magnetic resonance angiography (MRA) devices, magnetic resonance imaging (MRI) devices, computed tomography (CT) devices, imaging devices, ultrasound devices, etc.), navigation devices, global positioning system (GPS) receivers, event data recorders (EDRs), flight data recorders (FDRs), vehicle infotainment devices, marine electronic equipment (e.g., marine navigation systems, gyrocompasses, etc.), avionics equipment, security equipment, vehicle hosts, industrial or household robots, automated teller machines (ATMs) of financial institutions, or point of sale (POS) of stores.

[0033] In some implementations, the communication device 1 includes at least one of a piece of furniture or a part of a building / structure with image display capability, an electronic board, an electronic signature receiving device, a projector, or various measuring devices (e.g., water, electricity, gas, or radio wave measuring devices, etc.).

[0034] The processor 10 may control the overall operation of the communication device 1 and process data required for the operation. The processor 10 may be a baseband processor. As an example, the processor 10 may provide a digital input to the transmitter 20 and may receive a digital input from the receiver 30.

[0035] The transmitter 20 may transmit a radio frequency (RF) signal to a base station or another device through a transmit (TX) channel 2. The receiver 30 may receive an RF signal from a base station or another device through a receive (RX) channel 3.

[0036] In some implementations, the transmitter 20 includes a direct radio frequency (RF) synthesis architecture in which a mixer is omitted, and a digital-to-analog converter (DAC) 100 can generate an analog signal corresponding to the frequency band of the RF signal output from the transmitter 20. For example, the DAC 100 can generate an analog signal in a wide frequency band from a low frequency band to a high frequency band (e.g., a millimeter wave band). However, this is merely an example, and the present disclosure can also be applied to an up-conversion architecture or an intermediate frequency architecture. In addition, the use of the DAC 100 described herein is not limited to a direct RF synthesis architecture, but can be applied to various RF architectures and other types of devices.

[0037] In some implementations, the transmitter 20 and the receiver 30 are implemented as RF integrated circuits and may include amplifiers, oscillators, filters, frequency dividers, etc. necessary for transmitting / receiving RF signals.

[0038] In some implementations, the transmitter 20 includes a DAC 100 for generating an analog output based on a digital input received from the processor 10 .

[0039] In some implementations, as described herein, the DAC 100 generates an analog output by using a plurality of segmentation units, and the plurality of segmentation units includes an additional segmentation unit, as discussed in further detail below. Thus, by using the additional segmentation unit, the DAC 100 can reduce errors that occur in the process of converting a digital input to an analog output, thereby improving linearity and dynamic range performance (e.g., when the magnitude of the digital input is small).

[0040] The following will refer to Figure 2 2 and subsequent figures describe a more detailed structure and operation of the DAC 100 according to some embodiments.

[0041] Reference Figure 2, the DAC 100 may include a controller 110 and a segment unit circuit 120 . In addition, the DAC 100 may further include a detection circuit 130 .

[0042] The controller 110 may control the overall operation of the DAC 100 and process data required for the overall operation.

[0043] In some implementations, the controller 110 generates a control signal based on a digital input. The digital input may be an input including a binary code. The digital input may include a preset number of bits. The bits included in the digital input may be included in any one of a plurality of bit groups.

[0044] For example, when the digital input includes 9 bits and the plurality of bit groups is 2 bit groups, the first bit group may include 3 upper bits including the highest bits among the bits included in the digital input, and the second bit group may include the other 6 lower bits among the bits included in the digital input that are not included in the first bit group.

[0045] As another example, when the digital input includes 12 bits and the plurality of bit groups is 3 bit groups, the first bit group may include 3 upper bits including the 3 upper bits of the highest bits among the bits included in the digital input, the second bit group may include middle bits including the highest bits among the bits included in the digital input that are not included in the first bit group, and the third bit group may include the other 6 lower bits among the bits included in the digital input that are not included in the first and second bit groups.

[0046] The control signal may be a signal for turning on or off a plurality of segment units included in the segment unit circuit 120, for example, as described below. The plurality of segment units may be turned on or off based on the control signal.

[0047] In some implementations, the controller 110 generates a control signal based on the structure of multiple segment units included in the segment unit circuit 120. When the structure of the multiple segment units is configured to convert an input including only a binary code into an analog output, the controller 110 can turn on or off multiple corresponding segment units according to the value of each bit included in the digital input. For example, when the value of the highest bit included in the digital input is a first value, the controller 110 can generate a control signal for controlling the segment unit corresponding to the highest bit to turn off. As another example, when the value of the highest bit included in the digital input is a second value, the controller 110 can generate a control signal for controlling the segment unit corresponding to the highest bit to turn on. The following is explained by taking the first value as 0 and the second value as 1 as an example, but is not limited to this. For example, in some implementations, the first value is 1 and the second value is 0.

[0048] In some implementations, the controller 110 includes a decoder 111. The decoder 111 may generate a decoded input by decoding bits included in a selected bit group among a plurality of bit groups included in the digital input (eg, by a thermometer code).

[0049] For example, among the plurality of bit groups, the bit group to be decoded by the decoder 111 using the thermometer code may be selected based on a structure (described below) including a plurality of segment units included in the segment unit circuit 120. For example, when at least a portion of the structure of the plurality of segment units is configured to convert an input including a thermometer code into an analog output, the decoder 111 may generate a decoded input by decoding a digital input bit corresponding to the segment unit. The segment unit is configured to convert an input including a thermometer code into an analog output using the thermometer code.

[0050] As an example, when the plurality of bit groups are 2 bit groups, the decoder 111 may decode the bits included in the first bit group by a thermometer code according to the structure of the plurality of segment units to generate a decoded input. As another example, according to the structure of the plurality of segment units, the decoder 111 may decode the bits included in the first bit group by a thermometer code, and decode the bits included in the second bit group by a thermometer code to generate a decoded input. The generation of the decoded input may be flexibly performed according to various processes. For example, the decoder 111 may not decode all the bits included in the 2 bit groups (e.g., according to the structure of the plurality of segment units).

[0051] As another example, when the plurality of bit groups are 3 bit groups, the decoder 111 may decode the bits included in the first bit group by a thermometer code according to the structure of the plurality of segment units to generate a decoded input. As another example, according to the structure of the plurality of segment units, the decoder 111 may decode the bits included in the first bit group by a thermometer code, and decode the bits included in the second bit group by a thermometer code to generate a decoded input. As another example, according to the structure of the plurality of segment units, the decoder 111 may decode the bits included in the first bit group by a thermometer code, additionally decode the bits included in the second bit group by a thermometer code, and additionally decode the bits included in the third bit group by a thermometer code to generate a decoded input. As described above, in some implementations, the decoder 111 may not decode all the bits included in the 3 bit groups (e.g., according to the structure of the plurality of segment units).

[0052] In some implementations, the controller 110 generates a control signal based on the decoded input generated by the decoder 111. When the structure of the plurality of segment units is configured to convert an input including a binary code and a thermometer code into an analog output, the controller 110 may turn on or off the plurality of corresponding segment units according to the value of each bit included in the decoded input. When the structure of the plurality of segment units is configured to convert an input including only a thermometer code into an analog output, the controller 110 may turn on or off the plurality of corresponding segment units according to the value of each bit included in the decoded input.

[0053] In some implementations, the segment unit circuit 120 includes a plurality of segment units that are turned on or off based on a control signal generated by the controller 110. The plurality of segment units may be formed in a structure corresponding to a plurality of bit groups included in the digital input.

[0054] For example, when the plurality of bit groups included in the digital input is 2 bit groups, the plurality of segment units may include a plurality of first segment units, a plurality of second segment units, and an additional segment unit.

[0055] Each of the plurality of first segmentation units may generate an output corresponding to a corresponding bit among bits included in the first bit group of the digital input or decoded input. In this case, when the decoder 111 does not generate a decoded input, each of the plurality of first segmentation units may generate an output corresponding to each bit included in the first bit group of the digital input. On the other hand, when the decoder 111 generates a decoded input, each of the plurality of first segmentation units may generate an output corresponding to a corresponding bit among bits included in the first bit group of the decoded input.

[0056] Each of the plurality of first segment units may generate an output current according to the value of a corresponding bit included in the first bit group of the digital input or decoded input corresponding thereto. For example, each of the plurality of first segment units may generate an output current when the value of a corresponding bit included in the first bit group of the digital input or decoded input corresponding thereto is a second value. In this case, the magnitude of the output current (e.g., the total output current) generated by the plurality of first segment units may be proportional to the magnitude of the bit included in the first bit group of the digital input or decoded input corresponding thereto. On the other hand, each of the plurality of first segment units may not generate an output current when the value of a corresponding bit included in the first bit group of the digital input or decoded input corresponding thereto is a first value.

[0057] Each of the plurality of second segmentation units may generate an output corresponding to a corresponding bit included in the bits in the second bit group of the digital input or the decoded input. When the decoder 111 does not generate the decoded input, each of the plurality of second segmentation units may generate an output corresponding to a corresponding bit in the bits included in the second bit group of the digital input. On the other hand, when the decoder 111 generates the decoded input, each of the plurality of second segmentation units may generate an output corresponding to a corresponding bit in the bits included in the second bit group of the decoded input.

[0058] Each of the plurality of second segment units may generate an output current according to the value of a corresponding bit included in the second bit group of the digital input or decoded input, and the method of generating the output current may be the same as the method of generating the output current by the plurality of first segment units described above.

[0059] The additional segmentation unit may generate an output corresponding to a lowest bit among bits included in a second bit group of the digital input or the decoded input.

[0060] In some implementations, when the highest bit of the digital input is converted from the first value to the second value and all other bits of the digital input except the highest bit are converted from the second value to the first value, the additional segment unit is turned on based on the control signal received from the controller 110. For example, when the highest bit of the digital input is converted from the first value to the second value and all other bits of the digital input except the highest bit are converted from the second value to the first value, the controller 110 may generate a control signal to turn on the additional segment unit. In this way, since the additional segment unit is turned on when all other bits of the digital input except the highest bit are converted from the second value to the first value, all the plurality of second segment units may be maintained in the on state without being turned off. In this way, by using the additional segment unit, the DAC 100 according to some implementations may reduce errors occurring when the plurality of second segment units are converted from the on state to the off state, thereby improving the linearity and dynamic region performance when the magnitude of the digital input is small.

[0061] The following will refer to FIG. 3A to FIG. 4C An example of the operation of the additional segmentation unit is described below.

[0062] As another example, when the plurality of bit groups included in the digital input is 3 bit groups, the plurality of segment units may include a plurality of first segment units, a plurality of second segment units, and an additional segment unit.

[0063] In this case, operations of the plurality of first segment units and the plurality of second segment units may be the same as those of the plurality of first segment units and the plurality of second segment units in the case where the plurality of bit groups included in the above-mentioned digital input is 2 bit groups.

[0064] Each of the plurality of third segmentation units may generate an output corresponding to a corresponding bit among bits included in a third bit group of the digital input or decoded input. When the decoder 111 does not generate a decoded input, each of the plurality of third segmentation units may generate an output corresponding to a corresponding bit among bits included in the third bit group of the digital input. On the other hand, when the decoder 111 generates a decoded input, each of the plurality of third segmentation units may generate an output corresponding to a corresponding bit among bits included in the third bit group of the decoded input.

[0065] Each of the multiple third segment units can generate an output current according to the value of the corresponding bit included in the third bit group of the digital input or decoded input corresponding to it, and the method of generating the output current can be the same as the method of generating the output current by the above-mentioned multiple first segment units.

[0066] The additional segmentation unit may generate an output corresponding to a lowest bit among bits included in a second bit group of the digital input or the decoded input.

[0067] In some implementations, when the highest bit of the digital input is converted from the first value to the second value and all bits included in the second bit group of the digital input are converted from the second value to the first value, the additional segment unit can be turned on based on the control signal received from the controller 110. For example, when the highest bit of the digital input is converted from the first value to the second value and all bits included in the second bit group of the digital input are converted from the second value to the first value, the controller 110 can generate a control signal to turn on the additional segment unit. In this way, since the additional segment unit is turned on when all other bits except the highest bit of the digital input are converted from the second value to the first value, all the second segment units can be maintained in the on state without being turned off. In this way, by using the additional segment unit, the DAC 100 according to some implementations can reduce errors that occur when the plurality of second segment units are converted from the on state to the off state, thereby improving the linearity and dynamic area performance when the magnitude of the digital input is small.

[0068] The following will refer to FIG. 5A to FIG. 6C Another operation example of the additional segmentation unit is described in more detail.

[0069] In some implementations, when (i) the highest bit of the digital input is converted from the first value to the second value, (ii) all bits included in the second bit group of the digital input are converted from the second value to the first value, and (iii) a preset reference number or more of bits included in the third bit group of the digital input are converted from the second value to the first value, the additional segment unit may be turned on based on a control signal received from the controller 110. For example, when (i) the highest bit of the digital input is converted from the first value to the second value, (ii) all bits included in the second bit group of the digital input are converted from the second value to the first value, and (iii) a preset reference number (e.g., 3) or more of bits included in the third bit group of the digital input are converted from the second value to the first value, the controller 110 may generate a control signal to turn on the additional segment unit.

[0070] The reference number may be set to an appropriate number to reduce the degree of error that occurs when a plurality of segment units are switched from an on state to an off state.

[0071] In some implementations, the segment unit circuit 120 generates an analog output based on the outputs of the plurality of segment units. The segment unit circuit 120 may generate an analog output of corresponding magnitude by summing the outputs of the plurality of segment units. For example, the segment unit circuit 120 may sum the output currents of the plurality of segment units and generate a voltage corresponding to the summed output current as an analog output.

[0072] The detection circuit 130 may determine whether the digital input meets the reference condition, and determine whether to use the additional segment unit based on the determination result. For example, the detection circuit 130 may receive the digital input. The detection circuit 130 may determine whether the received digital input meets the reference condition.

[0073] The reference condition can be set based on whether the linearity and dynamic range performance are significantly degraded in the process of converting digital input to analog output when no additional segmentation unit is used, and can be based on the range of the digital input, the resolution of the digital input signal, etc.

[0074] In some implementations, the reference condition includes whether the range of the digital input is less than or equal to a preset reference size. For example, the reference size can be set to -19dBFs. In this case, when the range of the digital input is less than or equal to the reference size, the detection circuit 130 determines that the digital input meets the reference condition.

[0075] When it is determined that the digital input meets the reference condition, the detection circuit 130 may determine to use the additional segment unit. On the other hand, when it is determined that the digital input does not meet the reference condition, the detection circuit 130 may determine not to use the additional segment unit.

[0076] The controller 110 may generate a control signal based on the determination result of the detection circuit 130. For example, when the detection circuit 130 determines to use the additional segment unit, the controller 110 may control the segment unit circuit 120 to use the additional segment unit to generate the analog output. On the other hand, when the detection circuit 130 determines not to use the additional segment unit, the controller 110 may control the segment unit circuit 120 not to use the additional segment unit to generate the analog output.

[0077] By using the detection circuit 130 , additional segment cells may be used when they may be used to improve the performance of the DAC 100 .

[0078] Figure 3A is a circuit diagram showing an example of a segment unit circuit in which the digital input of a DAC is divided into two bit groups. Figure 3B is shown with Figure 3A A diagram of the structure of multiple segment units corresponding to the segment unit circuit. Figure 3C is shown with Figure 3A FIG. 1 is a table showing an example of a structure of a segment unit circuit in which a digital input of a DAC corresponds to the state of multiple segment units.

[0079] exist FIG. 3A to FIG. 3C In the configuration shown, the digital input may include 9 bits. In this case, the digital input may be divided into two bit groups, the first bit group may include the 9 bits including the bit at position 2. 8 The highest position including the 3 high positions (located at 2 8 Location, 2 7 Position and 2 6 Position), and the second bit group may include the other 6 low bits (positioned at 2 5 Location, 2 4 Location, 2 3 Location, 2 2 Location, 2 1 Position and 2 0 Likewise, the digital input may not be decoded by the decoder 111.

[0080] Reference Figure 3A , the segment unit circuit 120 includes a first segment unit circuit SCC1 , a second segment unit circuit SCC2 , and an additional segment unit circuit ASCC.

[0081] The first segment unit circuit SCC1 may include a plurality of first segment units, and Figure 3A In the example of FIG. 5 , the plurality of first segment units may be first to third upper cells UBC1 to UBC3 .

[0082] The second segment unit circuit SCC2 may include a plurality of second segment units, and Figure 3A In the example of FIG. 5 , the plurality of second segment units may be first to sixth lower bit cells LBC1 to LBC6 .

[0083] The additional segment cell circuit ASCC may include an additional segment cell, and Figure 3A In the example of , the additional segment unit may be an additional bit unit ABC.

[0084] Each of the first to third upper bit cells UBC1 to UBC3 , the first to sixth lower bit cells LBC1 to LBC6 , and the additional bit cells ABC may include a switch SW and a current source.

[0085] The switch SW included in each of the first upper unit UBC1 to the third upper unit UBC3, the first lower unit LBC1 to the sixth lower unit LBC6, and the additional unit ABC can be turned on or off by the control signal Control generated by the controller 110. For example, when the switch SW is turned on, the voltage connected between the switch SW and the operating voltage terminal V DD The current source between the switch SW and the working voltage terminal V can output the current to the output node Out. On the other hand, when the switch SW is turned off, the current source between the switch SW and the working voltage terminal V DD The current source between will not output current to the output node Out.

[0086] The current sources included in the first to third upper bit cells UBC1 to UBC3 and the first to sixth lower bit cells LBC1 to LBC6 may output a current corresponding to the size of a value represented by 9 bits included in the digital input.

[0087] exist Figure 3A In the example of FIG. 1 , the first upper bit unit UBC1 may correspond to the highest bit among the 9 bits included in the digital input, and may output the same bit as 2 8 =256 (ie, the size of the highest bit) corresponding to the current of 256I (where I is the reference current). The second upper unit UBC2 and the third upper unit UBC3 can correspond to the 2 at the digital input, respectively. 7 Position and 2 6 The bits at the positions can output currents of 128I and 64I corresponding thereto respectively.

[0088] Similarly, the first low-bit unit LBC1 to the sixth low-bit unit LBC6 may correspond to the 2 bits at the digital input, respectively. 5 Position to 2 0 The bits at the positions can output currents of 32I, 16I, 8I, 4I, 2I, and I corresponding thereto respectively.

[0089] The additional bit unit ABC can generate an output corresponding to the lowest bit among the bits included in the second bit group. Figure 3A In the example of FIG. 1 , the additional bit unit ABC may output 2 bits which are located as the lowest bits among the bits included in the second bit group. 0 The current I corresponding to the bit at the position.

[0090] The output node Out may output a voltage corresponding to the resistance R and an output current corresponding to the sum of currents output through the first to third upper bit cells UBC1 to UBC3 , the first to sixth lower bit cells LBC1 to LBC6 , and the additional bit cell ABC.

[0091] Reference Figure 3B , showing the Figure 3A The structure of the plurality of segment units corresponding to the segment unit circuit 120 of the embodiment of the present invention. The plurality of segment units may include first to third upper bit cells UBC1 to UBC3, first to sixth lower bit cells LBC1 to LBC6, and additional bit cells ABC. In this case, each of the first to third upper bit cells UBC1 to UBC3 and the first to sixth lower bit cells LBC1 to LBC6 has a size proportional to the size of the bit included in the digital input corresponding thereto.

[0092] exist Figure 3B In the example of FIG. 1 , the size of the first upper cell UBC1 may be twice the size of the second upper cell UBC2 . The size may decrease from the second upper cell UBC2 toward the sixth lower cell LBC6 , and the size may decrease by half each time the cell is lowered.

[0093] Since the additional bit cell ABC generates an output corresponding to the lowest bit among bits included in the second bit group, the additional bit cell ABC may have the same size as the sixth lower bit cell LBC6 corresponding to the lowest bit among bits included in the second bit group.

[0094] Reference Figure 3C , which shows that when the first digital input and the second digital input are continuously input to the DAC 100, Figure 3A The states of the plurality of segment units of the structure of the segment unit circuit 120. Each of the first digital input and the second digital input may include an upper bit UB and a lower bit LB.

[0095] exist Figure 3CIn the table, the digital input represented by the binary code is listed in the binary column of the table, the states of the first upper unit UBC1 to the third upper unit UBC3 are listed in numerical order in the UBCs column of the table, the states of the first lower unit LBC1 to the sixth lower unit LBC6 are listed in numerical order in the LBCs column of the table, and the state of the additional bit unit ABC is listed in the ABC column of the table. In this case, the state of the segment unit can be represented as 1 in the on state and represented as 0 in the off state.

[0096] First, when the first digital input DI1 represented by a binary code of "011111111" is input to the DAC 100, the controller 110 can generate a control signal based on the first digital input DI1. In this case, the first to third upper bit cells UBC1 to UBC3, the first to sixth lower bit cells LBC1 to LBC6, and the additional bit cells ABC can be turned on or off based on the control signal. Figure 3C In the example, the first upper bit cell UBC1 may be turned off, the second and third upper bit cells UBC2 and UBC3 and the first to sixth lower bit cells LBC1 to LBC6 may be turned on, and the additional bit cell ABC may be turned off.

[0097] When the second digital input DI2 represented as “100000000” in binary code is input to the DAC 100 after the first digital input D11 is input, the controller 110 may generate a control signal based on the second digital input D12.

[0098] In this case, when the additional bit cell ABC is not used, the first upper bit cell UBC1 should be changed from the off state to the on state, and the second upper bit cell UBC2 and the third upper bit cell UBC3 and the first to sixth lower bit cells LBC1 to LBC6 should be changed from the on state to the off state. Thus, when the states of a plurality of segment cells are changed at the same time, the possibility of an error occurring in the process of changing the cell states may be increased.

[0099] Since DAC 100 uses the additional bit cell ABC, Figure 3CIn the case shown, the highest bit of the digital input is converted from the first value to the second value, and all other bits of the digital input except the highest bit are converted from the second value to the first value, so the controller 110 can generate a control signal to turn on the additional bit unit ABC. Therefore, the states of the first upper bit unit UBC1 to the third upper bit unit UBC3 and the first lower bit unit LBC1 to the sixth lower bit unit LBC6 may not be changed, and only the additional bit unit ABC may be changed from the off state to the on state. In this way, by changing only the states of a relatively small number of segment units, the DAC 100 can reduce the possibility of errors occurring in the process of changing the unit state. Therefore, the linearity and dynamic range performance of the DAC 100 can be improved.

[0100] Figure 4A is a circuit diagram illustrating an example of a segment unit circuit that divides the digital input of a DAC into two bit groups and decodes the upper bit by a thermometer code according to some implementations. Figure 4B is shown with Figure 4A A diagram of the structure of multiple segment units corresponding to the segment unit circuit. Figure 4C is shown with Figure 4A A table of examples of the states of multiple segment units corresponding to the digital inputs of a DAC of a segment unit circuit structure.

[0101] FIG. 4A to FIG. 4C The structure and operation of the circuit shown in FIG. 3A to FIG. 3C The structure and operation of the circuits shown in are similar except for the differences discussed or implied herein. FIG. 4A to FIG. 4C In some implementations of the present invention, the bits included in the first bit group of the digital input can be decoded by the decoder 111. The 3 bits included in the first bit group of the digital input can be decoded into 7 bits represented by thermometer code. Accordingly, the decoder 111 can generate a decoded input including 7 high bits represented by thermometer code and 6 low bits represented by binary code. In this case, all 7 high bits represented by thermometer code in the decoded input can have the same size, and the 6 low bits in the decoded input can be the same as the low bits of the digital input.

[0102] Reference Figure 4A , the segment unit circuit 120 includes a first segment unit circuit SCC1 , a second segment unit circuit SCC2 , and an additional segment unit circuit ASCC.

[0103] The first segment unit circuit SCC1 may include a plurality of first segment units, and Figure 4A In the example of FIG. 5 , the plurality of first segment units may be a first upper unit UBC1 to a seventh upper unit UBC7 .

[0104] The second segment unit circuit SCC2 may include a plurality of second segment units, and Figure 4A In the example of FIG. 5 , the plurality of second segment units may be first to sixth lower bit cells LBC1 to LBC6 .

[0105] The additional segment cell circuit ASCC may include an additional segment cell, and Figure 4A In the example of , the additional segment unit may be an additional bit unit ABC.

[0106] Each of the first upper bit unit UBC1 to the seventh upper bit unit UBC7, the first lower bit unit LBC1 to the sixth lower bit unit LBC6, and the additional bit unit ABC may include a switch SW and a current source, and the state of the switch SW changes according to the control signal Control and whether the current source outputs current to the output node Out may be the same as the above reference Figure 3A Same as described.

[0107] Current sources included in the first to seventh upper bit cells UBC1 to UBC7 and the first to sixth lower bit cells LBC1 to LBC6 may output a current corresponding to the size of a value represented by 13 bits included in the decoded input.

[0108] exist Figure 4A In the example of FIG. 1 , the first upper unit UBC1 to the seventh upper unit UBC7 may respectively correspond to 7 upper bits among the 13 bits included in the decoded input, and may output a size 2 of the 7 upper bits. 6 =64 corresponds to a current of 64I.

[0109] Similarly, the first low-order unit LBC1 to the sixth low-order unit LBC6 may correspond to the 2 5 Position to 2 0 The bits at the positions can output currents of 32I, 16I, 8I, 4I, 2I and I corresponding thereto respectively.

[0110] The additional bit unit ABC may generate an output corresponding to the lowest bit among the bits included in the second bit group. Figure 4A In the case of the above, the additional bit unit ABC may output the 2 bits included in the second bit group as the lowest bit. 0 The current I corresponding to the bit at the position.

[0111] The output node Out may output a voltage corresponding to the resistance R and an output current corresponding to the sum of currents output through the first to seventh upper bit cells UBC1 to UBC7 , the first to sixth lower bit cells LBC1 to LBC6 , and the additional bit cell ABC.

[0112] Reference Figure 4B , showing the Figure 4A The structure of the plurality of segment units corresponding to the segment unit circuit 120 of the embodiment of the present invention. The plurality of segment units may include a first upper unit UBC1 to a seventh upper unit UBC7, a first lower unit LBC1 to a sixth lower unit LBC6, and an additional bit unit ABC. In this case, each of the first upper unit UBC1 to the seventh upper unit UBC7 and the first lower unit LBC1 to the sixth lower unit LBC6 may have a size proportional to the size of the bit included in the decoded input corresponding thereto.

[0113] exist Figure 4B In the example of FIG. 1 , the first upper unit UBC1 to the seventh upper unit UBC7 all have the same size. The size of the seventh upper unit UBC7 may be twice the size of the first lower unit LBC1. The size may decrease from the first lower unit LBC1 toward the sixth lower unit LBC6, and the size may decrease by half for each level down.

[0114] Since the additional bit cell ABC generates an output corresponding to the lowest bit among bits included in the second bit group, the additional bit cell ABC may have the same size as the sixth lower bit cell LBC6 corresponding to the lowest bit among bits included in the second bit group.

[0115] Reference Figure 4C , which shows that when the first digital input and the second digital input are continuously input to the DAC 100, Figure 4A The states of the plurality of segment units of the structure of the segment unit circuit 120. Each of the first digital input and the second digital input may include an upper bit UB and a lower bit LB.

[0116] exist Figure 4C In the table, the decoded input represented by the thermometer code and the binary code is listed in the (thermometer+binary) column of the table, the states of the first upper unit UBC1 to the seventh upper unit UBC7 are listed in numerical order in the UBCs column of the table, the states of the first lower unit LBC1 to the sixth lower unit LBC6 are listed in numerical order in the LBCs column of the table, and the state of the additional bit unit ABC is listed in the ABC column of the table. In this case, the state of the segment unit can be represented as 1 in the on state and as 0 in the off state.

[0117] First, when the first digital input DI1 represented as “011111111” in binary code is input to the DAC 100 , the controller 110 may decode the first digital input DI1 to generate a first decoded input represented as “000111111111” in thermometer code and binary code.

[0118] The controller 110 may generate a control signal based on the first decoded input. In this case, the first to seventh upper bit cells UBC1 to UBC7, the first to sixth lower bit cells LBC1 to LBC6, and the additional bit cells ABC may be turned on or off based on the control signal. Figure 4C In the example, the first to fourth upper cells UBC1 to UBC4 may be turned off, the fifth to seventh upper cells UBC5 to UBC7 and the first to sixth lower cells LBC1 to LBC6 may be turned on, and the additional bit cell ABC may be turned off.

[0119] When the second digital input DI2 represented by binary code as “100000000” is input to the DAC 100 after the first digital input DI1 is input, the decoder 111 may decode the second digital input DI2 to generate a second decoded input represented by thermometer code and binary code as “0001111000000”.

[0120] The controller 110 may generate a control signal based on the second decoded input.

[0121] In this case, when the additional bit cell ABC is not used, the first to sixth lower bit cells LBC1 to LBC6 should be changed from the on state to the off state. Thus, when the states of multiple segment cells are changed simultaneously, the possibility of errors occurring in the process of changing the cell states may increase.

[0122] Since DAC 100 uses the additional bit cell ABC, Figure 4C In the case shown, the highest bit of the digital input is converted from the first value to the second value, and all other bits of the digital input except the highest bit are converted from the second value to the first value, so the controller 110 can generate a control signal to turn on the additional bit unit ABC. Accordingly, the states of the first upper bit unit UBC1 to the seventh upper bit unit UBC7 and the first lower bit unit LBC1 to the sixth lower bit unit LBC6 may not be changed, and only the additional bit unit ABC may be changed from the off state to the on state. In this way, by changing the states of only a relatively small number of segment units, the DAC 100 can reduce the possibility of errors occurring in the process of changing the unit state. Therefore, the linearity and dynamic range performance of the DAC 100 can be improved.

[0123] Figure 5A is a circuit diagram illustrating an example of a segment unit circuit that divides the digital input of a DAC into three bit groups and decodes the upper bits by a thermometer code according to some implementations. Figure 5B is shown with Figure 5AA diagram of the structure of multiple segment units corresponding to the segment unit circuit. Figure 5C is shown with Figure 5A A table of examples of the states of multiple segment units corresponding to the digital inputs of a DAC of a segment unit circuit structure.

[0124] exist FIG. 5A to FIG. 5C In the example shown, the digital input includes 12 bits. In this case, the digital input can be divided into three bit groups. The first bit group can include the 12 bits including the bit at 2 11 The 3 highest bits of the highest bit at position (located at 2 11 Position, 2 10 Position and 2 9 The second bit group may include 3 middle bits (located at 2 8 Position, 2 7 Position and 2 6 Position), the 3 middle positions include the 8 The third bit group may include the other 6 low bits (positions at 2 5 Position, 2 4 Position, 2 3 Position, 2 2 Position, 2 1 Position and 2 0 In addition, the bits included in the first bit group of the digital input may be decoded by the decoder 111. In some implementations, such as FIG. 5A to FIG. 5C As shown, the 3 bits included in the first bit group of the digital input can be decoded into 7 bits represented by the thermometer code. Accordingly, the decoder 111 can generate a decoded input including 7 high bits represented by the thermometer code and 3 middle bits and 6 low bits represented by the binary code. In this case, all 7 high bits represented by the thermometer code in the decoded input can have the same size, and the 3 middle bits and 6 low bits of the decoded input can be the same as the 3 middle bits and 6 low bits of the digital input.

[0125] Reference Figure 5A The segment unit circuit 120 includes a first segment unit circuit SCC1, a second segment unit circuit SCC2, a third segment unit circuit SCC3, and an additional segment unit circuit ASCC.

[0126] The first segment unit circuit SCC1 may include a plurality of first segment units, and Figure 5A In the example of FIG. 5 , the plurality of first segment units may be a first upper unit UBC1 to a seventh upper unit UBC7 .

[0127] The second segment unit circuit SCC2 may include a plurality of second segment units, and Figure 5A In the example of , the plurality of second segment units may be first to third middle bit units MBC1 to MBC3.

[0128] The third segment unit circuit SCC3 may include a plurality of third segment units, and Figure 5A In the example of FIG. 5 , the plurality of third segment units may be first to sixth lower bit cells LBC1 to LBC6 .

[0129] The additional segment cell circuit ASCC may include an additional segment cell, and Figure 5A In the example of , the additional segment unit may be an additional bit unit ABC.

[0130] Each of the first upper bit cell UBC1 to the seventh upper bit cell UBC7, the first middle bit cell MBC1 to the third middle bit cell MBC3, the first lower bit cell LBC1 to the sixth lower bit cell LBC6, and the additional bit cell ABC may include a switch SW and a current source, and the state of the switch SW changes according to the control signal Control and whether the current source outputs current to the output node Out may be the same as the above reference Figure 3A Same as described.

[0131] Current sources included in first to seventh upper bit cells UBC1 to UBC7 , first to third middle bit cells MBC1 to MBC3 , and first to sixth lower bit cells LBC1 to LBC6 may output current corresponding to the magnitude of a value represented by 16 bits included in the decoded input.

[0132] exist Figure 5A In the example of FIG. 1 , the first upper unit UBC1 to the seventh upper unit UBC7 may respectively correspond to 7 upper bits among the 16 bits included in the decoded input, and may output a size 2 of the 7 upper bits. 9 =512 corresponds to the current of 512I.

[0133] Similarly, the first intermediate bit unit MBC1 to the third intermediate bit unit MBC3 may correspond to the 2 8 Position to 2 6 The bits at the positions can output currents of 256I, 128I and 64I corresponding thereto respectively.

[0134] Similarly, the first low-order unit LBC1 to the sixth low-order unit LBC6 may correspond to the 2 5 Position to 2 0The bits at the positions can output currents of 32I, 16I, 8I, 4I, 2I and I corresponding thereto respectively.

[0135] The additional bit unit ABC may generate an output corresponding to the lowest bit among the bits included in the second bit group. Figure 5A In this case, the additional bit cell ABC can output the same 6 The current of 64I corresponding to the bit at the position (the bit is the lowest bit among the bits included in the second bit group).

[0136] The output node Out can output a voltage corresponding to the resistance R, and an output current corresponding to the sum of currents output through the first upper bit cell UBC1 to the seventh upper bit cell UBC7, the first middle bit cell MBC1 to the third middle bit cell MBC3, the first lower bit cell LBC1 to the sixth lower bit cell LBC6, and the additional bit cell ABC.

[0137] Reference Figure 5B , showing the Figure 5A The structure of multiple segment units corresponding to the segment unit circuit 120 of the embodiment of the present invention. The multiple segment units include a first upper unit UBC1 to a seventh upper unit UBC7, a first middle unit MBC1 to a third middle unit MBC3, a first low unit LBC1 to a sixth low unit LBC6, and an additional bit unit ABC. In this case, each of the first upper unit UBC1 to the seventh upper unit UBC7 and the first middle unit MBC1 to the third middle unit MBC3 has a size proportional to the size of the bit included in the decoded input corresponding thereto. It is shown that the total size of the first low unit LBC to the sixth low unit LBC is equal to the size of the third middle unit MBC3; however, in some implementations, the total size may be smaller than the size of the third middle unit MBC3.

[0138] exist Figure 5B In the example of , the first upper bit unit UBC1 to the seventh upper bit unit UBC7 all have the same size. The size of the seventh upper bit unit UBC7 is twice the size of the first middle bit unit MBC1. The size can be reduced from the first middle bit unit MBC1 toward the third middle bit unit MBC3, and the size can be reduced by half for each level down.

[0139] Since the additional bit cell ABC generates an output corresponding to the lowest bit among the bits included in the second bit group, the additional bit cell ABC may have the same size as the third middle bit cell MBC3 corresponding to the lowest bit among the bits included in the second bit group.

[0140] Reference Figure 5C, which shows that when the first digital input and the second digital input are continuously input to the DAC 100, Figure 5A The state of the plurality of segment units of the structure of the segment unit circuit 120. Each of the first digital input and the second digital input may include an upper bit UB, a middle bit MB, and a lower bit LB.

[0141] exist Figure 5C In the table, the decoded input represented by the thermometer code and the binary code is listed in the (thermometer+binary) column of the table, the states of the first upper bit cell UBC1 to the seventh upper bit cell UBC7 are listed in numerical order in the UBCs column of the table, the states of the first middle bit cell MBC1 to the third middle bit cell MBC3 are listed in numerical order in the MBCs column of the table, the states of the first lower bit cell LBC1 to the sixth lower bit cell LBC6 are listed in numerical order in the LBCs column of the table, and the states of the additional bit cell ABC are listed in the ABC column of the table. In this case, the state of the segment unit can be represented as 1 in the on state and as 0 in the off state.

[0142] First, when the first digital input DI1 represented by “011111111111” in binary code is input to the DAC 100, the controller 110 may decode the first digital input DI1 to generate a first decoded input represented by “000111111111111” in thermometer code and binary code.

[0143] The controller 110 may generate a control signal based on the first decoded input. In this case, the first upper bit unit UBC1 to the seventh upper bit unit UBC7, the first middle bit unit MBC1 to the third middle bit unit MBC3, the first lower bit unit LBC1 to the sixth lower bit unit LBC6, and the additional bit unit ABC may be turned on or off based on the control signal. Figure 5C In the example, the first to fourth upper cells UBC1 to UBC4 can be turned off, the fifth to seventh upper cells UBC5 to UBC7, the first to third middle cells MBC1 to MBC3, and the first to sixth lower cells LBC1 to LBC6 can be turned on, and the additional bit cell ABC can be turned off.

[0144] After the first digital input DI1 is input, when the second digital input DI2 represented by binary code as “100000000000” is input to the DAC 100 , the decoder 111 may decode the second digital input DI2 to generate a second decoded input represented by thermometer code and binary code as “0001111000000000”.

[0145] The controller 110 may generate a control signal based on the second decoded input.

[0146] In this case, when the additional bit cell ABC is not used, the first to third middle bit cells MBC1 to MBC3 and the first to sixth lower bit cells LBC1 to LBC6 should be changed from the on state to the off state. Thus, when the states of a plurality of segment cells are changed at the same time, the possibility of an error occurring in the process of changing the cell states may be increased.

[0147] Since DAC 100 uses the additional bit cell ABC, Figure 5C In the case shown, the highest bit of the digital input is converted from the first value to the second value, and all bits included in the second bit group of the digital input are converted from the second value to the first value, so the controller 110 can generate a control signal to turn on the additional bit unit ABC. Accordingly, the states of the first upper bit unit UBC1 to the seventh upper bit unit UBC7 and the first middle bit unit MBC1 to the third middle bit unit MBC3 may not be changed, the first lower bit unit LBC1 to the sixth lower bit unit LBC6 may be changed from the on state to the off state, and the additional bit unit ABC may be changed from the off state to the on state. In this way, by changing only the states of a relatively small number of segment units, the DAC 100 can reduce the possibility of errors occurring in the process of changing the unit state. Therefore, the linearity and dynamic range performance of the DAC 100 can be improved.

[0148] Fig. 6A is a circuit diagram illustrating an example of a segment unit circuit that divides the digital input of a DAC into 3-bit groups and decodes the upper and middle bits with a thermometer code according to some implementations. Figure 6B is shown with Fig. 6A A diagram of the structure of multiple segment units corresponding to the segment unit circuit. Figure 6C is shown with Fig. 6A A table of examples of the states of multiple segment units corresponding to the digital inputs of a DAC of a segment unit circuit structure.

[0149] FIG. 6A to FIG. 6C The example shown in can have FIG. 5A to FIG. 5CUnless otherwise specified or implied, the decoder 111 may be similar to the structures and operations described in . In this example, the bits included in the first bit group of the digital input may be decoded by the decoder 111, and the 3 bits included in the second bit group of the digital input may be decoded into 7 bits represented by thermometer code. Accordingly, the decoder 111 may generate a decoded input including 7 high bits and 7 middle bits represented by thermometer code and 6 low bits represented by binary code. In this case, all 7 high bits represented by thermometer code in the decoded input may have the same size, all 7 middle bits represented by thermometer code may have the same size, and the 6 low bits of the decoded input may be the same as the 6 low bits of the digital input.

[0150] Reference Fig. 6A The segment unit circuit 120 includes a first segment unit circuit SCC1, a second segment unit circuit SCC2, a third segment unit circuit SCC3, and an additional segment unit circuit ASCC.

[0151] The first segment unit circuit SCC1 may include a plurality of first segment units, and Fig. 6A In the example of FIG. 5 , the plurality of first segment units may be a first upper unit UBC1 to a seventh upper unit UBC7 .

[0152] The second segment unit circuit SCC2 may include a plurality of second segment units, and Fig. 6A In the example of , the plurality of second segment units may be the first middle bit unit MBC1 to the seventh middle bit unit MBC7.

[0153] The third segment unit circuit SCC3 may include a plurality of third segment units, and Fig. 6A In the example of FIG. 5 , the plurality of third segment units may be first to sixth lower bit cells LBC1 to LBC6 .

[0154] The additional segment cell circuit ASCC may include an additional segment cell, and Fig. 6A In the example of , the additional segment unit may be an additional bit unit ABC.

[0155] Each of the first upper bit cell UBC1 to the seventh upper bit cell UBC7, the first middle bit cell MBC1 to the seventh middle bit cell MBC7, the first lower bit cell LBC1 to the sixth lower bit cell LBC6, and the additional bit cell ABC may include a switch SW and a current source, and the state of the switch SW changes according to the control signal Control and whether the current source outputs current to the output node Out may be the same as the above reference Figure 3A Same as described.

[0156] Current sources included in first to seventh upper bit cells UBC1 to UBC7 , first to seventh middle bit cells MBC1 to MBC7 , and first to sixth lower bit cells LBC1 to LBC6 may output current corresponding to the magnitude of a value represented by 20 bits included in the decoded input.

[0157] exist Fig. 6A In the example of FIG. 1 , the first upper unit UBC1 to the seventh upper unit UBC7 may respectively correspond to 7 upper bits among 20 bits included in the decoded input, and may output a size 2 of the 7 upper bits. 9 =512 corresponds to the current of 512I.

[0158] Likewise, the first to seventh middle bit units MBC1 to MBC7 may correspond to 7 middle bits among the 20 bits included in the decoded input, respectively, and may output a value equal to 2 of the size of the 7 middle bits. 6 =64 corresponds to a current of 64I.

[0159] Similarly, the first low-order unit LBC1 to the sixth low-order unit LBC6 may correspond to the 2 5 Position to 2 0 The bits at the positions can output currents of 32I, 16I, 8I, 4I, 2I and I corresponding thereto respectively.

[0160] The additional bit unit ABC may generate an output corresponding to the lowest bit among the bits included in the second bit group. Fig. 6A In the example, the additional bit cell ABC can output the same 6 The bit at the position corresponds to a current of 64I, which is the lowest bit among the bits included in the second bit group.

[0161] The output node Out can output a voltage corresponding to the resistance R, and an output current corresponding to the sum of currents output through the first upper bit cell UBC1 to the seventh upper bit cell UBC7, the first middle bit cell MBC1 to the seventh middle bit cell MBC7, the first lower bit cell LBC1 to the sixth lower bit cell LBC6, and the additional bit cell ABC.

[0162] Reference Figure 6B , showing the Fig. 6AThe structure of multiple segment units corresponding to the segment unit circuit 120 of the embodiment of the present invention. The multiple segment units may include a first upper unit UBC1 to a seventh upper unit UBC7, a first middle unit MBC1 to a seventh middle unit MBC7, a first low unit LBC1 to a sixth low unit LBC6, and an additional bit unit ABC. In this case, each of the first upper unit UBC1 to the seventh upper unit UBC7 and the first middle unit MBC1 to the seventh middle unit MBC7 may have a size proportional to the size of the bit included in the decoded input corresponding thereto. In this case, it is shown that the total size of the first low unit to the sixth low unit LBC is equal to the size of each of the first middle unit MBC1 to the seventh middle unit MBC7; however, in some implementations, the size is smaller than the size of each of the first middle unit MBC1 to the seventh middle unit MBC7.

[0163] exist Figure 6B In the example of , the first to seventh upper bit cells UBC1 to UBC7 all have the same size. The size of the seventh upper bit cell UBC7 is eight times the size of the first middle bit cell MBC1. Likewise, each of the first to seventh middle bit cells MBC1 to MBC7 has the same size.

[0164] Since the additional bit cell ABC generates an output corresponding to the lowest bit among the bits included in the second bit group, the additional bit cell ABC may have the same size as the seventh middle bit cell MBC7 corresponding to the lowest bit among the bits included in the second bit group.

[0165] Reference Figure 6C , which shows that when the first digital input and the second digital input are continuously input to the DAC 100, Fig. 6A The state of the plurality of segment units of the structure of the segment unit circuit 120. Each of the first digital input and the second digital input may include an upper bit UB, a middle bit MB, and a lower bit LB.

[0166] exist Figure 6CIn the table, the decoded input represented by the thermometer code and the binary code is listed in the (thermometer+binary) column of the table, the states of the first upper bit cell UBC1 to the seventh upper bit cell UBC7 are listed in numerical order in the UBCs column of the table, the states of the first middle bit cell MBC1 to the seventh middle bit cell MBC7 are listed in numerical order in the MBCs column of the table, the states of the first lower bit cell LBC1 to the sixth lower bit cell LBC6 are listed in numerical order in the LBCs column of the table, and the states of the additional bit cell ABC are listed in the ABC column of the table. In this case, the state of the segment unit can be represented as 1 in the on state and as 0 in the off state.

[0167] First, when the first digital input DI1 represented by binary code as “011111111111” is input to the DAC 100 , the controller 110 may decode the first digital input DI1 to generate a first decoded input represented by thermometer code and binary code as “00001111111111111111”.

[0168] The controller 110 may generate a control signal based on the first decoded input. In this case, the first upper bit unit UBC1 to the seventh upper bit unit UBC7, the first middle bit unit MBC1 to the seventh middle bit unit MBC7, the first lower bit unit LBC1 to the sixth lower bit unit LBC6, and the additional bit unit ABC may be turned on or off based on the control signal. Figure 6C In the example, the first to fourth upper cells UBC1 to UBC4 may be turned off, the fifth to seventh upper cells UBC5 to UBC7, the first to seventh middle cells MBC1 to MBC7, and the first to sixth lower cells LBC1 to LBC6 may be turned on, and the additional bit cell ABC may be turned off.

[0169] After the first digital input DI1 is input, when the second digital input DI2 represented by binary code as “100000000001” is input to the DAC 100, the decoder 111 can decode the second digital input DI2 to generate a second decoded input represented by thermometer code and binary code as “00011110000000000001”.

[0170] The controller 110 may generate a control signal based on the second decoded input.

[0171] In this case, when the additional bit cell ABC is not used, the first to sixth middle bit cells MBC1 to MBC6 and the first to fifth lower bit cells LBC1 to LBC5 are changed from the on state to the off state. Thus, when the states of a plurality of segment cells are changed at the same time, the possibility of an error occurring in the process of changing the cell states may be increased.

[0172] Since the DAC 100 uses the additional bit unit ABC, since the highest bit of the digital input is converted from the first value to the second value, all bits included in the second bit group of the digital input are converted from the second value to the first value, and a preset reference number (e.g., 3) or more of bits included in the third bit group of the digital input are converted from the second value to the first value, Figure 6C In the case shown, the controller 110 may generate a control signal to turn on the additional bit unit. Accordingly, the states of the first upper bit unit UBC1 to the seventh upper bit unit UBC7, the first middle bit unit MBC1 to the sixth middle bit unit MBC6, and the sixth lower bit unit LBC6 may not be changed, the first lower bit unit LBC1 to the fifth lower bit unit LBC5 may be changed from the on state to the off state, and the additional bit unit ABC may be changed from the off state to the on state. In this way, by changing only the states of a relatively small number of segmented units, the DAC 100 can reduce the possibility of errors occurring in the process of changing the cell state. Therefore, the linearity and dynamic range performance of the DAC 100 can be improved.

[0173] Figure 7 is a diagram showing a DAC (eg, having a Figures 1 to 6C A flowchart of an operating method of a DAC 100 having a structure described herein.

[0174] Reference Figure 7 In operation S710, the DAC 100 may receive a digital input. The DAC 100 may receive a digital input from another device (eg, the processor 10 in the communication device 1).

[0175] In operation S720 , the DAC 100 may generate a control signal based on a digital input.

[0176] For example, according to the configuration of the segment unit circuit 120 , the controller 110 of the DAC 100 may generate a decoded input based on a digital input through the decoder 111 , and generate a control signal based on the decoded input.

[0177] In some implementations, the controller 110 generates a control signal to turn on the additional segment unit when a specific condition is met, such as when the highest bit of the digital input transitions from the first value to the second value and all other bits of the digital input except the highest bit transition from the second value to the first value.

[0178] In operation S730, the DAC 100 may turn on or off the plurality of segment units based on the control signal. The segment unit circuit 120 of the DAC 100 may generate an analog output corresponding to a digital input by turning on or off the plurality of segment units based on the control signal.

[0179] Figure 8 is a flow chart illustrating a method of operating a detection circuit (eg, detection circuit 130 ) of a DAC according to some embodiments.

[0180] Reference Figure 8 In operation S810, the detection circuit 130 of the DAC 100 may determine whether the digital input satisfies a reference condition. Figure 7 After receiving the digital input in operation S710, the detection circuit 130 may determine whether the received digital input satisfies a reference condition. For example, the reference condition may be whether the range of the digital input is less than or equal to a preset reference size.

[0181] When it is determined that the digital input satisfies the reference condition, the detection circuit 130 may proceed to operation S820 and determine to use an additional segment unit.

[0182] On the other hand, when it is determined that the digital input does not satisfy the reference condition, the detection circuit 130 may proceed to operation S830 and determine not to use the additional segment unit.

[0183] Fig. 9 is a block diagram illustrating an electronic device according to some embodiments.

[0184] Reference Fig. 9 , the electronic device 1000 may include an application processor 1010 , a transceiver 1020 , a memory 1030 , a display 1040 , an input / output device 1050 , and a sensor 1060 .

[0185] The electronic device 1000 can communicate with the outside through the transceiver 1020. The transceiver 1020 may include, for example, a wireless short-range communication interface (such as a wired local area network (LAN), Bluetooth, wireless fidelity (WiFi), or ZigBee), a power line communication (PLC), or a modem communication interface that can access a mobile cellular network (such as the third generation (3G), long term evolution (LTE), 5G, NR, or next generation communication). The transceiver 1020 may include a modem communication interface according to the reference Figures 1 to 8The DAC 100 of any of the embodiments described.

[0186] The application processor 1010 may control the overall operation of the electronic device 1000 and the operations of the components of the electronic device 1000. The application processor 1010 may perform various operations. The application processor 1010 may include one processor core (single core) or may include multiple processor cores (multi-core).

[0187] The display 1040 may display the internal state information of the electronic device 1000. The display 1040 may include a touch sensor. Likewise, the display 1040 may include the appearance of a user interface and input or output functions. The user may control the electronic device 1000 through the touch sensor and the user interface.

[0188] The input / output device 1050 may include an input unit (e.g., a touch pad, a keypad, or an input button) and an output unit (e.g., a display or a speaker). The memory 1030 may store instruction codes, control data, or user data for controlling the electronic device 1000. The memory 1030 may include at least one of a volatile memory and a non-volatile memory.

[0189] For example, the sensor 1060 may be an image sensor for sensing an image. The sensor 1060 may be connected to the application processor 1010 to send the generated image information to the application processor 1010. The sensor 1060 may be a biosensor for detecting biometric information. The sensor 1060 may be any sensor, such as an illumination sensor, a sound sensor, or an acceleration sensor.

[0190] The electronic device 1000 may include a built-in battery to supply internal power or may also include a power supply unit for receiving power from the outside. Similarly, the electronic device 1000 may also include a storage device. The storage device may include a non-volatile medium such as a hard disk (HDD), a solid state drive (SSD), an embedded multimedia card (eMMC), or a universal flash memory (UFS). The storage device may store user information provided by the input / output device 1050 and sensing information collected by the sensor 1060.

[0191] At least some components of the electronic device 1000 (e.g., the application processor 1010, the transceiver 1020, the memory 1030, the display 1040, the input / output device 1050, and the sensor 1060) may include a DAC for digital-to-analog conversion, and according to the above reference Figures 1 to 8 The DAC 100 of any of the described embodiments may be used as a DAC.

[0192] Fig.10 is a diagram showing a communication device including a DAC.

[0193] Reference Fig.10 Each of the home device 2100, the home appliance 2120, the entertainment device 2140, and the access point (AP) 2200 may include the above reference Figures 1 to 8 The DAC 100 of any of the described embodiments. In some implementations, the home device 2100, the home appliance 2120, the entertainment device 2140, and the AP 2200 form an Internet of Things (IoT) network system. Fig.10 The communication devices shown in are examples only, and Fig.10 Other communication devices not shown in the figure may also include the communication devices according to the above reference Figures 1 to 8 The DAC 100 of any of the embodiments described.

[0194] Although the present disclosure contains many specific implementation details, these details should not be interpreted as limiting the scope of the claims. Certain features described in the present disclosure in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, different features described in the context of a single implementation may also be implemented individually in multiple implementations, or in appropriate sub-combinations. In addition, although the above features may be described as working in certain combinations, in some cases, one or more features in a combination may be removed from the combination, and a combination may refer to a sub-combination or a variant of a sub-combination.

[0195] While various examples have been particularly shown and described, it should be understood that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure.

Claims

1. A digital-to-analog converter (DAC) for generating an analog output from a digital input, the DAC comprising: a controller configured to generate a control signal based on the digital input; as well as A segment unit circuit includes a plurality of segment units, wherein the plurality of segment units are turned on or off based on the control signal, wherein the segment unit circuit is configured to generate the analog output based on the outputs of the plurality of segment units, Wherein, the multiple segmentation units include: a plurality of first segmentation units, each first segmentation unit being configured to generate a corresponding output based on a corresponding bit included in a first bit group of the digital input; a plurality of second segmentation units, each second segmentation unit being configured to generate a corresponding output based on a corresponding bit included in a second bit group of the digital input; and The additional segmentation unit is configured to generate a corresponding output based on the least significant bit of the second bit group.

2. The DAC according to claim 1, wherein The first bit group includes upper bits, the upper bits including the most significant bits among the bits included in the digital input, and The second bit group includes bits not included in the first bit group, wherein the bits not included in the first bit group are lower than the upper bits.

3. The DAC according to claim 1, wherein The controller is configured to control the control signal to turn on the additional segment unit based on (i) a highest bit of the digital input being converted from a first value to a second value and (ii) all bits of the digital input except the highest bit being converted from the second value to the first value.

4. The DAC according to claim 1, wherein The controller includes a decoder configured to generate a decoded input by decoding bits included in the first bit group of the digital input using a thermometer code, The controller is configured to: generate the control signal based on the decoded input, Each of the plurality of first segmentation units is configured to: generate the corresponding output based on a corresponding bit included in the first bit group of the decoded input, Each of the plurality of second segmentation units is configured to generate the corresponding output based on a corresponding bit included in the second bit group of the decoded input, and The additional segmentation unit is configured to generate the corresponding output based on the least significant bit of the second bit group of the decoded input.

5. The DAC according to claim 4, wherein: The decoder is configured to generate the decoded input by decoding bits included in the second bit group of the digital input using the thermometer code.

6. The DAC according to claim 1 , further comprising a detection circuit configured to: determine whether the digital input satisfies a reference condition, and determine whether to use the additional segment unit based on whether the digital input satisfies the reference condition, in, The controller is configured to generate the control signal based on the detection circuit determining whether to use the additional segment unit.

7. The DAC according to claim 6, wherein: The reference condition includes that the range of the digital input is less than or equal to a preset reference size.

8. The DAC according to claim 6, wherein The detection circuit is configured as follows: determining to use the additional segmentation unit based on determining that the digital input satisfies the reference condition, and Based on determining that the digital input does not satisfy the reference condition, it is determined not to use the additional segment unit.

9. A digital-to-analog converter (DAC) for generating an analog output from a digital input, the DAC comprising: a controller configured to generate a control signal based on the digital input; as well as A segment unit circuit includes a plurality of segment units, wherein the plurality of segment units are turned on or off based on the control signal, wherein the segment unit circuit is configured to generate the analog output based on the outputs of the plurality of segment units, Wherein, the multiple segmentation units include: a plurality of first segmentation units, each first segmentation unit being configured to generate a corresponding output based on a corresponding bit included in a first bit group of the digital input; a plurality of second segmentation units, each second segmentation unit being configured to generate a corresponding output based on a corresponding bit included in a second bit group of the digital input; a plurality of third segmentation units, each third segmentation unit being configured to generate a corresponding output based on a corresponding bit included in a third bit group of the digital input; and The additional segmentation unit is configured to generate a corresponding output based on the least significant bit of the second bit group.

10. The DAC according to claim 9, wherein the first bit group includes upper bits, the upper bits including the most significant bits among the bits included in the digital input, wherein the second bit group includes middle bits among bits included in the digital input, the middle bits including the highest bits among bits not included in the first bit group, and wherein the third bit group includes bits of the digital input that are not included in the first bit group and not included in the second bit group, wherein the bits not included in the first bit group and not included in the second bit group are lower than the bits included in the first bit group and the second bit group.

11. The DAC according to claim 9, wherein The controller is configured to control the control signal to turn on the additional segment unit based on (i) a highest bit of the digital input being converted from a first value to a second value and (ii) all bits of the digital input except the highest bit being converted from the second value to the first value.

12. The DAC according to claim 9, wherein: The controller includes a decoder configured to generate a decoded input by decoding bits included in the first bit group of the digital input using a thermometer code, The controller is configured to: generate the control signal based on the decoded input, Each of the plurality of first segmentation units is configured to: generate the corresponding output based on a corresponding bit included in the first bit group of the decoded input, Each of the plurality of second segmentation units is configured to: generate the corresponding output based on a corresponding bit included in the second bit group of the decoded input, Each of the plurality of third segmentation units is configured to generate the corresponding output based on a corresponding bit included in a third bit group of the decoded input, and The additional segmentation unit is configured to generate the corresponding output based on the least significant bit included in the second bit group of the decoded input.

13. The DAC according to claim 12, wherein: The decoder is configured to generate the decoded input by decoding bits included in the second bit group of the digital input using the thermometer code.

14. The DAC according to claim 13, wherein The decoder is configured to generate the decoded input by decoding bits included in the third bit group of the digital input using the thermometer code.

15. The DAC according to claim 9, wherein The controller is configured to control the control signal to turn on the additional segment unit based on (i) the highest bit of the digital input or the decoded input is converted from the first value to the second value and (ii) all bits included in the second bit group of the digital input or the decoded input are converted from the second value to the first value.

16. The DAC of claim 15, wherein: The controller is configured to control the control signal to turn on the additional segment unit based on (i) the highest bit of the digital input or the decoded input is converted from the first value to the second value, (ii) all bits included in the second bit group of the digital input or the decoded input are converted from the second value to the first value, and (iii) at least a preset reference number of bits included in the third bit group of the digital input or the decoded input are converted from the second value to the first value.

17. The DAC according to claim 9, further comprising a detection circuit configured to: determine whether the digital input satisfies a reference condition, and determine whether to use the additional segment unit based on whether the digital input satisfies the reference condition, in, The controller is configured to generate the control signal based on the detection circuit determining whether to use the additional segment unit.

18. The DAC of claim 17, wherein: The reference condition includes that the range of the digital input is less than or equal to a preset reference size.

19. The DAC of claim 17, wherein: The detection circuit is configured as follows: determining to use the additional segmentation unit based on determining that the digital input satisfies the reference condition, and Based on determining that the digital input does not satisfy the reference condition, it is determined not to use the additional segment unit.

20. A method for operating a digital-to-analog converter (DAC), the DAC being used to generate an analog output from a digital input, the method comprising: receiving the digital input; generating a control signal based on the digital input; as well as Based on the control signal, multiple segment units are turned on or off. Wherein, the multiple segmentation units include: a plurality of first segmentation units, each first segmentation unit being configured to generate a corresponding output based on a corresponding bit included in a first bit group of the digital input; a plurality of second segmentation units, each second segmentation unit being configured to generate a corresponding output based on a corresponding bit included in a second bit group of the digital input; and The additional segmentation unit is configured to generate a corresponding output based on the least significant bit of the second bit group.

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