Polarization decoder and polarization decoding method

Abstract

The invention discloses a polarization decoder and a polarization decoding method. The polarization decoder comprises a normalization receiving module, an intermediate LLR calculation module, a judgment module, a partial sum return module, a return bit storage module, an index storage module and a decoding output module, the normalization receiving module converts the received demodulation signal into a normalization channel LLR value; the intermediate LLR calculation module calculates an intermediate LLR value by using the normalized channel LLR value; the judgment module is used for carrying out hard judgment on an estimated bit according to the intermediate LLR value; outputting a return bit and an estimated information bit through the estimated bit; the index storage module is used for providing corresponding index values for the intermediate LLR calculation module, the judgment module, the partial sum return module and the decoding output module; the decoding output module is used for reading the estimated information bits from the return bit storage module and serially outputting the estimated information bits; normalization processing is carried out on demodulation data, and then decoding operation is carried out; the operation bit width is saved; and the calculation complexity between fixed point numbers is reduced.

Description

Technical Field

[0001] The invention discloses a polarization decoder and a polarization decoding method, and relates to the field of information communication. Background Art

[0002] Polarization codes are selected as the uplink and downlink short code scheme for control channels in the 5G communication system coding standard. However, due to the short development time of polarization codes, there is an urgent need to test theoretical research in practice, mainly by reducing hardware resource consumption.

[0003] Due to the inherent characteristics of serial decoding, polar codes have problems such as complex hardware structure and large decoding delay, which consume too many resources. When the code length is large, the number of data interactions and the amount of calculation required for the intermediate LLR calculation increase significantly, and a more excellent structure is needed to improve the parallelism of the calculation and minimize the calculation delay while ensuring low complexity. In the existing design, the basic operation unit of the intermediate LLR calculation module is composed of node interconnection modules. The complexity of this structure greatly affects the performance of the entire decoder. "Cao Zheng. High-speed Design and FPGA Implementation of Polar Code Encoder for 5G Standards [D]. Xidian University, 2022". Although it has been optimized, there are still inversion and redundant XOR circuits, and due to too many cascaded units, there is a hidden danger that the asynchronous output of the combinational logic may lead to calculation errors. Secondly, the selection of the quantization bit width of fixed-point numbers is also an important factor affecting the resource consumption of the decoder. The quantization bit width of 8 bits is selected in this paper. Although the performance is close to floating-point numbers, it still wastes redundant hardware resources. Summary of the invention

[0004] In view of the defects in the above-mentioned background technology, the present invention provides a polarization decoder and a polarization decoding method, which first normalizes the demodulated data and then performs a decoding operation, thereby saving operation bit width and reducing the calculation complexity between fixed-point numbers.

[0005] To achieve the above object, the technical solution adopted by the present invention is as follows: a polar decoder, characterized in that it includes: a normalized receiving module, an intermediate LLR storage module, an intermediate LLR calculation module, a decision module, a partial sum return module, a return bit storage module, a control module, an index storage module and a decoding output module; The data signal output terminal of the normalized receiving module is connected to the data signal input terminal of the intermediate LLR storage module; The control signal output terminal of the normalized receiving module is connected to the control signal input terminal of the control module; The control signal input terminal of the control module is connected to the control signal output terminal of the return module. The data signal output terminal of the control module is connected to the second output XOR gate input terminal and the data signal input terminal of the intermediate LLR calculation module, and its control signal output terminal is connected to the control signal input terminal of the decoding output module; The control signal output terminal of the decoding output module is connected to the second output XOR gate input terminal, and the data signal output terminal is connected to the third output XOR gate input terminal; The output end of the two-output XOR gate is connected to the input end of the index storage module; The output of the three-output XOR gate is connected to the input of the return bit storage module; The output end of the index storage module is respectively connected to the control signal input end of the intermediate LLR calculation module, the control signal input end of the decision module, the control signal input end of the partial sum return module and the control signal input end of the decoding output module; The output end of the return bit storage module is connected to the data signal input end of the intermediate LLR calculation module, the data signal input end of the partial sum return module and the data signal input end of the decoding output module; The data signal output terminal of the intermediate LLR storage module is connected to the data signal input terminal of the intermediate LLR calculation module; The control signal output terminal of the intermediate LLR calculation module is connected to the control signal input terminal of the intermediate LLR storage module and the input terminal of the three-input XOR gate, and the data signal output terminal is connected to the input terminal of the decision module; The output terminal of the decision module is connected to the data signal input terminal of the return module; The partial and return module control signal output terminal is connected to the return bit storage module control signal input terminal and the control module control signal input terminal, and the data signal output terminal is connected to the three-input XOR gate input terminal; The normalized receiving module is used to receive the demodulated signal and convert it into a normalized channel LLR value; The intermediate LLR calculation module is used to calculate the intermediate LLR value using the normalized channel LLR value; The intermediate LLR storage module is used to store the normalized channel LLR value and the intermediate LLR value output by the intermediate LLR calculation module; The decision module is used to make a hard decision on the estimated bit according to the intermediate LLR value; The part and return module outputs return bits and estimated information bits through estimated bits; The return bit storage module outputs the return bit and the estimated information bit to the intermediate LLR calculation module for performing intermediate LLR calculation; The control module is used to control each submodule to complete the entire process from receiving the demodulated signal to the decoding output module outputting the estimated information bit; The index storage module is used to provide corresponding index values ​​to the intermediate LLR calculation module, the decision module, the partial sum return module and the decoding output module; The decoding output module is used to read out the estimated information bits from the return bit storage module and output them serially.

[0006] Furthermore, the normalization module includes: two equal operation units, a right shift operation unit, a two-input XOR gate, a two-to-one selector and a register; the demodulated signal first passes through the right shift operation unit to complete the bitwise right shift operation, and then the two equal operation units determine the positive and negative of the input signal, and then the two-to-one selector selectively outputs the right shift output or its corresponding complement according to the positive and negative of the input data, and finally latches and outputs it through the register; the quantization bit width of 12bit data is shortened to the quantization bit width of 5bit data.

[0007] Furthermore, the intermediate LLR calculation module includes: a node interconnection module, the node interconnection module includes: a three-input selector, two two-input selectors, two registers, an XOR gate, an adder, a subtractor, an AND gate and two sign operations; low-complexity intermediate LLR calculation is realized, firstly, the two received intermediate LLR data are respectively added and subtracted through the adder and the subtractor and used as two of the inputs of the three-input selector, and at the same time, the sign bits of the two input signals are XORed through the sign operation unit and the XOR gate as the last input of the three-input selector. In addition, the input of the first two-input selector is composed of the output of the adder and the subtractor, and then the output of the three-input selector and the output of the first two-input selector are used as the input of the second two-input selector, and finally the output of the second two-input selector is input to the register for latching and output.

[0008] A polarization decoding method comprises the following steps: Step 1: normalize the received channel LLR, and after shift operation and saturation truncation to reduce the data quantization bit width, output the normalized channel LLR serially to the intermediate LLR storage module; Step 2: The intermediate LLR calculation module reads the intermediate LLR value stored in the intermediate LLR storage module and performs parallel calculation. The calculation result is stored in the intermediate LLR storage module according to the write address output by the state machine in the intermediate LLR calculation module. The state machine divides the polar code into states according to the code length of the polar code, and the initial state is determined by the LLR index. When the jump condition is met, the state jump is performed, and the intermediate LLR of the next state is calculated. When entering the IDLE state, it indicates that the intermediate LLR calculation of the bit is completed, and the sign bit of the intermediate LLR calculated in the LAYER_1 state is output for the next step of bit determination. Step 3: The decision module receives the sign bit of the intermediate LLR calculation module and the frozen bit index output by the index storage module, and makes a decision when the decision signal output by the intermediate LLR calculation module is pulled high; finally, the decision bit is output to the partial sum return module; Step 4: The partial sum return module receives the decision bit output by the decision module and the partial sum return index output by the index storage module to determine the number of XOR operations required in this partial sum return calculation and the number of bits for each XOR operation.

[0009] Step 5: After receiving the calculation completion signal output by the partial sum return module, the control module outputs a read address signal and a read enable signal to the index storage module. The index storage module decodes the read address signal and the read enable signal output by the output module according to the read address signal and the read enable signal output by the control module, and updates the LLR index, the frozen bit index and the partial sum return index in the intermediate LLR calculation module, the decision module and the partial sum return module respectively; Step 6: After detecting that the decoding end flag signal output by the control module is valid, the decoding output module selectively reads the estimated information bits in parallel from the return bit storage module in groups of 4 bits according to the output of the storage module, outputs all information bits in serial after parallel-to-serial conversion, and resets all modules inside the SC decoder at the same time, enters the waiting state, and prepares for the next decoding.

[0010] Furthermore, before normalization processing, the LLR index, frozen bit index and partial and return index are first imported into the index storage module of the decoder, and the reset port of the decoder is pulled high for one clock cycle to reset the data in the intermediate LLR storage module and the return bit storage module and synchronize the clock signal.

[0011] Furthermore, the judgment method in step 3 is: if the frozen bit index is 1, it means that the bit is a frozen bit, and it is directly judged as 0, otherwise the bit is an information bit. For the judgment of the information bit: if the input is 0, it means that the LLR value is non-negative, and the judgment is 1, otherwise the judgment is 0.

[0012] Furthermore, step 4 is specifically as follows: in an XOR operation, the partial sum return module reads 4 bits of data in the return bit storage module as input according to the read address, and outputs 4 bits of data according to the write address and stores them in the return bit storage module, wherein the initial values ​​of the read address and the write address calculated for each partial sum return are determined by the partial sum return index in the index storage module, and a counter is used to accumulate the count.

[0013] Beneficial effects: This method proposes to normalize the demodulated data before decoding. Compared with the unnormalized processing, the appropriate normalization coefficient has almost negligible performance loss, but can save the operation bit width and reduce the calculation complexity between fixed-point numbers. The normalization operation is completed by a simple right shift operation, and the complexity is extremely low.

[0014] The present invention uses a time division multiplexing design concept in both the intermediate LLR calculation module and the partial sum return module; during LLR calculation, the intermediate LLR values ​​are calculated in sequence by reusing the improved node interconnection module, and the appropriate cascade number in the array is calculated by analyzing resource consumption and utilization, thereby achieving an optimal solution for resource consumption and resource utilization; during partial sum calculation, the XOR array is reused, and calculations are performed in sequence according to the standard structure of the polar code generation matrix. Compared with a traditional direct reproduction operation circuit, the proposed method can save a large amount of hardware resources and reduce the implementation complexity.

[0015] The node interconnection module in the intermediate LLR calculation module of the present invention is improved. The traditional interconnection module requires "complement code-sign number", "sign number-complement code" and absolute value circuits, which are specifically composed of two complement code units and a two-output selector. The design utilizes the characteristics of interconnection operation, selects a simple three-input selector and a box of XOR gates, and reduces the delay and complexity of each operation.

[0016] The present invention needs to frequently read previously calculated values ​​when calculating intermediate LLRs and partial sum returns, and write new values ​​immediately at the same time. Therefore, the storage unit is designed to be write-first and the read-write bit width is changed to simplify the operation and save reading time and address storage resources. In the traditional design, the storage of return bits with a code length of 512 requires counting 1023 address units, and only single-bit output can be used when reading, which takes a lot of time for long code words. The present design is improved to store 4-bit outputs together in one storage unit, and the number of address units is shortened to 319 and matches the number of input bits required by the XOR array and the LLR calculation array. Data reading can be completed within one cycle, shortening the decoding delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of the hardware structure of the present invention; Figure 2 It is a schematic diagram of the structure connection of the normalized receiving module of the present invention; Figure 3 The node interconnection module structure of the present invention; Figure 4 It is the algorithm flow chart of the present invention; Figure 5 Calculate state jumps for invented LLRs; Figure 6 Calculate array resource consumption and utilization for the invented LLR; Figure 7 Schematic diagram of the designed decoder resource report. Implementation

[0018] The implementation of the technical solution is further described in detail below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and cannot be used to limit the protection scope of the present invention.

[0019] like Figure 1 An embodiment shown: This embodiment provides a polar decoder, including: a normalized receiving module, an intermediate LLR storage module, an intermediate LLR calculation module, a decision module, a partial sum return module, a return bit storage module, a control module, an index storage module and a decoding output module; The data signal output terminal of the normalized receiving module is connected to the data signal input terminal of the intermediate LLR storage module; The control signal output terminal of the normalized receiving module is connected to the control signal input terminal of the control module; The control signal input terminal of the control module is connected to the control signal output terminal of the return module. The data signal output terminal of the control module is connected to the second output XOR gate input terminal and the data signal input terminal of the intermediate LLR calculation module, and its control signal output terminal is connected to the control signal input terminal of the decoding output module; The control signal output terminal of the decoding output module is connected to the second output XOR gate input terminal, and the data signal output terminal is connected to the third output XOR gate input terminal; The output end of the two-output XOR gate is connected to the input end of the index storage module; The output of the three-output XOR gate is connected to the input of the return bit storage module; The output end of the index storage module is respectively connected to the control signal input end of the intermediate LLR calculation module, the control signal input end of the decision module, the control signal input end of the partial sum return module and the control signal input end of the decoding output module; The output end of the return bit storage module is connected to the data signal input end of the intermediate LLR calculation module, the data signal input end of the partial sum return module and the data signal input end of the decoding output module; The data signal output terminal of the intermediate LLR storage module is connected to the data signal input terminal of the intermediate LLR calculation module; The control signal output terminal of the intermediate LLR calculation module is connected to the control signal input terminal of the intermediate LLR storage module and the input terminal of the three-input XOR gate, and the data signal output terminal is connected to the input terminal of the decision module; The output terminal of the decision module is connected to the data signal input terminal of the return module; The partial and return module control signal output terminal is connected to the return bit storage module control signal input terminal and the control module control signal input terminal, and the data signal output terminal is connected to the three-input XOR gate input terminal; The normalized receiving module is used to receive the demodulated signal and convert it into a normalized channel LLR value; The intermediate LLR calculation module is used to calculate the intermediate LLR value using the normalized channel LLR value; The intermediate LLR storage module is used to store the normalized channel LLR value and the intermediate LLR value output by the intermediate LLR calculation module; The decision module is used to make a hard decision on the estimated bit according to the intermediate LLR value; The part and return module outputs return bits and estimated information bits through estimated bits; The return bit storage module outputs the return bit and the estimated information bit to the intermediate LLR calculation module for performing intermediate LLR calculation; The control module is used to control each submodule to complete the entire process from receiving a demodulated signal to outputting estimated information bits; The index storage module is used to provide corresponding index values ​​to the intermediate LLR calculation module, the decision module, the partial sum return module and the decoding output module; The decoding output module is used to read out the estimated information bits from the return bit storage module and output them serially.

[0020] like Figure 2 As shown, the normalization module includes: two equal operation units, a right shift operation unit, a two-input XOR gate, a two-to-one selector and a register; The demodulated signal (c_llr) first passes through the right shift operation unit to complete the bitwise right shift operation to obtain the 7-bit signal N_llr. Then, the upper three bits of N_llr (N_llr[6:4]) are passed through two equal operation units to determine the positive and negative and size relationship of the input signal. Then, the two-choice selector outputs the right-shifted data (N_llr[6:0]) or the extreme value within the quantization bit width ({N_llr[6],{4{!N_llr[6]}}) according to this relationship. Finally, it is latched and output through the register; the quantization bit width of 12 bits is shortened to the quantization bit width of 5 bits.

[0021] like Figure 3 As shown, the intermediate LLR calculation module includes: a node 2 interconnection module, the node interconnection module includes: a three-input selector, two two-input selectors, two registers, an XOR gate, an adder, a subtractor, an AND gate and two sign operations, realizing low-complexity intermediate LLR calculation; First, the two received intermediate LLR data (L1 and L2) are added (L2+L1) and subtracted (L2-L1) by the adder and subtractor respectively and used as two of the inputs of the three-input selector. At the same time, the sign bits of the two input signals are XORed by the sign operation unit (sign) and the XOR gate as the last input of the three-input selector. In addition, the input of the first two-input selector is composed of the output of the adder and subtractor (L2+L1 and L2-L1). Then, the output of the three-input selector (f) and the output of the first two-input selector (g) are used as the input of the second two-input selector. Finally, the output of the second two-input selector is input to the register latch and output.

[0022] like Figures 4 and 5 In the embodiment shown, the detailed working process is as follows: Step 1: Initialization In order to enable the decoder of the first embodiment to work properly, the first step is to import the LLR index, the frozen bit index and the partial and return index into the index storage module of the decoder, and pull the reset port of the decoder high for one clock cycle, reset the data in the intermediate LLR storage module and the return bit storage module and synchronize the clock signal. The decoder enters the waiting state and performs decoding when the decoding start flag signal is pulled high.

[0023] Step 2: Normalize the demodulator output signal When the decoder receives the decoding start flag signal, the normalization receiving module normalizes the channel LLR output by the demodulator. After the shift operation and saturation truncation reduce the data quantization bit width, the module outputs the data serially to the intermediate LLR storage module for the next intermediate LLR calculation.

[0024] Step 3: Calculate the bit-to-bit LLR The intermediate LLR calculation module is used to calculate the intermediate LLR of the bit. The calculation process is controlled by the state machine. The state machine outputs the read address and the enable signal to control the node interconnection module to read the LLR value stored in the intermediate LLR storage module for parallel calculation, and the calculation result is re-stored in the corresponding storage unit of the intermediate LLR storage module according to the write address output by the state machine.

[0025] The state machine is divided into states according to the code length, for example, there are 10 states when the code length is 512. When the llr_ctrl_in_flag signal is pulled high, the state machine enters the LATER state from the IDLE state, and the number of layers is determined by the LLR index. When the jump condition signal (jump_flag) is pulled high, the state jump is performed, and the intermediate LLR of the next state is calculated. When entering the IDLE state, it indicates that the calculation of the intermediate LLR of the bit is completed, and the sign bit (highest bit) of the intermediate LLR calculated in the LAYER_1 state is output for the next step of bit determination.

[0026] Step 4: Decision Bits The decision module receives the 1-bit output of the intermediate LLR calculation module and the corresponding frozen bit index, and makes a decision when the valid signal is pulled high. If the frozen bit index is 1, it means that the bit is a frozen bit and is directly judged as 0, otherwise the bit is an information bit; for the decision of the information bit: if the input is 0, it means that the LLR value is non-negative, and the decision is 1, otherwise the decision is 0; finally, the decision bit is output.

[0027] Step 5: Partial and Return The partial sum return module receives the judged bits and the partial sum return index to determine the number of times the partial sum return calculation needs to be performed and the number of bits for each XOR operation; 4 bits of data are read from the return bit storage module for each operation, and the result of the operation is also stored in the return bit storage module in groups of 4 bits; the address counter accumulates the count and outputs the read and write address of the return bit storage module, so that the partial sum return module can read or write the bits required for this partial sum calculation.

[0028] Step 6: Enter the bit decoding process After receiving the current bit calculation completion signal from the partial and return module, the control module outputs the LLR index, frozen bit index and partial and return index of the next bit; the decoding bit counter therein increments by 1 to count the number of decoded bits and pulls up the decoding start signal to enter the decoding of the bit; when the decoding bit counter counts to the end, the decoding ends and the decoding end mark signal level is pulled up for one clock cycle.

[0029] Step 7: Output the results When the decoding output module detects that the decoding end flag signal is valid, it selectively reads information bits in parallel from the return bit storage module in groups of 4 bits according to the frozen bit index, outputs all information bits in serial after parallel-to-serial conversion, and sends a signal to clear the control module counter to 0, enter the waiting state, and prepare for the next decoding.

[0030] like Figure 6As shown in the figure, when the number of node interconnect modules integrated in the LLR calculation array is 4, the normalized resource consumption of the normalized receiving module is 0.35, and the resource utilization is 0.5. If the number of node interconnect modules is further increased, the resource utilization will drop significantly, but the resource consumption will not drop significantly. Therefore, it is finally determined that integrating 4 node interconnect modules in the LLR calculation array module can maximize the balance between decoding delay and resource consumption.

[0031] like Figure 7 As shown in the figure, it can be seen that the hardware resource usage is obtained after the decoder is synthesized and placed and routed on the Vivado software. From the results after placement and routing, the system decoder consumes less resources and meets the requirements of low-complexity design.

[0032] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A polar decoder, characterized in that: include: Normalized receiving module, intermediate LLR storage module, intermediate LLR calculation module, decision module, partial sum return module, return bit storage module, control module, index storage module and decoding output module; The data signal output terminal of the normalized receiving module is connected to the data signal input terminal of the intermediate LLR storage module; The control signal output terminal of the normalized receiving module is connected to the control signal input terminal of the control module; The control signal input terminal of the control module is connected to the control signal output terminal of the return module. The data signal output terminal of the control module is connected to the second output XOR gate input terminal and the data signal input terminal of the intermediate LLR calculation module, and its control signal output terminal is connected to the control signal input terminal of the decoding output module; The control signal output terminal of the decoding output module is connected to the second output XOR gate input terminal, and the data signal output terminal is connected to the third output XOR gate input terminal; The output end of the two-output XOR gate is connected to the input end of the index storage module; The output of the three-output XOR gate is connected to the input of the return bit storage module; The output end of the index storage module is respectively connected to the control signal input end of the intermediate LLR calculation module, the control signal input end of the decision module, the control signal input end of the partial sum return module and the control signal input end of the decoding output module; The output end of the return bit storage module is connected to the data signal input end of the intermediate LLR calculation module, the data signal input end of the partial sum return module and the data signal input end of the decoding output module; The data signal output terminal of the intermediate LLR storage module is connected to the data signal input terminal of the intermediate LLR calculation module; The control signal output terminal of the intermediate LLR calculation module is connected to the control signal input terminal of the intermediate LLR storage module and the input terminal of the three-input XOR gate, and the data signal output terminal is connected to the input terminal of the decision module; The output terminal of the decision module is connected to the data signal input terminal of the return module; The partial and return module control signal output terminal is connected to the return bit storage module control signal input terminal and the control module control signal input terminal, and the data signal output terminal is connected to the three-input XOR gate input terminal; The normalized receiving module is used to receive the demodulated signal and convert it into a normalized channel LLR value; The intermediate LLR calculation module is used to calculate the intermediate LLR value using the normalized channel LLR value; The intermediate LLR storage module is used to store the normalized channel LLR value and the intermediate LLR value output by the intermediate LLR calculation module; The decision module is used to make a hard decision on the estimated bit according to the intermediate LLR value; The part and return module outputs return bits and estimated information bits through estimated bits; The return bit storage module outputs the return bit and the estimated information bit to the intermediate LLR calculation module for performing intermediate LLR calculation; The control module is used to control each submodule to complete the entire process from receiving the demodulated signal to the decoding output module outputting the estimated information bit; The index storage module is used to provide corresponding index values ​​to the intermediate LLR calculation module, the decision module, the partial sum return module and the decoding output module; The decoding output module is used to read out the estimated information bits from the return bit storage module and output them serially.

2. The polarization decoder according to claim 1, characterized in that: The normalization module as shown in FIG5 includes: two equal operation units, a right shift operation unit, a two-input XOR gate, a two-to-one selector and a register; the demodulated signal first passes through the right shift operation unit to complete the bitwise right shift operation, and then the two equal operation units determine the positive and negative of the input signal, and then the two-to-one selector selectively outputs the right shift output or its corresponding complement according to the positive and negative of the input data, and finally latches and outputs it through the register.

3. The polar decoder according to claim 1, characterized in that: The intermediate LLR calculation module includes: a node interconnection module, the node interconnection module includes: a three-input selector, two two-input selectors, two registers, an XOR gate, an adder, a subtractor, an AND gate and two sign operations; First, the two received intermediate LLR data are added and subtracted by the adder and subtractor respectively and used as two inputs of the three-input selector. At the same time, the sign bits of the two input signals are XORed by the sign operation unit and the XOR gate as the last input of the three-input selector. In addition, the input of the first two-input selector is composed of the output of the adder and the subtractor. Then, the output of the three-input selector and the output of the first two-input selector are used as the input of the second two-input selector. Finally, the output of the second two-input selector is input to the register latch and output.

4. A polar decoding method, characterized in that: The following steps are involved: Step 1: normalize the received channel LLR, and after shift operation and saturation truncation to reduce the data quantization bit width, output the normalized channel LLR serially to the intermediate LLR storage module; Step 2: The intermediate LLR calculation module reads the intermediate LLR value stored in the intermediate LLR storage module for parallel calculation, and the calculation result is stored in the intermediate LLR storage module again according to the write address output by the state machine in the intermediate LLR calculation module; The state machine divides the polar code into states according to the code length. The initial state is determined by the LLR index. When the jump condition is met, the state jump is performed and the intermediate LLR of the next state is calculated. When entering the IDLE state, it indicates that the calculation of the intermediate LLR of the bit is completed, and the sign bit of the intermediate LLR calculated in the LAYER_1 state is output for the next step of bit determination. Step 3: The decision module receives the sign bit of the intermediate LLR calculation module and the frozen bit index output by the index storage module, makes a decision when the decision signal output by the intermediate LLR calculation module is pulled high, and finally outputs the decision bit to the partial sum return module; Step 4: The partial sum return module receives the decision bit output by the decision module and the partial sum return index output by the index storage module to determine the number of XOR operations required in this partial sum return calculation and the number of bits for each XOR operation; Step 5: After receiving the calculation completion signal output by the partial sum return module, the control module outputs a read address signal and a read enable signal to the index storage module. The index storage module decodes the read address signal and the read enable signal output by the output module according to the read address signal and the read enable signal output by the control module, and updates the LLR index, the frozen bit index and the partial sum return index in the intermediate LLR calculation module, the decision module and the partial sum return module respectively; Step 6: After detecting that the decoding end flag signal output by the control module is valid, the decoding output module selectively reads the estimated information bits in parallel from the return bit storage module in groups of 4 bits according to the output of the storage module, outputs all information bits in serial after parallel-to-serial conversion, and resets all modules inside the SC decoder at the same time, enters the waiting state, and prepares for the next decoding.

5. The polar decoding method according to claim 4, characterized in that: Before normalization, the LLR index, frozen bit index and partial and return index are first imported into the index storage module of the decoder, and the reset port is pulled high for one clock cycle to reset the data in the intermediate LLR storage module and the return bit storage module and synchronize the clock signal.

6. The polar decoding method according to claim 5, characterized in that: The judgment method in step 3 is: if the frozen bit index is 1, it means that the bit is a frozen bit, and it is directly judged as 0; otherwise, the bit is an information bit. For the judgment of the information bit: if the input is 0, it means that the LLR value is a non-negative number, and the judgment is 1; otherwise, the judgment is 0.

7. The polar decoding method according to claim 4, characterized in that: Step 4 is specifically as follows: in an XOR operation, the partial sum return module reads 4 bits of data in the return bit storage module as input according to the read address, and outputs 4 bits of data according to the write address and stores them in the return bit storage module, wherein the initial values ​​of the read address and the write address calculated for each partial sum return are determined by the partial sum return index in the index storage module, and a counter is used to accumulate the count.

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