IRIGB code decoding method, system, device and program based on LFSR
By using the LFSR-based counting method and state machine to process the IRIGB code in the FPGA, the problem of high logical resource occupancy in the prior art is solved, and efficient IRIGB code decoding and result judgment are achieved.
Patent Information
- Application Number
- CN202411631666.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-15
- Publication Date
- 2025-02-25
AI Technical Summary
The existing IRIGB code decoding method is used in FPGAs with a large number of adders, resulting in high logical resource occupancy and difficult to efficiently decode.
Instead of the traditional time accumulation counting method, the IRIGB code is debounced and decoded, and the symbols are stored and processed by the state machine, and the absolute number of seconds is calculated to judge the decoding result.
It greatly reduces the occupancy rate of FPGA logical resources, improves decoding efficiency, and effectively judges the correctness of the decoding results through the comparison of absolute seconds, avoiding the difficulty of judging symbols incorrectly.
Smart Images
Figure CN119519732A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of industrial control technology, and in particular to an LFSR-based IRIGB code decoding method, system, device and program. Background Art
[0002] IRIGB code is a commonly used serial transmission method in the time system. Compared with the parallel transmission method, it is physically simpler, has a longer transmission distance, a standardized interface, and is internationally applicable. Each frame of the IRIGB code contains 100 code elements, each of which is 10ms. According to the different lengths of the high-level time, they are decoded into "0", "1", and "P". Since the time of each code element is fixed, the conventional decoding method is mainly to directly accumulate each code element in time, accumulating once per clock cycle. Due to the high clock frequency used, the number of data bits is large during the decoding process, and the amount of calculation required is large, and more adders are used. For FPGA, this method of using a large number of adders is extremely consuming of logic resources. A large part of the resource occupancy rate of the decoding logic engineering is consumed in the accumulation of decoded data, so this problem needs to be solved. Summary of the invention
[0003] In view of this, an embodiment of the present disclosure provides an IRIGB code decoding method based on LFSR, which at least partially solves the problems existing in the prior art.
[0004] In a first aspect, an embodiment of the present disclosure provides an IRIGB code decoding method based on LFSR, the method comprising the following steps: Debounce the IRIGB code; Decoding the de-jittered IRIGB code based on the count of the LFSR to obtain the content of the IRIGB code; The state machine stores the code elements into corresponding registers according to a preset order; At the end of the last state of the state machine, the absolute number of seconds is calculated according to the content of the IRIGB code; Whether the decoding result is normal is determined based on the absolute number of seconds.
[0005] According to a specific implementation manner of the embodiment of the present disclosure, the de-jittering of the IRIGB code includes: de-jittering the IRIGB code by digital filtering.
[0006] According to a specific implementation of the embodiment of the present disclosure, the LFSR-based counting method decodes the IRIGB code after de-jittering, including the following steps: Utilize cyclic calculation of LFSR to accumulate code elements of the IRIGB code; At the rising edge of the IRIGB code, the state of the LFSR is returned to the initial state; at the falling edge of the IRIGB code, the state of the LFSR is recorded, and the high level time in the code element is determined according to the state, including: when the LFSR state is between 0x82b00, 0x05601, 0x0ac02, 0x15804, 0x2b009, and 0x56012, the high level in the code element is 2ms; when the LFSR state is between 0x536ba, 0xa6d75, 0x4daeb, When the LFSR state is between 0x9b5d6, 0x36bac, and 0x6d759, the high level in the code element is 5ms; when the LFSR state is between 0x79a4c, 0xf3499, 0xe6932, 0xcd265, 0x9a4cb, and 0x34996, the high level in the code element is 8ms; Among them, when the high level time is 2ms, the code element is considered to be 0; when the high level time is 8ms, the code element is considered to be 1; when the high level time is 5ms, the code element is considered to be P.
[0007] According to a specific implementation of the embodiment of the present disclosure, the state machine stores the code elements into corresponding registers according to a preset order, including: The state machine determines the position of the double P code according to the code element; wherein the P code is a code element with a high level time of 5ms; When receiving the double P code, start recording the data in the IRIGB code, including: Receive the second data in the IRIGB code, and when the P code is received after receiving 8 data code elements, it will enter the minute state; Receive the data in the IRIGB code, and when the P code is received after receiving 9 data code elements, it will enter the time state; Receive the time data in the IRIGB code, and when the P code is received after receiving 9 data code elements, it will enter the day state; Receive the day data in the IRIGB code, and when the P code is received after receiving 9 data code elements, it will enter the 100-day state; Receive the 100-day data in the IRIGB code, and when the P code is received after receiving 9 data code elements, it will switch to the year state; Receive the year data in the IRIGB code, and when the P code is received after receiving 9 data code elements, it will enter the leap second state; Receive leap second data in IRIGB code, and when P code is received after receiving 9 data code elements, it will enter quality state; Receive the quality data in the IRIGB code, and when the P code is received after receiving 9 data code elements, it will enter the binary second 1 state; Receive binary second 1 data in IRIGB code, and when P code is received after receiving 9 data code elements, it will enter binary second 2 state; Receive the binary second 2 data in the IRIGB code, and enter the judgment state when the P code is received after receiving 9 data code elements.
[0008] According to a specific implementation of the embodiment of the present disclosure, when the last state of the state machine ends, the absolute number of seconds is calculated according to the content of the IRIGB code, including: the absolute number of seconds is calculated as follows: ((((current year + 30) × 365) + number of leap years + current day) × 86400) + current seconds - number of seconds in a day; Among them, the current year is the year in the time information + (2000-1970); the number of leap years is (7 + the year in the time information / 4); the current day and the number of seconds of the day are both directly obtained from the time information; the time information is obtained based on the content of the IRIGB code.
[0009] According to a specific implementation of the embodiment of the present disclosure, judging whether the decoding result is normal based on the absolute number of seconds includes: The absolute number of seconds calculated this time The absolute number of seconds calculated from the previous second For comparison, when When the value of is 1, the decoding is correct; when When the value is not 1, the decoding is incorrect; when the absolute number of seconds does not change after a preset time, the IRIGB code is considered lost.
[0010] In a second aspect, an embodiment of the present disclosure provides an IRIGB code decoding system based on LFSR, the system comprising: An IRIGB code de-jitter module is configured to de-jitter the IRIGB code; A codeword decoding module is configured to decode the de-jittered IRIGB code based on the count of the LFSR to obtain the content of the IRIGB code; A state machine module, configured to store the code elements into corresponding registers according to a preset order by the state machine; The second judgment module is configured to calculate the absolute number of seconds according to the content of the IRIGB code when the last state of the state machine ends; and judge whether the decoding result is normal based on the absolute number of seconds.
[0011] According to a specific implementation of the embodiment of the present disclosure, the system further includes: A register module, configured for the state machine to store the code elements into corresponding registers according to a preset order, comprising: The state machine determines the position of the double P code according to the code element; wherein the P code is a code element with a high level time of 5ms; When receiving the double P code, start recording the data in the IRIGB code, including: Receive the second data in the IRIGB code, and when the P code is received after receiving 8 data code elements, it will enter the minute state; Receive the data in the IRIGB code, and when the P code is received after receiving 9 data code elements, it will enter the time state; Receive the time data in the IRIGB code, and when the P code is received after receiving 9 data code elements, it will enter the day state; Receive the day data in the IRIGB code, and when the P code is received after receiving 9 data code elements, it will enter the 100-day state; Receive the 100-day data in the IRIGB code, and when the P code is received after receiving 9 data code elements, it will switch to the year state; Receive the year data in the IRIGB code, and when the P code is received after receiving 9 data code elements, it will enter the leap second state; Receive leap second data in IRIGB code, and when P code is received after receiving 9 data code elements, it will enter quality state; Receive the quality data in the IRIGB code, and when the P code is received after receiving 9 data code elements, it will enter the binary second 1 state; receiving binary second 1 data in IRIGB code, and when receiving P code after receiving 9 data code elements, switching to binary second 2 state; and, Receive the binary second 2 data in the IRIGB code, and enter the judgment state when the P code is received after receiving 9 data code elements.
[0012] In a third aspect, an embodiment of the present disclosure further provides an electronic device, the electronic device comprising: at least one processor; and, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and when the instructions are executed by the at least one processor, the at least one processor implements the LFSR-based IRIGB code decoding method as described in any one of the first aspect or any one of the implementations of the first aspect.
[0013] In a fourth aspect, an embodiment of the present disclosure further provides a computer program product, comprising a computer program stored on a non-transitory computer-readable storage medium, wherein the computer program comprises program instructions, and when the program instructions are executed by a computer, the computer executes the LFSR-based IRIGB code decoding method in the aforementioned first aspect or any implementation of the first aspect.
[0014] The LFSR-based IRIGB code decoding method of the present invention uses the LFSR calculation method to replace the conventional time accumulation counting method, which greatly reduces the FPGA logic resource occupancy rate. The comparison of absolute seconds can replace the parity check in the IRIGB code, eliminating the situation where the judgment cannot be made when more than two code elements are wrong. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] The above is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.
[0016] Figure 1 A flowchart of an LFSR-based IRIGB code decoding method provided in an embodiment of the present disclosure; Figure 2 A schematic diagram of a state machine module flow chart provided in an embodiment of the present disclosure; Figure 3 A schematic diagram of a module flow of an LFSR-based IRIGB code decoding method provided in an embodiment of the present disclosure; Figure 4 A schematic diagram of the structure of an IRIGB code decoding system based on LFSR provided in an embodiment of the present disclosure; and Figure 5 A schematic diagram of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION
[0017] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.
[0018] The following describes the embodiments of the present disclosure through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.
[0019] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein may be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present disclosure, it should be understood by those skilled in the art that an aspect described herein may be implemented independently of any other aspect, and two or more of these aspects may be combined in various ways. For example, any number of aspects described herein may be used to implement a device and / or practice a method. In addition, other structures and / or functionalities other than one or more of the aspects described herein may be used to implement this device and / or practice this method.
[0020] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects described may be practiced without these specific details.
[0021] LFSR, Linear Feedback Shift Register, usually consists of a shift register and an XOR gate, and is mainly used to generate pseudo-random sequences. The number of registers in an LFSR is called the LFSR level. An n-level LFSR has at most states, that is, an n-level LFSR can only traverse at most However, not all LFSRs can achieve This is related to the design of the tap. Only by choosing a suitable feedback function can the cycle of the sequence reach the maximum value. , the sequence whose period reaches the maximum value is called Although LFSR is used to generate pseudo-random sequences, the data it generates has certain regularities, which is related to its special calculation method. The calculation method of LFSR only includes XOR and displacement, and does not use adders or generate carries, which greatly reduces the resource occupancy of FPGA. Moreover, the more bits are required to be calculated, the more obvious this advantage is.
[0022] Figure 1 A schematic diagram of the process of the LFSR-based IRIGB code decoding method provided in an embodiment of the present disclosure.
[0023] like Figure 1 As shown, at step S110, the IRIGB code is de-jittered.
[0024] In the embodiment of the present invention, the de-jittering of the IRIGB code includes: de-jittering the IRIGB code by digital filtering.
[0025] More specifically, the influence of the circuit or external environment on the IRIGB code signal is reduced by digital filtering. For example, a majority filter is used to determine the signal value within a certain time period according to the amount of recorded data. This method reduces the influence of glitches in the signal source on the decoding module.
[0026] More specifically, the process proceeds to step S120.
[0027] In step S120, the de-jittered IRIGB code is decoded based on the count of the LFSR to obtain the content of the IRIGB code.
[0028] In an embodiment of the present invention, the LFSR-based counting method for decoding the de-jittered IRIGB code includes the following steps: accumulating the code elements of the IRIGB code by cyclic calculation of the LFSR; returning the state of the LFSR to the initial state at the rising edge of the IRIGB code; recording the state of the LFSR at the falling edge of the IRIGB code, and judging the high level time in the code element according to the state, including: when the LFSR state is between 0x82b00, 0x05601, 0x0ac02, 0x15804, 0x2b009, and 0x56012, the high level in the code element is 2ms; when the LFSR state is between 0x536ba, 0xa6d75, 0x4daeb, When the LFSR state is between 0x79a4c, 0xf3499, 0xe6932, 0xcd265, 0x9a4cb, and 0x34996, the high level in the code element is 8ms; when the high level time is 2ms, the code element is considered to be 0; when the high level time is 8ms, the code element is considered to be 1; when the high level time is 5ms, the code element is considered to be P.
[0029] According to the IRIGB code waveform calculated by LFSR, the content of the IRIGB code is decoded.
[0030] Furthermore, the cyclic calculation of LFSR is used to accumulate the code elements of IRIGB code. Each code element is 10ms, and the high and low levels change. If the high level time is 2ms, the code element is considered to be "0"; if the high level time is 8ms, the code element is considered to be "1"; if the high level time is 5ms, the code element is considered to be "P". Therefore, the cyclic calculation of LFSR only needs to be performed within 10ms. If the function uses a 100Mhz clock, then the LFSR must cycle at least 1000000 times. Therefore, LFSR needs to use at least 20-bit registers. In order to maximize the number of cycles, the feedback function is . The initial state of LFSR is 0xfffff. Each calculation shifts the 19th bit to the left by 1 bit, and adds the data of the 19th bit and the 16th bit as the 0th bit of the new data. The whole process only involves shifting and two-bit XOR operations. At the rising edge of the IRIGB code, the state of LFSR is returned to the initial state; at the falling edge, the state of LFSR is recorded, and the high level time in the code element is determined based on this state, and then the type of code element is decoded.
[0031] Next, go to step S130.
[0032] At step S130, the state machine stores the code elements into corresponding registers according to a preset order.
[0033] In an embodiment of the present invention, the state machine stores the code elements in a corresponding register according to a preset order, including: the state machine determines the position of the double P code according to the code elements; wherein the P code is a code element with a high level time of 5ms; when the double P code is received, the data in the IRIGB code starts to be recorded, including: receiving the second data in the IRIGB code, and when the P code is received after receiving 8 data code elements, the state machine enters the minute state; receiving the minute data in the IRIGB code, and when the P code is received after receiving 9 data code elements, the state machine enters the hour state; receiving the hour data in the IRIGB code, and when the P code is received after receiving 9 data code elements, the state machine enters the day state; receiving the day data in the IRIGB code, and when the P code is received after receiving 9 data code elements, the state machine enters the hundred-day state state; receiving hundred-day data in the IRIGB code, when the P code is received after 9 data code elements are received, the state turns to the year state; receiving year data in the IRIGB code, when the P code is received after 9 data code elements are received, the state turns to the leap second state; receiving leap second data in the IRIGB code, when the P code is received after 9 data code elements are received, the state turns to the quality state; receiving quality data in the IRIGB code, when the P code is received after 9 data code elements are received, the state turns to the binary second 1 state; receiving binary second 1 data in the IRIGB code, when the P code is received after 9 data code elements are received, the state turns to the binary second 2 state; receiving binary second 2 data in the IRIGB code, when the P code is received after 9 data code elements are received, the state turns to the judgment state.
[0034] More specifically, different states are set according to the content of the IRIGB code, and the data in the IRIGB code is recorded according to the different states.
[0035] The state machine module is set according to the frame structure of the IRIGB code. After receiving certain data, the state jumps and the state changes according to the "P" code. The data received in each state represents different data, for example, some represent seconds and some represent minutes. Each state has a judgment on the data and P code. If the P code appears abnormal, it is considered that this frame of IRIGB code is abnormal and will not be decoded. Until two consecutive P codes appear, the decoding will start again.
[0036] Next, go to step S140.
[0037] At step S140, when the last state of the state machine ends, the absolute number of seconds is calculated according to the content of the IRIGB code.
[0038] In an embodiment of the present invention, when the last state of the state machine ends, the absolute number of seconds is calculated according to the content of the IRIGB code, including: the absolute number of seconds is calculated as follows: ((((current year + 30) × 365) + number of leap years + current day) × 86400) + current number of seconds - number of seconds in a day; wherein the current year is the year in the time information + (2000-1970); the number of leap years is (7 + number of years in the time information / 4); the current day and the number of seconds of the day are both directly obtained from the time information; the time information is obtained based on the content of the IRIGB code.
[0039] More specifically, at the end of the IRIGB code, that is, when the last state of the state machine ends, the absolute second value is calculated by the decoded code, and the change of the absolute second value is used to judge the correctness of the IRIGB code decoding.
[0040] At the end of the IRIGB code, that is, when the state machine ends its last state, the absolute seconds are calculated using the month, day, year, hour, minute, and second information in the IRIGB code. Since the absolute seconds are counted from 1970, they are increasing all the time. Therefore, the absolute seconds calculated by decoding this time must be 1 greater than the value of the previous second. If it is any other case, it is considered that the decoding is wrong and the IRIGB code of this frame is abnormal. If the absolute seconds do not change for more than 1 and a half seconds, it is considered that the IRIGB code is lost and the state machine needs to be adjusted to the initial state.
[0041] Next, go to step S150.
[0042] In step S150, it is determined whether the decoding result is normal based on the absolute number of seconds.
[0043] In the embodiment of the present invention, judging whether the decoding result is normal based on the absolute number of seconds includes: The absolute number of seconds calculated from the previous second For comparison, when When the value of is 1, the decoding is correct; when When the value is not 1, the decoding is incorrect; when the absolute number of seconds does not change after a preset time, the IRIGB code is considered lost.
[0044] More specifically, when the last state of the state machine ends, the absolute number of seconds is calculated based on the content of the signal decoded at the end of the last state, and the absolute number of seconds is used to determine whether the decoding result is normal.
[0045] like Figure 2 As shown, Figure 2 The following is a flow chart of the state machine module: ① In the idle state, the state machine determines the position of the double "P" code based on the data transmitted by the codeword decoding module. If the double "P" code is received, it starts to enter the next state and starts to record the data in the B code.
[0046] ② In the following states, for different stages, the data output by the codeword decoding module is stored in the corresponding register in the specified order. In this process, every ten codewords are a state, and the transition between each state is based on the "P" code. If the "P" code does not appear where it should appear or appears where it should not appear, the IRIGB code of this frame is considered abnormal. The state machine module must jump to the initial state.
[0047] ③ In the last state of the state machine, use the decoded data to calculate the absolute number of seconds. The absolute number of seconds calculated from the previous second For comparison. If the value of is 1, the decoding is correct, if it is any other value, the decoding is incorrect. If the absolute number of seconds does not change over a certain period of time, the IRIGB code is lost.
[0048] The LFSR-based IRIGB code decoding method proposed in the present invention uses the LFSR calculation method to replace the conventional time accumulation counting method, which greatly reduces the FPGA logic resource occupancy rate. Then, by comparing the absolute number of seconds, the parity check in the IRIGB code can be replaced, eliminating the situation where the error cannot be judged when more than two code elements are in error.
[0049] Figure 4 The LFSR-based IRIGB code decoding system 400 provided by the present invention includes an IRIGB code de-jitter module 410 , a symbol decoding module 420 , a state machine module 430 and a second determination module 440 .
[0050] The IRIGB code de-jitter module 410 is used to de-jitter the IRIGB code; The codeword decoding module 420 is used to decode the de-jittered IRIGB code based on the count of the LFSR to obtain the content of the IRIGB code; The state machine module 430 is used for the state machine to store the code elements into corresponding registers according to a preset order; The second determination module 440 is used to calculate the absolute number of seconds according to the content of the IRIGB code when the last state of the state machine ends; and to determine whether the decoding result is normal based on the absolute number of seconds.
[0051] In an embodiment of the present invention, the system further includes: a register module, which is configured for the state machine to store the code elements into the corresponding registers according to a preset order, including: the state machine determines the position of the double P code according to the code elements; wherein the P code is a code element with a high level time of 5ms; when the double P code is received, the data in the IRIGB code is started to be recorded, including: receiving the second data in the IRIGB code, and when the P code is received after receiving 8 data code elements, the minute state is entered; receiving the minute data in the IRIGB code, and when the P code is received after receiving 9 data code elements, the hour state is entered; receiving the hour data in the IRIGB code, and when the P code is received after receiving 9 data code elements, the day state is entered; receiving the day data in the IRIGB code, and when the P code is received after receiving 9 data code elements, the day state is entered. When receiving the P code after receiving 9 data symbols, it enters the Hundred Days State; when receiving the Hundred Days data in the IRIGB code, it enters the Year State when the P code is received after receiving 9 data symbols; when receiving the Year data in the IRIGB code, it enters the Leap Second State when the P code is received after receiving 9 data symbols; when receiving the Leap Second data in the IRIGB code, it enters the Quality State when the P code is received after receiving 9 data symbols; when receiving the Quality data in the IRIGB code, it enters the Binary Second 1 State when the P code is received after receiving 9 data symbols; when receiving the Binary Second 1 data in the IRIGB code, it enters the Binary Second 2 State when the P code is received after receiving 9 data symbols; and, when receiving the Binary Second 2 data in the IRIGB code, it enters the Judgement State when the P code is received after receiving 9 data symbols.
[0052] See also Figure 5 The present disclosure also provides an electronic device 50, which includes: at least one processor; and, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the LFSR-based IRIGB code decoding method in the aforementioned method embodiment.
[0053] The embodiment of the present disclosure also provides a non-transitory computer-readable storage medium, which stores computer instructions, and the computer instructions are used to enable the computer to execute the LFSR-based IRIGB code decoding method in the aforementioned method embodiment.
[0054] The embodiments of the present disclosure also provide a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium, and the computer program includes program instructions. When the program instructions are executed by a computer, the computer executes the LFSR-based IRIGB code decoding method in the aforementioned method embodiment.
[0055] Reference below Figure 5 , which shows a schematic diagram of the structure of an electronic device 50 suitable for implementing the embodiment of the present disclosure. The electronic device in the embodiment of the present disclosure may include, but is not limited to, mobile terminals such as mobile phones, notebook computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 5 The electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.
[0056] like Figure 5 As shown, the electronic device 50 may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 501, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 502 or a program loaded from a storage device 508 into a random access memory (RAM) 503. In the RAM 503, various programs and data required for the operation of the electronic device 50 are also stored. The processing device 501, the ROM 502, and the RAM 503 are connected to each other via a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.
[0057] Typically, the following devices may be connected to the I / O interface 505: input devices 506 including, for example, a touch screen, a touchpad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; output devices 507 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; storage devices 508 including, for example, a magnetic tape, a hard disk, etc.; and communication devices 509. The communication device 509 may allow the electronic device 50 to communicate with other devices wirelessly or by wire to exchange data. Although the electronic device 50 having various devices is shown in the figure, it should be understood that it is not required to implement or have all the devices shown. More or fewer devices may be implemented or have alternatively.
[0058] In particular, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program contains program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication device 509, or installed from a storage device 508, or installed from a ROM 502. When the computer program is executed by the processing device 501, the above-mentioned functions defined in the method of the embodiment of the present disclosure are executed.
[0059] It should be noted that the computer-readable medium mentioned above in the present disclosure may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, device or device. In the present disclosure, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable program code. This propagated data signal may take a variety of forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. Computer readable signal media may also be any computer readable medium other than computer readable storage media, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. The program code contained on the computer readable medium may be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.
[0060] The computer-readable medium may be included in the electronic device, or may exist independently without being incorporated into the electronic device.
[0061] The computer-readable medium carries one or more programs. When the one or more programs are executed by the electronic device, the electronic device: obtains at least two Internet Protocol addresses; sends a node evaluation request including the at least two Internet Protocol addresses to a node evaluation device, wherein the node evaluation device selects an Internet Protocol address from the at least two Internet Protocol addresses and returns it; receives the Internet Protocol address returned by the node evaluation device; wherein the obtained Internet Protocol address indicates an edge node in a content distribution network.
[0062] Alternatively, the computer-readable medium carries one or more programs, and when the one or more programs are executed by the electronic device, the electronic device: receives a node evaluation request including at least two Internet Protocol addresses; selects an Internet Protocol address from the at least two Internet Protocol addresses; and returns the selected Internet Protocol address; wherein the received Internet Protocol address indicates an edge node in a content distribution network.
[0063] Computer program code for performing the operations of the present disclosure may be written in one or more programming languages or a combination thereof, including object-oriented programming languages such as Java, Smalltalk, C++, and conventional procedural programming languages such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).
[0064] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some implementations as replacements, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.
[0065] The units involved in the embodiments described in the present disclosure may be implemented by software or hardware. The name of a unit does not limit the unit itself in some cases. For example, the first acquisition unit may also be described as a "unit for acquiring at least two Internet Protocol addresses".
[0066] It should be understood that various parts of the present disclosure may be implemented in hardware, software, firmware or a combination thereof.
[0067] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.
Claims
1. A LFSR-based IRIGB code decoding method, characterized in that: The method comprises the following steps: Debounce the IRIGB code; Decoding the de-jittered IRIGB code based on the count of the LFSR to obtain the content of the IRIGB code; The state machine stores the contents of the IRIGB code into corresponding registers according to a preset order; At the end of the last state of the state machine, the absolute number of seconds is calculated according to the content of the IRIGB code; Whether the decoding result is normal is determined based on the absolute number of seconds.
2. The LFSR-based IRIGB code decoding method according to claim 1, characterized in that: The de-jittering the IRIGB code includes: de-jittering the IRIGB code by digital filtering.
3. The LFSR-based IRIGB code decoding method according to claim 1, characterized in that: The LFSR-based counting method decodes the IRIGB code after de-jittering, comprising the following steps: Utilize cyclic calculation of LFSR to accumulate code elements of the IRIGB code; At the rising edge of the IRIGB code, the state of the LFSR is returned to the initial state; at the falling edge of the IRIGB code, the state of the LFSR is recorded, and the high level time in the code element is determined according to the state, including: when the LFSR state is between 0x82b00, 0x05601, 0x0ac02, 0x15804, 0x2b009, and 0x56012, the high level in the code element is 2ms; when the LFSR state is between 0x536ba, 0xa6d75, 0x4daeb, When the LFSR state is between 0x9b5d6, 0x36bac, and 0x6d759, the high level in the code element is 5ms; when the LFSR state is between 0x79a4c, 0xf3499, 0xe6932, 0xcd265, 0x9a4cb, and 0x34996, the high level in the code element is 8ms; Among them, when the high level time is 2ms, the code element is considered to be 0; when the high level time is 8ms, the code element is considered to be 1; when the high level time is 5ms, the code element is considered to be P.
4. The LFSR-based IRIGB code decoding method according to claim 1, characterized in that: The state machine stores the code elements into corresponding registers according to a preset order, including: The state machine determines the position of the double P code according to the code element; wherein the P code is a code element with a high level time of 5ms; When receiving the double P code, start recording the data in the IRIGB code, including: Receive the second data in the IRIGB code, and when the P code is received after receiving 8 data code elements, it will enter the minute state; Receive the data in the IRIGB code, and when the P code is received after receiving 9 data code elements, it will enter the time state; Receive the time data in the IRIGB code, and when the P code is received after receiving 9 data code elements, it will enter the day state; Receive the day data in the IRIGB code, and when the P code is received after receiving 9 data code elements, it will enter the 100-day state; Receive the 100-day data in the IRIGB code, and when the P code is received after receiving 9 data code elements, it will switch to the year state; Receive the year data in the IRIGB code, and when the P code is received after receiving 9 data code elements, it will enter the leap second state; Receive leap second data in IRIGB code, and when P code is received after receiving 9 data code elements, it will enter quality state; Receive the quality data in the IRIGB code, and when the P code is received after receiving 9 data code elements, it will enter the binary second 1 state; Receive binary second 1 data in IRIGB code, and when P code is received after receiving 9 data code elements, it will enter binary second 2 state; Receive the binary second 2 data in the IRIGB code, and enter the judgment state when the P code is received after receiving 9 data code elements.
5. The LFSR-based IRIGB code decoding method according to claim 1, characterized in that: When the state machine ends in the last state, the absolute number of seconds is calculated according to the content of the IRIGB code, including: the absolute number of seconds is calculated as follows: ((((current year + 30) × 365) + number of leap years + current day) × 86400) + current seconds - number of seconds in a day; Among them, the current year is the year in the time information + (2000-1970); the number of leap years is (7 + the year in the time information / 4); the current day and the number of seconds of the day are both directly obtained from the time information; the time information is obtained based on the content of the IRIGB code.
6. The LFSR-based IRIGB code decoding method according to claim 1, characterized in that: Judging whether the decoding result is normal based on the absolute number of seconds includes: The absolute number of seconds calculated this time The absolute number of seconds calculated from the previous second For comparison, when When the value of is 1, the decoding is correct; when When the value is not 1, the decoding is incorrect; when the absolute number of seconds does not change after a preset time, the IRIGB code is considered lost.
7. An IRIGB code decoding system based on LFSR, characterized in that: The system comprises: An IRIGB code de-jitter module is configured to de-jitter the IRIGB code; A codeword decoding module is configured to decode the de-jittered IRIGB code based on the count of the LFSR to obtain the content of the IRIGB code; A state machine module, configured to store the code elements into corresponding registers according to a preset order by the state machine; The second judgment module is configured to calculate the absolute number of seconds according to the content of the IRIGB code when the last state of the state machine ends; and judge whether the decoding result is normal based on the absolute number of seconds.
8. The LFSR-based IRIGB code decoding system according to claim 7, characterized in that: The system further comprises: A register module, configured for the state machine to store the code elements into corresponding registers in a preset order, comprising: The state machine determines the position of the double P code according to the code element; wherein the P code is a code element with a high level time of 5ms; When receiving the double P code, start recording the data in the IRIGB code, including: Receive the second data in the IRIGB code, and when the P code is received after receiving 8 data code elements, it will enter the minute state; Receive the data in the IRIGB code, and when the P code is received after receiving 9 data code elements, it will enter the time state; Receive the time data in the IRIGB code, and when the P code is received after receiving 9 data code elements, it will enter the day state; Receive the day data in the IRIGB code, and when the P code is received after receiving 9 data code elements, it will enter the 100-day state; Receive the 100-day data in the IRIGB code, and when the P code is received after receiving 9 data code elements, it will switch to the year state; Receive the year data in the IRIGB code, and when the P code is received after receiving 9 data code elements, it will enter the leap second state; Receive leap second data in IRIGB code, and when P code is received after receiving 9 data code elements, it will enter quality state; Receive the quality data in the IRIGB code, and when the P code is received after receiving 9 data code elements, it will enter the binary second 1 state; receiving binary second 1 data in IRIGB code, and when receiving P code after receiving 9 data code elements, switching to binary second 2 state; and, Receive the binary second 2 data in the IRIGB code, and enter the judgment state when the P code is received after receiving 9 data code elements.
9. An electronic device, characterized in that: The electronic device includes: at least one processor; and, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and when the instructions are executed by the at least one processor, the at least one processor executes the LFSR-based IRIGB code decoding method according to any one of claims 1 to 6.
10. A computer program product, characterized in that The computer program product comprises a computer program stored on a non-transitory computer-readable storage medium, wherein the computer program comprises program instructions, and when the program instructions are executed by a computer, the computer is caused to execute the LFSR-based IRIGB code decoding method as claimed in any one of claims 1 to 6.