Ultra-wideband software radio signal analysis device

Abstract

The invention discloses an ultra-wideband software radio signal analysis device, which comprises an ultra-high-speed analog-to-digital conversion module, a large-scale signal retrieval FPGA (Field Programmable Gate Array) component and a heterogeneous reconfigurable signal processing system, and is characterized in that the ultra-high-speed analog-to-digital conversion module converts an ultra-wideband analog signal into a digital signal; the obtained digital signals are transmitted to the large-scale signal retrieval FPGA assembly through the high-speed data interface, and the large-scale signal retrieval FPGA assembly completes rapid channelization and signal real-time retrieval and sends the retrieved signals to the heterogeneous reconfigurable signal processing system to complete signal processing calculation. A large-scale signal retrieval FPGA assembly is designed according to the characteristics of high data rate, large calculation demand and the like of ultra-wideband digital signals, signal separation in the bandwidth is realized through signal retrieval logic based on power detection, redundant data is removed, the design difficulty of a heterogeneous reconfigurable signal processing system is reduced, and the design efficiency of the heterogeneous reconfigurable signal processing system is improved. The device has important application value in the aspects of reconnaissance receivers and broadband signal measurement.

Description

Technical Field

[0001] The invention belongs to the technical field of signal processing, and in particular relates to an ultra-wideband software radio signal analysis device applied to ultra-wideband signal detection and measurement. Background Art

[0002] With the advancement of electronic and communication technology, the dedicated frequency band for wireless signals is getting wider and wider, from tens of kHz for audio to GHz-level bandwidth occupied by mobile communications and radar signals. In communication detection and electronic countermeasure reconnaissance reception, there is an urgent need for wide-band ultra-wideband detection containing multi-channel signals and signals of different purposes for detection equipment. In instrumentation occasions, real-time analysis of ultra-wideband signals is of great significance for instantaneous signal detection, interference signal detection and full-band signal census. Therefore, the present invention carries out the design of ultra-wideband software radio signal analysis device for these occasions.

[0003] The problems caused by ultra-wideband signals include digital-to-analog conversion, intensive processing and real-time transmission of ultra-wideband signals, and the need for flexible processing of analysis and processing methods for multiple standard signals. In recent years, with the development of integrated circuit technology, high-speed ADC has developed from GHz level to 10GHz level, providing conditions for ultra-wideband signal analysis. In order to reduce the processing difficulty, it is necessary to perform real-time multi-path separation of signals within the ultra-wideband bandwidth to avoid signal loss, and the development of reconfigurable signal processing systems provides basic conditions for multi-standard signal analysis. Based on these advances, the present invention provides an ultra-wideband software radio signal analysis device for ultra-wideband signal detection and measurement occasions. Summary of the invention

[0004] The purpose of the present invention is to propose an ultra-wideband software radio signal analysis device, which converts ultra-wideband analog signals into digital signals, transmits the obtained digital signals to a large-scale signal retrieval FPGA component via a high-speed data interface, completes fast channelization and real-time signal retrieval, and sends the retrieved signals to a heterogeneous reconfigurable signal processing system to complete signal processing calculations. The device designs a large-scale signal retrieval FPGA component in view of the characteristics of ultra-wideband digital signals, such as high data rate and large computing requirements, and realizes signal separation within the bandwidth through signal retrieval logic based on power detection, thereby removing redundant data.

[0005] The present invention is achieved through the following technical solutions: An ultra-wideband software radio signal analysis device comprises an ultra-high-speed analog-to-digital conversion module, a large-scale signal retrieval FPGA component and a heterogeneous reconfigurable signal processing system.

[0006] Preferably, the ultra-high-speed analog-to-digital conversion module includes a high-speed clock generation circuit, an ultra-wideband analog-to-digital converter and an ultra-wideband data transmission interface.

[0007] Preferably, the large-scale signal retrieval FPGA component includes an ultra-wideband data transmission interface, a high-speed data transmission interface, and a large-scale FPGA that can be used to load ultra-wideband signal retrieval logic.

[0008] Preferably, the heterogeneous reconfigurable signal processing system includes a high-speed data transmission interface, an external interface, a processor system (PS) and a programmable logic (PL).

[0009] Preferably, the ultra-high-speed analog-to-digital conversion module is connected to the large-scale FPGA via the ultra-wideband data transmission interface; Preferably, the large-scale signal retrieval FPGA component is connected to the heterogeneous reconfigurable signal processing system through the high-speed data transmission interface to provide one or more signals retrieved, wherein the bandwidth of the one or more signals is much lower than the originally collected ultra-wideband signal; Preferably, the heterogeneous reconfigurable signal processing system is used to dynamically load different completed signal analysis and measurement algorithms, namely, for strong real-time processing completed by the programmable logic (PL) and weak real-time processing completed by the processor system (PS).

[0010] Preferably, the external interface provided in the heterogeneous reconfigurable signal processing system is a display control interface or an Ethernet interface for human-computer interaction.

[0011] Compared with the prior art, the present invention has the following advantages: 1. The present invention adopts an ultra-wideband data transmission interface and a high-speed data transmission interface to ensure the transmission rate and integrity of data and improve the overall efficiency of the system.

[0012] 2. The present invention performs high-speed data processing through a large-scale signal retrieval FPGA component to achieve rapid channelization and real-time signal retrieval, thereby adapting to the signal characteristics of high-speed ultra-wideband.

[0013] 3. The present invention adopts signal retrieval logic based on power detection, which can effectively realize signal separation within the bandwidth, thereby removing redundant data, improving the accuracy and efficiency of signal processing, reducing the waste of system resources, and reducing the design difficulty of heterogeneous reconfigurable signal processing systems. The device has important application value in reconnaissance receivers and broadband signal measurement.

[0014] 4. The present invention adopts a heterogeneous reconfigurable signal processing system, which can support analysis of signals of different formats. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 The invention provides an overall architecture of an ultra-wideband software radio signal analysis device; Figure 2 The data flow direction and interface rate are designed for an ultra-wideband software radio signal analysis device. DETAILED DESCRIPTION

[0016] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0017] Embodiment 1: See also Figure 1-Figure 2 The present invention provides an ultra-wideband software radio signal analysis device, comprising an ultra-high-speed analog-to-digital conversion module, a large-scale signal retrieval FPGA component, and a heterogeneous reconfigurable signal processing system; the ultra-high-speed analog-to-digital conversion module comprises a high-speed clock generation circuit, an ultra-wideband analog-to-digital converter, and an ultra-wideband data transmission interface; the large-scale signal retrieval FPGA component comprises an ultra-wideband data transmission interface, a large-scale FPGA, and a high-speed data transmission interface; the heterogeneous reconfigurable signal processing system comprises a high-speed data transmission interface, an external interface, a processor system (PS), and a programmable logic (PL).

[0018] Embodiment 2: On the basis of Example 1, more specifically, the sampling rate of the ultra-high-speed analog-to-digital conversion module in the present invention is 40 GSPS, and a domestic ADC chip is used to sample the signal with a bandwidth of 2-16 GHz in real time. In view of the demand for real-time acquisition and analysis of the signal with a bandwidth of 2-16 GHz, the ADC sampling clock frequency is 20 GHz, which is provided by a high-speed clock generation circuit; Among them, ADC selects the AAD08S040G analog-to-digital conversion chip that can meet the required performance. More specifically, the AAD08S040G analog-to-digital conversion chip is a high-speed analog-to-digital conversion chip manufactured using CMOS technology. The parameters of the AAD08S040G analog-to-digital conversion chip include a maximum sampling rate of 40GSPS, an input bandwidth of 18.5GHz, an input full scale (differential) of 600mV, an input common-mode voltage of 200mV, a resolution of 8Bits, ENOB 6.0@5.0GHz (typ, -3dBFS) 4.7@18.5GHz (typ, -3dBFS), SFDR 50dBc@5.0GHz (typ, -3dBFS) 30dBc@18.5GHz (typ, -3dBFS), and a SerDes line rate of 20Gbps*16Lanes (@40GSPS). The clock of the high-speed clock generation circuit is provided by the backplane SMP interface, with the HMC7044 jitter attenuator chip of ADI as the core device. The 20GHz clock signal provided by the backplane SMP interface first enters the variable gain amplifier HMC997LC4, and then enters the bandpass filter BFCQ-1932+ after being output from the HMC997LC4 variable gain amplifier. The insertion loss in the band is only 1.6dB, which can filter out high-frequency harmonics and noise and retain the 20GHz clock signal. The clock signal after bandpass filtering is connected to the ADC clock pin in an AC coupling manner through a 100pF ceramic capacitor; The variable gain amplifier HMC997LC4 has an operating frequency range of 17-27GHz. The output gain can be controlled by controlling the voltage value of the Vctrl pin, and the gain can reach up to 20.5dB. The bandpass filter BFCQ-1932+ has a passband range of 17.7-21GHz. When the ADC sampling rate is too high, the amount of data that needs to be processed also increases. The 16-channel SerDes high-speed signal differential transmission line used by the AAD08S040G analog-to-digital conversion chip has a transmission rate of up to 20Gbps. To ensure real-time data transmission, the ultra-high-speed analog-to-digital conversion module requires no less than 32 channels of high-speed transmission lines of no less than 20Gbps. Specifically, a board-to-board rectangular connector circuit is added to the ultra-high-speed analog-to-digital conversion module to connect to the ADC daughter card as a backup solution. The daughter card consists of the AAD08S040G analog-to-digital conversion chip, the LMX2595 phase-locked loop chip, and the corresponding power module. Faced with high sampling rate data acquisition and processing, large-scale signal retrieval FPGA components require a high-performance and bandwidth-intensive FPGA with sufficient high-speed serial interface resources and ordinary I / O interfaces. Xilinx's VirtexUltex+ series FPGA is selected, and the specific model is XCVU13P-FHGB2104, with the following parameters: system logic unit (K) 3780, CLB Flip-Flops (K) 3456, CLB LUTs (K) 1728, DSP Slices 12288, memory (Mb) 360.0, HPI / O number 832, GTY high-speed transceiver 128, maximum distributed RAM 48.3.

[0019] The large-scale signal retrieval FPGA component and the heterogeneous reconfigurable signal processing system are connected and communicated through the 16x GTY high-speed interface. The data transmission of the high-speed port is implemented based on the Aurora protocol with 64B / 66B encoding. The large-scale signal retrieval FPGA component is the transmitter. Its data first passes through the FIFO to realize cross-clock domain processing, and then passes through the Aurora IP core to encode the data and output it through the high-speed port. The heterogeneous reconfigurable signal processing system acts as the receiving end. The data is first processed by the Aurora IP core, then processed across clock domains by the FIFO, and finally transmitted to the data usage port.

[0020] Specifically, the heterogeneous reconfigurable signal processing system uses the ZU19EG system-on-chip (SoC), and the PS includes a dual-core ARM real-time processor Cortex-R5 and a quad-core 64-bit ARM application processor Cortex-A53; The PS end is composed of a real-time processing unit, an application processing unit, a platform management unit, a storage unit, a GPU unit, a configuration and security unit, a system function unit, high-speed peripherals and ordinary peripheral units. The platform management unit is mainly responsible for system management, power management, and functional assurance; The system function unit is mainly used for multi-channel DMA data transmission control, internal clock and system reset function control between PS and PL; The high-speed peripheral unit is mainly used to connect the interfaces required for high-speed peripherals, such as USB3.0 interface, PCIE interface, SATA3.1 interface, etc. The ordinary peripheral unit is used to provide common low-speed peripheral interface requirements, such as UART interface, SPI interface, USB2.0 interface, etc.

[0021] The PL side includes storage and signal processing modules, system management modules, general I / O interface modules, and high-speed interface modules. The storage and signal processing module contains logic resources such as Block RAM, Ultra RAM, and DSP required for digital signal processing; The system management module is mainly used for reasonable allocation of PL and PS resources to achieve system optimization and reduce equipment power consumption; The general I / O interface module is used as a low-speed interface, such as a serial port and SPI interface; The signal processing module connects to DDR4 and FLASH chips through external interfaces to realize data storage function, realizes human-computer interaction through display control interface, and can be used to realize communication function with host computer through Ethernet interface.

[0022] Embodiment 3: On the basis of Example 1 and Example 2, more specifically, the signal analysis process is: S1: The ultra-wideband analog-to-digital converter collects the analog signal and converts it into an ultra-wideband digital signal, and transmits the digital signal to the large-scale signal retrieval FPGA component through the ultra-wideband data transmission interface; S2: After the large-scale signal retrieval FPGA component receives the digital signal through the ultra-wideband data transmission interface, the large-scale FPGA performs a 50% overlap short-time Fourier transform on the digital signal to achieve digital channelization processing, obtain a frequency domain complex signal, perform a modulo operation, and compare it with the set detection threshold. After the signal is detected, the initial signal is stored in the register and compared with the next detected signal to complete the retrieval. The retrieved signal is transmitted to the high-speed data transmission interface; S3: The heterogeneous reconfigurable signal processing system receives the retrieval signal through the high-speed data transmission interface, sends the retrieval signal to the signal processing unit for real-time signal processing, and sends the processed signal to the external interface after strong real-time processing of the programmable logic and weak real-time processing of the processor system.

[0023] Embodiment 4: On the basis of Example 3, Figure 2 As shown, the data flow direction and interface rate of the 16GHz ultra-wideband analog signal are designed and analyzed by the present invention, the signal ultra-high-speed analog-to-digital conversion module collects the 16GHz analog signal, the sampling rate of the ultra-wideband analog-to-digital converter is 40GSa / s, and the analog signal is sampled and converted into a digital signal; According to the sampling rate, the ultra-wideband data transmission interface needs to meet the rate of 40*8*2Gbit / s to successfully transmit the signal to the large-scale signal retrieval FPGA component. Therefore, the use of 32-channel 20Gbps high-speed transmission lines can meet the real-time transmission of digital signals. After the large-scale signal retrieval FPGA component retrieves the signal, it is converted into a small bandwidth signal by digital signalization. There are 8 channels in total, and the bandwidth of each channel is 100MHz. Therefore, there is a total bandwidth of 8*100MHz. The high-speed data transmission interface needs to meet the rate of 800*8*2Mbit / s, that is, 1.6GB / s.

[0024] The high-speed data transmission interface transmits 8-channel signals to the heterogeneous reconfigurable signal processing system. The 250MHz clock rate on the PL side can meet the signal processing needs of 100MHz bandwidth.

[0025] The present invention adopts an ultra-wideband data transmission interface and a high-speed data transmission interface to ensure the transmission rate and integrity of data and improve the overall efficiency of the system; the present invention performs high-speed data processing through a large-scale signal retrieval FPGA component to achieve rapid channelization and real-time signal retrieval, thereby adapting to the signal characteristics of high-speed ultra-wideband; the present invention adopts a signal retrieval logic based on power detection, which can effectively achieve signal separation within the bandwidth, thereby removing redundant data, improving the accuracy and efficiency of signal processing, and reducing the waste of system resources; the present invention adopts a heterogeneous reconfigurable signal processing system, which can support signal analysis of different standards; in summary, the present invention realizes ultra-wideband analog-to-digital conversion through an ultra-high-speed analog-to-digital conversion module and a large-scale signal retrieval FPGA component, and performs rapid channelization and real-time signal retrieval on ultra-wideband digital signals, thereby achieving high data rate ultra-wideband digital signal processing, reducing the design difficulty of heterogeneous reconfigurable signal processing systems, and the device has important application value in reconnaissance receivers and broadband signal measurement.

[0026] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions. The sentence "includes an element defined by ... does not exclude the existence of other identical elements in the process, method, article or device including the element".

[0027] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. An ultra-wideband software radio signal analysis device, characterized in that: It includes an ultra-high-speed analog-to-digital conversion module, a large-scale signal retrieval FPGA component, and a heterogeneous reconfigurable signal processing system.

2. The ultra-wideband software radio signal analysis device according to claim 1, characterized in that: The ultra-high-speed analog-to-digital conversion module is composed of a high-speed clock generation circuit, an ultra-wideband analog-to-digital converter and an ultra-wideband data transmission interface.

3. The ultra-wideband software radio signal analysis device according to claim 2, characterized in that: The large-scale signal retrieval FPGA component includes an ultra-wideband data transmission interface, a high-speed data transmission interface, and a large-scale FPGA that can be used to load ultra-wideband signal retrieval logic.

4. The ultra-wideband software radio signal analysis device according to claim 3, characterized in that: The heterogeneous reconfigurable signal processing system includes a high-speed data transmission interface, an external interface, a processor system (PS) and a programmable logic (PL).

5. The ultra-wideband software radio signal analysis device according to claim 3, characterized in that: The ultra-high-speed analog-to-digital conversion module is connected to the large-scale FPGA via the ultra-wideband data transmission interface.

6. The ultra-wideband software radio signal analysis device according to claim 4, characterized in that: The large-scale signal retrieval FPGA component is connected to the heterogeneous reconfigurable signal processing system through the high-speed data transmission interface to provide one or more retrieved signals, wherein the bandwidth of the one or more signals is much lower than the originally collected ultra-wideband signal.

7. The ultra-wideband software radio signal analysis device according to claim 4, characterized in that: The heterogeneous reconfigurable signal processing system is used to dynamically load different completed signal analysis and measurement algorithms, namely, for strong real-time processing completed by the programmable logic (PL) and weak real-time processing completed by the processor system (PS).

8. The ultra-wideband software radio signal analysis device according to claim 4, characterized in that: The external interface provided in the heterogeneous reconfigurable signal processing system is a display control interface or an Ethernet interface for human-computer interaction.

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