Printed circuit board

Abstract

The present disclosure relates to a printed circuit board comprising: a glass layer; a plurality of blind cavities penetrating a part of the glass layer from the upper surface or the lower surface of the glass layer, respectively; the plurality of passive elements are respectively arranged in the plurality of blind cavities; and an insulating layer covering the glass layer and at least a portion of each of the plurality of passive elements, and disposed in at least a portion of each of the plurality of blind cavities. At least two blind cavities of the plurality of blind cavities have different depths.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0111716 filed on August 25, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a printed circuit board. Background Art

[0003] As the performance of semiconductors continues to improve, the size of package substrates continues to increase, and the thickness of the core continues to increase to reduce the warpage of large-area substrates. Recently, in order to reduce the pitch of through-vias formed in the core, it has been required to reduce the core thickness, and therefore, the application of glass cores is being considered. In the case of high-performance semiconductors to which glass cores are applied, it is necessary to embed passive components to improve power efficiency and improve power integrity characteristics, and various passive components such as ceramic capacitors or silicon capacitors may be required to improve performance. Summary of the invention

[0004] An aspect of the present disclosure is to provide a printed circuit board having excellent warpage control characteristics by applying a glass layer.

[0005] Another aspect of the present disclosure is to provide a printed circuit board that can embed various types of passive devices in a glass layer.

[0006] Another aspect of the present disclosure is to provide a printed circuit board that can increase capacitance, reduce parasitic inductance, and shorten a power path.

[0007] One of the various solutions proposed by the present disclosure is to form blind cavities with different depths in a glass layer used as a core layer of a substrate, and to also form through cavities as needed, and to respectively arrange and embed passive elements or electronic components including various types of capacitors in the blind cavities and the through cavities.

[0008] For example, according to one aspect of the present disclosure, a printed circuit board is provided, the printed circuit board comprising: a glass layer; a plurality of blind cavities, each penetrating a portion of the glass layer from an upper surface or a lower surface of the glass layer; a plurality of passive components, each disposed in the plurality of blind cavities; and an insulating layer, covering the glass layer and at least a portion of each of the plurality of passive components and disposed in at least a portion of each of the plurality of blind cavities. At least two of the plurality of blind cavities have different depths.

[0009] For example, according to one aspect of the present disclosure, a printed circuit board is provided, comprising: a glass layer; a blind cavity penetrating a portion of the glass layer from an upper surface or a lower surface of the glass layer; a through cavity penetrating the glass layer between the upper surface and the lower surface of the glass layer; a passive element disposed in the blind cavity; an electronic component disposed in the through cavity; and an insulating layer covering at least a portion of each of the glass layer, the passive element, and the electronic component, and disposed in at least a portion of each of the blind cavity and the through cavity.

[0010] For example, according to one aspect of the present disclosure, a printed circuit board is provided, comprising: a glass layer; a first blind cavity penetrating a first portion of the glass layer from an upper surface of the glass layer; a second blind cavity penetrating a second portion of the glass layer from a lower surface of the glass layer; a first passive element and a second passive element, respectively disposed in the first blind cavity and the second blind cavity, and connected to each other through a first via layer, the first via layer being disposed in a portion of the glass layer between the first blind cavity and the second blind cavity; and an insulating layer covering the glass layer, at least a portion of each of the first passive element and the second passive element, and disposed in at least a portion of each of the first blind cavity and the second blind cavity.

[0011] The present disclosure has the effect of providing a printed circuit board having excellent warpage control characteristics by applying a glass layer.

[0012] Another effect of the present disclosure is to provide a printed circuit board which can embed various types of passive devices in a glass layer.

[0013] Another effect of the present disclosure is to provide a printed circuit board which can increase capacitance, reduce parasitic inductance, and shorten a power path. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which: Figure 1 is a block diagram schematically illustrating an example embodiment of an electronic device system; Figure 2 is a perspective view schematically illustrating an example embodiment of an electronic device; Figure 3 is a cross-sectional view schematically illustrating an example embodiment of a printed circuit board; Figure 4 It is schematically shown Figure 3 A cross-sectional view of a modified example embodiment of a printed circuit board; FIG. 5A to FIG. 5G is a schematic diagram showing the manufacturing Figure 3 A process cross-sectional view of an exemplary embodiment of a printed circuit board; Figure 6 is a cross-sectional view schematically illustrating another example embodiment of a printed circuit board; Figure 7 It is schematically shown Figure 6 A cross-sectional view of a modified example embodiment of a printed circuit board; FIG. 8A to FIG. 8H is a schematic diagram showing the manufacturing Figure 6 A process cross-sectional view of an exemplary embodiment of a printed circuit board; Fig. 9 is a cross-sectional view schematically illustrating another example embodiment of a printed circuit board; Fig.10 It is schematically shown Fig. 9 A cross-sectional view of a modified example embodiment of a printed circuit board; and FIG. 11A to FIG. 11H is a schematic diagram showing the manufacturing Fig. 9 A process cross-sectional view of an example embodiment of a printed circuit board is shown. DETAILED DESCRIPTION

[0015] Hereinafter, the present disclosure will be described with reference to the accompanying drawings. In the accompanying drawings, the shapes and sizes of elements may be exaggerated or reduced for clearer explanation.

[0016] Electronic Devices Figure 1 is a block diagram schematically illustrating an example embodiment of an electronic device system.

[0017] Reference Figure 1 , the electronic device 1000 accommodates a main board 1010 therein. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to the main board 1010. These components are also connected to other electronic components to be described below through various signal lines 1090.

[0018] The chip-related components 1020 may include: memory chips, such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM, flash memory), etc.; application processor chips, such as central processing units (e.g., CPU), graphics processors (e.g., GPU), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific ICs (ASICs), etc. However, the chip-related components 1020 are not limited thereto, and may also include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other. The chip-related components 1020 may have the form of a package including the above-mentioned chips or electronic components.

[0019] The network-related components 1030 may include components that are compatible with or communicate according to protocols such as: Wireless Fidelity (Wi-Fi) (such as the IEEE 802.11 series), Worldwide Interoperability for Microwave Access (WiMAX) (such as the IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High Speed ​​Packet Access Plus (HSPA+), High Speed ​​Downlink Packet Access Plus (HSDPA+), High Speed ​​Uplink Packet Access Plus (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, Wireless Local Area Network (wireless LAN), third generation mobile communication technology (3G) protocols, fourth generation mobile communication technology (4G) protocols, and fifth generation mobile communication technology (5G) protocols, as well as any other wireless standards or protocols and wired standards or protocols specified hereafter. However, the network-related component 1030 is not limited thereto, and may also include a component that is compatible with or communicates according to any one of a plurality of other wireless standards or protocols and wired standards or protocols. In addition, the network-related component 1030 may be combined with the chip-related component 1020.

[0020] Other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, other components are not limited thereto, and may also include passive components in the form of chip components for various other purposes. In addition, other components 1040 may be combined with chip-related components 1020 and / or network-related components 1030.

[0021] Depending on the type of the electronic device 1000, the electronic device 1000 may include other electronic components that are physically and / or electrically connected to the mainboard 1010 or that are not physically and / or electrically connected to the mainboard 1010. These other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, and a battery 1080. However, these other electronic components are not limited thereto, but may also include an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a compact disk (CD) drive, a digital versatile disk (DVD) drive, etc. In addition to this, depending on the type of the electronic device 1000, the electronic device 1000 may also include other electronic components for various purposes.

[0022] The electronic device 1000 may be a smart phone, a personal digital assistant, a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet personal computer (PC), a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automotive component. However, the electronic device 1000 is not limited thereto and may be any other electronic device capable of processing data.

[0023] Figure 2 is a perspective view schematically illustrating an example embodiment of an electronic device.

[0024] Reference Figure 2 , the electronic device may be, for example, a smart phone 1100. A mainboard 1110 may be housed in the smart phone 1100, and various components 1120 may be physically and / or electrically connected to the mainboard 1110. In addition, other electronic components (such as a camera module 1130 and / or a speaker 1140) that are physically and / or electrically connected to the mainboard 1110 or that are not physically and / or electrically connected to the mainboard 1110 may be housed in the smart phone 1100. Some of the components 1120 may be the above-mentioned chip-related components, for example, a component package 1121, but the present disclosure is not limited thereto. The component package 1121 may have the form of a printed circuit board on which an electronic component including active components and / or passive components is surface-mounted. Alternatively, the component package 1121 may have the form of a printed circuit board in which an electronic component including active components and / or passive components is embedded. On the other hand, the electronic device is not necessarily limited to the smart phone 1100, and may be other electronic devices as described above.

[0025] Printed Circuit Board Figure 3 is a cross-sectional view schematically illustrating an example embodiment of a printed circuit board.

[0026] Reference Figure 3A printed circuit board 100A according to an example embodiment may include: a glass layer 111; a first blind cavity C1, a second blind cavity C2, a third blind cavity C3, and a fourth blind cavity C4, the first blind cavity C1 and the second blind cavity C2 penetrating a portion of the glass layer 111 from an upper surface of the glass layer 111, and the third blind cavity C3 and the fourth blind cavity C4 penetrating a portion of the glass layer 111 from a lower surface of the glass layer 111; a first passive component 151, a second passive component 152, a third passive component 153, and a fourth passive component 154, which are respectively disposed in the first blind cavity C1, the second blind cavity C2, the third blind cavity C3, and the fourth blind cavity C4. The printed circuit board 100A includes a first blind cavity C1, a second blind cavity C2, a third blind cavity C3, and a fourth blind cavity C4; a through cavity H penetrating the glass layer 111 between the upper surface and the lower surface of the glass layer 111; an electronic component 155 disposed in the through cavity H; and an insulating layer 112 covering at least a portion of each of the glass layer 111, the first passive component 151, the second passive component 152, the third passive component 153, the fourth passive component 154, and the electronic component 155 and filling at least a portion of each of the first blind cavity C1, the second blind cavity C2, the third blind cavity C3, and the fourth blind cavity C4. At least two of the first blind cavity C1, the second blind cavity C2, the third blind cavity C3, and the fourth blind cavity C4 may have different depths. Based on the thickness direction of the printed circuit board 100A, the first blind cavity C1 and the third blind cavity C3 may at least partially overlap each other, and the second blind cavity C2 and the fourth blind cavity C4 may at least partially overlap each other. The electronic component 155 may be thicker than each of the first passive element 151, the second passive element 152, the third passive element 153, and the fourth passive element 154. For example, the electronic component 155 may include a high-capacitance ceramic capacitor, and each of the first passive element 151, the second passive element 152, the third passive element 153, and the fourth passive element 154 may include a silicon capacitor having low parasitic inductance.

[0027] In addition, the printed circuit board 100A according to the example embodiment may include a plurality of blind cavities and a plurality of passive components. The plurality of blind cavities penetrate a portion of the glass layer 111 from the upper surface or the lower surface of the glass layer 111, respectively. The plurality of passive components are respectively disposed in the plurality of blind cavities. The insulating layer 112 covers at least a portion of each of the glass layer 111 and the plurality of passive components and is disposed in at least a portion of each of the plurality of blind cavities. At least two of the plurality of blind cavities have different depths.

[0028] In this way, the printed circuit board 100A according to the example embodiment may include the glass layer 111 as the core layer, and thus, warpage may be easily controlled even in various situations. In addition, the first blind cavity C1, the second blind cavity C2, the third blind cavity C3, and the fourth blind cavity C4 having various depths may be formed in the glass layer 111, and the first passive element 151, the second passive element 152, the third passive element 153, and the fourth passive element 154 may be respectively disposed in the first blind cavity C1, the second blind cavity C2, the third blind cavity C3, and the fourth blind cavity C4 having various depths. A through cavity H may be further formed as needed, and an electronic component 155 may be disposed in the through cavity H. In this case, the first passive element 151, the second passive element 152, the third passive element 153, the fourth passive element 154, and the electronic component 155 may include various types of capacitors. Therefore, various types of capacitors may be disposed at various locations on the printed circuit board 100A, thereby improving power efficiency and improving signal integrity (SI) characteristics and power integrity (PI) characteristics. In addition, the first passive element 151 and the third passive element 153 may be connected in parallel, and / or the second passive element 152 and the fourth passive element 154 may be connected in parallel. Therefore, effects such as increased capacitance, reduced parasitic inductance, and shortened power path may be achieved.

[0029] In addition, the printed circuit board 100A according to the example embodiment may further include: a first wiring layer 121, which is arranged on the bottom surface of the first blind cavity C1 and the second blind cavity C2; a second wiring layer 122, which is arranged on the bottom surface of the third blind cavity C3 and the fourth blind cavity C4; a third wiring layer 123 and a fourth wiring layer 124, which are respectively arranged on the upper surface and the lower surface of the glass layer 111; a fifth wiring layer 125 and a sixth wiring layer 126, which are respectively arranged on the upper surface and the lower surface of the insulating layer 112; a first via layer 131, which penetrates the glass layer 111 between the first blind cavity C1 and the third blind cavity C3 and between the second blind cavity C2 and the fourth blind cavity C4; a second via layer 132, which penetrates the glass layer 111 between the upper surface and the lower surface of the glass layer 111; a third via layer 133, which penetrates a portion of the upper side of the insulating layer 112; and a fourth via layer 134, which penetrates a portion of the lower side of the insulating layer 112. Each of the first passive element 151, the second passive element 152, the third passive element 153 and the fourth passive element 154 may include a through silicon via v, and the through silicon via v of each of the first passive element 151 and the second passive element 152 may be connected to at least a portion of the first wiring layer 121 through the first electrical connection metal 160, and the through silicon via v of each of the third passive element 153 and the fourth passive element 154 may be connected to at least a portion of the second wiring layer 122 through the first electrical connection metal 160. Each of the first passive element 151, the second passive element 152, the third passive element 153, and the fourth passive element 154 may have a connection pad p, and the connection pad p of each of the first passive element 151 and the second passive element 152 may be connected to at least a portion of the fifth wiring layer 125 through at least a portion of the third via layer 133, and the connection pad p of each of the third passive element 153 and the fourth passive element 154 may be connected to at least a portion of the sixth wiring layer 126 through at least a portion of the fourth via layer 134. The electronic component 155 may have an external electrode P, and the external electrode P of the electronic component 155 may be connected to at least a portion of each of the fifth wiring layer 125 and the sixth wiring layer 126 through at least a portion of each of the third via layer 133 and the fourth via layer 134, respectively.

[0030] In this manner, in the printed circuit board 100A according to the example embodiment, the first wiring layer 121 may be disposed on the bottom surface of each of the first blind cavity C1 and the second blind cavity C2, the second wiring layer 122 may be disposed on the bottom surface of each of the third blind cavity C3 and the fourth blind cavity C4, and the first passive element 151 and the second passive element 152 may be respectively connected to the first wiring layer 121, and the third passive element 153 and the fourth passive element 154 may be respectively connected to the second wiring layer 122. In addition, each of the first passive element 151, the second passive element 152, the third passive element 153, and the fourth passive element 154 may include a through silicon via v. Therefore, parallel connection between silicon capacitors may be more easily achieved. In addition, the first passive element 151, the second passive element 152, the third passive element 153, the fourth passive element 154, and the electronic component 155 can be more easily electrically connected to the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, the fourth wiring layer 124, the fifth wiring layer 125, and the sixth wiring layer 126 in the printed circuit board 100A. Therefore, power efficiency can be more effectively improved, and signal integrity (SI) characteristics and power integrity (PI) characteristics can be more effectively improved. In addition, increased capacitance, reduced parasitic inductance, and shortened power paths can be more effectively achieved.

[0031] Hereinafter, components of a printed circuit board 100A according to example embodiments will be described in more detail with reference to the accompanying drawings.

[0032] The glass layer 111 may include glass as an amorphous solid. The glass may include, for example, pure silicon dioxide (about 100% SiO2), soda-lime glass, borosilicate glass, and aluminosilicate glass. However, the present disclosure is not limited thereto, and optional glass materials (such as fluorine glass, phosphate glass, chalcogenide glass, etc.) may also be used. In addition, other additives may be further included to form glass with specific physical properties. These additives may include at least one of magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, antimony, and carbonates of these and other elements (such as calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda)) and / or oxides. The glass layer 111 may be a layer different from a layer formed using an organic insulating material (e.g., copper clad laminate (CCL) and prepreg (PPG)) including glass fibers (such as glass fabric, for example, glass cloth). For example, the glass layer 111 may include flat glass.

[0033] The insulating layer 112 may include an insulating material. The insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a material prepared by impregnating an inorganic filler, an organic filler, and / or a glass fiber (such as a glass fabric exemplified by glass cloth) in a resin. For example, the insulating material may be a non-photosensitive insulating material (such as Ajinomoto built-up film (ABF) or prepreg (PPG)), but the present disclosure is not limited thereto, and other polymer materials may be used. In addition, the insulating material may be a photosensitive insulating material, such as a photosensitive dielectric (PID). The insulating layer 112 may include a plurality of layers, but their boundaries may not be clear after curing.

[0034] Each of the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, the fourth wiring layer 124, the fifth wiring layer 125, and the sixth wiring layer 126 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The metal material may preferably include copper (Cu), but the present disclosure is not limited thereto. Each of the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, the fourth wiring layer 124, the fifth wiring layer 125, and the sixth wiring layer 126 may perform various functions according to the design. For example, each of the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, the fourth wiring layer 124, the fifth wiring layer 125, and the sixth wiring layer 126 may include a signal pattern, a power pattern, and / or a ground pattern. Each of these patterns may have various forms such as lines, planes, and pads. Each of the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, the fourth wiring layer 124, the fifth wiring layer 125, and the sixth wiring layer 126 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Alternatively, each of the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, the fourth wiring layer 124, the fifth wiring layer 125, and the sixth wiring layer 126 may include a metal foil (e.g., a copper foil) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Alternatively, each of the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, the fourth wiring layer 124, the fifth wiring layer 125, and the sixth wiring layer 126 may include a metal foil (e.g., a copper foil), an electroless plating layer (e.g., a chemical copper plating layer), and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Each of the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, the fourth wiring layer 124, the fifth wiring layer 125 and the sixth wiring layer 126 may include a sputtered layer instead of an electroless plating layer (e.g., a chemical copper plating layer), and may include both an electroless plating layer (e.g., a chemical copper plating layer) and a sputtered layer as needed.

[0035] Each of the first via layer 131 and the second via layer 132 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or alloys thereof. The metal material may preferably include copper (Cu), but the present disclosure is not limited thereto. Each of the first via layer 131 and the second via layer 132 may include a glass through-hole. For example, the glass through-hole of the first via layer 131 may include a plated through hole (PTH) formed by filling the first through hole 131v penetrating the glass layer 111 with the above-mentioned metal material. The glass through-hole of the second via layer 132 may include a plated through hole (PTH) formed conformally by plating the above-mentioned metal material on the wall surface of the second through hole 132v penetrating the glass layer 111 and by filling the inside of the second through hole 132v with an insulating material. The glass through-hole of each of the first via layer 131 and the second via layer 132 may perform various functions according to the design of the corresponding layer. For example, each of the first via layer 131 and the second via layer 132 may include a ground via, a power via, and / or a signal via. Each of the first via layer 131 and the second via layer 132 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer), but the present disclosure is not limited thereto. Each of the first via layer 131 and the second via layer 132 may include a sputtering layer instead of an electroless plating layer, and may include both an electroless plating layer (e.g., a chemical copper plating layer) and a sputtering layer as needed.

[0036] Each of the third via layer 133 and the fourth via layer 134 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or their alloys. The metal material may preferably include copper (Cu), but the present disclosure is not limited thereto. Each of the third via layer 133 and the fourth via layer 134 may include a micro via. The micro via may be a filled via formed by filling a via hole with a metal material or a conformal via formed by arranging a metal material along the wall surface of the via hole. The micro via may be arranged in a stacked type and / or an interlaced type. The micro vias of each of the third via layer 133 and the fourth via layer 134 may perform various functions according to the design of the corresponding layer. For example, each of the third via layer 133 and the fourth via layer 134 may include a ground via, a power via and / or a signal via. Each of the third via layer 133 and the fourth via layer 134 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer), but the present disclosure is not limited thereto. Each of the third via layer 133 and the fourth via layer 134 may include a sputtering layer instead of an electroless plating layer, and may include both a sputtering layer and an electroless plating layer as required. The third via layer 133 and the fourth via layer 134 may have a shape that tapers in opposite directions.

[0037] The first via layer 131 may penetrate the glass layer 111 between the first blind cavity C1 and the third blind cavity C3 and between the second blind cavity C2 and the fourth blind cavity C4, and may connect at least a portion of each of the first wiring layer 121 and the second wiring layer 122 to each other. The second via layer 132 may penetrate the glass layer 111 between the upper surface and the lower surface of the glass layer 111 to connect at least a portion of each of the third wiring layer 123 and the fourth wiring layer 124 to each other. The third via layer 133 may penetrate a portion of the upper side of the insulating layer 112, and may connect at least a portion of each of the third wiring layer 123 and the fifth wiring layer 125 to each other. The fourth via layer 134 may penetrate a portion of the lower side of the insulating layer 112, and may connect at least a portion of each of the fourth wiring layer 124 and the sixth wiring layer 126 to each other.

[0038] Each of the first passive element 151, the second passive element 152, the third passive element 153, and the fourth passive element 154 may include a chip capacitor. The chip capacitor may include a silicon capacitor. Each silicon capacitor may include a connection pad p and a silicon through-via v. Each of the connection pad p and the silicon through-via v may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The first passive element 151, the second passive element 152, the third passive element 153, and the fourth passive element 154 may have the same thickness or different thicknesses. For example, the first passive element 151 and the third passive element 153 may have substantially the same thickness. In addition, the first passive element 151 and the third passive element 153 may have different thicknesses from the second passive element 152 and the fourth passive element 154. From this perspective, the first blind cavity C1 and the third blind cavity C3 may have substantially the same depth. In addition, the first blind cavity C1 and the third blind cavity C3 may have different depths from the second blind cavity C2 and the fourth blind cavity C4. However, this is only an example, and the thicknesses of the first passive element 151, the second passive element 152, the third passive element 153, and the fourth passive element 154 and the depths of the first blind cavity C1, the second blind cavity C2, the third blind cavity C3, and the fourth blind cavity C4 may have various relationships. Disposing the first passive element 151, the second passive element 152, the third passive element 153, and the fourth passive element 154 in the first blind cavity C1, the second blind cavity C2, the third blind cavity C3, and the fourth blind cavity C4, respectively, may include disposing at least a portion of each of the first passive element 151, the second passive element 152, the third passive element 153, and the fourth passive element 154 in the first blind cavity C1, the second blind cavity C2, the third blind cavity C3, and the fourth blind cavity C4, respectively.

[0039] The electronic component 155 may be a chip-type component, and may be an active component or a passive component. For example, the electronic component 155 may be: a memory chip, such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM, flash memory), etc.; an application processor chip, such as a central processing unit (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, etc.; or a logic chip, such as an analog-to-digital converter, an application-specific IC (ASIC), etc. Optionally, the electronic component 155 may be a passive component, such as a high-frequency inductor, a ferrite inductor, a power inductor, a ferrite bead, a low-temperature co-fired ceramic (LTCC) component, an electromagnetic interference (EMI) filter, and a multilayer ceramic capacitor (MLCC). The electronic component 155 may preferably be a ceramic capacitor, such as a multilayer ceramic capacitor (MLCC). The electronic component 155 may have an external electrode P including copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or an alloy thereof. Disposing the electronic component 155 in the through-cavity H may include disposing at least a portion of the electronic component 155 in the through-cavity H.

[0040] The first electrical connection metal 160 may be formed using a low melting point metal (e.g., solder (such as tin (Sn)-aluminum (Al)-copper (Cu) solder)), etc.), but this is only an example, and the material of the first electrical connection metal 160 is not particularly limited thereto. The first electrical connection metal 160 may be formed in a multi-layer or a single layer. When the first electrical connection metal 160 is formed in a multi-layer structure, the first electrical connection metal 160 may include a copper column and a solder, and when the first electrical connection metal 160 is formed in a single-layer structure, the first electrical connection metal 160 may include a tin-silver solder or copper, but the present disclosure is not limited thereto.

[0041] Figure 4 It is schematically shown Figure 3 A cross-sectional view of a modified example embodiment of a printed circuit board.

[0042] Reference Figure 4Compared with the printed circuit board 100A according to the above-mentioned example embodiment, the printed circuit board 500A according to the modified example embodiment may further include: a first stacking insulating layer 113 and a second stacking insulating layer 114, which are respectively arranged on the upper surface and the lower surface of the insulating layer 112; a first stacking wiring layer 127, which is arranged on the upper surface of the first stacking insulating layer 113; a second stacking wiring layer 128, which is arranged on the lower surface of the second stacking insulating layer 114; a first stacking via layer 135, which penetrates the first stacking insulating layer 113; a second stacking via layer 136, which penetrates the second stacking insulating layer 114; a first resist layer 141, which is arranged on the upper surface of the first stacking insulating layer 113 and covers at least a portion of the first stacking wiring layer 127; a second resist layer 142, which is arranged on the lower surface of the second stacking insulating layer 114 and covers at least a portion of the second stacking wiring layer 128; and a semiconductor chip 200, which is arranged on the first resist layer 141 and connected to the first stacking wiring layer 127 through a second electrical connection metal 210.

[0043] In this way, the printed circuit board 500A according to the modified example embodiment may include the printed circuit board 100A according to the above-mentioned example embodiment as a package board in which the first passive component 151, the second passive component 152, the third passive component 153, the fourth passive component 154 and the electronic component 155 are embedded, and may have the form of a semiconductor package on which the semiconductor chip 200 is mounted.

[0044] Hereinafter, components of a printed circuit board 500A according to a modified example embodiment will be described in more detail with reference to the accompanying drawings.

[0045] Each of the first stacked insulating layer 113 and the second stacked insulating layer 114 may include an insulating material. The insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a material prepared by impregnating an inorganic filler, an organic filler, and / or a glass fiber (such as a glass fabric such as glass cloth) in a resin. For example, the insulating material may be a non-photosensitive insulating material such as an Ajinomoto stacked film (ABF) or a prepreg (PPG), but the present disclosure is not limited thereto, and other polymer materials may be used as the insulating material. The insulating material may be a photosensitive insulating material such as a photosensitive dielectric (PID).

[0046] Each of the first buildup wiring layer 127 and the second buildup wiring layer 128 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or alloys thereof. The metal material may preferably include copper (Cu), but the present disclosure is not limited thereto. Each of the first buildup wiring layer 127 and the second buildup wiring layer 128 may perform various functions according to the design. For example, each of the first buildup wiring layer 127 and the second buildup wiring layer 128 may include a signal pattern, a power pattern and / or a ground pattern. Each of these patterns may have various forms such as lines, surfaces, and pads. Each of the first buildup wiring layer 127 and the second buildup wiring layer 128 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Alternatively, each of the first buildup wiring layer 127 and the second buildup wiring layer 128 may include a metal foil (e.g., a copper foil) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Alternatively, each of the first buildup wiring layer 127 and the second buildup wiring layer 128 may include a metal foil (e.g., a copper foil), an electroless plating layer (e.g., a chemical copper plating layer), and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Each of the first buildup wiring layer 127 and the second buildup wiring layer 128 may include a sputtering layer instead of an electroless plating layer (e.g., a chemical copper plating layer), and may include both a sputtering layer and an electroless plating layer (e.g., a chemical copper plating layer) as needed.

[0047] Each of the first stacked via layer 135 and the second stacked via layer 136 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or alloys thereof. The metal material may preferably include copper (Cu), but the present disclosure is not limited thereto. Each of the first stacked via layer 135 and the second stacked via layer 136 may include a micro via. The micro via may be a filled via formed by filling a via hole with a metal material or a conformal via formed by arranging a metal material along the wall surface of the via hole. The micro via may be arranged in a stacked type and / or a staggered type. The micro vias of each of the first stacked via layer 135 and the second stacked via layer 136 may perform various functions according to the design of the corresponding layer. For example, each of the first stacked via layer 135 and the second stacked via layer 136 may include a ground via, a power via and / or a signal via. Each of the first stacked via layer 135 and the second stacked via layer 136 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer), but the present disclosure is not limited thereto. Each of the first stacked via layer 135 and the second stacked via layer 136 may include a sputtering layer instead of an electroless plating layer, and may include both a sputtering layer and an electroless plating layer as required. The first stacked via layer 135 and the second stacked via layer 136 may have a shape that tapers in opposite directions. The first stacked via layer 135 may connect at least a portion of each of the fifth wiring layer 125 and the first stacked wiring layer 127 to each other. The second stacked via layer 136 may connect at least a portion of each of the sixth wiring layer 126 and the second stacked wiring layer 128 to each other.

[0048] Each of the first resist layer 141 and the second resist layer 142 may include a liquid solder resist or a film type solder resist, but the present disclosure is not limited thereto, and each of the first resist layer 141 and the second resist layer 142 may include other types of insulating materials such as ABF. The first resist layer 141 may have an opening that exposes at least a portion of the first build-up wiring layer 127, the second resist layer 142 may have an opening that exposes at least a portion of the second build-up wiring layer 128, and a surface treatment layer may be formed on the exposed pattern as needed.

[0049] The semiconductor chip 200 may include an integrated circuit (IC) chip in which hundreds to millions of elements are integrated into one chip. In this case, for example, the integrated circuit may be: an application processor chip, such as a central processing unit (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, an application processor (AP); or a logic chip, such as a field programmable gate array (FPGA), an analog-to-digital converter, or an application specific IC (ASIC), but the present disclosure is not limited thereto, and the integrated circuit may be: a memory chip, such as a volatile memory (e.g., DRAM, high bandwidth memory (HBM)), a non-volatile memory (e.g., ROM, flash memory), etc.; or other types of chips, such as a power management IC (PMIC).

[0050] The semiconductor chip 200 may be formed based on an effective wafer, in which case silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. may be used as a substrate for forming the body of the semiconductor chip 200. Various circuits may be formed in the body. A connection pad may be formed on the body, and the connection pad may include a conductive material such as aluminum (Al) or copper (Cu). The semiconductor chip 200 may be a bare die, and in this case, a metal bump may be provided on the connection pad. The semiconductor chip 200 may be a packaged chip, in which case a redistribution layer may be further formed on the connection pad, and the metal bump may be provided on the redistribution layer.

[0051] The second electrical connection metal 210 may be formed using a low melting point metal, for example, solder (such as tin (Sn)-aluminum (Al)-copper (Cu) solder), but this is merely an example, and the material of the second electrical connection metal 210 is not particularly limited thereto. The second electrical connection metal 210 may be formed in multiple layers or in a single layer. When the second electrical connection metal 210 is formed in multiple layers, the second electrical connection metal 210 may include a copper column and solder, and when the second electrical connection metal 210 is formed in a single layer, the second electrical connection metal 210 may include tin-silver solder or copper, but the present disclosure is not limited thereto.

[0052] The other contents are substantially the same as those described in the printed circuit board 100A according to the above-described exemplary embodiment, and thus redundant descriptions thereof will be omitted.

[0053] FIG. 5A to FIG. 5G is a schematic diagram showing the manufacturing Figure 3 A process cross-sectional view of an example embodiment of a printed circuit board is shown.

[0054] Reference Figure 5A, prepare a glass layer 111. The glass layer 111 may be in the form of a flat glass. Next, a first blind cavity C1, a second blind cavity C2, a third blind cavity C3, a fourth blind cavity C4, a through cavity H, and a second through hole 132v are formed in the glass layer 111. The first blind cavity C1, the second blind cavity C2, the third blind cavity C3, the fourth blind cavity C4, the through cavity H, and the second through hole 132v may be formed by etching using a mask, but the present disclosure is not limited thereto. In addition, when the glass layer 111 is used, the depths of the first blind cavity C1, the second blind cavity C2, the third blind cavity C3, and the fourth blind cavity C4 may be easily adjusted, and various depths may be formed. In addition, the glass layer 111 has a high rigidity characteristic, and even if the gaps between the first blind cavity C1, the second blind cavity C2, the third blind cavity C3, and the fourth blind cavity C4 are narrow, the risk of deformation may be reduced.

[0055] Reference Figure 5B , a first through hole 131v is formed in the glass layer 111. The first through hole 131v may also be formed by etching using a mask, but the present disclosure is not limited thereto. Even in this case, the above-described effects may be achieved by the glass layer 111.

[0056] Reference Figure 5C , a first wiring layer 121, a second wiring layer 122, and a first via layer 131 are formed on the glass layer 111. The first wiring layer 121, the second wiring layer 122, and the first via layer 131 may be formed by a plating process, and may be formed using, for example, an additive process (AP), a semi-AP (SAP), a modified SAP (MSAP), a via sealing (TT) process, and the like.

[0057] Reference Figure 5D , a third wiring layer 123, a fourth wiring layer 124, and a second via layer 132 are formed on the glass layer 111. The third wiring layer 123, the fourth wiring layer 124, and the second via layer 132 may also be formed by a plating process, and may be formed using, for example, an additive process (AP), a semi-AP (SAP), a modified SAP (MSAP), a via sealing (TT) process, etc. When the second via layer 132 is formed, a plugging process may be further performed after the plating process.

[0058] Reference Figure 5E, the first passive element 151, the second passive element 152, the third passive element 153, and the fourth passive element 154 may be respectively disposed in the first blind cavity C1, the second blind cavity C2, the third blind cavity C3, and the fourth blind cavity C4. In this case, the first passive element 151 and the second passive element 152 may be connected to the first wiring layer 121 through the first electrical connection metal 160, and the third passive element 153 and the fourth passive element 154 may be connected to the second wiring layer 122 through the first electrical connection metal 160. On the other hand, when the glass layer 111 is used, the risk of deformation due to heat may be low even if soldering is performed on a narrow gap.

[0059] Reference Fig. 5F , the electronic component 155 is disposed in the through cavity H. For example, the electronic component 155 may be disposed in the through cavity H by attaching the tape 310 to the lower side of the glass layer 111 and then attaching the electronic component 155 to the tape 310 .

[0060] Reference Figure 5G , forming the insulating layer 112. The insulating layer 112 may be formed by forming a portion of the insulating layer 112 on the tape 310, then removing the tape 310 and forming another portion of the insulating layer 112 in the region where the tape 310 has been removed. The insulating layer 112 may be formed by a lamination process while being attached to a film such as a polyethylene terephthalate (PET) film. Next, the fifth and sixth wiring layers 125 and 126 and the third and fourth via layers 133 and 134 are formed on the insulating layer 112. Via holes for forming the third and fourth via layers 133 and 134 may be formed using laser drilling or the like. The fifth and sixth wiring layers 125 and 126 and the third and fourth via layers 133 and 134 may also be formed by a plating process, and may be formed using, for example, an additive process (AP), a semi-AP (SAP), a modified SAP (MSAP), a hole sealing (TT) process, or the like.

[0061] The printed circuit board 100A according to the above-described exemplary embodiment may be manufactured through a series of processes, and a redundant description thereof will be omitted.

[0062] Figure 6 is a cross-sectional view schematically illustrating another example embodiment of a printed circuit board.

[0063] Figure 7 It is schematically shown Figure 6 A cross-sectional view of a modified example embodiment of a printed circuit board.

[0064] Reference Figure 6 and Figure 7Compared with the printed circuit board 100A according to the above-described example embodiment and the printed circuit board 500A according to the modified example embodiment, the printed circuit board 100B according to another example embodiment and the printed circuit board 500B according to the modified example embodiment may further include: an insulating material 170 disposed between each of the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, and the fourth wiring layer 124 and the glass layer 111; and a fifth via layer 137 penetrating the insulating material 170 and connecting at least a portion of each of the first wiring layer 121 and the second wiring layer 122 and the first via layer 131 to each other, and connecting at least a portion of each of the third wiring layer 123 and the fourth wiring layer 124 and the second via layer 132 to each other. The insulating material 170 may include an insulating material similar to that of the insulating layer 112. The glass layer 111 may be protected by the insulating material 170, and adhesion of the glass layer 111 to the insulating layer 112 may be improved. Furthermore, the adhesion of the glass layer 111 to the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, and the fourth wiring layer 124 can be improved, and plating for forming the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, and the fourth wiring layer 124 can be more easily performed. In addition, similar to the through-glass vias of the first via layer 131, the through-glass vias of the second via layer 132 can be formed only by the plating process without using the plug process for the sake of conductivity and easier connection with the fifth via layer 137.

[0065] The other contents are substantially the same as those described with respect to the printed circuit board 100A according to the above-described example embodiment and the printed circuit board 500A according to the modified example embodiment, and thus redundant descriptions thereof will be omitted.

[0066] FIG. 8A to FIG. 8H is a schematic diagram showing the manufacturing Figure 6 A process cross-sectional view of an example embodiment of a printed circuit board is shown.

[0067] Reference Fig. 8A and Figure 8B , as in the above Figure 5A and Figure 5B As described, the glass layer 111 is prepared. Next, the first blind cavity C1 , the second blind cavity C2 , the third blind cavity C3 , the fourth blind cavity C4 , the through cavity H and the first through hole 131 v and the second through hole 132 v are formed in the glass layer 111 .

[0068] Reference Figure 8C , a first via layer 131 and a second via layer 132 are formed on the glass layer 111. The first via layer 131 and the second via layer 132 may be formed by filling the first through hole 131v and the second through hole 132v, respectively, with a metal material using a plating process.

[0069] Reference Fig.8D , forming the insulating material 170. For example, the insulating material 170 is coated on the upper and lower surfaces of the glass layer 111 and the bottom surface of each of the first blind cavity C1, the second blind cavity C2, the third blind cavity C3, and the fourth blind cavity C4.

[0070] Reference Fig. 8E , a first wiring layer 121, a second wiring layer 122, a third wiring layer 123, a fourth wiring layer 124, and a fifth via layer 137 are formed on the insulating material 170. The first wiring layer 121, the second wiring layer 122, the third wiring layer 123, the fourth wiring layer 124, and the fifth via layer 137 may be formed by a plating process, and may be formed using, for example, an additive process (AP), a semi-AP (SAP), a modified SAP (MSAP), a via sealing (TT) process, and the like.

[0071] Reference FIG. 8F to FIG. 8H , such as for Figure 5E to Figure 5G As described, the first passive element 151, the second passive element 152, the third passive element 153 and the fourth passive element 154 may be respectively disposed in the first blind cavity C1, the second blind cavity C2, the third blind cavity C3 and the fourth blind cavity C4. Next, an electronic component 155 is disposed in the through cavity H. Next, the insulating layer 112 is formed. Next, the fifth wiring layer 125 and the sixth wiring layer 126 and the third via layer 133 and the fourth via layer 134 are formed on the insulating layer 112.

[0072] The printed circuit board 100B according to the above-described another exemplary embodiment may be manufactured through a series of processes, and a redundant description thereof will be omitted.

[0073] Fig. 9 is a cross-sectional view schematically illustrating another example embodiment of a printed circuit board.

[0074] Fig.10 It is schematically shown Fig. 9 A cross-sectional view of a modified example embodiment of a printed circuit board.

[0075] Reference Fig. 9 and Fig.10 , compared with the printed circuit board 100B according to the above-described another example embodiment and the printed circuit board 500B according to the modified example embodiment, in the printed circuit board 100C according to the another example embodiment and the printed circuit board 500C according to the modified example embodiment, the insulating material 170 may extend on the wall surface of each of the first blind cavity C1, the second blind cavity C2, the third blind cavity C3, the fourth blind cavity C4, and the through cavity H. Therefore, the wall surface of each of the first blind cavity C1, the second blind cavity C2, the third blind cavity C3, the fourth blind cavity C4, and the through cavity H may be protected, and the adhesion of the glass layer 111 to the insulating layer 112 may be further improved.

[0076] The other contents are substantially the same as those described for the printed circuit board 100A according to the above example embodiment and the printed circuit board 500A according to the modified example embodiment and the printed circuit board 100B according to the above another example embodiment and the printed circuit board 500B according to the modified example embodiment, and thus redundant descriptions thereof will be omitted.

[0077] FIG. 11A to FIG. 11H is a schematic diagram showing the manufacturing Fig. 9 A process cross-sectional view of an example embodiment of a printed circuit board is shown.

[0078] Reference FIG. 11A to FIG. 11C , such as for Figure 5A and Figure 5B as well as FIG. 8A to FIG. 8C As described, the glass layer 111 is prepared. Next, the first blind cavity C1, the second blind cavity C2, the third blind cavity C3, the fourth blind cavity C4, the through cavity H, and the first through hole 131v and the second through hole 132v are formed in the glass layer 111. Next, the first via layer 131 and the second via layer 132 are formed on the glass layer 111.

[0079] Reference Fig.11D , forming the insulating material 170. For example, the insulating material 170 is coated on the upper and lower surfaces of the glass layer 111, the bottom surface and the wall surface of each of the first blind cavity C1, the second blind cavity C2, the third blind cavity C3 and the fourth blind cavity C4, and the wall surface of the through cavity H.

[0080] Reference FIG. 11E to FIG. 11H , as mentioned above for FIG. 8E to FIG. 8H As described, a first wiring layer 121, a second wiring layer 122, a third wiring layer 123, a fourth wiring layer 124, and a fifth via layer 137 are formed on the insulating material 170. Next, a first passive element 151, a second passive element 152, a third passive element 153, and a fourth passive element 154 are respectively disposed in the first blind cavity C1, the second blind cavity C2, the third blind cavity C3, and the fourth blind cavity C4. Next, an electronic component 155 is disposed in the through cavity H. Next, an insulating layer 112 is formed. Next, a fifth wiring layer 125 and a sixth wiring layer 126 and a third via layer 133 and a fourth via layer 134 are formed on the insulating layer 112.

[0081] The printed circuit board 100C according to the above-described another exemplary embodiment may be manufactured through a series of processes, and a redundant description thereof will be omitted.

[0082] In the present disclosure, the expression "covering" may include the case of covering at least a part as well as the case of covering the whole, and may also include the case of not only direct covering but also indirect covering. In addition, the expression "filling" may include not only the case of completely filling but also the case of substantially filling, for example, may include the case of having some holes or gaps.

[0083] In the present disclosure, the meaning of a cross section may refer to a cross-sectional shape when an object is cut vertically, or a cross-sectional shape when the object is viewed from a side view. In addition, the meaning of a plane may refer to a plane shape when an object is cut horizontally, or a plane shape when the object is viewed from a top view or an upward view.

[0084] In the present disclosure, thickness, width, length, depth, etc. can be measured by a scanning microscope or an optical microscope based on a polished cross section or a cut cross section of a printed circuit board. The cut cross section can be a vertical cross section or a horizontal cross section, and the various values ​​of thickness, width, length, depth, etc. can be measured based on the desired cut cross section. When the value is not constant, the value can be determined as the average value of the values ​​measured at any 5 points. The width of the upper end and / or lower end of the via or the width of the upper end and / or lower end of the cavity can be measured on a cross section obtained by cutting the central axis of the via or cavity in the thickness direction of the substrate (e.g., the above-mentioned printed circuit board). The depth of the via or cavity can be measured as: the distance from the upper end to the lower end of the via or cavity on a cross section obtained by cutting the central axis of the via or cavity in the thickness direction of the substrate.

[0085] In the present disclosure, "lower" in lower side, lower part and lower surface is used to refer to the downward direction relative to the cross section of the drawing, and "upper" in upper side, upper part and upper surface is used to refer to the opposite direction. In addition, "side" in side part, side surface, etc. is used to indicate a direction perpendicular to the direction perpendicular to the upper surface and the lower surface (for example, downward direction). However, the directions are defined in this way for the convenience of explanation, and the scope of rights of the claims is not particularly limited by the description of such directions, and the concepts of upper and lower can be changed at any time.

[0086] In the present disclosure, the meaning of connection is a concept including not only direct connection but also indirect connection through an adhesive layer or the like. In addition, electrical connection is a concept including both physical connection and non-physical connection. In addition, expressions such as first and second are used to distinguish one component from another component and do not limit the order and / or importance of the components. In some cases, a first component may be referred to as a second component, or similarly, a second component may be referred to as a first component without departing from the scope of the claims.

[0087] The expression "exemplary embodiment" used in this disclosure does not mean the same embodiment, but is provided to illustrate different unique features. However, the exemplary embodiments presented above do not exclude implementation in combination with features of other exemplary embodiments. For example, even if the contents described in a particular embodiment are not described in other embodiments, they can be understood as descriptions related to other exemplary embodiments, unless there is a description contrary to or contradictory to the contents in other exemplary embodiments.

[0088] The terms used in the present disclosure are only used to describe example embodiments and are not intended to limit the present disclosure. In this case, a singular expression includes a plural expression unless they have obviously different meanings in the context.

[0089] While example embodiments have been shown and described above, it will be readily apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A printed circuit board, comprising: Glass layer; A plurality of blind cavities respectively penetrate a portion of the glass layer from an upper surface or a lower surface of the glass layer; A plurality of passive components are respectively arranged in the plurality of blind cavities; as well as an insulating layer covering the glass layer and at least a portion of each of the plurality of passive elements and disposed in at least a portion of each of the plurality of blind cavities, Wherein, at least two blind cavities among the plurality of blind cavities have different depths.

2. The printed circuit board according to claim 1, further comprising: a through cavity penetrating the glass layer between the upper surface and the lower surface of the glass layer; as well as an electronic component disposed in the through cavity, Wherein, the insulating layer also covers the electronic component and is also arranged in at least a portion of the through cavity.

3. The printed circuit board according to claim 2, wherein: The electronic component is thicker than each of the plurality of passive components.

4. The printed circuit board according to claim 3, wherein: A passive component of the plurality of passive components comprises a silicon capacitor, and The electronic component includes a ceramic capacitor.

5. The printed circuit board according to claim 2, wherein: The plurality of blind cavities include a first blind cavity and a second blind cavity respectively penetrating a portion of the glass layer from the upper surface of the glass layer, and a third blind cavity and a fourth blind cavity respectively penetrating a portion of the glass layer from the lower surface of the glass layer, and The plurality of passive components include a first passive component, a second passive component, a third passive component, and a fourth passive component respectively disposed in the first blind cavity, the second blind cavity, the third blind cavity, and the fourth blind cavity.

6. The printed circuit board according to claim 5, wherein: Based on the thickness direction of the printed circuit board, The first blind cavity and the third blind cavity at least partially overlap each other, and The second blind cavity and the fourth blind cavity at least partially overlap.

7. The printed circuit board according to claim 6, further comprising: A first wiring layer is disposed on a bottom surface of the first blind cavity and a bottom surface of the second blind cavity; A second wiring layer is arranged on the bottom surface of the third blind cavity and the bottom surface of the fourth blind cavity; A third wiring layer and a fourth wiring layer are respectively arranged on the upper surface and the lower surface of the glass layer; A fifth wiring layer and a sixth wiring layer are respectively arranged on the upper surface and the lower surface of the insulating layer; a first via layer that penetrates the glass layer between the first blind cavity and the third blind cavity and between the second blind cavity and the fourth blind cavity and connects at least a portion of each of the first wiring layer and the second wiring layer to each other; a second via layer penetrating the glass layer between the upper surface and the lower surface of the glass layer and connecting at least a portion of each of the third wiring layer and the fourth wiring layer to each other; a third via layer penetrating a portion of an upper side of the insulating layer and connecting at least a portion of each of the third wiring layer and the fifth wiring layer to each other; as well as A fourth via layer penetrates a portion of a lower side of the insulating layer and connects at least a portion of each of the fourth wiring layer and the sixth wiring layer to each other.

8. The printed circuit board according to claim 7, wherein: Each of the first passive component, the second passive component, the third passive component, and the fourth passive component includes a through silicon via, and A through silicon via of each of the first passive element and the second passive element is connected to at least a portion of the first wiring layer through a first-first electrical connection metal, and a through silicon via of each of the third passive element and the fourth passive element is connected to at least a portion of the second wiring layer through a first-second electrical connection metal.

9. The printed circuit board according to claim 7, further comprising: an insulating material disposed between each of the first wiring layer, the second wiring layer, the third wiring layer, and the fourth wiring layer and the glass layer; as well as A fifth via layer penetrates the insulating material and connects at least a portion of each of the first wiring layer and the second wiring layer to the first via layer, and connects at least a portion of each of the third wiring layer and the fourth wiring layer to the second via layer.

10. The printed circuit board according to claim 9, wherein: The insulating material is disposed to extend on a wall surface of each of the first blind cavity, the second blind cavity, the third blind cavity, the fourth blind cavity, and the through cavity.

11. The printed circuit board according to claim 7, further comprising: A first stacked insulating layer and a second stacked insulating layer are respectively disposed on the upper surface and the lower surface of the insulating layer; a first buildup wiring layer, disposed on an upper surface of the first buildup insulating layer; a second build-up wiring layer, disposed on a lower surface of the second build-up insulating layer; a first buildup via layer that penetrates the first buildup insulating layer and connects at least a portion of each of the fifth wiring layer and the first buildup wiring layer to each other; a second buildup via layer that penetrates the second buildup insulating layer and connects at least a portion of each of the sixth wiring layer and the second buildup wiring layer to each other; a first resist layer disposed on an upper surface of the first buildup insulating layer and covering at least a portion of the first buildup wiring layer; a second resist layer disposed on a lower surface of the second buildup insulating layer and covering at least a portion of the second buildup wiring layer; as well as A semiconductor chip is provided on the first resist layer and is connected to the first buildup wiring layer through a second electrical connection metal.

12. The printed circuit board according to any one of claims 1 to 11, wherein: The glass layer includes flat glass.

13. A printed circuit board, comprising: Glass layer; a blind cavity penetrating a portion of the glass layer from an upper surface or a lower surface of the glass layer; a through cavity penetrating the glass layer between the upper surface and the lower surface of the glass layer; A passive component is arranged in the blind cavity; An electronic component is disposed in the through cavity; as well as An insulating layer covers at least a portion of each of the glass layer, the passive element, and the electronic component, and is disposed in at least a portion of each of the blind cavity and the through cavity.

14. The printed circuit board according to claim 13, wherein: The passive components include silicon capacitors, and The electronic component includes a ceramic capacitor.

15. The printed circuit board according to claim 14, further comprising: A first wiring layer is disposed on the bottom surface of the blind cavity; A third wiring layer and a fourth wiring layer are respectively arranged on the upper surface and the lower surface of the glass layer; A first stacked insulating layer and a second stacked insulating layer are respectively disposed on the upper surface and the lower surface of the insulating layer; a first buildup wiring layer, disposed on an upper surface of the first buildup insulating layer; a second build-up wiring layer, disposed on a lower surface of the second build-up insulating layer; a first resist layer disposed on an upper surface of the first buildup insulating layer and covering at least a portion of the first buildup wiring layer; a second resist layer disposed on a lower surface of the second buildup insulating layer and covering at least a portion of the second buildup wiring layer; as well as A semiconductor chip is provided on the first resist layer and is connected to the first buildup wiring layer through an electrical connection metal.

16. A printed circuit board, comprising: Glass layer; a first blind cavity penetrating a first portion of the glass layer from an upper surface of the glass layer; a second blind cavity penetrating a second portion of the glass layer from a lower surface of the glass layer; A first passive component and a second passive component are disposed in the first blind cavity and the second blind cavity, respectively, and the first passive component and the second passive component are connected to each other through a first via layer, and the first via layer is disposed in a portion of the glass layer between the first blind cavity and the second blind cavity; as well as An insulating layer covers the glass layer, at least a portion of each of the first passive element and the second passive element, and is disposed in at least a portion of each of the first blind cavity and the second blind cavity.

17. The printed circuit board according to claim 16, wherein: The first passive component and the second passive component have different thicknesses.

18. The printed circuit board according to claim 17, further comprising: a through cavity penetrating the glass layer between the upper surface and the lower surface of the glass layer; as well as an electronic component disposed in the through cavity and having a thickness greater than a thickness of each of the first passive element and the second passive element, Wherein, the insulating layer also covers the electronic component and is also arranged in at least a portion of the through cavity.

19. The printed circuit board according to claim 16, further comprising: a first wiring layer disposed on a bottom surface of the first blind cavity and connected to the first passive element; a second wiring layer disposed on a bottom surface of the second blind cavity and connected to the second passive element; A third wiring layer and a fourth wiring layer are respectively arranged on the upper surface and the lower surface of the glass layer; A fifth wiring layer and a sixth wiring layer are respectively arranged on the upper surface and the lower surface of the insulating layer; a second via layer penetrating the glass layer between the upper surface and the lower surface of the glass layer and connecting at least a portion of each of the third wiring layer and the fourth wiring layer to each other; a third via layer penetrating a portion of an upper side of the insulating layer and connecting at least a portion of each of the third wiring layer and the fifth wiring layer to each other; as well as a fourth via layer penetrating a portion of the lower side of the insulating layer and connecting at least a portion of each of the fourth wiring layer and the sixth wiring layer to each other, The first via layer connects at least a portion of each of the first wiring layer and the second wiring layer to each other.

20. The printed circuit board according to claim 19, wherein The third via layer connects the fifth wiring layer to the pad of the first passive element, and The fourth via layer connects the sixth wiring layer to the pad of the second passive element.

21. The printed circuit board according to any one of claims 16 to 20, wherein: The glass layer includes flat glass.

Images