Semiconductor device and method of manufacturing the same, memory system

Abstract

The application provides a semiconductor device, a preparation method thereof and a memory system. The semiconductor device comprises a stack structure and a plurality of lead-out contact groups in the stack structure. The stack structure comprises alternately stacked gate layers and insulating layers. One of the lead-out contact groups comprises a plurality of mutually insulated lead-out contacts, which respectively extend to different depths of the stack structure along a first direction and are respectively connected to one of the gate layers at different layers. Therefore, one lead-out contact group can be connected to a plurality of gate layers, improving the utilization rate of the lead-out contact group and reducing the number and overall area of the lead-out contact groups.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, in particular to a semiconductor device, a preparation method thereof and a memory system. BACKGROUND

[0002] NAND memory devices are non-volatile storage products with low power consumption, light weight and good performance, and have been widely used in electronic products. The planar structure of NAND devices has reached the limit of practical expansion. In order to further improve the storage capacity and reduce the storage cost per bit, 3D NAND memory is proposed. In the structure of 3D NAND memory, a vertically stacked multi-layer data storage unit is used to realize a stacked memory structure.

[0003] With the increase of the number of 3D NAND layers, the number of lead-out contacts is further increased, and the area occupied is too large, which raises the problem of how to reduce the area. SUMMARY

[0004] Therefore, the present application provides a semiconductor device, a preparation method thereof and a memory system which can solve the above technical problems.

[0005] To solve the above problems, the technical scheme provided by the present application is as follows:

[0006] The present application provides a semiconductor device, which comprises: a stack structure comprising alternately stacked gate layers, first insulating layers and dielectric layers, the first insulating layers and the gate layers being stacked in a first direction, and the dielectric layers and the first insulating parts being arranged in the same layer as the gate layers; and a lead-out contact group located in the stack structure; one lead-out contact group comprises a plurality of lead-out contacts which are insulated from each other, and the plurality of lead-out contacts respectively extend to different depths of the stack structure along the first direction and are respectively connected to one gate layer located in different layers.

[0007] In some embodiments, the stack structure further comprises a second insulating layer, the second insulating layer comprises a first insulating part, the dielectric layers and the first insulating part are arranged in the same layer as the gate layers, the dielectric layers are located between the gate layers and the first insulating parts, and an end of the second insulating layer away from the gate layers is in contact with the lead-out contacts.

[0008] In some embodiments, an end of the first insulating part away from the gate layers is directly connected to the lead-out contacts.

[0009] In some embodiments, the first insulating part is located between two adjacent first insulating layers.

[0010] In some embodiments, the second insulating layer further comprises a second insulating portion, the second insulating portion extending along the first direction and connected with the first insulating portion.

[0011] In some embodiments, the second insulating portion surrounds and is connected with one of the lead-out contacts.

[0012] In some embodiments, one of the second insulating portions is connected with at least one of the first insulating portions and at least one of the first insulating layers.

[0013] In some embodiments, the gate layers extend along a second direction perpendicular to the first direction, the gate layers, the dielectric layers and the first insulating portions of the same layer being arranged along the second direction.

[0014] The second insulating portion comprises a first inclined surface extending along a third direction, the third direction intersecting the first direction and the second direction, the first inclined surface being away from the first insulating portion connected with the second insulating portion, the first inclined surface being connected with one of the lead-out contacts.

[0015] In some embodiments, one of the lead-out contact groups comprises a first lead-out contact and a second lead-out contact, the first lead-out contact being arranged around the second lead-out contact; the first insulating portion being connected with the first lead-out contact.

[0016] In some embodiments, the stack structure further comprises a first surface, the lead-out contact groups extending from the first surface into the stack structure along the first direction; the first lead-out contact comprises a first connecting portion and a second connecting portion, the first connecting portion being located between two adjacent first insulating layers and connected with a gate layer, the second connecting portion extending along the first direction and connected with an end of the first connecting portion away from the gate layer, an end of the second connecting portion away from the first connecting portion extending to the first surface.

[0017] In some embodiments, the second lead-out contact comprises a third connecting portion, a fourth connecting portion and a fifth connecting portion, the third connecting portion being located between two adjacent first insulating layers and connected with the gate layer, the fourth connecting portion extending along the first direction and connected with an end of the third connecting portion away from the gate layer, an end of the fourth connecting portion away from the third connecting portion being connected with the fifth connecting portion, an end of the fifth connecting portion away from the fourth connecting portion extending to the first surface, the second connecting portion being arranged around part of the fifth connecting portion.

[0018] In some embodiments, the fifth connecting portion comprises a second inclined surface away from one end of the first surface, the second inclined surface extends along a third direction intersecting the first direction and the extending direction of the gate layer, and the second inclined surface is connected with the fourth connecting portion.

[0019] In some embodiments, the group of lead-out contacts further comprises a third insulating layer, the third insulating layer comprises a third insulating portion and a fourth insulating portion, the third insulating portion and the fourth insulating portion are discontinuously arranged, the third insulating portion is located between the second connecting portion of the first lead-out contact and the fifth connecting portion of the second lead-out contact, the fourth connecting portion surrounds the fourth insulating portion, and the fifth connecting portion is located on the fourth insulating portion.

[0020] In some embodiments, different groups of lead-out contacts are connected with different gate layers.

[0021] The application further provides a method for manufacturing a semiconductor device, comprising: forming an initial stack structure comprising alternately stacked gate layers and first insulating layers; the initial stack structure further comprises a dielectric layer, the dielectric layer is arranged in the same layer as the gate layers; forming a first recess and a second recess penetrating at least part of the first insulating layers and at least part of the dielectric layer on the initial stack structure, the first recess and the second recess extend in a first direction and are connected; and forming a plurality of groups of lead-out contacts penetrating the initial stack structure in the first recess and the second recess, one group of lead-out contacts comprises a plurality of lead-out contacts extending to different depths of the initial stack structure in the first direction and being insulated from each other, and the plurality of lead-out contacts are respectively connected with one gate layer.

[0022] In some embodiments, before the step of forming a plurality of groups of lead-out contacts penetrating the initial stack structure in the first recess and the second recess, the method further comprises: removing part of the dielectric layer to obtain a plurality of third recesses; the third recesses extend along the extending direction of the gate layers and are respectively connected with the first recess and the second recess; filling insulating material on the side walls and bottom walls of the first recess and the second recess and in the third recesses; and removing at least part of the insulating material and retaining the insulating material located in the third recesses, and exposing at least part of the dielectric layer at the junction of the first recess and the second recess and at least part of the dielectric layer located below the bottom of the second recess.

[0023] In some embodiments, before the step of removing part of the dielectric layer to form a plurality of third recesses, a first insulating layer is formed on the bottom of the second recess; the step of removing at least part of the insulating material and retaining the insulating material in the third recesses comprises: removing at least part of the insulating material on the sidewalls of the first and second recesses and all of the insulating material on the bottom of the second recess to form a second insulating layer; the second insulating layer comprises a first insulating portion in the third recesses; and removing the first insulating layer on the bottom of the second recess to expose at least part of the dielectric layer.

[0024] In some embodiments, in the step of removing at least part of the insulating material on the sidewalls of the first and second recesses and all of the insulating material on the bottom of the second recess to form a second insulating layer, part of the insulating material on the sidewalls of the first and / or second recesses is retained, which is a second insulating portion, and the second insulating portion is connected to the first insulating portions.

[0025] In some embodiments, the step of forming a plurality of groups of lead-out contacts penetrating through the initial stack structure in the first and second recesses comprises: removing the entire layer of dielectric layer on which the dielectric layer exposed from the first and second recesses is formed, to form a fourth recess in communication with the first recess and a fifth recess in communication with the second recess; forming a first lead-out contact in the fourth recess and on the sidewalls of the first recess; and forming an initial second lead-out contact in the fifth recess and on the sidewalls of the second recess; forming a third insulating portion on the surface of the first lead-out contact in the first recess and a fourth insulating portion in the space formed by the initial second lead-out contact in the second recess and the dielectric layer exposed from the second recess to form a third insulating layer; and forming a conductive material in the space surrounded by the third insulating portion to form a second lead-out contact connected to the initial second lead-out contact.

[0026] The application also provides a storage system, comprising: a semiconductor device as described above; and a controller coupled to the memory for controlling the memory to store data.

[0027] The semiconductor device and its fabrication method, as well as the memory system provided in this application, include a stacked structure and multiple sets of lead contacts located within the stacked structure. The stacked structure includes alternately stacked gate layers and insulating layers. Each set of lead contacts includes multiple mutually insulated lead contacts, which extend along a first direction to different depths within the stacked structure and are respectively connected to a gate layer located in a different layer. Therefore, one set of lead contacts can connect to multiple gate layers, improving the utilization rate of the lead contact sets and reducing the number of lead contact sets and the overall occupied area. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in some embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1A A top view of a semiconductor structure provided for some embodiments of this application.

[0030] Figure 1B For along Figure 1A The sectional view shown is of II.

[0031] Figure 2 A flowchart illustrating a method for fabricating a semiconductor structure according to some embodiments of this application.

[0032] Figure 3 A cross-sectional view of the initial stacked structure provided for this application.

[0033] Figure 4 In order to be in Figure 3 A cross-sectional view of the initial stacked structure after the first and second grooves are formed.

[0034] Figure 5 In order to be in Figure 4 The cross-sectional view of the initial stacked structure after the third groove is formed.

[0035] Figure 6 In order to be in Figure 5 The cross-sectional view shown is of the third groove and the first and second grooves after they have been filled with insulating material.

[0036] Figure 7 To remove Figure 6 The diagram shows a cross-sectional view of the insulating material after the second insulating layer has been obtained.

[0037] Figure 8 In order to be in Figure 7A cross-sectional view of the initial stacked structure after the fourth and fifth grooves have been formed.

[0038] Figure 9 In order to be in Figure 8 The cross-sectional view shown is taken after the initial lead-out contact layer is formed in the fourth, fifth, first, and second grooves.

[0039] Figure 10 To be Figure 9 The diagram shows a cross-sectional view after the initial lead-out contact layer has been fabricated to form the first lead-out contact layer.

[0040] Figure 11 In order to be in Figure 10 The cross-sectional view shown is of the first and second grooves after the third insulating layer has been formed.

[0041] Figure 12 This is a schematic diagram of a memory system provided for some embodiments of this application. Detailed Implementation

[0042] The technical solutions of some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0043] In the description of this application, it should be understood that the terms "upper," "lower," etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly and specifically defined.

[0044] In the description of this application, it should be understood that the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a structure below or above, or may have a range smaller than that of the structure below or above. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (where interconnect lines and / or via contacts are formed), and one or more dielectric sublayers.

[0045] Reference numerals and / or reference letters may be repeated in different embodiments of this application. Such repetition is for the purpose of simplification and clarity and does not in itself indicate the relationship between the various implementations and / or settings discussed.

[0046] This application addresses the technical problem that as the number of layers in 3D NAND flash memory increases, the number of lead-in contacts further increases, resulting in excessively large area occupied. It provides a semiconductor device and its fabrication method, as well as a memory system. The semiconductor device includes a stacked structure and multiple lead-in contact groups located within the stacked structure. The stacked structure includes alternately stacked gate layers and insulating layers. Each lead-in contact group includes multiple mutually insulated lead-in contacts, which extend along a first direction to different depths of the stacked structure and are respectively connected to a gate layer located in a different layer. Therefore, one lead-in contact group can connect to multiple gate layers, improving the utilization efficiency of the lead-in contact group and reducing the number of lead-in contact groups and the overall occupied area.

[0047] The following will combine Figure 1A and 1B The structure of semiconductor device 100 is described in detail.

[0048] Semiconductor device 100 may be a wafer or a 3D memory, or a portion thereof. 3D memory can be applied to communication products, consumer electronics, automotive products, aerospace products, artificial intelligence products, or big data applications. Consumer electronics include, but are not limited to, mobile phones, computers, tablets, cameras, smart glasses, or gaming products.

[0049] Semiconductor device 100 includes a stacked structure 120 and a lead-out contact group 130. The stacked structure 120 includes alternating gate layers 11 and a first insulating layer 12, which are stacked in a first direction Z. The lead-out contact group 130 is located within the stacked structure 120. A lead-out contact group 130 includes a plurality of mutually insulated lead-out contacts, which extend along the first direction Z to different depths in the stacked structure 120 and are respectively connected to a gate layer 11 located in a different layer.

[0050] In some embodiments, the gate layer 11 extends along a second direction X that is perpendicular to the first direction Z.

[0051] In some embodiments, different lead-out contact groups 130 are connected to different gate layers 11.

[0052] The semiconductor device 100 provided in this application includes a lead-out contact group 130 comprising a plurality of mutually insulated lead-out contacts. Thus, a lead-out contact group 130 can connect to a plurality of gate layers 11, thereby improving the utilization rate of the lead-out contact group 130, reducing the number of lead-out contact groups 130, and saving the overall occupied area of ​​the non-core area (lead-out contact group).

[0053] One lead-out contact has an L-shaped cross-section in the first direction Z. A portion of the lead-out contact extends along the first direction Z to different depths of the stacked structure 120, and another portion extends along the second direction X, which is perpendicular to the first direction Z, between two adjacent first insulating layers 12 and connected to the gate layer 11.

[0054] Among them, the part of the lead-out contacts that extends along the second direction X, is located between two adjacent first insulating layers 12 and is connected to the gate layer 11 can lead out the signal from the gate layer 11, and the part of the lead-out contacts that extend along the first direction Z to different depths of the stacked structure 120 can conduct the signal from the gate layer 11 to the outside of the stacked structure 120. One lead-out contact is arranged in an L-shape, which can also increase the reliability of the connection between the lead-out contact and the stacked structure 120 and the gate layer 11.

[0055] The gate layer 11 includes, but is not limited to, at least one of tungsten, cobalt, copper, aluminum, doped silicon, or doped silicide, and the first insulating layer 12 includes, but is not limited to, any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride. In this embodiment, the first insulating layer 12 is made of silicon oxide. This application does not limit the number of gate layers 11 and first insulating layers 12.

[0056] In some embodiments, the stacked structure 120 may further include a dielectric layer 13 disposed on the same layer as the gate layer 11. The dielectric layer 13 is located between two adjacent first insulating layers 12. In the same etching solution, the etching rates of the dielectric layer 13 and the first insulating layer 12 are different.

[0057] The dielectric layer 13 includes, but is not limited to, any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride. In this embodiment, the dielectric layer 13 is made of silicon nitride or the like.

[0058] The stacked structure 120 may include a core region 101 and a non-core region 102 adjacent to the core region 101. The core region 101 is used to form a memory channel structure 30, and the non-core region 102 is used to form a lead-out contact group 130. A first insulating layer is located within the core region 101 and the non-core region 102, a dielectric layer 13 is located within the non-core region 102, and a gate layer 11 is located within the core region 101. The memory channel structure 30 penetrates the gate layer 11 and the first insulating layer 12 along a first direction Z, and the lead-out contact group 130 penetrates the dielectric layer 13 and the first insulating layer 12 along the first direction Z.

[0059] In some embodiments, the gate layer 11 may include a dielectric layer and a conductive layer. The conductive layer may include a first conductive layer and a second conductive layer formed sequentially, with the first conductive layer located between the dielectric layer and the second conductive layer. The dielectric layer serves to isolate the conductive layer from the storage channel structure 30. The dielectric layer has an upper surface and a lower surface that contact two adjacent first insulating layers 12, and a side surface that contacts the storage channel structure 30. The conductive layer is surrounded by the upper surface, lower surface, and side surface of the dielectric layer. The material of the dielectric layer may include a high-k dielectric layer (such as alumina), the material of the first conductive layer may include titanium nitride, and the material of the second conductive layer may include tungsten. The primary function of the first conductive layer is to mitigate the diffusion of the second conductive layer into the dielectric layer and to improve the adhesion of the second conductive layer. The first conductive layer also improves fluorine diffusion in the second conductive layer.

[0060] In some embodiments, the stacked structure 120 further includes a second insulating layer 14, the second insulating layer 14 including a first insulating portion 141, the first insulating portion 141 being disposed in the same layer as the dielectric layer 13 and the gate layer 11, the dielectric layer 13 being located between the gate layer 11 and the first insulating portion 141, and one end of the second insulating layer 14 away from the gate layer 11 being in contact with a lead-out contact.

[0061] In some embodiments, the second insulating layer 14 includes, but is not limited to, any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride. In this embodiment, the material of the second insulating layer 14 is silicon oxide. This application does not limit the number of second insulating layers 14.

[0062] In some embodiments, the first insulating portion 141 is located between two adjacent first insulating layers 12.

[0063] In some embodiments, one end of the dielectric layer 13 is in contact with the gate layer 11, and the other end is in contact with the second insulating layer 14.

[0064] In some embodiments, the end of the first insulating portion 141 away from the gate layer 11 is directly connected to the lead-out contact.

[0065] In forming the lead-out contacts, the industry generally adopts the following approach: first, at least two interconnected holes (nested holes, one with a larger diameter and the other with a smaller diameter) are formed on the stacked structure along the first direction Z. Then, an oxide layer is formed on the trench wall. A punching process is then used to remove part of the oxide layer on the trench wall. During this punching process, the oxide layer on the inner wall of the smaller hole in the nested holes, near the larger hole, is easily etched away completely. This results in some sacrificial layers (e.g., dielectric layer 13) in the stacked structure being exposed from the smaller holes. When the sacrificial layers (e.g., dielectric layer 13) are subsequently replaced with gates through an etching process, multiple adjacent gates are obtained. The lead-out contacts connect these adjacent gates in series. Here, "adjacent" refers to two gates located on either side of the first insulating layer in the first direction Z. This application provides a second insulating layer 14 (e.g., a first insulating portion 141) at the end far from the gate layer 11 and close to the lead-out contact. This can be understood as the second insulating layer 14 (e.g., the first insulating portion 141) being disposed between the gate layer 11 and the lead-out contact. This can better protect the dielectric layer 13 located between two adjacent lead-out contacts during the formation of the lead-out contact, thereby reducing the risk of the dielectric layer 13 located between two adjacent lead-out contacts being etched. This can further reduce the risk of the dielectric layer 13 being subjected to indiscriminate etching, thus solving the problem of multiple gates connected in series.

[0066] In some embodiments, the second insulating layer 14 further includes a second insulating portion 142 extending along a first direction Z and connected to the first insulating portion 141. The second insulating portion 142 surrounds and is connected to the lead-out contact. One second insulating portion 142 connects at least one first insulating portion 141 and at least one first insulating layer 12. In this case, the first insulating portion 141 is indirectly connected to the lead-out contact through the second insulating portion 142.

[0067] In some embodiments, the second insulating portion 142 includes a first inclined surface 214 extending along a third direction Y perpendicular to the first direction Z and intersecting the second direction X. The first inclined surface 214 is away from the first insulating portion 141 connected to the second insulating portion 142, and the first inclined surface 214 is connected to the lead-out contact.

[0068] The second insulating layer 14 includes, but is not limited to, any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride. In some embodiments, the second insulating layer 14 is made of silicon oxide. This application does not limit the number of second insulating layers 14. The number of second insulating layers 14 is less than the number of gate layers 11.

[0069] The second insulating portion 142 can further protect the dielectric layer 13 located between two adjacent lead-out contacts during the formation of lead-out contacts, thereby further reducing the risk of the dielectric layer 13 located between two adjacent lead-out contacts being etched, and further reducing the risk of the dielectric layer 13 being subjected to indiscriminate etching, so as to better solve the problem of multiple gates connected in series.

[0070] The stacked structure 120 also includes a first surface 15 and a second surface 16 opposite to the first surface 15 in the first direction Z, with lead-out contacts extending from the first surface 15 to the second surface 16 and penetrating the first surface 15.

[0071] In some embodiments, one of the lead-out contact groups 130 includes a first lead-out contact 21 and a second lead-out contact 22 that are insulated from each other, wherein the depth of the first lead-out contact 21 extending in the first direction Z within the stacked structure 120 is less than the depth of the second lead-out contact 22 extending in the first direction Z within the stacked structure 120.

[0072] In other embodiments, one of the lead-out contact groups 130 may also include other lead-out contacts besides the first lead-out contact 21 and the second lead-out contact 22, the other lead-out contacts extending to the same depth as the first lead-out contact 21 extending to the same depth as the second lead-out contact 22 extending to the same depth as the first lead-out contact 21 extending to the same depth as the second lead-out contact 22 extending to the same depth as the first lead-out contact 22 in the same direction Z within the stacked structure 120.

[0073] In some embodiments, the first lead-out contact 21 includes a first connection portion 211 and a second connection portion 212. The first connection portion 211 is located between two adjacent first insulating layers 12 and is connected to the gate layer 11. The second connection portion 212 extends along the first direction Z and is connected to the end of the first connection portion 211 away from the gate layer 11. The end of the second connection portion 212 away from the first connection portion 211 extends along the first direction Z to the first surface 15.

[0074] The second lead-out contact 22 includes a third connecting portion 221, a fourth connecting portion 222, and a fifth connecting portion 223. The third connecting portion 221 is located between two adjacent first insulating layers 12 and is connected to the gate layer 11. The fourth connecting portion 222 extends along the first direction Z and is connected to the end of the third connecting portion 221 away from the gate layer 11. The fourth connecting portion 222 extends from the third connecting portion 221 towards the first surface 15 along the first direction Z. The end of the fourth connecting portion 222 away from the third connecting portion 221 is connected to the fifth connecting portion 223. The end of the fifth connecting portion 223 away from the fourth connecting portion 222 extends to the first surface 15. The second connecting portion 212 is disposed around the portion of the fifth connecting portion 223. The third connecting portion 221 is insulated from the second connecting portion 212, which can also be understood as the third connecting portion 221 and the second connecting portion 212 not being connected. The second connecting portion 212 is insulated from the fifth connecting portion 223, which can also be understood as the second connecting portion 212 and the fifth connecting portion 223 not being connected. The fourth connection portion 222 is insulated from the second connection portion 212 and its distance from the first surface 15 is greater than 0. If the first surface 15 is considered as the top and the second surface 16 as the bottom, the fact that the fourth connection portion 222 is insulated from the second connection portion 212 and its distance from the first surface 15 is greater than 0 can also be understood as the fourth connection portion 222 being located below the second connection portion 212. The fifth connection portion 223 can lead the signal from the gate layer 11 out from the fourth connection portion 222 to the outside of the stacked structure 120.

[0075] In some embodiments, the surface on which the fourth connecting portion 222 connects to the second insulating portion 142 is an inclined surface, which is caused by the manufacturing process.

[0076] In some embodiments, the second insulating layer 14 opposite to the second connecting portion 212 of the first lead-out contact 21 may also include a second insulating portion 142. In this case, the surface on which the second insulating portion 142 connects to the second connecting portion 212 of the first lead-out contact 21 may be an inclined surface or not.

[0077] In some embodiments, the end of the fifth connecting portion 223 away from the first surface 15 includes a second inclined surface 213. The second inclined surface 213 extends along a third direction Y that intersects the first direction Z and the second direction X. The second inclined surface 213 is connected to the fourth connecting portion 222. The surface where the fourth connecting portion 222 connects to the second inclined surface 213 is also an inclined surface.

[0078] In some embodiments, the lead-out contact group 130 further includes a third insulating layer 23, which includes a third insulating portion 231 and a fourth insulating portion 232. The third insulating portion 231 and the fourth insulating portion 232 are discontinuous, or can be understood as being disconnected. The third insulating portion 231 is located between the second connecting portion 212 of the first lead-out contact 21 and the fifth connecting portion 223 of the second lead-out contact 22. The fourth connecting portion 222 surrounds the fourth insulating portion 232, and the fifth connecting portion 223 is located on the fourth insulating portion 232. The third insulating portion 231 serves to space the first lead-out contact 21 and the second lead-out contact 22, and the fourth insulating portion 232 serves to support the fifth connecting portion 223.

[0079] Please see Figures 1A to 11 Some embodiments of this application provide a method for fabricating a semiconductor device 100, including:

[0080] Step S1, please refer to Figure 2 and Figure 3 An initial stacked structure 110 is formed, comprising alternating gate layers 11 and a first insulating layer 12. The initial stacked structure 110 also includes a dielectric layer 13, which is disposed on the same layer as the gate layer 11. The gate layer 11 and the dielectric layer 13 located on the same layer are arranged along the second direction X.

[0081] The stacked structure 120 may include a core region 101 and a non-core region 102 adjacent to the core region 101. The core region 101 is used to form a memory channel structure 30, and the non-core region 102 is used to form a lead-out contact group 130. A first insulating layer 12 is located within the core region 101 and the non-core region 102, a dielectric layer 13 is located within the non-core region 102, and a gate layer 11 is located within the core region 101. The memory channel structure 30 penetrates the gate layer 11 and the first insulating layer 12 along a first direction Z, and the lead-out contact group 130 penetrates the dielectric layer 13 and the first insulating layer 12 along the first direction Z.

[0082] The stacked structure 120 also includes a first surface 15 and a second surface 16 opposite to the first surface 15 in the first direction Z, with lead-out contacts extending from the first surface 15 to the second surface 16 and penetrating the first surface 15.

[0083] For step S2, please refer to [link / reference]. Figure 2 and Figure 4 A first groove 103 and a second groove 104 are formed on the initial stacked structure 110, penetrating at least a portion of the first insulating layer 12 and at least a portion of the dielectric layer 13. The first groove 103 and the second groove 104 extend and communicate in the first direction Z.

[0084] In other embodiments, additional grooves are formed on the initial stacked structure 110, penetrating at least a portion of the first insulating layer 12 and at least a portion of the dielectric layer 13. This application illustrates an example of a nested groove or nested hole formed by two grooves.

[0085] The dimension of the first groove 103 in the second direction X is larger than the dimension of the second groove 104 in the second direction X. A first insulating layer 12 is exposed from both the first groove 103 and the second groove 104. This can also be understood as follows: in step S2, the bottom of both the first groove 103 and the second groove 104 is a first insulating layer 12. The orthographic projection of the second groove 104 onto the first insulating layer 12 lies within the orthographic projection of the first groove 103 onto the first insulating layer 12.

[0086] Step S3, please refer to Figure 2 and Figure 5 A portion of the dielectric layer 13 is removed to obtain a plurality of third grooves 105. The third grooves 105 extend along the extension direction of the gate layer 11 and are respectively connected to the first groove 103 and the second groove 104.

[0087] For step S4, please refer to [link / reference]. Figure 2 and Figure 6 Insulating material is filled on the side walls and bottom walls of the first groove 103 and the second groove 104, as well as in the third groove 105.

[0088] The material of the insulating material and the material of the first insulating layer 12 include, but are not limited to, any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride. In this embodiment, both the insulating material and the first insulating layer 12 are made of silicon oxide.

[0089] For step S5, please refer to [link / reference]. Figure 2 and Figure 7 At least part of the insulating material is removed and the insulating material located in the third groove 105 is retained, and at least part of the dielectric layer 13 at the junction of the first groove 103 and the second groove 104 and at least part of the dielectric layer 13 located below the bottom of the second groove 104 are exposed.

[0090] In some implementations, a punching process is used to remove part of the insulating material. In other embodiments, processes other than punching can also be used to remove part of the insulating material.

[0091] The insulating material remaining in the third groove 105 is the first insulating portion 141, and the insulating material remaining on the sidewall of the first groove 103 and / or the second groove 104 and connected to the first insulating portion 141 is the second insulating portion 142. The second insulating portion 142 extends along the first direction Z and is connected to a plurality of first insulating portions 141. The first insulating portion 141 or the first insulating portion 141 and the second insulating portion 142 constitute the second insulating layer 14.

[0092] In this application, the following description will take the example of having a second insulating portion 142 only on the inner wall of the second groove 104.

[0093] In some implementations, step S5 includes: removing at least a portion of the insulating material on the sidewalls of the first groove 103 and the second groove 104, and all the insulating material at the bottom of the second groove 104, to obtain a second insulating layer 14; and removing the first insulating layer 12 at the bottom of the second groove 104 to expose at least a portion of the dielectric layer 13.

[0094] For step S6, please refer to [link / reference]. Figure 2 and Figures 8 to 10 Multiple lead-out contact groups 130 are formed in the first groove 103 and the second groove 104, penetrating the initial stacked structure 110. Each lead-out contact group 130 includes multiple lead-out contacts extending to different depths along the first direction Z to the initial stacked structure 110 and insulated from each other. The multiple lead-out contacts are respectively connected to a gate layer 11.

[0095] In some implementations, step S6 includes: First, please refer to Figure 8 The entire dielectric layer containing the dielectric layer 13 exposed from the first groove 103 and the second groove 104 is removed to form a fourth groove 106 communicating with the first groove 103 and a fifth groove 107 communicating with the second groove 104; next, please refer to Figure 9 and Figure 10 A first lead-out contact 21 is formed in the fourth groove 106 and on the sidewall of the first groove 103, and an initial second lead-out contact 220 is formed in the fifth groove 107 and on the sidewall of the second groove 104; again, please refer to Figure 11 A third insulating portion 231 is formed on the surface of the first lead-out contact 21 located within the first groove 103, and a fourth insulating portion 232 is formed within the space formed by the initial second lead-out contact 220 located within the second groove 104 and the dielectric layer 13 exposed from the second groove 104, to obtain a third insulating layer 23; finally, please refer to Figure 1A and Figure 1B Conductive material (fifth connection portion) is formed within the space enclosed by the third insulating portion 231 to connect with the initial second lead-out contact 220, thereby obtaining the second lead-out contact 22.

[0096] In some embodiments, the steps of forming a first lead-out contact 21 in the fourth groove 106 and on the sidewall of the first groove 103, and forming an initial second lead-out contact 220 in the fifth groove 107 and on the sidewall of the second groove 104 include: Please refer to Figure 9An initial lead-out contact layer 109 is formed in the fourth groove 106 and on the sidewall of the first groove 103; a portion of the initial lead-out contact layer 109 is removed to obtain the first lead-out contact 21 and the initial second lead-out contact 220.

[0097] In some embodiments, a portion of the initial lead-out contact layer 109 is removed by a punching process to obtain the first lead-out contact 21 and the initial second lead-out contact 220.

[0098] In some embodiments, an initial lead-out contact layer 109 is formed by a deposition process. The initial lead-out contact layer 109 includes, but is not limited to, at least one of tungsten, cobalt, copper, aluminum, doped silicon, or doped silicide.

[0099] The conductive material formed within the space enclosed by the third insulating portion 231 and connected to the initial second lead-out contact 220 is the fifth connecting portion 223.

[0100] In some embodiments, the first lead-out contact 21 includes a first connection portion 211 and a second connection portion 212. The first connection portion 211 is located between two adjacent first insulating layers 12 and is connected to the gate layer 11. The second connection portion 212 extends along the first direction Z and is connected to the end of the first connection portion 211 away from the gate layer 11. The end of the second connection portion 212 away from the first connection portion 211 extends along the first direction Z to the first surface 15.

[0101] The second lead-out contact 22 includes a third connecting portion 221, a fourth connecting portion 222, and a fifth connecting portion 223. The third connecting portion 221 is located between two adjacent first insulating layers 12 and is connected to the gate layer 11. The fourth connecting portion 222 extends along the first direction Z and is connected to the end of the third connecting portion 221 away from the gate layer 11. The fourth connecting portion 222 extends from the third connecting portion 221 towards the first surface 15 along the first direction Z. The end of the fourth connecting portion 222 away from the third connecting portion 221 is connected to the fifth connecting portion 223. The end of the fifth connecting portion 223 away from the fourth connecting portion 222 extends to the first surface 15. The second connecting portion 212 is disposed around the portion of the fifth connecting portion 223. The third connecting portion 221 is insulated from the second connecting portion 212, which can also be understood as the third connecting portion 221 and the second connecting portion 212 not being connected. The second connecting portion 212 is insulated from the fifth connecting portion 223, which can also be understood as the second connecting portion 212 and the fifth connecting portion 223 not being connected. The fourth connection portion 222 is insulated from the second connection portion 212 and its distance from the first surface 15 is greater than 0. If the first surface 15 is considered as the top and the second surface 16 as the bottom, the fact that the fourth connection portion 222 is insulated from the second connection portion 212 and its distance from the first surface 15 is greater than 0 can also be understood as the fourth connection portion 222 being located below the second connection portion 212. The fifth connection portion 223 can lead the signal from the gate layer 11 out from the fourth connection portion 222 to the outside of the stacked structure 120.

[0102] In some embodiments, the surface on which the fourth connecting portion 222 connects to the second insulating portion 142 is an inclined surface, which is caused by the manufacturing process.

[0103] In some embodiments, the second insulating layer 14 opposite to the second connecting portion 212 of the first lead-out contact 21 may also include a second insulating portion 142. In this case, the surface on which the second insulating portion 142 connects to the second connecting portion 212 of the first lead-out contact 21 may be an inclined surface or not.

[0104] In some embodiments, the end of the fifth connecting portion 223 away from the first surface 15 includes a second inclined surface 213. The second inclined surface 213 extends along a third direction Y that intersects the first direction Z and the second direction X. The second inclined surface 213 is connected to the fourth connecting portion 222. The surface where the fourth connecting portion 222 connects to the second inclined surface 213 is also an inclined surface.

[0105] In some embodiments, the lead-out contact group 130 further includes a third insulating layer 23, which includes a third insulating portion 231 and a fourth insulating portion 232. The third insulating portion 231 and the fourth insulating portion 232 are discontinuous, or can be understood as being disconnected. The third insulating portion 231 is located between the second connecting portion 212 of the first lead-out contact 21 and the fifth connecting portion 223 of the second lead-out contact 22. The fourth connecting portion 222 surrounds the fourth insulating portion 232, and the fifth connecting portion 223 is located on the fourth insulating portion 232. The third insulating portion 231 serves to space the first lead-out contact 21 and the second lead-out contact 22, and the fourth insulating portion 232 serves to support the fifth connecting portion 223.

[0106] Please see Figure 12 This application also provides a memory system 1000, which includes one or more semiconductor devices 100 as described above and a controller 200. The controller 200 is coupled to the semiconductor device 100 and is configured to control the semiconductor device 100.

[0107] The memory system 1000 can be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. The controller can be configured to control the operation of the semiconductor device, such as read, erase, and program operations.

[0108] In some embodiments, the controller is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media for use in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0109] In some embodiments, the controller is designed to operate in a high duty cycle environment solid-state disk (SSD) or embedded multi-media card (eMMC), which serves as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0110] In some embodiments, when the semiconductor device 100 is part of a three-dimensional memory, the memory system 1000 includes peripheral circuitry (not shown), which may be a CMOS (Complementary Metal-Oxide-Semiconductor). This peripheral circuitry is electrically connected to the semiconductor device to transmit signals. The peripheral circuitry can be used for logic operations and for controlling and detecting the switching states of each memory cell in the semiconductor device 301 via metal interconnects, thereby enabling data storage and retrieval.

[0111] The semiconductor device and its fabrication method, as well as the memory system provided in this application, include a stacked structure and multiple sets of lead contacts located within the stacked structure. The stacked structure includes alternately stacked gate layers and insulating layers. Each set of lead contacts includes multiple mutually insulated lead contacts, which extend along a first direction to different depths within the stacked structure and are respectively connected to a gate layer located in a different layer. Therefore, one set of lead contacts can connect to multiple gate layers, improving the utilization rate of the lead contact sets and reducing the number of lead contact sets and the overall occupied area.

[0112] Furthermore, by providing a second insulating layer (e.g., a first insulating portion) at the end far from the gate layer and close to the lead-out contact, this application can be understood as follows: the second insulating layer (e.g., the first insulating portion) is disposed between the gate layer and the lead-out contact, which can better protect the dielectric layer located between two adjacent lead-out contacts during the formation of the lead-out contact, thereby reducing the risk of the dielectric layer located between two adjacent lead-out contacts being etched, and thus reducing the risk of the dielectric layer being subjected to indiscriminate etching, thereby solving the problem of multiple gates connected in series.

[0113] In addition, the second insulating layer also includes a second insulating portion that can further protect the dielectric layer between two adjacent lead-out contacts during the formation of the lead-out contacts, thereby further reducing the risk of the dielectric layer between two adjacent lead-out contacts being etched, and further reducing the risk of the dielectric layer being subjected to indiscriminate etching, so as to better solve the problem of multiple gates connected in series.

[0114] In summary, although the present application has disclosed the preferred embodiments as described above, the above preferred embodiments are not intended to limit the present application. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be determined by the scope defined in the claims.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: A stacked structure includes alternately stacked gate layers, a first insulating layer, and a dielectric layer, wherein the first insulating layer and the gate layers are stacked in a first direction, and the dielectric layer is disposed on the same layer as the gate layer; and A lead-out contact group is located within the stacked structure; one lead-out contact group includes a plurality of mutually insulated lead-out contacts, the plurality of lead-out contacts extending along a first direction to different depths of the stacked structure and respectively connected to a gate layer located in a different layer.

2. The semiconductor device as claimed in claim 1, characterized in that, The stacked structure further includes a second insulating layer, which includes a first insulating portion. The dielectric layer and the first insulating portion are disposed on the same layer as the gate layer. The dielectric layer is located between the gate layer and the first insulating portion. One end of the second insulating layer away from the gate layer is in contact with the lead-out contact.

3. The semiconductor device as described in claim 2, characterized in that, The end of the first insulating portion away from the gate layer is directly connected to the lead-out contact.

4. The semiconductor device as described in claim 2, characterized in that, The first insulating portion is located between two adjacent first insulating layers.

5. The semiconductor device as claimed in claim 2, characterized in that, The second insulating layer further includes a second insulating portion that extends along the first direction and is connected to the first insulating portion.

6. The semiconductor device as claimed in claim 5, characterized in that, The second insulating portion surrounds the lead-out contact and is connected to the lead-out contact.

7. The semiconductor device as claimed in claim 5, characterized in that, A second insulating portion connects at least one first insulating portion and at least one first insulating layer.

8. The semiconductor device as claimed in claim 5, characterized in that, The gate layer extends along a second direction perpendicular to the first direction, and the gate layer, the dielectric layer, and the first insulating portion of the same layer are arranged along the second direction. The second insulating portion includes a first inclined surface extending along a third direction, the third direction intersecting the first direction and the second direction, the first inclined surface being away from the first insulating portion connected to the second insulating portion, and the first inclined surface being connected to one of the lead-out contacts.

9. The semiconductor device as claimed in claim 2, characterized in that, One of the lead-out contact groups includes a first lead-out contact and a second lead-out contact, the first lead-out contact being disposed around the second lead-out contact; the first insulating portion is connected to the first lead-out contact.

10. The semiconductor device as claimed in claim 9, characterized in that, The stacked structure further includes a first surface, and the lead-out contact group extends from the first surface into the interior of the stacked structure along the first direction; The first lead-out contact includes a first connection portion and a second connection portion. The first connection portion is located between two adjacent first insulating layers and is connected to the gate layer. The second connection portion extends along the first direction and is connected to the end of the first connection portion away from the gate layer. The end of the second connection portion away from the first connection portion extends to the first surface.

11. The semiconductor device as claimed in claim 10, characterized in that, The second lead-out contact includes a third connection portion, a fourth connection portion, and a fifth connection portion. The third connection portion is located between two adjacent first insulating layers and is connected to the gate layer. The fourth connection portion extends along the first direction and is connected to the end of the third connection portion away from the gate layer. The end of the fourth connection portion away from the third connection portion is connected to the fifth connection portion. The end of the fifth connection portion away from the fourth connection portion extends to the first surface. The second connection portion is disposed around a portion of the fifth connection portion.

12. The semiconductor device as claimed in claim 11, characterized in that, The fifth connection portion includes a second inclined surface at one end away from the first surface. The second inclined surface extends along a third direction that intersects the first direction and the gate layer extension direction. The second inclined surface is connected to the fourth connection portion.

13. The semiconductor device as claimed in claim 11, characterized in that, The lead-out contact group further includes a third insulating layer, which includes a third insulating portion and a fourth insulating portion. The third insulating portion and the fourth insulating portion are not discontinuously arranged. The third insulating portion is located between the second connecting portion of the first lead-out contact and the fifth connecting portion of the second lead-out contact. The fourth connecting portion surrounds the fourth insulating portion, and the fifth connecting portion is located on the fourth insulating portion.

14. The semiconductor device according to any one of claims 1-13, characterized in that, Different sets of lead-out contacts are connected to different gate layers.

15. A method for fabricating a semiconductor device, characterized in that, include: An initial stacked structure is formed, comprising alternating layers of gate layers and a first insulating layer; The initial stacked structure further includes a dielectric layer, which is disposed on the same layer as the gate layer; A first groove and a second groove are formed on the initial stacked structure, penetrating at least a portion of the first insulating layer and at least a portion of the dielectric layer, the first groove and the second groove extending and communicating in a first direction; and Multiple lead-out contact groups are formed in the first groove and the second groove, penetrating the initial stacked structure. Each lead-out contact group includes multiple lead-out contacts extending to different depths of the stacked structure along a first direction and insulated from each other. The multiple lead-out contacts are respectively connected to one of the gate layers.

16. The method for fabricating a semiconductor device as described in claim 15, characterized in that, Prior to the step of forming a plurality of lead-out contact groups penetrating the initial stacked structure within the first and second grooves, the method further includes: A portion of the dielectric layer is removed to obtain a plurality of third grooves; the third grooves extend along the extension direction of the gate layer and are respectively connected to the first groove and the second groove. Insulating material is filled on the sidewalls and bottom walls of the first and second grooves, and inside the third groove; and At least a portion of the insulating material is removed while the insulating material located within the third groove is retained, exposing at least a portion of the dielectric layer at the junction of the first and second grooves and at least a portion of the dielectric layer located below the bottom of the second groove.

17. The method for fabricating a semiconductor device as described in claim 16, characterized in that, Prior to the step of removing part of the dielectric layer to obtain a plurality of third grooves, a first insulating layer is located at the bottom of the second groove; The steps of removing at least a portion of the insulating material and retaining the insulating material located within the third groove include: At least a portion of the insulating material located on the sidewalls of the first and second grooves, as well as all the insulating material located at the bottom of the second groove, is removed to obtain a second insulating layer; the second insulating layer includes a first insulating portion located within the third groove. and Remove the first insulating layer located at the bottom of the second groove to expose at least a portion of the dielectric layer.

18. The method for fabricating a semiconductor device as described in claim 17, characterized in that, In the step of removing at least a portion of the insulating material located on the sidewalls of the first and second grooves, and all of the insulating material at the bottom of the second groove, to obtain the second insulating layer A portion of the insulating material located on the sidewall of the first groove and / or the second groove is retained, and this portion of the insulating material is a second insulating portion connected to the plurality of first insulating portions.

19. The method for fabricating a semiconductor device as described in claim 16, characterized in that, The step of forming a plurality of lead-out contact groups penetrating the stacked structure within the first and second grooves includes: Remove the entire dielectric layer containing the dielectric layer exposed from the first groove and the second groove to form a fourth groove communicating with the first groove and a fifth groove communicating with the second groove. A first lead-out contact is formed in the fourth groove and on the sidewall of the first groove; and an initial second lead-out contact is formed in the fifth groove and on the sidewall of the second groove. A third insulating portion is formed on the surface of the first lead-out contact located within the first groove, and a fourth insulating portion is formed within the space formed by the initial second lead-out contact located within the second groove and the dielectric layer exposed from the second groove, to obtain a third insulating layer; and A conductive material is formed within the space enclosed by the third insulating portion to connect with the initial second lead-out contact, thereby obtaining the second lead-out contact.

20. A storage system, characterized in that, include: The semiconductor device as described in claims 1-14; and A controller, coupled to the memory, is used to control the memory to store data.

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