Semiconductor memory device and electronic system including same

Abstract

The invention provides a semiconductor memory device and an electronic system including the same, the semiconductor memory device may include: a cell substrate including a first surface and a second surface opposite the first surface; and a landing pattern including a third surface and a fourth surface opposite to the third surface, the landing pattern being spaced apart from the cell substrate in the horizontal direction. The semiconductor memory device may include: a plurality of gate electrodes sequentially stacked on a first surface and a third surface; a channel structure on the cell substrate, the channel structure extending vertically and crossing the plurality of gate electrodes; an upper insulating film covering the second surface and the fourth surface; an input / output pad on the upper insulating film, the input / output pad overlapping at least a portion of the plurality of gate electrodes in a vertical direction; and a support contact extending through the upper insulating film and connecting the landing pattern and the input / output pad.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor memory device, a method of manufacturing the same, and an electronic system including the same, and more particularly, to a semiconductor memory device including three-dimensionally arranged memory cells, a method of manufacturing the same, and an electronic system including the same. Background Art

[0002] As electronic systems increasingly use semiconductor memory devices that can store large amounts of data, methods that can increase the data storage capacity of semiconductor memory devices are being studied. One of the methods that has been proposed for increasing the data storage capacity of semiconductor memory devices provides a semiconductor memory device that includes three-dimensionally arranged memory cells instead of two-dimensionally arranged memory cells. Summary of the invention

[0003] Aspects of the present disclosure provide a semiconductor memory device having improved integration.

[0004] Aspects of the present disclosure also provide methods of manufacturing semiconductor devices having improved integration.

[0005] Aspects of the present disclosure also provide an electronic system including a semiconductor device having improved integration.

[0006] However, aspects of the present disclosure are not limited to those set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0007] According to some aspects of the present disclosure, a semiconductor memory device is provided, comprising: a unit substrate, comprising a first surface and a second surface opposite to the first surface; a landing pattern, comprising a third surface and a fourth surface opposite to the third surface, the landing pattern being spaced apart from the unit substrate in a horizontal direction; a plurality of gate electrodes stacked in sequence on the first surface and the third surface; a channel structure on the unit substrate, the channel structure extending in a vertical direction intersecting the first surface, the channel structure intersecting the plurality of gate electrodes; an upper insulating film covering the second surface and the fourth surface; an input / output pad on the upper insulating film, the input / output pad overlapping with at least a portion of the plurality of gate electrodes in a vertical direction; and a supporting contact extending through the upper insulating film and connecting the landing pattern and the input / output pad.

[0008] According to some aspects of the present disclosure, a semiconductor memory device is provided, which includes: a peripheral circuit structure, including a peripheral circuit substrate and a peripheral circuit element on the peripheral circuit substrate; and a unit structure stacked on the peripheral circuit structure, wherein the unit structure includes: a unit substrate, including a first surface facing the peripheral circuit structure and a second surface opposite to the first surface; a landing pattern, including a third surface facing the peripheral circuit structure and a fourth surface opposite to the third surface, the landing pattern being spaced apart from the unit substrate in a horizontal direction; a stacked structure, including a plurality of mold insulating films and a plurality of gate electrodes alternately stacked on the first surface and the third surface; a channel structure extending in a vertical direction intersecting the first surface, the channel structure extending through the stacked structure; an input / output pad, on the second surface and the fourth surface, the input / output pad overlapping with at least a portion of the stacked structure in a vertical direction; a contact plug extending in a vertical direction and electrically connecting the peripheral circuit element and the input / output pad; an upper insulating film interposed between the unit substrate and the input / output pad and between the landing pattern and the input / output pad; and a supporting contact extending through the upper insulating film and connecting the landing pattern and the input / output pad.

[0009] According to some aspects of the present disclosure, there is provided a method for manufacturing a semiconductor memory device, the method comprising: forming a plurality of gate electrodes stacked in sequence on a base substrate; forming a channel structure intersecting the plurality of gate electrodes; forming a preliminary substrate that replaces the base substrate; patterning the preliminary substrate to form a unit substrate connected to the channel structure and a landing pattern spaced apart from the unit substrate; forming an upper insulating film covering the unit substrate and the landing pattern in a horizontal direction; forming a supporting contact extending through the upper insulating film and connected to the landing pattern; and forming an input / output pad connected to the supporting contact on the upper insulating film, at least a portion of the input / output pad overlapping a portion of the plurality of gate electrodes.

[0010] According to some aspects of the present disclosure, an electronic system is provided, which includes: a main board; a semiconductor memory device, including a peripheral circuit structure and a unit structure stacked in sequence on the main board; and a controller on the main board, the controller being electrically connected to the semiconductor memory device, wherein the unit structure includes: a unit substrate, including a first surface and a second surface opposite to the first surface; a landing pattern, including a third surface and a fourth surface opposite to the third surface, the landing pattern being spaced apart from the unit substrate in a horizontal direction; a plurality of gate electrodes stacked in sequence on the first surface and the third surface; a channel structure on the unit substrate, the channel structure extending in a vertical direction intersecting the first surface, the channel structure intersecting the plurality of gate electrodes; an upper insulating film covering the second surface and the fourth surface; an input / output pad on the upper insulating film, the input / output pad overlapping with at least a portion of the plurality of gate electrodes in a vertical direction and being electrically connected to the controller; and a supporting contact extending through the upper insulating film and connecting the landing pattern with the input / output pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0012] Figure 1 is a block diagram for describing a semiconductor memory device according to some embodiments.

[0013] Figure 2 is a circuit diagram for describing a semiconductor memory device according to some embodiments.

[0014] Figure 3 is a schematic layout diagram for describing a semiconductor memory device according to some embodiments.

[0015] Figure 4 Is used to describe Figure 3 Layout diagram of area S1.

[0016] Figure 5 It is along Figure 4 A cross-sectional view taken along line AA.

[0017] Figure 6 Is used to describe Figure 5 Magnified view of region R1.

[0018] Figure 7 Is used to describe Figure 5 Magnified view of region R2.

[0019] Figure 8 and Fig. 9 is a cross-sectional view for describing a semiconductor memory device according to some embodiments.

[0020] Fig.10 is a layout diagram for describing a semiconductor memory device according to some embodiments.

[0021] Fig.11 It is along Fig.10 A cross-sectional view taken along line BB.

[0022] Fig.12 is a layout diagram for describing a semiconductor memory device according to some embodiments.

[0023] Fig.13 It is along Fig.12 A cross-sectional view taken along line CC.

[0024] Fig.14 is a layout diagram for describing a semiconductor memory device according to some embodiments.

[0025] Fig.15 It is along Fig.14 A cross-sectional view taken along line DD.

[0026] Figures 16 to 18 are various layout diagrams for describing a semiconductor memory device according to some embodiments.

[0027] Fig.19 is a schematic layout diagram for describing a semiconductor memory device according to some embodiments.

[0028] Fig. 20 Is used to describe Fig.19 Layout diagram of area S2.

[0029] Fig.21 It is along Fig. 20 A cross-sectional view taken along line EE.

[0030] Fig. 22 is a layout diagram for describing a semiconductor memory device according to some embodiments.

[0031] Fig.23 It is along Fig. 22 A cross-sectional view taken along line FF.

[0032] Fig.24 and Fig.25 are various layout diagrams for describing a semiconductor memory device according to some embodiments.

[0033] Figures 26 to 37 is a diagram for describing intermediate steps of a method of manufacturing a semiconductor memory device according to some embodiments.

[0034] Fig.38 is a block diagram for describing an electronic system according to some embodiments.

[0035] Fig.39 is a perspective view for describing an electronic system according to some embodiments.

[0036] Fig.40 It is along Fig.39 A schematic cross-sectional view taken along line II. DETAILED DESCRIPTION

[0037] In the following, reference will be made to Figures 1 to 25 Semiconductor memory devices according to some embodiments are described.

[0038] Figure 1 is a block diagram for describing a semiconductor memory device according to some embodiments.

[0039] The memory cell array 20 may include a plurality of memory cell blocks BLK1 to BLKn. Each of the memory cell blocks BLK1 to BLKn may include Figure 1 The memory cell array 20 may be connected to the peripheral circuit 30 through at least one bit line BL, at least one word line WL, at least one string selection line SSL, and at least one ground selection line GSL. Specifically, the memory cell blocks BLK1 to BLKn may be connected to the row decoder 33 through the word lines WL, the string selection lines SSL, and the ground selection lines GSL. In addition, the memory cell blocks BLK1 to BLKn may be connected to the page buffer 35 through the bit lines BL.

[0040] The peripheral circuit 30 may be external to the semiconductor memory device 10 ( Figure 1 The peripheral circuit 30 receives the address ADDR, the command CMD and the control signal CTRL from an external device or an external component (not shown in the figure), and the peripheral circuit 30 can send data DATA to and receive data DATA from an external device of the semiconductor memory device 10 (the external device can be the same as or different from the external device or external component that provides the address ADDR, the command CMD and the control signal CTRL to the peripheral circuit 30). The peripheral circuit 30 may include a control logic 37, a row decoder 33 and a page buffer 35. Although not shown in the figure, the peripheral circuit 30 may include a control logic 37, a row decoder 33 and a page buffer 35. Figure 1 , but the peripheral circuit 30 may further include various sub-circuits such as an input / output circuit, a voltage generating circuit configured to generate various voltages used in the operation of the semiconductor memory device 10, and an error correction circuit configured to correct errors in the data DATA read from the memory cell array 20.

[0041] The control logic 37 may be connected to the row decoder 33, the input / output circuit, and the voltage generating circuit. The control logic 37 may be configured to control the overall operation of the semiconductor memory device 10. The control logic 37 may generate various internal control signals used in the semiconductor memory device 10 in response to the control signal CTRL. For example, when performing a storage operation such as a program operation or an erase operation, the control logic 37 may adjust the voltage level supplied to at least one word line WL and at least one bit line BL.

[0042] The row decoder 33 may select at least one of the plurality of memory cell blocks BLK1 to BLKn in response to the address ADDR, and may select at least one word line WL, at least one string selection line SSL, and at least one ground selection line GSL of the selected memory cell block BLK1 to BLKn. In addition, the row decoder 33 may transmit a voltage used in performing a storage operation to the word line WL of the selected memory cell block BLK1 to BLKn.

[0043] The page buffer 35 may be connected to the memory cell array 20 through the bit line BL. The page buffer 35 may operate as a write driver or a sense amplifier. Specifically, when a program operation is performed, the page buffer 35 may operate as a write driver to apply a voltage to the bit line BL according to the data DATA to be stored in the memory cell array 20. At the same time, when a read operation is performed, the page buffer 35 may operate as a sense amplifier to sense the data DATA stored in the memory cell array 20.

[0044] Figure 2 is a circuit diagram for describing a semiconductor memory device according to some embodiments.

[0045] Reference Figure 2 , a memory cell array (eg, Figure 1 The memory cell array 20) in FIG. 1 may include a common source line CSL, a plurality of bit lines BL, and a plurality of cell strings CSTR.

[0046] The plurality of bit lines BL may be arranged two-dimensionally in a plane including a first direction X and a second direction Y. For example, the bit lines BL may each extend in the second direction Y and may be arranged in the first direction X while being spaced apart from each other in the first direction X. Some of the plurality of cell strings CSTR may be connected in parallel to each bit line BL. The cell strings CSTR may be connected in common to a common source line CSL. That is, the plurality of cell strings CSTR may be between the bit lines BL and the common source line CSL.

[0047] Each cell string CSTR may include a ground selection transistor GST connected to a common source line CSL, a string selection transistor SST connected to a bit line BL, and a plurality of memory cell transistors MCT between the ground selection transistor GST and the string selection transistor SST. Each memory cell transistor MCT may include a data storage element. The ground selection transistor GST, the string selection transistor SST, and the memory cell transistor MCT may be connected in series.

[0048] The common source line CSL may be commonly connected to the source of the ground selection transistor GST. In addition, the ground selection line GSL, a plurality of word lines WL11 to WL1n and WL21 to WL2n, and a string selection line SSL may be between the common source line CSL and the bit line BL. The ground selection line GSL may be used as a gate electrode of the ground selection transistor GST, the word lines WL11 to WL1n and WL21 to WL2n may be used as gate electrodes of the memory cell transistors MCT, and the string selection line SSL may be used as a gate electrode of the string selection transistor SST.

[0049] Figure 3 is a schematic layout diagram for describing a semiconductor memory device according to some embodiments. Figure 4 Is used to describe Figure 3 Layout diagram of area S1. Figure 5 It is along Figure 4 A cross-sectional view taken along line AA. Figure 6 Is used to describe Figure 5 Magnified view of region R1. Figure 7 Is used to describe Figure 5 Magnified view of region R2.

[0050] Reference Figures 3 to 7 , a semiconductor memory device according to some embodiments includes a cell structure CELL, a peripheral circuit structure PERI, an upper insulating film 342 , a supporting contact 350 , and an input / output pad 380 .

[0051] The cell structure CELL may include a cell array area CA and an external area PA. A memory cell array (eg, Figure 1 The memory cell array 20 in the cell array region CA may be formed in the cell array region CA. For example, the cell substrate 100, the channel structure CH, the gate electrodes 112 and 117, and the bit lines BL, which will be described in more detail later, may be in the cell array region CA. The external region PA may be a peripheral region surrounding the cell array region CA. Figure 3 Four cell array areas CA arranged in a lattice form in the outer area PA are shown, but this is only an example, and the number and arrangement of the cell array areas CA are not limited to those shown in the drawings.

[0052] The cell structure CELL may include a cell substrate 100 , a landing pattern 102 , an insulating substrate 105 , stack structures MS1 and MS2 , interlayer insulating films 142 and 144 , a channel structure CH, a word line cutting region WC, a bit line BL, and a cell wiring structure 180 .

[0053] The unit substrate 100 may be arranged in the unit array area CA. The unit substrate 100 may include, for example, a semiconductor substrate such as a silicon substrate, a germanium substrate, or a silicon germanium substrate. Alternatively, the unit substrate 100 may also include a silicon on insulator (SOI) substrate or a germanium on insulator (GOI) substrate.

[0054] The unit substrate 100 may include a first surface 100 a and a second surface 100 b opposite to each other. In the following description, the first surface 100 a may be referred to as a front surface of the unit substrate 100 , and the second surface 100 b may also be referred to as a back surface of the unit substrate 100 .

[0055] In some embodiments, the unit substrate 100 may include a conductive material. The conductive material may include, but is not limited to, for example, polysilicon doped with impurities, metal, or metal silicide. For example, the unit substrate 100 may include polysilicon (poly-Si) doped with N-type impurities (e.g., phosphorus (P), arsenic (As), etc.). The unit substrate 100 may be provided as a common source line (e.g., Figure 2 in CSL).

[0056] The insulating substrate 105 may be formed around the unit substrate 100. The insulating substrate 105 may form an insulating region around the unit substrate 100 on the cell array region CA and / or the outer region PA. The insulating substrate 105 may include, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, and / or silicon carbide.

[0057] The landing pattern 102 may be provided in the cell array area CA. The landing pattern 102 may be formed around the unit substrate 100. The landing pattern 102 may be spaced apart from the unit substrate 100. For example, a portion of the insulating substrate 105 may be interposed between the unit substrate 100 and the landing pattern 102. When viewed in a plan view, the landing pattern 102 may be provided within the insulating substrate 105, and the landing pattern 102 may be electrically separated from the unit substrate 100. In some embodiments, the landing pattern 102 may be electrically separated from the unit substrate 100 by the insulating substrate 105.

[0058] like Figure 7As shown, the landing pattern 102 may include a third surface 102a and a fourth surface 102b opposite to each other. The third surface 102a of the landing pattern 102 may face the same direction as the first surface 100a of the unit substrate 100, and the fourth surface 102b of the landing pattern 102 may face the same direction as the second surface 100b of the unit substrate 100. In some embodiments, the third surface 102a of the landing pattern 102 may be coplanar with the first surface 100a of the unit substrate 100. In some embodiments, the fourth surface 102b of the landing pattern 102 may be coplanar with the second surface 100b of the unit substrate 100.

[0059] In some embodiments, the landing pattern 102 may be closer to the outer area PA than the unit substrate 100. In some embodiments, the landing pattern 102 may extend longitudinally in the first direction X, and may have a larger size in the first direction X than in the second direction Y.

[0060] In some embodiments, the landing pattern 102 may include a conductive material. The conductive material may include, but is not limited to, polysilicon doped with impurities, metal, or metal silicide. As an example, the landing pattern 102 may include polysilicon (poly-Si) doped with N-type impurities (e.g., phosphorus (P), arsenic (As), etc.).

[0061] In some embodiments, the landing pattern 102 may be formed at the same level as the unit substrate 100. Here, the term "same level" may refer to or include formation by the same manufacturing process. For example, the landing pattern 102 may include the same material as the unit substrate 100. Alternatively, the landing pattern 102 may have the same material composition as the unit substrate 100.

[0062] The stacked structures MS1 and MS2 may be formed on the first surface 100a of the unit substrate 100 and the third surface 102a of the landing pattern 102. The stacked structures MS1 and MS2 may include a plurality of gate electrodes 112 and 117 and a plurality of mold insulating films 110 and 115 stacked on the unit substrate 100 and the landing pattern 102. Each of the gate electrodes 112 and 117 and each of the mold insulating films 110 and 115 may have a layered structure extending in a horizontal direction (e.g., a first direction X and / or a second direction Y) parallel to the upper surface of the unit substrate 100. The gate electrodes 112 and 117 may be sequentially stacked on the unit substrate 100 while being spaced apart from each other by the mold insulating films 110 and 115.

[0063] In some embodiments, edges of the gate electrodes 112 and 117 adjacent to the outer area PA may be stacked in a step shape. For example, edges of the stack structures MS1 and MS2 adjacent to the outer area PA may be patterned in a step shape.

[0064] In some embodiments, the stack structures MS1 and MS2 may include a plurality of stacks (e.g., a first stack MS1 and a second stack MS2) sequentially stacked on the unit substrate 100 and the landing pattern 102. The number of stacks stacked on the unit substrate 100 and the landing pattern 102 is shown to be two, but this is only for ease of description, and in some embodiments, the number of stacks stacked on the unit substrate 100 may also be three or more.

[0065] The first stack MS1 may include a first mold insulating film 110 and a first gate electrode 112 alternately stacked on the unit substrate 100 and the landing pattern 102. In some embodiments, the first gate electrode 112 may include at least one ground selection line (e.g., Figure 2 ) and a plurality of first word lines (eg, Figure 2 The number and shape of the first mold insulating film 110 and the first gate electrode 112 are merely examples and are not limited to the numbers and shapes shown.

[0066] The second stack MS2 may include a second mold insulating film 115 and a second gate electrode 117 alternately stacked on the first stack MS1. In some embodiments, the second gate electrode 117 may include a plurality of second word lines (eg, Figure 2 WL21 to WL2n in the example) and at least one string selection line (eg, Figure 2 The number and shape of the second mold insulating film 115 and the second gate electrode 117 are only examples and are not limited to the number and shape shown.

[0067] The gate electrodes 112 and 117 may each include, but are not limited to, a conductive material, such as a metal (such as tungsten (W), cobalt (Co), or nickel (Ni)) or a semiconductor material (such as silicon). As an example, the gate electrodes 112 and 117 may each include at least one of tungsten (W), molybdenum (Mo), and ruthenium (Ru). As another example, the gate electrodes 112 and 117 may each include polysilicon.

[0068] The mold insulating films 110 and 115 may each include, for example, but not limited to, at least one of silicon oxide, silicon nitride, and silicon oxynitride. As an example, the mold insulating films 110 and 115 may each include a silicon oxide film.

[0069] Interlayer insulating films 142 and 144 may be formed on the unit substrate 100, the landing pattern 102, and the insulating substrate 105. The interlayer insulating films 142 and 144 may cover the stacked structures MS1 and MS2. In some embodiments, the interlayer insulating films 142 and 144 may include a first interlayer insulating film 142 and a second interlayer insulating film 144. The first interlayer insulating film 142 may cover the first stack MS1, and the second interlayer insulating film 144 may cover the second stack MS2. The first interlayer insulating film 142 and the second interlayer insulating film 144 may each include, but are not limited to, at least one of, for example, silicon oxide, silicon oxynitride, and a low-k material having a dielectric constant lower than that of silicon oxide.

[0070] The channel structure CH may be formed on the first surface 100a of the unit substrate 100. The channel structure CH may extend in a vertical direction (hereinafter, referred to as a third direction Z) intersecting the first surface 100a of the unit substrate 100. The channel structure CH may penetrate or extend through the stacked structures MS1 and MS2. For example, the channel structure CH may have a column shape (e.g., a cylindrical shape) extending longitudinally in the third direction Z. Therefore, the channel structure CH may intersect the plurality of gate electrodes 112 and 117.

[0071] In some embodiments, the channel structure CH may be connected to the unit substrate 100. For example, as shown, the upper surface of the channel structure CH may be coplanar with the first surface 100a of the unit substrate 100, or may be higher than the first surface 100a of the unit substrate 100. The upper surface of the channel structure CH may extend into the unit substrate 100.

[0072] In some embodiments, the plurality of channel structures CH may be arranged in a zigzag shape. Figure 4 As shown, the channel structures CH can be arranged to be staggered with each other in the first direction X and the second direction Y. The channel structure CH can further improve the integration of the semiconductor memory device. The number and arrangement of the channel structures CH are only examples and are not limited to the number and arrangement shown. In some embodiments, a plurality of channel structures CH can be arranged in a honeycomb shape.

[0073] In some embodiments, the channel structure CH may have a step between the first stack MS1 and the second stack MS2. Figure 5 As shown, a side surface of the channel structure CH may have a curved portion at a boundary between the first stack MS1 and the second stack MS2.

[0074] In some embodiments, Figure 6 As shown, each channel structure CH may include a semiconductor pattern 130 and an information storage film 132 .

[0075] The semiconductor pattern 130 may extend in the third direction Z and may intersect the plurality of gate electrodes 112 and 117. The semiconductor pattern 130 is shown to have a cup shape, but this is only an example. For example, the semiconductor pattern 130 may also have various shapes, such as a cylindrical shape, a rectangular shape, and a densely packed column shape. The semiconductor pattern 130 may include, but is not limited to, for example, semiconductor materials such as single crystal silicon, polycrystalline silicon, organic semiconductor materials, and carbon nanostructures.

[0076] In some embodiments, the semiconductor pattern 130 may be connected to the unit substrate 100. For example, one end (e.g., an upper end) of the semiconductor pattern 130 may be exposed from the information storage film 132 and connected to the unit substrate 100. In some exemplary embodiments, the semiconductor pattern 130 may penetrate the first surface 100a of the unit substrate 100. For example, one end (e.g., an upper end) of the semiconductor pattern 130 may protrude more than the information storage film 132. Such a semiconductor pattern 130 may reduce contact resistance by increasing a contact area with the unit substrate 100.

[0077] The information storage film 132 may be interposed between the semiconductor pattern 130 and each of the gate electrodes 112 and 117. For example, the information storage film 132 may extend along the outer side surface of the semiconductor pattern 130. The information storage film 132 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high-k material having a dielectric constant higher than that of silicon oxide. The high-k material may include, for example, at least one of aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide, lanthanum aluminum oxide, or dysprosium scandium oxide, or a combination of two or more thereof, but the present disclosure is not limited thereto.

[0078] In some embodiments, the information storage film 132 may be formed as multiple films. Figure 6 As shown, the information storage film 132 may include a tunnel insulating film 132 a , a charge storage film 132 b , and a blocking insulating film 132 c sequentially stacked on the outer side surface of the semiconductor pattern 130 .

[0079] The tunnel insulating film 132a may include, for example, silicon oxide or a high-k material having a higher dielectric constant than silicon oxide (eg, aluminum oxide (Al 2 O 3 ) or hafnium oxide (HfO 2 )). The charge storage film 132b may include, for example, silicon nitride. The blocking insulating film 132c may include, for example, silicon oxide or a high-k material having a higher dielectric constant than silicon oxide (for example, aluminum oxide (Al 2 O 3 ) or hafnium oxide (HfO 2)).

[0080] In some embodiments, the channel structure CH may further include a filling insulating film 134. The filling insulating film 134 may fill the inside of the semiconductor pattern 130 having the cup shape or may be within the inside of the semiconductor pattern 130 having the cup shape. The filling insulating film 134 may include, but is not limited to, an insulating material such as silicon oxide.

[0081] In some embodiments, the channel structure CH may further include a channel pad 136. The channel pad 136 may be formed to be connected to the other end (eg, lower end) of the semiconductor pattern 130. The channel pad 136 may include, but is not limited to, a conductive material such as polysilicon doped with impurities or a metal.

[0082] In some embodiments, the dummy channel structure DCH may be formed on the third surface 102a of the landing pattern 102. The dummy channel structure DCH may extend in the third direction Z and penetrate or extend through at least a portion of the stacked structures MS1 and MS2. When the edges of the stacked structures MS1 and MS2 adjacent to the outer area PA are patterned in a step shape, the dummy channel structure DCH may penetrate or extend through only a portion of the stacked structures MS1 and MS2.

[0083] In some embodiments, the dummy channel structure DCH may be connected to the landing pattern 102. For example, as shown, the upper surface of the dummy channel structure DCH may be coplanar with the third surface 102a of the landing pattern 102, or may be higher than the third surface 102a of the landing pattern 102. The upper surface of the dummy channel structure DCH may extend into the landing pattern 102.

[0084] In some exemplary embodiments, the dummy channel structure DCH may be formed at the same level and by the same process as the channel structure CH. For example, the dummy channel structure DCH may include the semiconductor pattern 130 , the information storage film 132 , the filling insulating film 134 , and the channel pad 136 described above.

[0085] It is shown that the size (eg, height and / or width) of the dummy channel structure DCH is the same as that of the channel structure CH, but this is only an example, and the size of the dummy channel structure DCH may be larger or smaller than that of the channel structure CH.

[0086] The word line cutting region WC may extend in the first direction X and may cut the stacked structures MS1 and MS2. A plurality of word line cutting regions WC may each extend in the first direction X and be arranged along the second direction Y while being spaced apart from each other. The stacked structures MS1 and MS2 may be divided by the word line cutting regions WC to form a plurality of memory cell blocks (e.g., Figure 1BLK1 to BLKn in the .

[0087] In some embodiments, the word line cutting region WC may be filled with an insulating material. The insulating material may include, but is not limited to, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0088] Each bit line BL may be formed on the stacked structures MS1 and MS2. Each bit line BL may extend longitudinally in the second direction Y and may be connected to a plurality of channel structures CH arranged along the second direction Y. For example, a bit line contact 182 may be connected to the channel pad 136 and may be within the interlayer insulating films 142 and 144. Each bit line BL may be electrically connected to the channel structure CH through the bit line contact 182. The plurality of bit lines BL may each extend in the second direction Y and may be arranged along the first direction X while being spaced apart from each other.

[0089] In some example embodiments, each bit line BL may be interposed between the channel structure CH and the peripheral circuit structure PERI.

[0090] The cell wiring structure 180 may be formed on the stack structures MS1 and MS2 . For example, the first inter-wiring insulating film 146 may be formed on the interlayer insulating films 142 and 144 , and the cell wiring structure 180 may be in the first inter-wiring insulating film 146 .

[0091] The cell wiring structure 180 may be electrically connected to a plurality of memory cells formed in the cell array area CA. For example, the cell wiring structure 180 may be electrically connected to the bit line BL. Thus, the cell wiring structure 180 may be electrically connected to the channel structure CH. In addition, although not specifically shown, the cell wiring structure 180 may be electrically connected to each of the gate electrodes 112 and 117 and the cell substrate 100. For example, a source contact (not shown) extending in the third direction Z and connected to the cell substrate 100 and a plurality of gate contacts (not shown) extending in the third direction Z and connected to the corresponding gate electrodes 112 and 117 may be formed. The cell wiring structure 180 may be electrically connected to the source contact and the gate contact. The number and arrangement of the layers of the cell wiring structure 180 shown are examples only and are not limited thereto.

[0092] The peripheral circuit structure PERI may include a peripheral circuit substrate 200 , at least one peripheral circuit element PT, and a peripheral circuit wiring structure 260 .

[0093] The peripheral circuit substrate 200 may include, for example, a semiconductor substrate such as a silicon substrate, a germanium substrate, or a silicon germanium substrate. Alternatively, the peripheral circuit substrate 200 may include a silicon on insulator (SOI) substrate or a germanium on insulator (GOI) substrate.

[0094] The peripheral circuit substrate 200 may have a fifth surface 200 a and a sixth surface 200 b opposite to each other. In the following description, the fifth surface 200 a may be referred to as the front surface of the peripheral circuit substrate 200 , and the sixth surface 200 b may also be referred to as the back surface of the peripheral circuit substrate 200 .

[0095] The peripheral circuit element PT may be formed on the fifth surface 200a of the peripheral circuit substrate 200. The peripheral circuit element PT may constitute a peripheral circuit (eg, Figure 1 For example, the peripheral circuit element PT may include control logic (e.g., Figure 1 control logic 37 in), a row decoder (e.g., Figure 1 The row decoder 33 in the embodiment of the present invention and the page buffer (eg, Figure 1 The page buffer 35 in.

[0096] The peripheral circuit element PT may include, but is not limited to, for example, a transistor. In some embodiments, the peripheral circuit element PT may include various active elements (such as transistors) and various passive elements (such as capacitors, resistors, and inductors).

[0097] The peripheral circuit wiring structure 260 may be formed on the peripheral circuit element PT. For example, the second inter-wiring insulating film 240 may be formed on the fifth surface 200a of the peripheral circuit substrate 200, and the peripheral circuit wiring structure 260 may be within the second inter-wiring insulating film 240. The peripheral circuit wiring structure 260 may be electrically connected to the peripheral circuit element PT. The number and arrangement of the layers of the peripheral circuit wiring structure 260 shown are examples only and are not limited thereto.

[0098] In some embodiments, the cell structure CELL may be stacked on the peripheral circuit structure PERI in the third direction Z. For example, the cell structure CELL may be stacked on the second inter-wiring insulating film 240 .

[0099] In some embodiments, the first surface 100 a of the unit substrate 100 may face the peripheral circuit structure PERI. For example, the first surface 100 a of the unit substrate 100 may face the fifth surface 200 a of the peripheral circuit substrate 200 .

[0100] According to some embodiments, a semiconductor memory device may have a chip-to-chip (C2C) structure. The C2C structure may refer to a structure in which an upper chip including a cell structure CELL is manufactured on a first wafer, a lower chip including a peripheral circuit structure PERI is manufactured on a second wafer different from the first wafer, and then the upper chip and the lower chip are connected to each other by a bonding method.

[0101] As an example, the bonding method may refer to a method of electrically connecting a first bonding metal 190 formed on the uppermost metal layer of an upper chip (e.g., a chip including a cell structure CELL) and a second bonding metal 290 formed on the uppermost metal layer of a lower chip (e.g., a chip including a peripheral circuit structure PERI). For example, when the first bonding metal 190 and the second bonding metal 290 are formed of copper (Cu), the bonding method may be a Cu-Cu bonding method. However, this is only an example, and the first bonding metal 190 and the second bonding metal 290 may also be formed of various other metals such as aluminum (Al) or tungsten (W).

[0102] As the first bonding metal 190 and the second bonding metal 290 are bonded, the cell wiring structure 180 may be electrically connected to the peripheral circuit wiring structure 260. Thus, the bit line BL, each of the gate electrodes 112 and 117, and / or the cell substrate 100 may be electrically connected to the peripheral circuit element PT.

[0103] The upper insulating film 342 may be formed on the unit substrate 100, the landing pattern 102, and / or the insulating substrate 105. The upper insulating film 342 may cover the second surface 100b of the unit substrate 100 and the fourth surface 102b of the landing pattern 102. The upper insulating film 342 may include, but is not limited to, at least one of silicon oxide, silicon oxynitride, and a low-k material having a dielectric constant lower than that of silicon oxide. The thickness of the upper insulating film 342 may be, for example, in the range from about 300 nm to about 1000 nm, including 300 nm and 1000 nm, but is not limited thereto.

[0104] The input / output pad 380 may be formed on the upper insulating film 342. The upper insulating film 342 may be interposed between the cell structure CELL and the input / output pad 380. At least a portion of the input / output pad 380 may overlap with the cell array area CA in the third direction Z. In some embodiments, the input / output pad 380 may be formed on the cell array area CA and the external area PA or extend over the cell array area CA and the external area PA. For example, a portion of the input / output pad 380 may overlap with the cell array area CA in the third direction Z, and another portion of the input / output pad 380 may overlap with the external area PA in the third direction Z.

[0105] The input / output pad 380 may be electrically connected to the cell structure CELL and / or the peripheral circuit structure PERI. For example, a first contact plug 360 may be formed, and the cell wiring structure 180 may be connected to the input / output pad 380. For example, the first contact plug 360 may extend in the third direction Z within the external area PA, and may penetrate or extend through the interlayer insulating films 142 and 144, the insulating substrate 105, and the upper insulating film 342. The input / output pad 380 may be electrically connected to the cell wiring structure 180 through the first contact plug 360. The first contact plug 360 may include, but is not limited to, a conductive material, for example, a metal material such as tungsten (W), molybdenum (Mo), ruthenium (Ru), cobalt (Co), or nickel (Ni).

[0106] In some embodiments, a plurality of first contact plugs 360 connected to one input / output pad 380 may be formed. Figure 4 4 shows seven first contact plugs 360 arranged along the first direction X with respect to one input / output pad 380 , but this is only an example, and the number and arrangement of the first contact plugs 360 are not limited to the number and arrangement shown.

[0107] In some embodiments, the first contact plug 360 may be spaced apart from the landing pattern 102 in a horizontal direction (eg, the first direction X and / or the second direction Y).

[0108] In some embodiments, the first contact plug 360 may include a first plug pattern 360a, a second plug pattern 360b, and a third plug pattern 360c. The first plug pattern 360a may be formed at the side of the stacked structures MS1 and MS2. The second plug pattern 360b may connect the cell wiring structure 180 and the first plug pattern 360a. The third plug pattern 360c may connect the input / output pad 380 and the first plug pattern 360a.

[0109] In some embodiments, the width of the first plug pattern 360a may decrease toward the third plug pattern 360c. In some embodiments, the width of the second plug pattern 360b may decrease toward the first plug pattern 360a. In some embodiments, the width of the third plug pattern 360c may decrease toward the first plug pattern 360a.

[0110] In some embodiments, the first plug pattern 360a and the third plug pattern 360c may contact each other within the insulation substrate 105. For example, an interface between the first plug pattern 360a and the third plug pattern 360c may be within the insulation substrate 105.

[0111] The supporting contact 350 may be formed on the landing pattern 102. The supporting contact 350 may extend in the third direction Z. The supporting contact 350 may connect the landing pattern 102 and the input / output pad 380 by penetrating the upper insulating film 342. The landing pattern 102 and the supporting contact 350 may form a load distribution structure that supports the input / output pad 380 on the cell array area CA. The supporting contact 350 may have a column shape (e.g., a cylindrical shape, a square column shape, or another polygonal column shape) extending longitudinally in the third direction Z. The width W1 of the supporting contact 350 may be about 200 nm to about 500 nm, but is not limited thereto.

[0112] In some embodiments, a plurality of support contacts 350 connected to one input / output pad 380 may be formed. Figure 4 14 support contacts 350 are shown arranged in a grid form with respect to one input / output pad 380 , but this is only an example, and the number and arrangement of the support contacts 350 are not limited to the number and arrangement shown.

[0113] In some embodiments, the width of each supporting contact 350 in one or more horizontal directions may decrease toward the landing pattern 102. This may result from an etching process performed on the fourth surface 102b of the landing pattern 102 to form the supporting contact 350.

[0114] In some embodiments, the lower surface of each support contact 350 may be formed below the fourth surface 102b of the landing pattern 102. For example, the lower surface of each support contact 350 may be formed between the third surface 102a of the landing pattern 102 and the fourth surface 102b of the landing pattern 102. In this case, the support contact 350 may be supported (e.g., strongly supported) by the landing pattern 102 to form a more effective load distribution structure.

[0115] In some embodiments, each support contact 350 may be formed at the same level as the third plug pattern 360c. For example, the support contact 350 may include the same conductive material as the third plug pattern 360c. Alternatively, the support contact 350 may have the same material composition as the third plug pattern 360c.

[0116] In some embodiments, the support contact 350 may be formed to be shallower than the third plug pattern 360c of the first contact plug 360. For example, Figure 7 As shown, based on the fourth surface 102b of the landing pattern 102 (or using the fourth surface 102b as a reference), the depth D1 of forming the support contact 350 may be less than the depth D2 of forming the third plug pattern 360c. This may be caused by the etching processes for forming the support contact 350 and the third plug pattern 360c being performed on different materials.

[0117] It is shown that the width W1 of the support contact 350 and the width W2 of the landing pattern 102 are the same, but this is only an example, and the width W1 of the support contact 350 and the width W2 of the landing pattern 102 may also be different from each other.

[0118] In some embodiments, a cover insulating film 344 may be formed on the upper insulating film 342. The cover insulating film 344 may include a pad opening 344o exposing at least a portion of the input / output pad 380. The input / output pad 380 may be electrically connected to an external device or the like through the pad opening 344o.

[0119] In some embodiments, an external contact structure 365 and an external pad 385 may be formed in the external area PA. The external pad 385 may be formed on the upper insulating film 342 and may be spaced apart from the input / output pad 380. The external contact structure 365 may connect the cell wiring structure 180 and the external pad 385. For example, the external contact structure 365 may extend in the third direction Z to penetrate or extend through the interlayer insulating films 142 and 144, the insulating substrate 105, and the upper insulating film 342.

[0120] The external pad 385 and the external contact structure 365 may be arranged at the edge of the external area PA. For example, the external pad 385 and the external contact structure 365 may be spaced farther from the cell array area CA than the input / output pad 380 and the first contact plug 360. According to some embodiments, the external pad 385 and the external contact structure 365 may form a crack detection circuit (CDC) of a semiconductor memory device.

[0121] In some embodiments, the external contact structure 365 may include a first contact pattern 365a, a second contact pattern 365b, and a third contact pattern 365c. The first contact pattern 365a may be formed at the side of the stacked structures MS1 and MS2. The second contact pattern 365b may connect the cell wiring structure 180 and the first contact pattern 365a. The third contact pattern 365c may connect the external pad 385 and the first contact pattern 365a.

[0122] In order to improve the integration of semiconductor memory devices, a so-called cell-on-pad structure has been proposed in which at least a portion of the input / output pad 380 overlaps with the cell array area CA. However, the cell-on-pad structure may present problems such as when the structure of the cell array area CA below the input / output pad 380 (e.g., stacked structures MS1 and MS2, etc.) is damaged or destroyed due to pressure applied to the input / output pad 380 during a bonding process (e.g., a wire bonding process). In addition, in the cell-on-pad structure, since at least a portion of the input / output pad 380 overlaps with the cell array area CA, parasitic capacitance may be generated between the input / output pad 380 and an electrical structure of the cell array area CA adjacent to the input / output pad 380 (e.g., the cell substrate 100 and / or the gate electrodes 112 and 117), and the parasitic capacitance may cause performance degradation of the semiconductor memory device.

[0123] The semiconductor memory device according to some exemplary embodiments may protect (e.g., effectively protect) the structure (e.g., stacked structures MS1 and MS2, etc.) in the cell array region CA using the landing pattern 102 and the supporting contact 350. Specifically, as described above, the landing pattern 102 may be in the cell array region CA, and the supporting contact 350 may connect the landing pattern 102 and the input / output pad 380 by penetrating or extending through the upper insulating film 342. By supporting the input / output pad 380 on the cell array region CA, the landing pattern 102 and the supporting contact 350 may form a load distribution structure for the pressure applied to the input / output pad 380. Thus, a semiconductor memory device with improved integration may be provided using an effective cell upper pad structure.

[0124] In some embodiments, the landing pattern 102 may include a different material from the unit substrate 100 .

[0125] As an example, the unit substrate 100 may include polysilicon doped with impurities, and the landing pattern 102 may include a material having higher mechanical strength than the unit substrate 100, such as a metal material. In this case, the supporting contact 350 may be supported (e.g., strongly supported) by the landing pattern 102 to form a more efficient load distribution structure.

[0126] As another example, the unit substrate 100 may include polysilicon doped with impurities, and the landing pattern 102 may include an insulating material such as silicon oxide. In this case, since parasitic capacitance is prevented from occurring between the unit substrate 100 and the landing pattern 102 or the occurrence of parasitic capacitance is reduced, a semiconductor memory device with improved performance may be provided.

[0127] Figure 8 and Fig. 9is a cross-sectional view for describing a semiconductor memory device according to some embodiments. For ease of description, only the above reference Figures 1 to 7 The descriptions of the parts overlap or their descriptions are omitted.

[0128] Reference Figure 3 , Figure 4 and Figure 8 The semiconductor memory device according to some example embodiments may further include a first conductive plate 106 and a second conductive plate 108 .

[0129] The first conductive plate 106 may be formed on the unit substrate 100. The first conductive plate 106 may be interposed between the unit substrate 100 and the upper insulating film 342. The first conductive plate 106 may be electrically connected to the unit substrate 100. For example, the first conductive plate 106 may be in contact with the upper surface of the unit substrate 100. The first conductive plate 106 may include, but is not limited to, a conductive material, such as a metal (such as tungsten (W), cobalt (Co), nickel (Ni)) or a metal silicide. The first conductive plate 106 may be used to reduce the common source line (for example, Figure 2 The common source line is a unit substrate 100 or includes a unit substrate 100.

[0130] The second conductive plate 108 may be formed on the landing pattern 102. The second conductive plate 108 may be interposed between the landing pattern 102 and the upper insulating film 342. The second conductive plate 108 may be electrically connected to the landing pattern 102. For example, the second conductive plate 108 may contact the upper surface of the landing pattern 102. The second conductive plate 108 may include, but is not limited to, a conductive material, for example, a metal (such as tungsten (W), cobalt (Co), nickel (Ni)) or a metal silicide.

[0131] The supporting contact 350 may be formed on the second conductive plate 108. The supporting contact 350 may connect the second conductive plate 108 and the input / output pad 380, and may penetrate or extend through the upper insulating film 342. The landing pattern 102, the second conductive plate 108, and the supporting contact 350 may be formed in a load distribution structure supporting the input / output pad 380 on the cell array area CA.

[0132] In some embodiments, the second conductive plate 108 may be formed at the same level as the first conductive plate 106. For example, the second conductive plate 108 may include the same conductive material as the first conductive plate 106. Alternatively, the second conductive plate 108 may have the same material composition as the first conductive plate 106.

[0133] Reference Figure 3 , Figure 4 and Fig. 9, in the semiconductor memory device according to some embodiments, the dummy channel structure DCH may be formed at a different level from the channel structure CH.

[0134] For example, the dummy channel structure DCH may include a material different from the channel structure CH. In some embodiments, the dummy channel structure DCH may include an insulating pattern 139. The insulating pattern 139 may include, but is not limited to, at least one of, for example, silicon oxide, silicon nitride, and silicon oxynitride. As an example, the insulating pattern 139 may include silicon oxide. In this case, since parasitic capacitance is prevented from occurring between the stacked structures MS1 and MS2 and the dummy channel structure DCH, a semiconductor memory device with additional improved performance may be provided.

[0135] Fig.10 is a layout diagram for describing a semiconductor memory device according to some embodiments. Fig.11 It is along Fig.10 For ease of explanation, only the above reference will be briefly described. Figures 1 to 7 Parts of the description overlap, or their description will be omitted.

[0136] Reference Figure 3 , Fig.10 and Fig.11 , the semiconductor memory device according to some embodiments may not include the above using Figures 3 to 7 In this case, since parasitic capacitance is prevented from occurring between the stack structures MS1 and MS2 and the dummy channel structure DCH, a semiconductor memory device having additional improved performance may be provided.

[0137] Fig.12 is a layout diagram for describing a semiconductor memory device according to some embodiments. Fig.13 It is along Fig.12 For ease of explanation, only the cross-sectional view similar to that shown above will be briefly described. Figures 1 to 7 Parts of the description overlap, or their description will be omitted.

[0138] Reference Figure 3 , Fig.12 and Fig.13 , the semiconductor memory device according to some embodiments may further include a second contact plug 362 .

[0139] A second contact plug 362 may be provided in the cell array region CA. The second contact plug 362 may connect the cell wiring structure 180 and the input / output pad 380. For example, the second contact plug 362 may extend longitudinally in the third direction Z within the cell array region CA, and may penetrate or extend through the interlayer insulating films 142 and 144, the stacked structures MS1 and MS2, the cell substrate 100, and the upper insulating film 342. The input / output pad 380 may be electrically connected to the cell wiring structure 180 through the first contact plug 360 and the second contact plug 362. The second contact plug 362 may include, but is not limited to, a conductive material, for example, a metal material such as tungsten (W), molybdenum (Mo), ruthenium (Ru), cobalt (Co), or nickel (Ni).

[0140] In some embodiments, an insulating spacer 363 extending along a side surface of the second contact plug 362 may be formed. For example, the insulating spacer 363 may surround the side surface of the second contact plug 362. The insulating spacer 363 may include, but is not limited to, at least one of, for example, silicon oxide, silicon nitride, and silicon oxynitride. The insulating spacer 363 may electrically separate the second contact plug 362 from the unit substrate 100 and the stacked structures MS1 and MS2.

[0141] Fig.14 are layout diagrams for describing a semiconductor memory device according to some example embodiments. Fig.15 It is along Fig.14 For ease of explanation, only the cross-sectional view similar to that shown above will be briefly described. Figures 1 to 7 Parts that are described overlap, or their description will be omitted.

[0142] Reference Figure 3 , Fig.14 and Fig.15 , in the semiconductor memory device according to some embodiments, the input / output pad 380 may not overlap with the unit substrate 100 .

[0143] For example, the input / output pad 380 may be formed over the landing pattern 102 and the outer area PA and may not overlap the unit substrate 100 in the third direction Z. In some embodiments, as the overlapping area between the input / output pad 380 and the outer area PA is enlarged, a greater number of first contact plugs 360 may be provided.

[0144] Figures 16 to 18 are various layout diagrams for describing semiconductor memory devices according to some embodiments. For ease of description, only the above reference Figures 1 to 15 Parts that are described overlap, or their description will be omitted.

[0145] Reference Figure 3 and Fig.16 In the semiconductor memory device according to some embodiments, the supporting contact 350 may extend in the first direction X to be relatively long.

[0146] For example, one supporting contact 350 may overlap with the plurality of first contact plugs 360 in the second direction Y. In other words, the length of one supporting contact 350 in the horizontal direction (eg, the first direction X) may be longer than the length of each of the plurality of first contact plugs 360 in the same horizontal direction. Fig.16 2 shows that two support contacts 350 are arranged along the second direction Y with respect to one input / output pad 380 , but this is only an example, and the number and arrangement of the support contacts 350 are not limited to the number and arrangement shown.

[0147] Reference Figure 3 and Fig.17 , a semiconductor memory device according to some embodiments may include a plurality of landing patterns 102 corresponding to a plurality of input / output pads 380 .

[0148] For example, the input / output pad 380 may include a first input / output pad 3801 and a second input / output pad 3802 arranged in the first direction X. In addition, for example, the landing pattern 102 may include a first landing pattern 1021 and a second landing pattern 1022 arranged in the first direction X. The first landing pattern 1021 may overlap the first input / output pad 3801 in the third direction Z, and the second landing pattern 1022 may overlap the second input / output pad 3802 in the third direction Z. The supporting contact 350 may connect the first landing pattern 1021 and the first input / output pad 3801, and may connect the second landing pattern 1022 and the second input / output pad 3802. In some embodiments, the first landing pattern 1021 and the second landing pattern 1022 may each extend longitudinally in the second direction Y.

[0149] exist Fig.17 14 support contacts 350 are shown arranged in a matrix with respect to each of the first landing pattern 1021 and the second landing pattern 1022 , but this is only an example, and the number and arrangement of the support contacts 350 are not limited to the number and arrangement shown.

[0150] Reference Figure 3 and Fig.18 , a semiconductor memory device according to some embodiments may include a plurality of landing patterns 102 corresponding to one input / output pad 380 .

[0151] For example, the supporting contact 350 may include a first supporting contact 3501 and a second supporting contact 3502 connected to one input / output pad 380. In addition, for example, the landing pattern 102 may include a third landing pattern 1023 and a fourth landing pattern 1024 overlapping one input / output pad 380. The first supporting contact 3501 may connect the third landing pattern 1023 and the input / output pad 380, and the second supporting contact 3502 may connect the fourth landing pattern 1024 and the input / output pad 380.

[0152] exist Fig.18 2 shows that two supporting contacts 350 are arranged along the second direction Y relative to each of the third landing pattern 1023 and the fourth landing pattern 1024, but this is only an example, and the number and arrangement of the supporting contacts 350 are not limited to the number and arrangement shown.

[0153] Fig.19 is a schematic layout diagram for describing a semiconductor memory device according to some embodiments. Fig. 20 Is used to describe Fig.19 Layout diagram of area S2. Fig.21 It is along Fig. 20 For ease of explanation, only the above reference will be briefly described. Figures 1 to 18 Parts that are described overlap, or their description will be omitted.

[0154] Reference Figures 19 to 21 , in the semiconductor memory device according to some embodiments, the input / output pad 380 completely overlaps the cell array area CA.

[0155] For example, the input / output pad 380 may overlap the cell array area CA in the third direction Z, and may not overlap the external area PA in the third direction Z. In some embodiments, since the input / output pad 380 does not overlap the external area PA, the above-mentioned Figures 3 to 7 Furthermore, in some embodiments, as the overlap area between the input / output pad 380 and the cell array area CA is enlarged, a greater number of second contact plugs 362 may be provided.

[0156] Fig. 22 is a layout diagram for describing a semiconductor memory device according to some embodiments. Fig.23 It is along Fig. 22 For ease of explanation, only the above reference will be briefly described. Figures 1 to 21 Parts that are described overlap, or their description will be omitted.

[0157] Reference Fig.19 , Fig. 22 and Fig.23 In the semiconductor memory device according to some embodiments, the second contact plug 362 may penetrate or extend through the landing pattern 102 .

[0158] For example, the second contact plug 362 may extend in the third direction Z to penetrate or extend through the interlayer insulating films 142 and 144 , the stacked structures MS1 and MS2 , the landing pattern 102 , and the upper insulating film 342 . The input / output pad 380 may be electrically connected to the cell wiring structure 180 through the second contact plug 362 .

[0159] Fig.24 and Fig.25 are various layout diagrams for describing semiconductor memory devices according to some embodiments. For ease of description, only the above reference Figures 1 to 21 Parts that are described overlap, or their description will be omitted.

[0160] Reference Fig.19 , Fig.24 and Fig.25 , in the semiconductor memory device according to some embodiments, the unit substrate 100 surrounds at least a portion of a periphery of the landing pattern 102 when viewed in a plan view.

[0161] For example, the input / output pad 380 may include a first input / output pad 3801 and a second input / output pad 3802 arranged along the first direction X. In addition, for example, the landing pattern 102 may include a first landing pattern 1021 and a second landing pattern 1022 arranged along the first direction X. In this case, the first landing pattern 1021 and the second landing pattern 1022 may each overlap a portion of the unit substrate 100 in the first direction X. For example, as Fig.24 As shown, when viewed in a plan view, the unit substrate 100 may surround a portion of the periphery of the drop pattern 102. As another example, Fig.25 As shown, in a plan view, the unit substrate 100 may completely surround the periphery of the drop pattern 102 .

[0162] In the following, reference will be made to Figures 1 to 37 A method of manufacturing a semiconductor memory device according to some embodiments is described.

[0163] Figures 26 to 37 is an intermediate step diagram for describing a method of manufacturing a semiconductor memory device according to some embodiments. For ease of explanation, only the above reference will be briefly described. Figures 1 to 25 Parts that are described overlap, or their description will be omitted.

[0164] Reference Fig.26, a first preliminary mold pMS1 and a first preliminary channel pCH1 are formed on a base substrate.

[0165] The first preliminary mold pMS1 may be formed on the cell array area CA of the base substrate 100P. The first preliminary mold pMS1 may include a plurality of first mold insulating films 110 and a plurality of first mold sacrificial films 111 alternately stacked on the base substrate 100P. The first mold sacrificial films 111 may include a material having an etching selectivity relative to the first mold insulating films 110. For example, each of the first mold insulating films 110 may include a silicon oxide film, and each of the first mold sacrificial films 111 may include a silicon nitride film. In some embodiments, the first preliminary mold pMS1 adjacent to the outer area PA may be patterned into a step shape.

[0166] The first preliminary channel pCH1 may extend in the third direction Z and penetrate or extend through the first preliminary mold pMS1. In some embodiments, the first preliminary channel pCH1 may be connected to the base substrate 100P. For example, a first interlayer insulating film 142 covering the first preliminary mold pMS1 may be formed on the base substrate 100P. The first preliminary channel pCH1 may penetrate or extend through the first interlayer insulating film 142 and the first preliminary mold pMS1 and be connected to the base substrate 100P.

[0167] The first preliminary channel pCH1 may include a material having an etch selectivity with respect to the first mold insulating film 110 and the first mold sacrificial film 111. For example, the first preliminary channel pCH1 may include polysilicon (poly Si).

[0168] Reference Fig. 27 , a second preliminary pattern pMS2 and a second preliminary channel pCH2 are formed on the first preliminary pattern pMS1.

[0169] The second preliminary mold pMS2 may include a plurality of second mold insulating films 115 and a plurality of second mold sacrificial films 116 alternately stacked on the first preliminary mold pMS1. Since forming the second preliminary mold pMS2 may be similar to forming the first preliminary mold pMS1, a detailed description thereof will be omitted below.

[0170] The second preliminary channel pCH2 may extend in the third direction Z and penetrate or extend through the second preliminary mold pMS2. In addition, the second preliminary channel pCH2 may be connected to the first preliminary channel pCH1. Since forming the second preliminary channel pCH2 may be similar to forming the first preliminary channel pCH1, a detailed description thereof will be omitted below.

[0171] Reference Fig.28 , forming a channel structure CH and a dummy channel structure DCH.

[0172] For example, the first preliminary channel pCH1 and the second preliminary channel pCH2 may be selectively removed. Subsequently, a channel structure CH may be formed to replace the region where the first preliminary channel pCH1 and the second preliminary channel pCH2 existed before their removal. Thus, a channel structure CH extending along a third direction Z and penetrating or extending through the first preliminary mold pMS1 and the second preliminary mold pMS2 may be formed. In some embodiments, the channel structure CH may include a semiconductor pattern 130, an information storage film 132, a filling insulating film 134, and a channel pad 136. In some examples, a dummy channel structure DCH may be formed simultaneously with the channel structure CH, and the dummy channel structure DCH may have the same structure and configuration as the channel structure CH.

[0173] Reference Fig.29 , a word line cutting region WC can be formed.

[0174] The word line cutting region WC may extend in the first direction X to cut the first preliminary mold pMS1 and the second preliminary mold pMS2.

[0175] Reference Fig.30 , forming a plurality of gate electrodes 112 and 117.

[0176] For example, the mold sacrificial films 111 and 116 exposed by the word line cut region WC may be selectively removed. Subsequently, gate electrodes 112 and 117 may be formed to replace the regions where the mold sacrificial films 111 and 116 existed before their removal. Thus, stacked structures MS1 and MS2 including mold insulating films 110 and 115 and gate electrodes 112 and 117 may be formed. In some embodiments, after the stacked structures MS1 and MS2 are formed, the word line cut region WC may be filled with an insulating material.

[0177] Reference Fig.31 , a bit line contact 182 , a first contact plug 360 , an external contact structure 365 , a bit line BL and a cell wiring structure 180 are formed.

[0178] The bit line contact 182 may extend in the third direction Z and be connected to the channel structure CH. The first contact plug 360 may extend in the third direction Z and be connected to the base substrate 100P. The external contact structure 365 may be spaced farther from the cell array area CA than the first contact plug 360. The bit line BL may be connected to the bit line contact 182 and may extend in the second direction Y. The cell wiring structure 180 may be electrically connected to the bit line BL, the first contact plug 360 and / or the external contact structure 365.

[0179] Reference Fig.32 , a cell structure CELL is stacked on the peripheral circuit structure PERI.

[0180] In some embodiments, the cell structure CELL and the peripheral circuit structure PERI may be stacked such that the front sides of the base substrate 100P and the peripheral circuit substrate 200 face each other. For example, the cell wiring structure 180 may be stacked on the peripheral circuit wiring structure 260 .

[0181] As an example, a first bonding metal 190 formed on the uppermost metal layer of the cell structure CELL and a second bonding metal 290 formed on the uppermost metal layer of the peripheral circuit structure PERI may be bonded. When the first bonding metal 190 and the second bonding metal 290 are formed of copper (Cu), the bonding method may be a Cu-Cu bonding method. However, this is only an example, and the first bonding metal 190 and the second bonding metal 290 may also be formed of various other metals such as aluminum (Al) or tungsten (W).

[0182] Reference Fig.33 , one end of the semiconductor pattern 130 is exposed.

[0183] For example, a planarization process or a recess process may be performed on the back side of the base substrate 100P. Thus, since at least a portion of the base substrate 100P is removed, one end (e.g., the upper end) of the channel structure CH may be exposed. In addition, a portion of the information storage film 132 of the exposed channel structure CH may be removed. In some exemplary embodiments, one end (e.g., the upper end) of the semiconductor pattern 130 may protrude more than one end of the information storage film 132.

[0184] Reference Fig.34 , a preliminary substrate 100S connected to the semiconductor pattern 130 is formed.

[0185] For example, the preliminary substrate 100S may be deposited on the surface of the first stacked structure MS1 from which the base substrate 100P has been removed. In some exemplary embodiments, the preliminary substrate 100S may include a conductive material. The conductive material may include, but is not limited to, for example, polysilicon doped with impurities, metal, or metal silicide. As an example, the preliminary substrate 100S may include polysilicon (poly-Si) doped with N-type impurities (e.g., phosphorus (P), arsenic (As), etc.).

[0186] Reference Fig.35 , forming a unit substrate 100 and a landing pattern 102 .

[0187] For example, the preliminary substrate 100S may be patterned to form a unit substrate 100 and a landing pattern 102 spaced apart from each other. Subsequently, an insulating substrate 105 may be formed to fill a region between the unit substrate 100 and the landing pattern 102 and a region on the outer area PA. The insulating substrate 105 may electrically separate the unit substrate 100 and the landing pattern 102.

[0188] Reference Fig.36 , an upper insulating film 342 and a supporting contact 350 are formed.

[0189] The upper insulating film 342 may cover the unit substrate 100, the landing pattern 102, and / or the insulating substrate 105. The supporting contact 350 may penetrate or extend through the upper insulating film 342 and be connected to the landing pattern 102.

[0190] In some embodiments, a third plug pattern 360c and / or a third contact pattern 365c may be formed penetrating or extending through the upper insulating film 342. In some embodiments, the support contact 350, the third plug pattern 360c, and / or the third contact pattern 365c may be formed at the same level.

[0191] Reference Fig.37 , an input / output pad 380 is formed on the upper insulating film 342 .

[0192] The input / output pad 380 may be connected to the supporting contact 350 and the first contact plug 360 .

[0193] In some embodiments, an external pad 385 may be formed on the upper insulating film 342. In some embodiments, the input / output pad 380 and the external pad 385 may be formed at the same level.

[0194] Then, refer to Figure 5 , a cap insulating film 344 is formed on the upper insulating film 342. Thus, the above-mentioned reference Figures 3 to 7 A semiconductor memory device is described.

[0195] In the following, reference will be made to Figures 1 to 40 An electronic system including a semiconductor memory device according to some embodiments is described.

[0196] Fig.38 is an example of a block diagram for describing an electronic system according to some embodiments. Fig.39 is a perspective view for describing an electronic system according to some embodiments. Fig.40 It is along Fig.39 For ease of explanation, only the schematic cross-sectional view of the above reference line II will be briefly described. Figures 1 to 37 Parts that are described overlap, or their description will be omitted.

[0197] Reference Fig.38, an electronic system 1000 according to some embodiments may include a semiconductor memory device 1100 and a controller 1200 electrically connected to the semiconductor memory device 1100. The electronic system 1000 may be a storage device including one semiconductor memory device 1100 or a plurality of semiconductor memory devices 1100 or an electronic device including the storage device. For example, the electronic system 1000 may be a solid state drive (SSD) device, a universal serial bus (USB), a computing system, a medical device, or a communication device including one semiconductor memory device 1100 or a plurality of semiconductor memory devices 1100.

[0198] The semiconductor memory device 1100 may be a nonvolatile memory device (eg, a NAND flash memory device), and may include, for example, Figures 1 to 25 At least one of the semiconductor memory devices described herein. The semiconductor memory device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F.

[0199] The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110 (eg, Figure 1 , a row decoder 33 in the page buffer 1120 (eg, Figure 1 , and logic circuits 1130 (eg, Figure 1 For example, the first structure 1100F may correspond to the control logic 37 in the above Figures 1 to 25 Describe the peripheral circuit structure PERI.

[0200] The second structure 1100S may include the above reference Figure 2 The common source line CSL, a plurality of bit lines BL, and a plurality of cell strings CSTR described above. The cell string CSTR may be connected to the decoder circuit 1110 through the word line WL, at least one string selection line SSL, and at least one ground selection line GSL. In addition, the cell string CSTR may be connected to the page buffer 1120 through the bit line BL. For example, the second structure 1100S may correspond to the above using Figures 1 to 25 Described cell structure CELL.

[0201] In some embodiments, the common source line CSL and the cell string CSTR may be electrically connected to the decoder circuit 1110 through a first connection wiring 1115 extending from the first structure 1100F to the second structure 1100S.

[0202] In some embodiments, the bit lines BL may be electrically connected to the page buffer 1120 through the second connection wiring 1125 .

[0203] The semiconductor memory device 1100 may be electrically connected to a logic circuit 1130 (eg, Figure 1 The input / output pad 1101 of the control logic 37 in the embodiment communicates with the controller 1200. For example, the input / output pad 1101 may correspond to the control logic 37 in the embodiment described above. Figures 1 to 25 The input / output pad 1101 may be electrically connected to the logic circuit 1130 through an input / output connection wiring 1135 extending from the first structure 1100F to the second structure 1100S. For example, the connection wiring 1135 may correspond to the input / output pad 380 described above. Figures 1 to 25 A first contact plug 360 is described.

[0204] The controller 1200 may include a processor 1210 , a NAND controller 1220 , and a host interface 1230 . In some embodiments, the electronic system 1000 may include a plurality of semiconductor memory devices 1100 , in which case the controller 1200 may control the plurality of semiconductor memory devices 1100 .

[0205] The processor 1210 may control the overall operation of the electronic system 1000 including the controller 1200. The processor 1210 may operate according to a predetermined firmware, and may access the semiconductor memory device 1100 by controlling the NAND controller 1220. The NAND controller 1220 may include a NAND interface 1221 that processes communication with the semiconductor memory device 1100. A control command for controlling the semiconductor memory device 1100, data to be written into the memory cell transistor MCT of the semiconductor memory device 1100, data to be read from the memory cell transistor MCT of the semiconductor memory device 1100, etc. may be transmitted through the NAND interface 1221. The host interface 1230 may provide a communication function between the electronic system 1000 and an external host. When a control command is received from an external host through the host interface 1230, the processor 1210 may control the semiconductor memory device 1100 in response to the control command.

[0206] Reference Fig.39 and Fig.40 , an electronic system according to some embodiments may include a main board 2001, and a main controller 2002, one or more semiconductor packages 2003, and a dynamic random access memory (DRAM) 2004 mounted on the main board 2001. The semiconductor package 2003 and the DRAM 2004 may be connected to the main controller 2002 through a wiring pattern 2005 formed on the main board 2001.

[0207] The mainboard 2001 may include a connector 2006 including a plurality of pins connected to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the electronic system 2000 and the external host. In some embodiments, the electronic system 2000 may communicate with the external host according to any one of interfaces such as a universal serial bus (USB), a peripheral component interconnect high speed (PCI-Express), a serial advanced technology attachment (SATA), and M-Phy for universal flash memory (UFS). In some embodiments, the electronic system 2000 may be operated by power supplied from an external host via the connector 2006. The electronic system 2000 may further include a power management integrated circuit (PMIC) for distributing power supplied from an external host to the main controller 2002 and the semiconductor package 2003.

[0208] The main controller 2002 may write data to or read data from the semiconductor package 2003 , and may increase the operation speed of the electronic system 2000 .

[0209] The DRAM 2004 may be a buffer memory that can mitigate the speed difference between the semiconductor package 2003 as a data storage space and an external host. The DRAM 2004 included in the electronic system 2000 may operate as a high-speed cache memory and may also provide a space for temporarily storing data in a control operation of the semiconductor package 2003. When the electronic system 2000 includes the DRAM 2004, the main controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to the NAND controller for controlling the semiconductor package 2003.

[0210] The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. The first semiconductor package 2003a and the second semiconductor package 2003b may each include a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 on the lower surface of each semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chip 2200 to the package substrate 2100, and a mold layer 2500 covering the semiconductor chip 2200 and the connection structure 2400 on the package substrate 2100.

[0211] The package substrate 2100 may be a printed circuit board including a package upper pad 2130. Each semiconductor chip 2200 may include an input / output pad 380. The input / output pad 380 may correspond to Fig.38 The input / output pad 1101.

[0212] In some embodiments, the connection structure 2400 may be a bonding wire that electrically connects the input / output pad 380 to the package upper pad 2130. For example, the connection structure 2400 may be connected to the input / output pad 380 by bonding solder 390. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other by a bonding wire method and electrically connected to the package upper pad 2130 of the package substrate 2100. In some embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may also be electrically connected to each other by a connection structure including a through silicon via (TSV) instead of a bonding wire method.

[0213] In some embodiments, the main controller 2002 and the semiconductor chip 2200 may also be included in one package. In some embodiments, the main controller 2002 and the semiconductor chip 2200 may be mounted on a separate interposer substrate different from the mainboard 2001, and the main controller 2002 and the semiconductor chip 2200 may also be connected to each other through wiring formed on the interposer substrate.

[0214] In some embodiments, the package substrate 2100 may be a printed circuit board. The package substrate 2100 may include a package substrate main body portion 2120, a package upper pad 2130 on an upper surface of the package substrate main body portion 2120, a lower pad 2125 exposed on or through a lower surface of the package substrate main body portion 2120, and an internal wiring 2135 electrically connecting the package upper pad 2130 and the package lower pad 2125 to each other in the package substrate main body portion 2120. The package upper pad 2130 may be electrically connected to the connection structure 2400. The package lower pad 2125 may be connected to the connection structure 2400 through a conductive connector 2800. Fig.39 A wiring pattern 2005 of a mainboard 2001 of an electronic system 2000 is shown.

[0215] In the electronic system according to some example embodiments, each semiconductor chip 2200 may include the above-mentioned Figures 1 to 25 For example, each semiconductor chip 2200 may include a cell structure CELL, a peripheral circuit structure PERI, an upper insulating film 342, a supporting contact 350, and an input / output pad 380. For example, the peripheral circuit structure PERI may include the above Figures 3 to 7 The peripheral circuit substrate 200, the peripheral circuit element PT and the peripheral circuit wiring structure 260 described above. In addition, for example, the cell structure CELL may include the above-mentioned Figures 3 to 7 The cell substrate 100, landing pattern 102, insulating substrate 105, stacked structures MS1 and MS2, channel structure CH, word line cutting region WC, bit line BL and cell wiring structure 180 are described. The peripheral circuit structure PERI and the cell structure CELL may be bonded to each other by the first bonding metal 190 and the second bonding metal 290.

[0216] Although the present invention has been specifically shown and described with reference to some examples of embodiments of the present invention, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the present invention as defined by the appended claims. It is therefore desired that the embodiments described herein be considered in all respects to be illustrative and not restrictive, with reference to the appended claims rather than the foregoing description to indicate the scope of the present invention.

[0217] CROSS-REFERENCE TO RELATED APPLICATIONS

[0218] This application claims priority and all benefits arising from Korean Patent Application No. 10-2023-0112031 filed in the Korean Intellectual Property Office on August 25, 2023, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor memory device, comprising: A unit substrate, comprising a first surface and a second surface opposite to the first surface; a landing pattern, comprising a third surface and a fourth surface opposite to the third surface, the landing pattern being spaced apart from the unit substrate in a horizontal direction; A plurality of gate electrodes are sequentially stacked on the first surface and the third surface; a channel structure on the unit substrate, the channel structure extending in a vertical direction intersecting the first surface, the channel structure intersecting the plurality of gate electrodes; an upper insulating film covering the second surface and the fourth surface; an input / output pad on the upper insulating film, the input / output pad overlapping at least a portion of the plurality of gate electrodes in the vertical direction; as well as A supporting contact extends through the upper insulating film and connects the landing pattern and the input / output pad. 2 . The semiconductor memory device according to claim 1 , further comprising a contact plug spaced apart from the landing pattern in the horizontal direction, extending in the vertical direction, and connected to the input / output pad.

3. The semiconductor memory device according to claim 2, further comprising: a peripheral circuit substrate including a fifth surface facing the first surface and the third surface; as well as peripheral circuit elements on said fifth surface, The contact plug electrically connects the input / output pad and the peripheral circuit element.

4. The semiconductor memory device according to claim 1, wherein: The unit substrate and the landing pattern include the same material.

5. The semiconductor memory device according to claim 4, wherein: The unit substrate and the landing pattern each include polysilicon doped with impurities.

6. The semiconductor memory device according to claim 1, wherein The first surface and the third surface are coplanar, and The second surface and the fourth surface are coplanar.

7. The semiconductor memory device according to claim 1, wherein: The width of the supporting contact decreases in a direction toward the landing pattern.

8. The semiconductor memory device according to claim 1, wherein: The lower surface of the support contact is between the third surface and the fourth surface.

9. The semiconductor memory device according to claim 1, wherein: The thickness of the upper insulating film is in the range of 300 nm to 1000 nm inclusive. 10 . The semiconductor memory device of claim 1 , further comprising an insulating substrate between the unit substrate and the landing pattern, the insulating substrate electrically separating the unit substrate and the landing pattern.

11. A semiconductor memory device comprising: A peripheral circuit structure, comprising a peripheral circuit substrate and peripheral circuit elements on the peripheral circuit substrate; as well as a unit structure stacked on the peripheral circuit structure, Wherein, the unit structure comprises: a unit substrate, comprising a first surface facing the peripheral circuit structure and a second surface opposite to the first surface; a landing pattern, comprising a third surface facing the peripheral circuit structure and a fourth surface opposite to the third surface, the landing pattern being spaced apart from the unit substrate in a horizontal direction; a stacked structure comprising a plurality of mold insulating films and a plurality of gate electrodes alternately stacked on the first surface and the third surface; a channel structure extending in a vertical direction intersecting the first surface, the channel structure extending through the stacked structure; an input / output pad, on the second surface and the fourth surface, the input / output pad overlapping at least a portion of the stacked structure in the vertical direction; a contact plug extending in the vertical direction and electrically connecting the peripheral circuit element and the input / output pad; an upper insulating film interposed between the unit substrate and the input / output pad and between the landing pattern and the input / output pad; and A supporting contact extends through the upper insulating film and connects the landing pattern and the input / output pad.

12. The semiconductor memory device according to claim 11, wherein The contact plug includes a first plug pattern extending in the vertical direction at a first side of the stack structure and a second plug pattern extending through the upper insulating film and connecting the input / output pad and the first plug pattern, and Wherein, based on the fourth surface, the depth to which the supporting contact extends is smaller than the depth to which the second plug pattern extends.

13. The semiconductor memory device according to claim 12, wherein: The width of the first plug pattern decreases in a direction toward the second plug pattern, and A width of the second plug pattern decreases in a direction toward the first plug pattern.

14. The semiconductor memory device according to claim 11, wherein: The input / output pad completely overlaps the stack structure in the vertical direction.

15. The semiconductor memory device according to claim 14, wherein: The contact plug extends in the vertical direction and extends through the stack structure.

16. The semiconductor memory device according to claim 14, wherein: The unit substrate surrounds at least a portion of a periphery of the landing pattern when viewed in a plan view.

17. The semiconductor memory device according to claim 11, wherein: The unit structure further comprises: a word line cutting region extending through the stack structure in a first direction intersecting the vertical direction; and a bit line extending between the peripheral circuit structure and the stack structure in a second direction intersecting the vertical direction and the first direction, Wherein, the channel structure connects the unit substrate and the bit line.

18. The semiconductor memory device according to claim 17, wherein: The cell structure further includes a cell wiring structure electrically connected to the plurality of gate electrodes, the bit lines, and the contact plugs, Wherein, the peripheral circuit structure further includes a peripheral circuit wiring structure electrically connected to the peripheral circuit element, and Wherein, the cell wiring structure and the peripheral circuit wiring structure are joined to each other.

19. An electronic system comprising: Motherboard; A semiconductor memory device, comprising a peripheral circuit structure and a unit structure sequentially stacked on the main board; as well as a controller on the main board, the controller being electrically connected to the semiconductor memory device, The unit structure comprises: A unit substrate, comprising a first surface and a second surface opposite to the first surface; a landing pattern, comprising a third surface and a fourth surface opposite to the third surface, the landing pattern being spaced apart from the unit substrate in a horizontal direction; A plurality of gate electrodes are sequentially stacked on the first surface and the third surface; a channel structure on the unit substrate, the channel structure extending in a vertical direction intersecting the first surface, the channel structure intersecting the plurality of gate electrodes; an upper insulating film covering the second surface and the fourth surface; an input / output pad on the upper insulating film, the input / output pad overlapping at least a portion of the plurality of gate electrodes in the vertical direction and electrically connected to the controller; and A supporting contact extends through the upper insulating film and connects the landing pattern with the input / output pad. 20 . The electronic system of claim 19 , further comprising a contact plug spaced apart from the landing pattern and extending in the vertical direction, the contact plug electrically connecting the peripheral circuit structure and the input / output pad.

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