Semiconductor structure and preparation method thereof, storage system and electronic equipment

Abstract

The embodiment of the invention provides a semiconductor structure and a preparation method thereof, a storage system and electronic equipment, relates to the technical field of semiconductor chips, and aims to prevent the semiconductor structure from generating electric leakage. According to the semiconductor structure provided by the embodiment of the invention, the stacked structure comprises a plurality of insulating layers and a plurality of grid line layers which are alternately stacked, each grid line layer comprises a dielectric layer and a second grid line layer which are arranged on the same layer, and a barrier layer is arranged between the dielectric layer and the second grid line layer. The connecting structures extend to the corresponding dielectric layers in the alternate stacking direction of the dielectric layers and the insulating layers and penetrate through the barrier layers in the direction perpendicular to the stacking direction to be connected with the corresponding second grid line layers. Through the arrangement, in the process of removing part of the dielectric layer to form the connecting structure, the barrier layer can be used as an etching stop layer, so that the high dielectric constant layer between the middle conductive layer and the insulating layer is prevented from being removed in the process of removing part of the dielectric layer, and electric leakage between the adjacent middle conductive layers is avoided.

Description

Technical Field

[0001] The present application relates to the field of semiconductor chip technology, and in particular to a semiconductor structure and a preparation method thereof, a storage system, and an electronic device. Background Art

[0002] As the feature size of the memory cell approaches the process lower limit, the planar process and manufacturing technology become challenging and costly, which causes the storage density of 2D or planar NAND flash memory to approach the upper limit. To overcome the limitations of 2D or planar NAND flash memory, the industry has developed a memory with a three-dimensional structure (3D NAND), which increases the storage density by arranging the memory cells three-dimensionally on the substrate.

[0003] The semiconductor structure includes a plurality of gate line layers and a plurality of dielectric layers which are alternately stacked, and leakage is likely to occur between adjacent gate line layers. Summary of the invention

[0004] Embodiments of the present application provide a semiconductor structure and a method for manufacturing the same, a storage system, and an electronic device, which are intended to prevent leakage between adjacent gate line layers.

[0005] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0006] On the one hand, an embodiment of the present application provides a semiconductor structure. The semiconductor structure includes a stacking structure and a connection structure, the stacking structure includes a plurality of insulating layers and a plurality of gate line layers alternately stacked; the stacking structure includes an array region and a connection region, the array region and the connection region are adjacently arranged; each gate line layer includes a first gate line layer located in the array region and a second gate line layer located in the connection region; the stacking structure also includes a plurality of dielectric layers located in the connection region, the plurality of dielectric layers and the plurality of insulating layers are alternately stacked, and the dielectric layer and the second gate line layer are arranged in the same layer, and a barrier layer is arranged between the dielectric layer and the second gate line layer; the connection structure extends to the corresponding dielectric layer along the alternating stacking direction of the plurality of dielectric layers and the plurality of insulating layers, and passes through the barrier layer perpendicular to the stacking direction to connect with the corresponding second gate line layer.

[0007] The semiconductor structure provided by the embodiment of the present application, the stacked structure includes multiple insulating layers and multiple gate line layers alternately stacked, each gate line layer includes a first gate line layer located in the array area and a second gate line layer located in the connection area, multiple dielectric layers and multiple insulating layers located in the connection area are alternately stacked, and the dielectric layer and the second gate line layer are arranged in the same layer, a barrier layer is arranged between the dielectric layer and the second gate line layer, and the connection structure extends to the corresponding dielectric layer along the alternating stacking direction of the multiple dielectric layers and the multiple insulating layers, and passes through the barrier layer perpendicular to the stacking direction to connect with the corresponding second gate line layer. Through the above arrangement, in the process of removing part of the dielectric layer to form the connection structure, the barrier layer can be used as an etching stop layer, thereby avoiding the high dielectric constant layer located between the intermediate conductive layer and the insulating layer from being removed in the process of removing part of the dielectric layer, so as to avoid leakage between adjacent intermediate conductive layers.

[0008] In some embodiments, the material of the barrier layer includes polysilicon to improve the stability of the barrier layer.

[0009] In some embodiments, the dielectric layer is made of silicide, and the barrier layer is formed by a selective epitaxial growth process, so that the barrier layer can be formed between the dielectric layer and the second gate line layer to prevent the integrity of the second gate line layer from being damaged during the removal of the dielectric layer.

[0010] In some embodiments, the second gate line layer includes an intermediate conductive layer and a high dielectric constant layer, the high dielectric constant layer is wrapped around the outside of the intermediate conductive layer, and the barrier layer is disposed between the high dielectric constant layer and the dielectric layer.

[0011] Through the above arrangement, the high dielectric constant layer is wrapped around the outside of the middle conductive layer, and the high dielectric constant layer can protect the middle conductive layer to prevent the middle conductive layer from being oxidized and affecting the conductive performance of the middle conductive layer. The barrier layer can prevent part of the high dielectric constant layer from being removed at the same time during the process of removing part of the dielectric layer, exposing the middle conductive layer and causing leakage in the semiconductor structure.

[0012] In some embodiments, the connection structure includes a first connection portion extending along the alternating stacking direction of the plurality of dielectric layers and the plurality of insulating layers and a second connection portion connected to the first connection portion, and the second connection portion is connected to the second gate line layer.

[0013] Through the above arrangement, the second connection part is connected to the second gate line layer, and the first connection part is connected to the second connection part, so that the second gate line layer can be connected to the external circuit through the connection part.

[0014] In some embodiments, the second connection portion passes through the barrier layer and the high dielectric constant layer along an extension direction perpendicular to the first connection portion and is connected to the intermediate conductive layer.

[0015] Through the above arrangement, in the process of forming the second connecting part, part of the dielectric layer can be removed first to form a cavity, and part of the blocking layer and part of the high dielectric constant layer can be removed in sequence through the cavity, so that the second connecting part can pass through the blocking layer and the high dielectric constant layer to connect to the middle conductive layer without leakage.

[0016] In some embodiments, the stacked structure further includes a first isolation structure and a second isolation structure, both of which penetrate multiple insulating layers and multiple gate line layers, and the first isolation structure and the second isolation structure are spaced apart.

[0017] Through the above arrangement, the first isolation structure and the second isolation structure can support the stack structure to improve the stability of the semiconductor structure.

[0018] On the other hand, an embodiment of the present application further provides a method for preparing a semiconductor structure, comprising:

[0019] Forming a stacked structure, the stacked structure includes a plurality of insulating layers and a plurality of sacrificial layers alternately stacked, the stacked structure also includes an array region and a connection region, the array region and the connection region are adjacently arranged; the sacrificial layer includes a first sacrificial layer located in the array region and a second sacrificial layer located in the connection region;

[0020] removing the first sacrificial layer and a portion of the second sacrificial layer to form a first gap layer, and using the remaining portion of the second sacrificial layer as a dielectric layer;

[0021] forming a barrier layer at one end of the dielectric layer close to the first gap layer;

[0022] forming a first gate line layer in the first gap layer in the array region, and forming a second gate line layer in the first gap layer in the connection region;

[0023] Forming a conductive hole on the connection area of ​​the stacked structure, the conductive hole extending to a dielectric layer; and removing at least a portion of the corresponding dielectric layer by using the conductive hole to form a second gap layer;

[0024] removing a portion of the barrier layer using the second interstitial layer to form a hole;

[0025] Conductive material is filled in the hole, the second gap layer and the conductive hole to form a connection structure.

[0026] In some embodiments, forming a barrier layer at one end of the dielectric layer close to the first gap layer comprises:

[0027] The material of the dielectric layer includes silicon nitride, the barrier layer is formed by a selective epitaxial growth process, and the material of the barrier layer includes polysilicon.

[0028] Through the above arrangement, there is a high selectivity ratio between the polysilicon formed by selective epitaxial growth on the dielectric layer and the silicon nitride of the dielectric layer, that is, in the process of removing the dielectric layer, the barrier layer composed of polysilicon can prevent the second gate line layer located in the first gap layer from being removed at the same time, thereby ensuring the integrity of the second gate line layer and avoiding leakage of the semiconductor structure. At the same time, polysilicon can improve the stability of the barrier layer compared with single crystal silicon.

[0029] In some embodiments, polysilicon is formed on both the dielectric layer and the insulating layer in the selective epitaxial growth process.

[0030] Through the above arrangement, polysilicon is formed on both the dielectric layer and the insulating layer, so that both ends of the barrier layer in the stacking direction can be directly connected to the insulating layer, thereby achieving sealing of one end of the dielectric layer close to the first gap layer.

[0031] In some embodiments, the growth rate of polysilicon on the dielectric layer is greater than the growth rate on the insulating layer, and after the selective epitaxial growth process, the method further includes:

[0032] The polysilicon on the insulating layer is removed, and the polysilicon remaining on the dielectric layer serves as a barrier layer.

[0033] Through the above arrangement, during the process of removing the dielectric layer, the barrier layer composed of polysilicon can prevent the second gate line layer located in the first gap layer from being removed simultaneously, thereby ensuring the integrity of the second gate line layer and avoiding leakage of the semiconductor structure.

[0034] In some embodiments, removing the first sacrificial layer and a portion of the second sacrificial layer includes:

[0035] forming a first gate gap on the stacked structure, wherein the first gate gap penetrates the stacked structure;

[0036] The first sacrificial layer and a portion of the second sacrificial layer are removed by utilizing the first gate gap.

[0037] Through the above arrangement, the first sacrificial layer and part of the second sacrificial layer are removed by using the first gate gap to form a first gap layer, and the remaining part of the second sacrificial layer is used as a dielectric layer to form a barrier layer at one end of the dielectric layer close to the first gap layer.

[0038] In some embodiments, forming the first gate slit on the stacked structure also includes: forming a second gate slit in the array region, the second gate slit running through the stacked structure;

[0039] Removing the first sacrificial layer and a portion of the second sacrificial layer includes: removing the first sacrificial layer and a portion of the second sacrificial layer by using the first gate gap and the second gate gap.

[0040] Through the above arrangement, the first and second gate gaps are used to remove the first sacrificial layer and part of the second sacrificial layer, which increases the channels for removing the first and part of the second sacrificial layer and improves the efficiency of removing the first and part of the second sacrificial layer.

[0041] In some embodiments, forming a stacked structure includes forming a first gate line layer in a first gap layer in an array region, and forming a second gate line layer in the first gap layer in a connection region, and further includes:

[0042] A first isolation structure is formed in the first gate gap, and a second isolation structure is formed in the second gate gap.

[0043] Through the above arrangement, the first isolation structure and the second isolation structure can support the stack structure to improve the stability of the semiconductor structure.

[0044] In some embodiments, using the conductive hole to remove at least a portion of the corresponding dielectric layer to form the second gap layer includes: removing at least a portion of the dielectric layer corresponding to the conductive hole by etching; under the same etching conditions, the etching rate of the barrier layer is less than the etching rate of the dielectric layer.

[0045] Through the above arrangement, after removing part of the dielectric layer, part of the barrier layer is still located on the side of the second gate line layer close to the second gap layer, which prevents the second gate line layer from being removed at the same time, ensures the integrity of the second gate line layer, and avoids leakage of the semiconductor structure.

[0046] In some embodiments, the second gate line layer includes an intermediate conductive layer and a high dielectric constant layer, the high dielectric constant layer is wrapped around the outside of the intermediate conductive layer, and the barrier layer is disposed between the intermediate conductive layer and the dielectric layer;

[0047] After using the second gap layer to remove part of the barrier layer to form the hole, the method further includes:

[0048] A portion of the high dielectric constant layer corresponding to the second gap layer is removed through the hole.

[0049] Through the above arrangement, after removing part of the high dielectric constant layer, part of the middle conductive layer is exposed, so that the connection structure can be connected to the middle conductive layer during the process of forming the connection structure.

[0050] In some embodiments, filling the holes, the second void layer, and the conductive holes with conductive material to form a connection structure also includes the conductive material forming a first connection part in the conductive hole, the conductive material forming a second connection part in the hole and the second void layer, and the second connection part passes through the hole to connect with the intermediate conductive layer.

[0051] Through the above arrangement, the second connection part is connected to the middle conductive layer, and the first connection part is connected to the second connection part, so that the middle conductive layer can be connected to the external circuit through the connection part.

[0052] On the other hand, an embodiment of the present application further provides a storage system, including a semiconductor structure and a controller, wherein the semiconductor structure is the semiconductor structure as described above; the controller is coupled to the semiconductor structure to control the semiconductor structure to store data.

[0053] On the other hand, an embodiment of the present application further provides an electronic device, comprising the above storage system.

[0054] It can be understood that the beneficial effects that can be achieved by the semiconductor structure preparation method, storage system and electronic device provided by the above embodiments of the present application can refer to the beneficial effects of the semiconductor structure above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the technical solutions in the present application, the following is a brief introduction to the drawings required for use in some embodiments of the present application. Obviously, the drawings described below are only drawings of some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not intended to limit the actual size of the product involved in the embodiments of the present application, the actual process of the method, the actual timing of the signal, etc.

[0056] Figure 1 A schematic diagram of a three-dimensional structure of a three-dimensional memory in some embodiments of the present application;

[0057] Figure 2 A cross-sectional view of a three-dimensional memory in some embodiments of the present application;

[0058] Figure 3 for Figure 1 A cross-sectional view of a memory cell string in the three-dimensional memory along the AA' direction;

[0059] Figure 4 An equivalent circuit diagram of a memory cell string in some embodiments of the present application;

[0060] Figure 5 A schematic cross-sectional view of a connection region of a semiconductor structure in some embodiments of the present application;

[0061] Figure 6 A schematic cross-sectional view of a semiconductor structure array region in some embodiments of the present application;

[0062] Figure 7 for Figure 5 The enlarged view of point A in the middle;

[0063] Figure 8 for Figure 5 Cross-section along the middle BB direction;

[0064] Fig. 9 A flowchart of a method for preparing a semiconductor structure in some embodiments of the present application;

[0065] Fig. 10A A schematic diagram of the structure of the connection area of ​​the stacked structure in the method provided in an embodiment of the present application;

[0066] Fig. 10B A schematic diagram of the structure of the stacked structure array region in the method provided in an embodiment of the present application;

[0067] Fig. 10C A schematic diagram of the structure after a first gap layer is formed in a connection area in the method provided in an embodiment of the present application;

[0068] Fig. 10D A schematic diagram of the structure after a first gap layer is formed in the array area in the method provided in an embodiment of the present application;

[0069] Fig.10E A schematic diagram of the structure after a barrier layer is formed in the method provided in an embodiment of the present application;

[0070] Fig.10F A schematic diagram of the structure after a second gate line layer is formed in a connection area in the method provided in an embodiment of the present application;

[0071] Figure 10G A schematic diagram of the structure after the first gate line layer is formed in the array area in the method provided in an embodiment of the present application;

[0072] Fig. 10H A schematic diagram of a structure after a first isolation structure is formed in a connection area in the method provided in an embodiment of the present application;

[0073] Fig.10I A schematic diagram of a structure after a second isolation structure is formed in an array region in the method provided in an embodiment of the present application;

[0074] Fig.10J This is a schematic diagram of the structure after the barrier layer is removed in the method provided in an embodiment of the present application;

[0075] Figure 10J1 for Fig.10J The enlarged view of point B in the middle;

[0076] Figure 10K A schematic diagram of the structure after a connection structure is formed in the method provided in an embodiment of the present application;

[0077] Fig.11 is a block diagram of a storage system according to some embodiments;

[0078] Fig.12 is a block diagram of a storage system according to some other embodiments. DETAILED DESCRIPTION

[0079] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0080] In the description of the present application, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0081] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present application. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described may be included in any one or more embodiments or examples in any appropriate manner.

[0082] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0083] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments invented here are not necessarily limited to the contents of this document.

[0084] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0085] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0086] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0087] In the context of this application, the meaning of "on", "above", and "over" should be interpreted in the broadest manner, so that "on" not only means "directly on something", but also includes the meaning of "on something" with intervening features or layers in between, and "above" or "over" not only means "above" or "over" something, but also includes the meaning of "above" or "over" something without intervening features or layers in between (i.e., directly on something).

[0088] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0089] As used herein, the term "substrate" refers to a material on which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0090] The term "three-dimensional memory" refers to a semiconductor device formed by a memory cell transistor string (referred to herein as a "memory cell string", such as a NAND memory cell string) arranged in an array on a main surface of a substrate or source layer and extending in a direction perpendicular to the substrate or source layer. As used herein, the term "vertical / vertically" means nominally perpendicular to the main surface (i.e., lateral surface) of the substrate or source layer.

[0091] Please refer to Figure 1 and Figure 2 , the three-dimensional memory 10 extends in the XY plane, the first direction X and the second direction Y are, for example, two orthogonal directions in the plane where the semiconductor structure 200 is located (for example, the plane where the source layer SL is located): the first direction X is, for example, the extension direction of the word line WL, and the second direction Y is, for example, the extension direction of the bit line BL. The third direction Z is perpendicular to the plane where the semiconductor structure 200 is located, that is, perpendicular to the XY plane.

[0092] As used in this application, whether a component (e.g., layer, structure, or device) is "on," "over," or "under" another component (e.g., layer, structure, or device) of a semiconductor device (e.g., a three-dimensional memory) is determined relative to a substrate or source layer of the semiconductor device in a third direction Z when the substrate or source layer is located in the lowest plane of the semiconductor device in the third direction Z. The same concept is applied throughout the content of this application to describe spatial relationships.

[0093] In order to more clearly illustrate the structure of the device, Figure 2 In the figure, a view of the array area CA and a view of the connection area SS are shown. The view of the array area CA is based on the left coordinate system, and the view of the connection area SS is based on the right coordinate system, that is, the view of the array area CA shows the cross-sectional structure along the Y direction, and the view of the connection area SS shows the cross-sectional structure along the X direction.

[0094] Reference Figure 1 and Figure 2Some embodiments of the present application provide a three-dimensional memory 10. The three-dimensional memory 10 may include a semiconductor structure 200. The three-dimensional memory 10 may also include a peripheral device 100 coupled to the semiconductor structure 200. The semiconductor structure 200 includes a source layer SL, and the peripheral device 100 may be disposed on a side of the semiconductor structure 200 away from the source layer SL.

[0095] The source layer SL may include a semiconductor material, such as single crystal silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials. The source layer SL may be partially or fully doped. Exemplarily, the source layer SL may include a doped region, and the doped region is doped with a p-type dopant. The source layer SL may also include a non-doped region.

[0096] The semiconductor structure 200 may include memory cell transistor strings (referred to herein as “channel structures”) 400 arranged in an array. A source layer SL may be coupled to source terminals of the plurality of memory cell strings 40.

[0097] In some embodiments, please refer to Figure 3 and Figure 4 , the memory cell string 40 may include a plurality of transistors T, a transistor T (eg Figure 4 The transistors T1 to T6 in the figure can be set as a memory cell, and these transistors T are connected together to form a memory cell string. A transistor T (for example, each transistor T) can be formed by a semiconductor channel 241 and a gate line G surrounding the semiconductor channel 241. The gate line G is configured to control the conduction state of the transistor.

[0098] Understandably, Figure 1 to Figure 4 The number of transistors is only illustrative. The storage cell string of the three-dimensional memory provided in the embodiment of the present application may also include other numbers of transistors, such as 4, 16, 32, or 64.

[0099] In some embodiments, along the third direction Z, the gate line located at the bottom among the multiple gate lines G (for example, the gate line closest to the source layer SL among the multiple gate lines G) is constructed as a source selection gate SGS, and the source selection gate SGS is configured to control the conduction state of the transistor T6, thereby controlling the conduction state of the source channel in the memory cell string 40. The gate line located at the top among the multiple gate lines G (for example, the gate line farthest from the source layer SL among the multiple gate lines G) is constructed as a drain selection gate SGD, and the drain selection gate SGD is configured to control the conduction state of the transistor T1, thereby controlling the conduction state of the drain channel in the memory cell string 40. The gate line located in the middle among the multiple gate lines G can be constructed as a plurality of word lines WL, for example, including word line WL0, word line WL1, word line WL2, and word line WL3. Data writing, reading, and erasing of corresponding memory cells (for example, transistors T) in the memory cell string 40 can be completed through the word lines WL.

[0100] Continue to refer to Figure 1 and Figure 2 In some embodiments, the semiconductor structure 200 may further include an array interconnect layer 290. The array interconnect layer 290 may be coupled to the memory cell string 40. The array interconnect layer 290 may include a drain terminal (i.e., a bit line BL) of the memory cell string 40, and the drain terminal may be coupled to a semiconductor channel of each transistor T in at least one memory cell string 40.

[0101] The array interconnect layer 290 may include one or more first interlayer insulating layers 292, and may also include a plurality of contacts insulated from each other by these first interlayer insulating layers 292, the contacts may include, for example, a bit line contact BL-CNT coupled to the bit line BL, and a drain select gate contact SGD-CNT coupled to the drain select gate SGD. The array interconnect layer 290 may also include one or more first interconnect conductor layers 291. The first interconnect conductor layer 291 may include a plurality of connection lines, for example, a bit line BL, and a word line connection line WL-CL coupled to the word line WL. The material of the first interconnect conductor layer 291 and the contacts may be a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, or other suitable materials. The material of the first interlayer insulating layer 292 is an insulating material, such as a combination of one or more of silicon oxide, silicon nitride, and high dielectric constant insulating material, or other suitable materials.

[0102] The peripheral device 100 may include peripheral circuits. The peripheral circuits are configured to control and sense the array device. The peripheral circuits may be any suitable digital, analog, and / or mixed signal control and sensing circuits for supporting the operation (or work) of the array device, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuits may also include any other circuits compatible with advanced logic processes, including logic circuits (e.g., processors and programmable logic devices (PLDs) or storage circuits (e.g., static random access memories (SRAMs)).

[0103] In some embodiments, the peripheral device 100 may include a substrate 110, a transistor 120 disposed on the substrate 110, and a peripheral interconnect layer 130 disposed on the substrate 110. The peripheral circuit may include the transistor 120.

[0104] The material of the substrate 110 may be single crystal silicon, or other suitable materials, such as silicon germanium, germanium, or silicon-on-insulator thin film.

[0105] The peripheral interconnection layer 130 is coupled to the transistor 120 to transmit electrical signals between the transistor 120 and the peripheral interconnection layer 130. The peripheral interconnection layer 130 may include one or more second interlayer insulating layers 131, and may also include one or more second interconnect conductor layers 132. Different second interconnect conductor layers 132 may be coupled through contacts. The material of the second interconnect conductor layer 132 and the contact may be a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, or other suitable materials. The material of the second interlayer insulating layer 131 is an insulating material, such as a combination of one or more of silicon oxide, silicon nitride, and high dielectric constant insulating materials, or other suitable materials.

[0106] The peripheral interconnect layer 130 may be coupled to the array interconnect layer 290, so that the semiconductor structure 200 and the peripheral device 100 may be coupled. Specifically, since the peripheral interconnect layer 130 is coupled to the array interconnect layer 290, the peripheral circuit in the peripheral device 100 may be coupled to the memory cell string in the semiconductor structure 200 to achieve transmission of electrical signals between the peripheral circuit and the memory cell string. In some possible implementations, a bonding interface 50 may be provided between the peripheral interconnect layer 130 and the array interconnect layer 290, and the peripheral interconnect layer 130 and the array interconnect layer 290 may be bonded and coupled to each other through the bonding interface 50.

[0107] Please refer to Figure 5 and Figure 6 ,in, Figure 5 is a schematic cross-sectional view of a connection region SS of a semiconductor structure 200 in some embodiments of the present application. Figure 6 Schematic diagram of the cross section of the array area CA of the semiconductor structure 200 in some embodiments of the present application. The semiconductor structure 200 provided in the embodiment of the present application may include a stacked structure 300, and one side of the stacked structure 300 is used to couple with the wafer layer 280. Among them, the wafer layer 280 includes a peripheral circuit wafer, which may also be called a complementary metal oxide semiconductor (CMOS) wafer. The CMOS Wafer includes a peripheral circuit for signal transmission to the storage unit. The stacked structure 300 includes an array area CA and a connection area SS, and the array area CA and the connection area SS are adjacent to each other, that is, the projections of the array area CA and the connection area SS on the array interconnection layer are adjacent.

[0108] Continue to refer to Figure 5 and Figure 6 The stacked structure 300 includes a plurality of insulating layers 310 and a plurality of gate line layers 320 alternately stacked. For example, the number of insulating layers 310 in the stacked structure 300 may be 32, 48, 64, 96, 128, 256, 300, etc., and the number of gate line layers 320 in the stacked structure 300 may be 32, 48, 64, 96, 128, 256, 300, etc. In some embodiments, the insulating layer 310 may include an insulating material, for example, at least one of silicon oxide and silicon oxynitride. The gate line layer 320 may include a conductive material, for example, at least one of tungsten, cobalt, copper, aluminum, doped silicon, and silicide.

[0109] Each gate line layer 320 includes a first gate line layer 321 located in the array area CA and a second gate line layer 322 located in the connection area SS; it is understood that the first gate line layer 321 and the second gate line layer 322 can also include a conductive material, for example, at least one of tungsten, cobalt, copper, aluminum, doped silicon, and silicide. In some embodiments, the first gate line layer 321 and the second gate line layer 322 can be made of the same material.

[0110] Continue to refer to Figure 5The stacked structure 300 further includes a plurality of dielectric layers 330 located in the connection area SS. The plurality of dielectric layers 330 and the plurality of insulating layers 310 are alternately stacked, and the dielectric layers 330 and the gate line layers 320 are arranged in the same layer (each dielectric layer 330 is arranged in the same layer as one gate line layer 320), and the dielectric layers 330 and the second gate line layers 322 are both located in the connection area SS. It can be understood that the dielectric layers 330 and the second gate line layers 322 are arranged in the same layer, and the dielectric layers 330 are located on one side of the second gate line layers 322, and a barrier layer 340 is arranged between the dielectric layers 330 and the second gate line layers 322.

[0111] In the embodiment of the present application, the barrier layer 340 may include at least one of monocrystalline silicon and polycrystalline silicon. In some implementations, the barrier layer 340 may include polycrystalline silicon to improve the stability of the barrier layer 340.

[0112] In the implementation mode in which the stacked structure 300 includes a dielectric layer 330, the dielectric layer 330 may include silicide, and illustratively, the material of the dielectric layer 330 may be silicon nitride. In some embodiments, before forming the second gate line layer 322, the barrier layer 340 may be formed on the dielectric layer 330 including silicide by a selective epitaxial growth process, and illustratively, polysilicon may be selectively epitaxially grown to form the barrier layer 340. The barrier layer 340 may be formed between the dielectric layer 330 and the second gate line layer 322 to prevent the integrity of the second gate line layer 322 from being damaged during the removal of the dielectric layer 330.

[0113] Please refer to Figure 7 In the embodiment of the present application, the second gate line layer 322 may include an intermediate conductive layer 3221 and a high dielectric constant layer 3222. The high dielectric constant layer 3222 is wrapped around the outer side of the intermediate conductive layer 3221. The high dielectric constant layer 3222 may be located between the intermediate conductive layer 3221 and the insulating layer 310, so as to avoid leakage between two adjacent second gate line layers 322.

[0114] In the implementation mode in which the barrier layer 340 is disposed between the dielectric layer 330 and the second gate line layer 322, the barrier layer 340 may be disposed between the high dielectric constant layer 3222 and the dielectric layer 330. The barrier layer 340 may prevent the high dielectric constant layer 3222 between the middle conductive layer 3221 and the insulating layer 310 from being removed simultaneously during the process of removing part of the dielectric layer 330, thereby preventing leakage between two adjacent second gate line layers 322.

[0115] Among them, the intermediate conductive layer 3221 may include a conductive material, for example, at least one of tungsten, cobalt, copper, aluminum, doped silicon, and silicide. The high dielectric constant layer 3222 may be formed of a high dielectric constant material. In the semiconductor industry, a high dielectric constant is generally defined as: a material having a dielectric constant higher than that of silicon dioxide, and the dielectric constant of silicon dioxide is 3.9. The dielectric constant of the high dielectric constant material may be 4.0, 4.6, 5.2, 5.5, 6.0, 6.3, 6.7, 7.2, 8.5, 9.1, 9.8, 10.4, and the like. The material of the high dielectric constant layer 3222 may include aluminum oxide (Al2O3), hafnium dioxide (HfO2), tantalum pentoxide (Ta2O5), titanium dioxide (TiO2), silicon oxynitride (SiO x N y ) at least one of.

[0116] It can be understood that the structures of the first gate line layer 321 and the second gate line layer 322 are substantially the same, that is, the first gate line layer 321 may also include an intermediate conductive layer 3221 and a high dielectric constant layer 3222 .

[0117] Continue to refer to Figure 5 In some embodiments, the semiconductor structure 200 may further include a connection structure 400, which extends to the corresponding dielectric layer 330 along the alternating stacking direction of the plurality of dielectric layers 330 and the plurality of insulating layers 310; it is understandable that there may be a plurality of connection structures 400, and the bottom of each connection structure 400 along the alternating stacking direction is located at a different dielectric layer 330. The connection structure 400 passes through the barrier layer 340 in a direction perpendicular to the stacking direction and is connected to the corresponding second gate line layer 322.

[0118] In one embodiment, the semiconductor structure includes a gate line layer and a dielectric layer, the gate line layer includes a conductive layer and a high dielectric constant layer, wherein the high dielectric constant layer is wrapped around the outside of the conductive layer, and the high dielectric constant layer located at one end of the conductive layer close to the dielectric layer is directly connected to the dielectric layer. During the manufacturing process, it is necessary to remove part of the dielectric layer to form a gap, and form a connection structure in the gap to connect the connection structure to the conductive layer; in the process of removing part of the dielectric layer, since the etching selection of the dielectric layer and the high dielectric constant layer is relatively close, that is, when removing part of the dielectric layer, the high dielectric constant layer located between the conductive layer and the insulating layer will also be removed at the same time, which makes it easy for leakage to occur between the two adjacent conductive layers.

[0119] When forming the semiconductor structure 200 in the embodiment of the present application, before forming the second gate line layer 322, a blocking layer can be formed at one end of the dielectric layer 330 close to the first gap layer, and then the second gate line layer 322 is formed in the first gap layer 741. Since the blocking layer 340 includes at least one of single crystal silicon and polycrystalline silicon, the etching selectivity of the blocking layer 340 and the dielectric layer 330 is different, and the etching selectivity of the blocking layer 340 and the high dielectric constant layer 3222 is also different. That is to say, in the process of removing part of the dielectric layer 330, the blocking layer 340 located at one end of the dielectric layer 330 close to the second gate line layer 322 will not be removed at the same time, or it can be said that only part of the blocking layer 340 is removed, and the blocking layer 340 can prevent the high dielectric constant layer 3222 from being removed.

[0120] In the process of forming the connection structure 400 in the embodiment of the present application, a second void layer is formed after removing part of the dielectric layer 330. The second void layer can expose the blocking layer 340, and then the blocking layer 340 can be removed through the second void layer. Since the etching selectivity of the blocking layer 340 and the high dielectric constant layer 3222 is different, that is, in the process of removing the blocking layer 340, the high dielectric constant layer 3222 will not be removed at the same time, thereby avoiding leakage between two adjacent second gate line layers 322.

[0121] The semiconductor structure 200 provided in the embodiment of the present application, the stacked structure 300 includes a plurality of insulating layers 310 and a plurality of gate line layers 320 that are alternately stacked, each gate line layer 320 includes a first gate line layer 321 located in the array area CA and a second gate line layer 322 located in the connection area SS, a plurality of dielectric layers 330 located in the connection area SS and the plurality of insulating layers 310 are alternately stacked, and the dielectric layer 330 and the second gate line layer 322 are arranged in the same layer, a blocking layer 340 is arranged between the dielectric layer 330 and the second gate line layer 322, and the connection structure 400 extends to the corresponding dielectric layer 330 along the alternating stacking direction of the plurality of dielectric layers 330 and the plurality of insulating layers 310, and is connected to the corresponding second gate line layer 322 through the blocking layer 340 in a direction perpendicular to the stacking direction. Through the above-mentioned setting, in the process of removing part of the dielectric layer 330 to form the connecting structure 400, the barrier layer 340 can be used as an etching stop layer, thereby preventing the high dielectric constant layer 3222 located between the intermediate conductive layer 3221 and the insulating layer 310 from being removed in the process of removing part of the dielectric layer 330, so as to avoid leakage between adjacent intermediate conductive layers 3221.

[0122] Continue to refer to Figure 5In an implementation in which the semiconductor structure 200 includes a connection structure 400, the connection structure 400 may include a first connection portion 410 and a second connection portion 420, wherein the first connection portion 410 extends along the alternating stacking direction of the plurality of dielectric layers 330 and the plurality of insulating layers 310, the extension direction of the second connection portion 420 is perpendicular to the extension direction of the first connection portion 410, and the edge of the second connection portion 420 is connected to the second gate line layer 322.

[0123] Through the above configuration, the second connection portion 420 is connected to the second gate line layer 322 , and the first connection portion 410 is connected to the second connection portion 420 , so that the second gate line layer 322 can be connected to the external circuit through the connection portion 400 .

[0124] Please refer to Figure 5 and Figure 8 In the above implementation, the second connection part 420 is in a pancake shape, wherein the thickness of the second connection part 420 is substantially the same as the thickness of the dielectric layer 330, and the projection of the second connection part 420 on the XY plane is circular. In the circumferential direction of the second connection part 420, the dielectric layer 330 surrounds the second connection part 420, and an opening 331 is provided on one side of the dielectric layer 330 close to the second gate line layer 322, and an end of the second connection part 420 close to the second gate line layer 322 is connected to the second gate line layer 322 through the opening 331. The first connecting portion 410 may be columnar, and the first connecting portion 410 extends into the stacking structure 300 from a side of the stacking structure 300 away from the wafer layer 280, that is, the first connecting portion 410 extends along the third direction Z, so that one end of the first connecting portion 410 extending into the stacking structure 300 is connected to the second connecting portion 420; in an implementation in which the first connecting portion 410 is columnar and the second connecting portion 420 is pie-shaped, the axial direction of the first connecting portion 410 points to the center of the second connecting portion 420.

[0125] Continue to refer to Figure 5 and Figure 8 In an implementation in which the blocking layer 340 can be disposed between the high dielectric constant layer 3222 and the dielectric layer 330 , the second connection portion 420 passes through the blocking layer 340 and the high dielectric constant layer 3222 along an extension direction perpendicular to the first connection portion 410 , and is connected to the intermediate conductive layer 3221 .

[0126] In the process of forming the second connecting part 420, part of the dielectric layer 330 can be removed first to form a cavity, and part of the blocking layer 340 and part of the high dielectric constant layer 3222 can be removed in sequence through the cavity, so that the second connecting part 420 can pass through the blocking layer 340 and the high dielectric constant layer 3222 to connect to the intermediate conductive layer 3221 without leakage.

[0127] Please refer to Figure 5 and Figure 6 In the embodiment of the present application, the semiconductor structure 200 may further include a channel structure 500. The channel structure 500 may be provided in plurality, and the plurality of channel structures 500 may be respectively arranged in the array area CA and the connection area SS. The channel structure 500 runs through the stacked structure 300, that is, the channel structure 500 runs through the plurality of insulating layers 310 and the plurality of gate line layers 320 that are alternately stacked. A storage unit is formed between the channel structure 500 and each gate line layer 320 to realize data storage, and at the same time, the semiconductor structure has a higher storage density.

[0128] Continue to refer to Figure 7 The channel structure 500 may include a channel column 510 and a storage medium layer 520 , wherein the channel column 510 penetrates the stack structure 300 , and the storage medium layer 520 covers the sidewalls of the channel column 510 and is located between the channel column 510 and the stack structure 300 .

[0129] Exemplarily, the channel pillar 510 may include at least one of polycrystalline silicon or single crystal silicon.

[0130] Continue to refer to Figure 7 The storage medium layer 520 may include an isolation layer 521, a storage layer 522 and a tunneling layer 523, and the isolation layer 521, the storage layer 522 and the tunneling layer 523 are arranged in sequence in the direction from the channel column 510 to the stacking structure 300, wherein the tunneling layer 523 covers the side wall of the channel column 510, the storage layer 522 is located between the tunneling layer 523 and the isolation layer 521, and the isolation layer 521 is located between the storage layer 522 and the stacking structure 300.

[0131] Exemplarily, the isolation layer 521 may include at least one of silicon oxide and metal oxide; the storage layer 522 may include at least one of silicon nitride and silicon oxynitride; and the tunneling layer 523 may include at least one of silicon oxide and metal oxide.

[0132] Please refer to Figures 5 to 7 The channel structure 500 may include a storage channel structure located in the array area CA and a dummy channel structure located in the connection area SS, wherein the storage channel structure is used to store charges, and the dummy channel structure is used to support the stack structure 300 and improve the stability of the semiconductor structure 200. In some embodiments, the dummy channel structure and the storage channel structure may have the same structure.

[0133] In other embodiments, the structures of the virtual channel structure and the storage channel structure may be different. For example, the channel column 510 of the storage channel structure may be a solid column, and the channel column 510 of the virtual channel structure may be a hollow column. When the channel column 510 is a hollow column, the channel column 510 may further include a support portion 530. The support portion 530 may be located inside the channel column 510, that is, the channel column 510 surrounds the support portion 530, and the support portion 530 may provide support for the channel structure 500. The support portion 530 may include an insulating material, such as silicon oxide.

[0134] Please refer to Figure 5 and Figure 6 In the embodiment of the present application, the semiconductor structure 200 may further include a first isolation structure 610 and a second isolation structure 620, both of which penetrate the stacked structure 300, that is, both of the first isolation structure 610 and the second isolation structure 620 penetrate the plurality of insulating layers 310 and the plurality of gate line layers 320, and the first isolation structure 610 and the second isolation structure 620 are arranged at intervals. In some embodiments, the first isolation structure 610 may penetrate the connection area SS and the array area CA, and the second isolation structure 620 may also penetrate the connection area SS and the array area CA. Through the above arrangement, the first isolation structure 610 and the second isolation structure 620 may support the stacked structure 300 to improve the stability of the semiconductor structure 200.

[0135] Continue to refer to Figure 5 In the above embodiment, the first isolation structure 610 includes a filling column 611 and a spacer layer 612. The filling column 611 can support the semiconductor structure 200. The filling column 611 can include at least one of metal (such as tungsten, copper, aluminum, etc.), metal silicide, metal nitride, and doped polysilicon. The spacer layer 612 is disposed between the filling column 611 and the sidewall of the stacked structure 300. The spacer layer 612 can include at least one of silicon oxide and metal oxide. It can be understood that the second isolation structure 620 has the same structure as the first isolation structure 610.

[0136] The present application also provides a method for preparing a semiconductor structure. Fig. 9 The preparation method may include steps S100-S700:

[0137] S100: forming a stacked structure, the stacked structure comprising a plurality of insulating layers and a plurality of sacrificial layers alternately stacked, the stacked structure further comprising an array region and a connection region, the array region and the connection region being adjacently arranged; the sacrificial layer comprising a first sacrificial layer located in the array region and a second sacrificial layer located in the connection region.

[0138] Please refer to Fig. 10A and Fig. 10BIn step S100, forming the stacked structure 700 may include:

[0139] A plurality of insulating layers 310 and a plurality of sacrificial layers 710 are alternately stacked on the substrate by a thin film deposition process. "Alternate stacking" means that after forming a layer of insulating layer 310 on the substrate 411, a layer of sacrificial layer 710 is formed on the insulating layer 310, and then another layer of insulating layer 310 is formed on the sacrificial layer 710, and then the above steps are repeated. In the embodiment of the present application, the first sacrificial layer 711 located in the array area CA and the second sacrificial layer 712 located in the connection area SS are distinguished according to the position of the sacrificial layer 710. For the convenience of description, it can be understood that the structure, material, relative position relationship with the insulating layer 310, etc. of the first sacrificial layer 711 and the second sacrificial layer 712 are the same.

[0140] Exemplarily, the thin film deposition process may include a combination of one or more of chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) and electroplating processes.

[0141] The formation of the stacked structure 700 may also include forming a channel hole (not shown) on the alternately stacked insulating layer 310 and the sacrificial layer 710. The channel hole may be formed by etching. The etched channel hole extends into the substrate 411 to ensure that the channel structure 500 formed in the channel hole can pass through the stacked structure 700.

[0142] After the channel hole is formed, a channel structure 500 is formed in the channel hole.

[0143] After forming the channel hole, the method provided in the embodiment of the present application further includes:

[0144] S200: removing the first sacrificial layer and a portion of the second sacrificial layer to form a first gap layer, and the remaining portion of the second sacrificial layer is used as a dielectric layer.

[0145] Please refer to Fig. 10A and Fig. 10B In some embodiments, step S200 may include forming a first gate slit 721 on the stacked structure 700 , wherein the first gate slit 721 penetrates the stacked structure 700 ; and removing the first sacrificial layer 711 and a portion of the second sacrificial layer 712 using the first gate slit 721 .

[0146] Through the above arrangement, the first sacrificial layer 711 and part of the second sacrificial layer 712 are removed by using the first gate gap 721 to form a first gap layer 741, and the remaining part of the second sacrificial layer 712 is used as the dielectric layer 330 (eg Fig. 10C As shown), so that the dielectric layer 330 is close to the first gap layer 741 (as shown Fig. 10C A barrier layer 340 is formed at one end of Figure 5 shown).

[0147] Continue to refer to Fig. 10A and Fig. 10B In the above implementation, while forming the first gate slit 721 on the stacked structure 700, it also includes: forming a second gate slit 722 in the array area CA, and the second gate slit 722 penetrates the stacked structure 700;

[0148] Removing the first sacrificial layer 711 and a portion of the second sacrificial layer 712 includes: removing the first sacrificial layer 711 and a portion of the second sacrificial layer 712 by using the first gate slits 721 and the second gate slits 722 .

[0149] Through the above arrangement, the first gate slits 721 and the second gate slits 722 are used to remove the first sacrificial layer 711 and part of the second sacrificial layer 712, thereby increasing the channels for removing the first sacrificial layer 711 and part of the second sacrificial layer 712 and improving the efficiency of removing the first sacrificial layer 711 and part of the second sacrificial layer 712.

[0150] Step S200 removes the first sacrificial layer 711 and part of the second sacrificial layer 712. Fig. 10C and Fig. 10D Please refer to Fig. 10C and Fig. 10D , the first sacrificial layer 711 and a portion of the second sacrificial layer 712 are removed to form a first gap layer 741 , and the remaining portion of the second sacrificial layer 712 forms a dielectric layer 330 .

[0151] After forming the first gap layer, the method provided in the embodiment of the present application further includes:

[0152] S300: forming a barrier layer at one end of the dielectric layer close to the first gap layer.

[0153] Please refer to Fig.10E In some embodiments, the material of the dielectric layer 330 includes silicon nitride, the material of the barrier layer 340 includes polysilicon, and the barrier layer 340 is formed by a selective epitaxial growth process. This arrangement facilitates the formation of the barrier layer and simplifies the manufacturing difficulty.

[0154] Through the above arrangement, there is a high selectivity ratio between the polysilicon formed by selective epitaxial growth on the dielectric layer 330 and the silicon nitride of the dielectric layer 330, that is, in the process of removing the dielectric layer 330, the barrier layer 340 composed of polysilicon can prevent the second gate line layer 322 (such as the second gate line layer 322) located in the first gap layer 741 from being formed. Figure 5 ) are removed at the same time, thereby ensuring the integrity of the second gate line layer 322 and preventing leakage of the semiconductor structure 200. At the same time, polycrystalline silicon can improve the stability of the barrier layer 340 compared to single crystal silicon.

[0155] Continue to refer to Fig.10E In some embodiments, in the selective epitaxial growth process, polysilicon is formed on both the dielectric layer and the insulating layer.

[0156] Through the above arrangement, polysilicon is formed on both the dielectric layer 330 and the insulating layer 310 , so that both ends of the barrier layer 340 in the stacking direction can be directly connected to the insulating layer 310 , thereby achieving sealing of one end of the dielectric layer 330 close to the first gap layer 741 .

[0157] Continue to refer to Fig.10E In some embodiments, the growth rate of polysilicon on the dielectric layer 330 is greater than the growth rate on the insulating layer 310 , and after the selective epitaxial growth process, the polysilicon on the insulating layer 310 is removed, and the polysilicon retained on the dielectric layer 330 serves as a barrier layer 340 .

[0158] In the above implementation, since the growth rate of polysilicon on the dielectric layer 330 is greater than the growth rate on the insulating layer 310, the thickness of the polysilicon located on the insulating layer 310 is less than the thickness of the polysilicon located on the dielectric layer 330. By isotropic etching, the polysilicon on the insulating layer 310 is removed and the thickness of the polysilicon on the dielectric layer 330 is reduced, wherein the polysilicon retained on the dielectric layer 330 serves as a barrier layer 340.

[0159] By controlling the time of the isotropic etching, the polysilicon on the insulating layer 310 can be removed while a portion of the polysilicon can be retained on the dielectric layer 330 .

[0160] Through the above arrangement, in the process of removing the dielectric layer 330, the blocking layer 340 composed of polysilicon can prevent the second gate line layer 322 (such as Figure 5 As shown in the figure, the second gate line layer 322 is removed at the same time, thereby ensuring the integrity of the second gate line layer 322 and preventing the semiconductor structure 200 from leaking electricity.

[0161] S400: forming a stacked structure, including forming a first gate line layer in a first gap layer in the array region, and forming a second gate line layer in the first gap layer in the connection region.

[0162] Please compare Fig.10E and Fig.10F , and comparative reference Fig. 10D and Figure 10G The stacked structure 300 is formed by forming a first gate line layer 321 and a second gate line layer 322 in a first gap layer 741 through a first gate gap 721. It is understandable that the stacked structure 300 can also be formed by forming a first gate line layer 321 and a second gate line layer 322 in a first gap layer 741 through a second gate gap 722, or by forming a first gate line layer 321 and a second gate line layer 322 in a first gap layer 741 through a first gate gap 721 and a second gate gap 722 at the same time.

[0163] Please compare Fig.10F and Fig. 10H , and comparative reference Figure 10G and Fig.10I In some embodiments, after forming the first gate line layer 321 and the second gate line layer 322 , a first isolation structure 610 may be formed in the first gate gap 721 , and a second isolation structure 620 may be formed in the second gate gap 722 .

[0164] Through the above configuration, the first isolation structure 610 and the second isolation structure 620 can support the stack structure 300 to improve the stability of the semiconductor structure 200 .

[0165] S500: forming a conductive hole on the connection area of ​​the stacked structure 300, wherein the conductive hole extends to a dielectric layer; and removing at least a portion of the corresponding dielectric layer by using the conductive hole to form a second gap layer.

[0166] Please refer to Fig.10J In some embodiments, in step S500, a conductive hole 750 is formed on the stacked structure 300, and the corresponding at least part of the dielectric layer 330 is removed by using the conductive hole 750 to form the second gap layer 742, including: removing at least part of the dielectric layer 330 corresponding to the conductive hole 750 by etching; under the same etching conditions, the etching rate of the barrier layer 340 is less than the etching rate of the dielectric layer 330.

[0167] Through the above configuration, after removing part of the dielectric layer 330 , part of the blocking layer 340 is still located on the side of the second gate line layer 322 close to the second gap layer 742 , which prevents the second gate line layer 322 from being removed at the same time, ensures the integrity of the second gate line layer 322 , and avoids leakage of the semiconductor structure 200 .

[0168] S600: using the second gap layer to remove part of the barrier layer to form a hole.

[0169] Please refer to Figure 10J1In some embodiments, the second gate line layer 322 includes an intermediate conductive layer 3221 and a high dielectric constant layer 3222 , the high dielectric constant layer 3222 is wrapped around the outer side of the intermediate conductive layer 3221 , and the barrier layer 340 is disposed between the intermediate conductive layer 3221 and the dielectric layer 330 ;

[0170] After removing a portion of the barrier layer 340 by using the second gap layer 742 to form a hole, the method further includes:

[0171] The high dielectric constant layer 3222 corresponding to the second gap layer 742 is removed through the hole.

[0172] Through the above configuration, after a portion of the high dielectric constant layer 3222 is removed, a portion of the intermediate conductive layer 3221 is exposed, so that the connection structure 400 is connected to the intermediate conductive layer 3221 during the process of forming the connection structure 400 .

[0173] S700: Filling the holes, the second gap layer and the conductive holes with a conductive material to form a connection structure.

[0174] Please refer to Figure 10K In some embodiments, step S700 may further include forming a first connection part 410 in the conductive hole 750 with a conductive material, forming a second connection part 420 in the hole and the second gap layer 742 with a conductive material, and the second connection part 420 passing through the hole to connect with the intermediate conductive layer 3221. Through the above configuration, the second connection part 420 is connected to the intermediate conductive layer 3221, and the first connection part 410 is connected to the second connection part 420, so that the intermediate conductive layer 3221 can be connected to the external circuit through the connection part 400.

[0175] Continue to refer to Fig.10J and Figure 10K After forming the connection structure 400, the substrate 411 can be removed and the wafer layer 280 can be formed to facilitate electrical connection between the semiconductor structure 200 and the peripheral circuit.

[0176] Please refer to Figures 5 to 7, a semiconductor structure manufactured by the method provided in an embodiment of the present application, the stacked structure 300 includes a plurality of insulating layers 310 and a plurality of gate line layers 320 alternately stacked, each gate line layer 320 includes a first gate line layer 321 located in an array area CA and a second gate line layer 322 located in a connection area SS, a plurality of dielectric layers 330 located in the connection area SS are alternately stacked with the plurality of insulating layers 310, and the dielectric layers 330 and the second gate line layers 322 are arranged in the same layer, a barrier layer 340 is arranged between the dielectric layers 330 and the second gate line layers 322, and a connection structure 400 extends to the corresponding dielectric layer 330 along the alternating stacking direction of the plurality of dielectric layers 330 and the plurality of insulating layers 310, and is connected to the corresponding second gate line layer 322 through the barrier layer 340 in a direction perpendicular to the stacking direction. Through the above-mentioned setting, in the process of removing part of the dielectric layer 330 to form the connecting structure 400, the barrier layer 340 can be used as an etching stop layer, thereby preventing the high dielectric constant layer 3222 located between the intermediate conductive layer 3221 and the insulating layer 310 from being removed in the process of removing part of the dielectric layer 330, so as to avoid leakage between adjacent intermediate conductive layers 3221.

[0177] Please refer to Fig.11 and Fig.12 Some embodiments of the present application further provide a storage system 1000. The storage system 1000 includes a controller 20 and a three-dimensional memory 10, wherein the three-dimensional memory 10 may include the semiconductor structure 200 as described above, and the controller 20 is coupled to the three-dimensional memory 10 to control the three-dimensional memory 10 to store data.

[0178] The storage system 1000 may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the storage system 1000 may be applied to and packaged into different types of electronic products, for example, mobile phones (e.g., cell phones), desktop computers, tablet computers, laptop computers, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0179] In some embodiments, reference Fig.11 The storage system 1000 includes a controller 20 and a three-dimensional memory 10, and the storage system 1000 can be integrated into a memory card.

[0180] Among them, the memory card includes any one of PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital (SD) card, and UFS.

[0181] In other embodiments, referring to Fig.12 The storage system 1000 includes a controller 20 and a plurality of three-dimensional memories 10, and the storage system 1000 is integrated into a solid state drive (SSD).

[0182] In the storage system 1000, in some embodiments, the controller 20 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones.

[0183] In other embodiments, the controller 20 is configured to operate in a high duty cycle environment SSD or eMMC used for data storage in mobile devices such as smartphones, tablets, notebooks, and enterprise storage arrays.

[0184] In some embodiments, the controller 20 may be configured to manage data stored in the three-dimensional memory 10 and communicate with an external device (e.g., a host). In some embodiments, the controller 20 may also be configured to control operations of the three-dimensional memory 10, such as read, erase, and program operations. In some embodiments, the controller 20 may also be configured to manage various functions regarding data stored or to be stored in the three-dimensional memory 10, including at least one of bad block management, garbage collection, logical to physical address conversion, and wear leveling. In some embodiments, the controller 20 is also configured to process error correction codes regarding data read from or written to the three-dimensional memory 10.

[0185] Of course, the controller 20 may also perform any other suitable functions, such as formatting the three-dimensional memory 10; for example, the controller 20 may communicate with an external device (eg, a host) via at least one of various interface protocols.

[0186] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer interface (SCSI) protocol, enhanced minidisk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, and Firewire protocol.

[0187] Some embodiments of the present application also provide an electronic device. The electronic device can be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0188] The electronic device may include the storage system 1000 described above, and may also include at least one of a central processing unit (CPU) and a cache.

[0189] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that: include: A stacked structure, wherein the stacked structure comprises a plurality of insulating layers and a plurality of gate line layers alternately stacked; the stacked structure comprises an array region and a connection region, wherein the array region and the connection region are adjacently arranged; each of the gate line layers comprises a first gate line layer located in the array region and a second gate line layer located in the connection region; the stacked structure further comprises a plurality of dielectric layers located in the connection region, wherein the plurality of dielectric layers and the plurality of insulating layers are alternately stacked, and the dielectric layer and the second gate line layer are arranged in the same layer, and a barrier layer is arranged between the dielectric layer and the second gate line layer; A connection structure extends to the corresponding dielectric layer along the alternating stacking direction of the plurality of dielectric layers and the plurality of insulating layers, and passes through the barrier layer in a direction perpendicular to the stacking direction to connect with the corresponding second gate line layer.

2. The semiconductor structure according to claim 1, characterized in that: The material of the barrier layer includes polysilicon.

3. The semiconductor structure according to claim 2, characterized in that: The dielectric layer is made of silicide, and the barrier layer is formed by a selective epitaxial growth process.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The second gate line layer includes an intermediate conductive layer and a high dielectric constant layer, the high dielectric constant layer is wrapped around the outer side of the intermediate conductive layer, and the barrier layer is arranged between the high dielectric constant layer and the dielectric layer.

5. The semiconductor structure according to claim 4, characterized in that: The connection structure includes a first connection portion extending along the alternating stacking direction of the plurality of dielectric layers and the plurality of insulating layers and a second connection portion connected to the first connection portion, wherein the second connection portion is connected to the second gate line layer.

6. The semiconductor structure according to claim 5, characterized in that: The second connection portion passes through the barrier layer and the high dielectric constant layer along an extension direction perpendicular to that of the first connection portion, and is connected to the intermediate conductive layer.

7. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The stacked structure further includes a first isolation structure and a second isolation structure. Both the first isolation structure and the second isolation structure penetrate through the plurality of insulating layers and the plurality of gate line layers. The first isolation structure and the second isolation structure are arranged at intervals.

8. A method for manufacturing a semiconductor structure, characterized in that: include: Forming a stacked structure, the stacked structure comprising a plurality of insulating layers and a plurality of sacrificial layers alternately stacked, the stacked structure further comprising an array region and a connection region, the array region and the connection region being adjacently arranged; the sacrificial layer comprising a first sacrificial layer located in the array region and a second sacrificial layer located in the connection region; removing the first sacrificial layer and a portion of the second sacrificial layer to form a first gap layer, and using the remaining portion of the second sacrificial layer as a dielectric layer; forming a barrier layer at one end of the dielectric layer close to the first gap layer; Forming a stacked structure, including forming a first gate line layer in the first gap layer in the array area, and forming a second gate line layer in the first gap layer in the connection area; forming a conductive hole on the connection area of ​​the stacked structure, wherein the conductive hole extends to one of the dielectric layers; and using the conductive holes to remove at least a corresponding portion of the dielectric layer to form a second gap layer; Using the second gap layer to remove part of the barrier layer to form a hole; Conductive material is filled in the hole, the second gap layer and the conductive hole to form a connection structure.

9. The method for manufacturing a semiconductor structure according to claim 8, characterized in that: Forming a barrier layer at one end of the dielectric layer close to the first gap layer comprises: The material of the dielectric layer includes silicon nitride, the barrier layer is formed by a selective epitaxial growth process, and the material of the barrier layer includes polysilicon.

10. The method for manufacturing a semiconductor structure according to claim 9, characterized in that: In the selective epitaxial growth process, polysilicon is formed on both the dielectric layer and the insulating layer.

11. The method for manufacturing a semiconductor structure according to claim 10, characterized in that: The growth rate of polysilicon on the dielectric layer is greater than the growth rate on the insulating layer, and after the selective epitaxial growth process, the method further includes: The polysilicon on the insulating layer is removed, and the polysilicon remaining on the dielectric layer forms the barrier layer.

12. The method for manufacturing a semiconductor structure according to any one of claims 8 to 11, characterized in that: Removing the first sacrificial layer and a portion of the second sacrificial layer includes: forming a first gate gap on the stacked structure, wherein the first gate gap penetrates the stacked structure; The first sacrificial layer and a portion of the second sacrificial layer are removed by utilizing the first gate gap.

13. The method for manufacturing a semiconductor structure according to claim 12, characterized in that: The method further comprises: forming a second gate slit in the array region while forming the first gate slit on the stacked structure, wherein the second gate slit runs through the stacked structure; Removing the first sacrificial layer and a portion of the second sacrificial layer includes: removing the first sacrificial layer and a portion of the second sacrificial layer by using the first gate slit and the second gate slit.

14. The method for manufacturing a semiconductor structure according to any one of claims 8 to 11, characterized in that: The forming of the stacked structure includes forming a first gate line layer in the first gap layer in the array region, and forming a second gate line layer in the first gap layer in the connection region, and further includes: A first isolation structure is formed in the first gate gap, and a second isolation structure is formed in the second gate gap.

15. The method for manufacturing a semiconductor structure according to any one of claims 8 to 11, characterized in that: The method of removing at least a portion of the dielectric layer corresponding to the conductive hole to form a second void layer includes: removing at least a portion of the dielectric layer corresponding to the conductive hole by etching; under the same etching conditions, the etching rate of the barrier layer is lower than the etching rate of the dielectric layer.

16. The method for manufacturing a semiconductor structure according to any one of claims 8 to 11, wherein the second gate line layer comprises an intermediate conductive layer and a high dielectric constant layer, the high dielectric constant layer is wrapped around the outer side of the intermediate conductive layer, and the barrier layer is disposed between the intermediate conductive layer and the dielectric layer; After the method uses the second gap layer to remove a portion of the barrier layer to form a hole, the method further comprises: A portion of the high dielectric constant layer corresponding to the second gap layer is removed through the hole.

17. According to the semiconductor structure manufacturing method of claim 16, filling the hole, the second void layer and the conductive hole with conductive material to form a connection structure also includes: the conductive material forms a first connection part in the conductive hole, the conductive material forms the second connection part in the hole and the second void layer, and the second connection part passes through the hole to connect with the intermediate conductive layer.

18. A storage system, characterized in that: include: A controller and a semiconductor structure as claimed in any one of claims 1 to 7, wherein the controller is coupled to the semiconductor structure to control the semiconductor structure to store data.

19. An electronic device, characterized in that: Comprising the storage system as claimed in claim 18.

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