Gallium oxide-based power device with double-layer field plate and preparation method of gallium oxide-based power device

Abstract

The invention discloses a gallium oxide-based power device with a double-layer field plate and a preparation method of the gallium oxide-based power device, and relates to the field of semiconductor devices. The gallium oxide-based power device comprises a first electrode layer, a gallium oxide substrate and a gallium oxide epitaxial layer which are sequentially stacked from bottom to top. The first dielectric layer is positioned on the surface of the gallium oxide epitaxial layer; the p-type semiconductor layer is continuously located on the surface of the gallium oxide epitaxial layer and a part of the surface of the first dielectric layer, and the part, located on the part of the surface of the first dielectric layer, of the p-type semiconductor layer is a first field plate; the second dielectric layer is continuously positioned on the surface of the first dielectric layer and a part of the surface of the first field plate; and the second electrode layer is continuously positioned on the surface of the p-type semiconductor layer and a part of the surface of the second dielectric layer, and the part, positioned on the part of the surface of the second dielectric layer, of the second electrode layer is a second field plate. Through introduction of the double-layer field plate structure, the gallium oxide-based power device has a higher breakdown electric field and has better voltage withstanding performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to a gallium oxide-based power device with a double-layer field plate and a preparation method thereof. Background Art

[0002] Gallium oxide (Ga2O3) materials have an ultra-wide bandgap of about 4.8eV and an ultra-high critical breakdown field strength of about 8MV / cm, which makes power devices based on gallium oxide materials have a Baliga figure of merit of more than 3000, which is 4 times that of gallium nitride (GaN)-based power devices and 10 times that of silicon carbide (SiC)-based power devices. It has great development potential for high breakdown voltage and high power density. Unlike SiC and GaN, the new generation of semiconductor materials can only grow substrates through the vapor phase method, gallium oxide substrate materials can be grown through the melt method, and also have the application advantages of high quality and low cost.

[0003] However, due to the lack of effective p-type doping in gallium oxide materials at this stage, the terminal technology that is maturely applied in silicon (Si)-based or SiC-based power devices (such as the combination of field plate structure and p-type field limiting ring structure, Ga2O3 cannot prepare field limiting ring structure due to the lack of effective p-type doping) cannot be directly applied to gallium oxide-based power devices, resulting in significant electric field concentration in the terminal area of ​​the device, and the breakdown voltage of the device is still low. Therefore, the current technology is still just to simply introduce a field plate structure (a terminal technology with simple process and significant effect) in gallium oxide-based power devices. Specifically, a layer of oxide layer is first grown on the surface of the semiconductor by process means, and then the anode metal is extended to the top of the oxide layer. The field plate metal is equivalent to the extension of the anode metal. Its principle is that when a reverse bias voltage is applied, a part of the electric field lines emitted by the donor positive charge in the terminal depletion region can be terminated on the field plate metal, which slows down the electric field concentration and reduces the electric field peak at the edge of the electrode. The introduction of the field plate can alleviate the electric field at the edge of the electrode, but at the same time, a new electric field will be introduced at the edge of the field plate. However, the existing field plate terminal of gallium oxide-based power devices only has a single-layer field plate structure (such as Chinese invention patent CN112186032A), which has limited effect on uniform electric field and limited regulation of electric field distribution, resulting in insignificant effect on improving device breakdown voltage. In addition, due to the ultra-high critical breakdown electric field and high relative dielectric constant (k) of gallium oxide, it is very easy to cause premature breakdown of the dielectric layer in the device during withstand voltage, affecting the performance of the device.

[0004] Therefore, it is urgent to develop a terminal structure suitable for gallium oxide-based power devices to increase the breakdown voltage of the device and thereby improve the device's voltage resistance. Summary of the invention

[0005] Based on the above-mentioned deficiencies of the prior art, the purpose of the present invention is to provide a gallium oxide-based power device with a double-layer field plate and a preparation method thereof, aiming to solve the problem that the withstand voltage performance of the existing gallium oxide-based power device with a single-layer field plate structure needs to be further improved.

[0006] The technical solution of the present invention is as follows:

[0007] In a first aspect of the present invention, a gallium oxide-based power device with a double-layer field plate is provided, wherein the gallium oxide-based power device with a double-layer field plate comprises a first electrode layer, a gallium oxide substrate and a gallium oxide epitaxial layer stacked in sequence from bottom to top;

[0008] The gallium oxide-based power device with a double-layer field plate further includes:

[0009] A first dielectric layer, located on the surface of the gallium oxide epitaxial layer;

[0010] A p-type semiconductor layer is continuously located on the surface of the gallium oxide epitaxial layer and on a portion of the surface of the first dielectric layer, and a portion of the p-type semiconductor layer located on the portion of the surface of the first dielectric layer is a first field plate;

[0011] A second dielectric layer, continuously disposed on the surface of the first dielectric layer and on a portion of the surface of the first field plate;

[0012] The second electrode layer is continuously located on the surface of the p-type semiconductor layer and on a portion of the surface of the second dielectric layer. The portion of the second electrode layer located on the portion of the surface of the second dielectric layer is the second field plate.

[0013] Optionally, a relative dielectric constant of the first dielectric layer is greater than a relative dielectric constant of the gallium oxide epitaxial layer.

[0014] Optionally, the breakdown electric field of the second dielectric layer is greater than the breakdown electric field of the first dielectric layer. Optionally, the thickness of the first dielectric layer is 100nm-1μm; the material of the first dielectric layer includes at least one of hafnium oxide, titanium oxide, zirconium oxide, strontium titanate and barium titanate;

[0015] The thickness of the second dielectric layer is 200 nm to 2 μm; the material of the second dielectric layer includes at least one of silicon oxide, silicon nitride and aluminum oxide.

[0016] Optionally, the material of the first electrode layer includes at least one of Ti, Ni, Ag and Au;

[0017] The material of the second electrode layer includes Ni, Mo, W, Pt, PtO x , Al, Au and Ag.

[0018] Optionally, the gallium oxide substrate has a thickness of 50 to 650 μm;

[0019] The gallium oxide substrate is a highly doped n-type gallium oxide substrate with a doping concentration of 10 18 ~10 20 cm -3 ;

[0020] The thickness of the gallium oxide epitaxial layer is 2 to 20 μm;

[0021] The gallium oxide epitaxial layer is a low-doped n-type gallium oxide epitaxial layer with a doping concentration of 10 15 ~10 17 cm -3 Optionally, the thickness of the p-type semiconductor layer is 100-600 nm; the p-type semiconductor layer includes at least one of p-type NiO, p-type Cu2O and p-type diamond;

[0022] The gallium oxide-based power device with a double-layer field plate further includes:

[0023] A passivation layer is continuously located on the surface of the second dielectric layer and on a portion of the surface of the second electrode layer.

[0024] Optionally, when the width of the p-type semiconductor layer is the same as the width of the first dielectric layer in a first direction on the horizontal plane, the width of the first field plate in a direction perpendicular to the first direction on the horizontal plane is greater than or equal to 2 μm.

[0025] Optionally, the projection of the second electrode layer on the gallium oxide epitaxial layer covers the projection of the p-type semiconductor layer on the gallium oxide epitaxial layer; or, the projection of the second electrode layer on the gallium oxide epitaxial layer coincides with the projection of the p-type semiconductor layer on the gallium oxide epitaxial layer.

[0026] A second aspect of the present invention provides a method for preparing a gallium oxide-based power device with a double-layer field plate as described above, comprising the following steps:

[0027] providing a gallium oxide substrate;

[0028] forming a gallium oxide epitaxial layer on the surface of the gallium oxide substrate;

[0029] forming a first dielectric layer on the surface of the gallium oxide epitaxial layer;

[0030] forming a p-type semiconductor layer on the surface of the gallium oxide epitaxial layer and on a portion of the surface of the first dielectric layer, wherein the portion of the p-type semiconductor layer located on the portion of the surface of the first dielectric layer is a first field plate;

[0031] forming a second dielectric layer on a surface of the first dielectric layer and on a portion of a surface of the first field plate;

[0032] forming a second electrode layer on the surface of the p-type semiconductor layer and on a portion of the surface of the second dielectric layer, wherein a portion of the second electrode layer located on the portion of the surface of the second dielectric layer is a second field plate;

[0033] A first electrode layer is formed on a side of the gallium oxide substrate away from the gallium oxide epitaxial layer to obtain the gallium oxide-based power device with a double-layer field plate.

[0034] Beneficial effects: The present invention introduces a double-layer field plate structure in the gallium oxide-based power device. By extending the p-type semiconductor layer to the surface of the first dielectric layer, a first field plate structure is formed to suppress the electric field concentration phenomenon at the edge of the interface between the p-type semiconductor layer and the gallium oxide epitaxial layer, and reduce the electric field peak. At the same time, the presence of the first dielectric layer can further even out the electric field distribution on the device surface. By extending the second electrode layer to the surface of the second dielectric layer to form a second field plate structure, the electric field concentration on the surface of the first dielectric layer and the gallium oxide epitaxial layer below the edge of the first field plate structure can be suppressed. Therefore, compared with the gallium oxide-based power device with a single-layer field plate structure, the gallium oxide-based power device with a double-layer field plate provided by the present invention has a higher breakdown electric field and better withstand voltage performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 Schematic diagram of the structure of a gallium oxide-based power device with a double-layer field plate in an embodiment of the present invention.

[0036] Figure 2 Schematic diagram of the preparation process of a gallium oxide-based power device with a double-layer field plate in an embodiment of the present invention, wherein (a) is a schematic diagram of forming a gallium oxide epitaxial layer on the surface of a gallium oxide substrate, (b) is a schematic diagram of forming a first dielectric layer precursor layer on the surface of the gallium oxide epitaxial layer, (c) is a schematic diagram of etching the first dielectric layer precursor layer to obtain the first dielectric layer, (d) is a schematic diagram of forming a p-type semiconductor layer on the surface of the gallium oxide epitaxial layer and on a portion of the surface of the first dielectric layer, (e) is a schematic diagram of forming a second dielectric layer on the surface of the first dielectric layer and on a portion of the surface of the first field plate, (f) is a schematic diagram of forming a second electrode layer on the surface of the p-type semiconductor layer and on a portion of the surface of the second dielectric layer, (g) is a schematic diagram of forming a passivation layer on the surface of the second dielectric layer and on a portion of the surface of the second electrode layer, and (h) is a schematic diagram of forming a first electrode layer on the side of the gallium oxide substrate away from the gallium oxide epitaxial layer.

[0037] Figure 3 Schematic diagram of the structure of a gallium oxide-based power device with a single-layer field plate structure terminal.

[0038] Figure 4It is a schematic diagram of the structure of a gallium oxide-based power device with a junction terminal extension structure terminal.

[0039] Figure 5 This is a comparison diagram of the surface electric field distribution of the drift region of the gallium oxide based power device with a double-layer field plate and a variable-k dielectric layer terminal structure, the gallium oxide based power device with a single-layer field plate structure terminal, and the gallium oxide based power device with a terminal extension structure terminal during breakdown in Example 1.

[0040] Reference numerals in the accompanying drawings:

[0041] 1. First electrode layer; 2. Gallium oxide substrate; 3. Gallium oxide epitaxial layer; 4. First dielectric layer; 4', first dielectric layer precursor layer; 5. P-type semiconductor layer; 51. First field plate; 52. Second part of the P-type semiconductor layer; 6. Second dielectric layer; 7. Second electrode layer; 71. Second field plate; 72. Second part of the second electrode layer; 8. Passivation layer. DETAILED DESCRIPTION

[0042] The present invention provides a gallium oxide-based power device with a double-layer field plate and a preparation method thereof. To make the purpose, technical solution and effect of the present invention clearer and more specific, the present invention is further described in detail below. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0043] Unless otherwise defined, all technical terms and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0044] The terms used herein such as “vertical”, “horizontal”, “upper”, “lower”, “left”, “right” and similar expressions are for illustrative purposes only and do not represent the only implementations.

[0045] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0046] If there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features.

[0047] An embodiment of the present invention provides a gallium oxide-based power device with a double-layer field plate, wherein: Figure 1 As shown, the gallium oxide-based power device with a double-layer field plate comprises a first electrode layer 1, a gallium oxide substrate 2, and a gallium oxide epitaxial layer 3 which are stacked in sequence from bottom to top;

[0048] The gallium oxide-based power device with a double-layer field plate further includes:

[0049] A first dielectric layer 4, located on the surface of the gallium oxide epitaxial layer 3;

[0050] A p-type semiconductor layer 5 is continuously disposed on the surface of the gallium oxide epitaxial layer 3 and a portion of the surface of the first dielectric layer 4, and a portion of the p-type semiconductor layer 5 disposed on the portion of the surface of the first dielectric layer 4 is a first field plate 51;

[0051] A second dielectric layer 6 is continuously disposed on the surface of the first dielectric layer 4 and on a portion of the surface of the first field plate 51;

[0052] The second electrode layer 7 is continuously located on the surface of the p-type semiconductor layer 5 and on a portion of the surface of the second dielectric layer 6 . The portion of the second electrode layer 7 located on the portion of the surface of the second dielectric layer 6 is the second field plate 71 .

[0053] The embodiment of the present invention introduces a double-layer field plate structure in the gallium oxide-based power device. By extending the p-type semiconductor layer to the surface of the first dielectric layer, a first field plate structure is formed to suppress the electric field concentration phenomenon at the interface edge of the p-type semiconductor layer and the gallium oxide epitaxial layer, and reduce the electric field peak. At the same time, the existence of the first dielectric layer can further even the electric field distribution on the device surface; by extending the second electrode layer to the surface of the second dielectric layer, a second field plate structure is formed, which can suppress the electric field concentration on the surface of the first dielectric layer and the gallium oxide epitaxial layer below the edge of the first field plate structure, thereby improving the breakdown electric field of the gallium oxide-based power device and improving the withstand voltage performance of the gallium oxide-based power device. Therefore, compared with the gallium oxide-based power device with a single-layer field plate structure, the gallium oxide-based power device with a double-layer field plate provided by the present invention has a higher breakdown electric field and better withstand voltage performance.

[0054] In the embodiment of the present invention, Figure 1As shown, the p-type semiconductor layer 5 is continuously located on the surface of the gallium oxide epitaxial layer 3 and on a portion of the surface of the first dielectric layer 4. That is, the p-type semiconductor layer 5 includes two parts, namely a first part and a second part, wherein the first part of the p-type semiconductor layer, namely the first field plate 51, is located on a portion of the surface of the first dielectric layer 4 (a portion of the surface in the present invention is not the entire surface), and the second part 52 of the p-type semiconductor layer is located on the surface of the gallium oxide epitaxial layer 3. Specifically, in the left-right direction, the second part 52 of the p-type semiconductor layer is connected to the first dielectric layer 4.

[0055] The second electrode layer 7 is continuously located on the surface of the p-type semiconductor layer 5 and on a portion of the surface of the second dielectric layer 6. That is, the second electrode layer 7 includes two parts, namely, a first part and a second part, the first part of the second electrode layer, namely, the second field plate 71, is located on a portion of the surface of the second dielectric layer 6, and the second part 72 of the second electrode layer is located on the surface of the p-type semiconductor layer 5. Specifically, in the left-right direction, the second part 72 of the second electrode layer is connected to the second dielectric layer 6.

[0056] In some embodiments, the relative dielectric constant of the first dielectric layer is greater than the relative dielectric constant of the gallium oxide epitaxial layer. The first dielectric layer has a higher relative dielectric constant than the gallium oxide epitaxial layer, which can further even out the electric field distribution on the device surface and improve the voltage resistance performance of the device.

[0057] In some embodiments, the breakdown electric field of the second dielectric layer is greater than the breakdown electric field of the first dielectric layer. The use of a second dielectric layer with a higher breakdown electric field than the first dielectric layer can alleviate the problem of premature breakdown of the dielectric layer in a conventional field plate structure, and can make the dielectric layer of the gallium oxide-based power device in the present invention less likely to be broken down prematurely, and the gallium oxide-based power device has better voltage resistance.

[0058] In the present invention, a double-layer field plate is introduced to further even out the electric field distribution in the device terminal region, and a variable-k dielectric layer (a first dielectric layer and a second dielectric layer) is introduced to relieve the high electric field stress in the dielectric layer, thereby achieving a higher breakdown voltage of the device.

[0059] In some embodiments, the thickness of the first dielectric layer is 100 nm to 1 μm (for example, 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm or 1 μm, etc. Figure 1 The thickness in the vertical direction shown in the figure is as follows, unless otherwise specified. Figure 1 The material of the first dielectric layer includes at least one of hafnium oxide, titanium oxide, zirconium oxide, strontium titanate and barium titanate, but is not limited thereto.

[0060] In some embodiments, the thickness of the second dielectric layer is 200 nm to 2 μm (i.e., the thickness of each part of the second dielectric layer is within this range), for example, it can be 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1 μm, 1.2 μm, 1.5 μm, 1.8 μm or 2 μm, etc.; the material of the second dielectric layer includes at least one of silicon oxide, silicon nitride and aluminum oxide, but is not limited thereto.

[0061] In some embodiments, the material of the first electrode layer includes at least one of Ti, Ni, Ag and Au, but is not limited thereto. In some specific embodiments, the first electrode layer is composed of a stacked Ti layer and an Au layer, or the first electrode layer is composed of a stacked Ti layer and an Ag layer, or the first electrode layer is composed of a stacked Ti layer, a Ni layer and an Ag layer.

[0062] In some embodiments, the thickness of the first electrode layer is 200 nm to 2 μm, for example, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1 μm, 1.2 μm, 1.5 μm, 1.8 μm or 2 μm.

[0063] In some embodiments, the material of the second electrode layer includes Ni, Mo, W, Pt, PtO x In some specific embodiments, the second electrode layer is composed of a stacked Ni layer and an Al layer, and further, the Ni layer can be replaced by a Mo layer, a W layer, a Pt layer or a PtO x layer, the Al layer can be replaced by an Au layer or an Ag layer.

[0064] In some embodiments, the thickness of the second electrode layer is 200 nm to 4 μm, for example, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1 μm, 1.2 μm, 1.5 μm, 1.8 μm, 2 μm, 2.2 μm, 2.5 μm, 2.8 μm, 3 μm, 3.2 μm, 3.5 μm, 3.8 μm or 4 μm, etc.

[0065] In some embodiments, the gallium oxide substrate has a thickness of 50 to 650 μm, for example, 50, 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, 550 μm, 600 μm or 650 μm.

[0066] In some embodiments, the gallium oxide substrate is a highly doped n-type gallium oxide substrate with a doping concentration (ie, electron concentration) of 10 18 ~10 20 cm -3 , the doping element is at least one of Sn and Si.

[0067] In some embodiments, the gallium oxide epitaxial layer has a thickness of 2 to 20 μm, for example, 2 μm, 3 μm, 5 μm, 8 μm, 10 μm, 12 μm, 15 μm, 18 μm or 20 μm.

[0068] In some embodiments, the gallium oxide epitaxial layer is a low-doped n-type gallium oxide epitaxial layer, and the doping concentration (ie, electron concentration) is 10 15 ~10 17 cm -3 , the doping element is at least one of Sn and Si. In some embodiments, the thickness of the p-type semiconductor layer is 100 to 600 nm (i.e., the thickness of the first part and the second part of the p-type semiconductor layer are both within the range, and the thickness of the first part and the second part of the p-type semiconductor layer can be the same or different), for example, it can be 100 nm, 200 nm, 300 nm, 400 nm, 500 nm or 600 nm. The doping concentration (i.e., hole concentration) of the p-type semiconductor layer is 10 16 ~10 19 cm -3 .

[0069] In some embodiments, the p-type semiconductor layer includes at least one of p-type NiO, p-type Cu2O, and p-type diamond.

[0070] In some embodiments, when the width of the p-type semiconductor layer is the same as the width of the first dielectric layer in a first direction on the horizontal plane, the width of the first field plate in a direction perpendicular to the first direction on the horizontal plane is greater than or equal to 2 μm. Figure 1 Taking the structure shown as an example, the horizontal plane is the plane where the front-to-back direction (the direction perpendicular to the paper surface) and the left-to-right direction are located. In the front-to-back direction, the width of the p-type semiconductor layer is the same as the width of the first dielectric layer. At this time, in the left-to-right direction perpendicular to the front-to-back direction, the width L1 of the first field plate 51 is greater than or equal to 2μm. In this way, the electric field concentration phenomenon at the interface edge of the p-type semiconductor layer and the gallium oxide epitaxial layer can be better suppressed.

[0071] In some embodiments, the projection of the second electrode layer on the gallium oxide epitaxial layer covers the projection of the p-type semiconductor layer on the gallium oxide epitaxial layer; or, the projection of the second electrode layer on the gallium oxide epitaxial layer coincides with the projection of the p-type semiconductor layer on the gallium oxide epitaxial layer. Figure 1 As shown, the rightmost end of the projection of the second electrode layer on the gallium oxide epitaxial layer covers the rightmost end of the projection of the p-type semiconductor layer on the gallium oxide epitaxial layer. In this way, the second field plate can better suppress the electric field concentration on the surface of the first dielectric layer and the gallium oxide epitaxial layer below the edge of the first field plate.

[0072] In some embodiments, Figure 1 As shown, the gallium oxide-based power device with a double-layer field plate further includes:

[0073] A passivation layer 8 is continuously disposed on the surface of the second dielectric layer 6 and on a portion of the surface of the second electrode layer 7. The passivation layer can be provided according to actual needs. In some embodiments, the material of the passivation layer includes at least one of polyimide (PI), silicon nitride, silicon oxide, and SU-8 glue.

[0074] The present invention also provides a method for preparing a gallium oxide-based power device having a double-layer field plate as described above in the present invention, wherein: Figure 2 As shown, the following steps are included:

[0075] S1, such as Figure 2 As shown in (a), a gallium oxide substrate 2 is provided;

[0076] S2, such as Figure 2 As shown in (a), a gallium oxide epitaxial layer 3 is formed on the surface of the gallium oxide substrate 2;

[0077] S3, such as Figure 2 As shown in (c), a first dielectric layer 4 is formed on the surface of the gallium oxide epitaxial layer 3;

[0078] S4, such as Figure 2 As shown in (d), a p-type semiconductor layer 5 is formed on the surface of the gallium oxide epitaxial layer 3 and on a portion of the surface of the first dielectric layer 4; the portion of the p-type semiconductor layer 5 located on the portion of the surface of the first dielectric layer 4 is a first field plate 51;

[0079] S5, such as Figure 2 As shown in (e), a second dielectric layer 6 is formed on the surface of the first dielectric layer 4 and on a portion of the surface of the first field plate 51;

[0080] S6, such as Figure 2As shown in (f), a second electrode layer 7 is formed on the surface of the p-type semiconductor layer 5 and on a portion of the surface of the second dielectric layer 6, and a portion of the second electrode layer 7 located on the portion of the surface of the second dielectric layer 6 is a second field plate 71;

[0081] S7, such as Figure 2 As shown in (g), a passivation layer 8 is formed on the surface of the second dielectric layer 6 and on a portion of the surface of the second electrode layer 7;

[0082] S8, such as Figure 2 As shown in (h), a first electrode layer 1 is formed on the side of the gallium oxide substrate 2 away from the gallium oxide epitaxial layer 3 to obtain the gallium oxide-based power device with a double-layer field plate.

[0083] In the present invention, in steps S1 and S2, a gallium oxide substrate having a gallium oxide epitaxial layer on its surface may be directly provided, and then inorganic and organic cleaning may be performed before the subsequent steps are performed.

[0084] In step S1, the selection of the gallium oxide substrate is specifically described above and will not be repeated here.

[0085] In step S2, the material, thickness, etc. of the gallium oxide epitaxial layer are as described above and will not be described again here.

[0086] In step S3, the material, thickness, etc. of the first dielectric layer are as described above and will not be described again here.

[0087] In some embodiments, the step of forming a first dielectric layer on the surface of the gallium oxide epitaxial layer specifically includes: Figure 2 As shown in (b), a first dielectric layer precursor layer 4' is formed on the surface of the gallium oxide epitaxial layer by a deposition method; wherein the deposition method includes but is not limited to one of a plasma enhanced chemical vapor deposition (PECVD) method, an atomic layer deposition (ALD) method, a low pressure chemical vapor deposition (LPCVD) method, an inductively coupled plasma chemical vapor deposition (ICPCVD) method and a magnetron sputtering method.

[0088] like Figure 2 As shown in (c), photolithography is performed on the surface of the first dielectric layer precursor layer 4', and then the first dielectric layer precursor layer 4' is patterned by dry-wet combined etching or wet etching to obtain the first dielectric layer 4.

[0089] In step S4 , the material and thickness of the p-type semiconductor layer are as described above and will not be described again here.

[0090] In some embodiments, a deposition method (including but not limited to magnetron sputtering deposition, pulsed laser deposition, metal organic chemical vapor deposition, metal thermal oxidation, etc.) may be used to form a p-type semiconductor layer precursor layer (see the case of the first dielectric precursor layer);

[0091] Then, the p-type semiconductor layer precursor layer is patterned by a stripping or etching method to obtain a p-type semiconductor layer.

[0092] For example, when the material of the p-type semiconductor layer is p-type NiO, a Ni metal thermal oxidation method may be used to prepare the p-type NiO precursor layer.

[0093] In step S5, the material and thickness of the second dielectric layer are as described above and will not be described again here.

[0094] The method for forming the second dielectric layer is similar to the method for forming the first dielectric layer.

[0095] In step S6, the material and thickness of the second electrode layer are as described above and will not be described again here.

[0096] Specifically, the deposition is performed by electron beam evaporation or magnetron sputtering, and the second electrode layer is formed by a lift-off process.

[0097] In step S7, the material of the passivation layer is as described above and will not be described again here.

[0098] Specifically, when the material of the passivation layer is PI, a standard PI photolithography process can be used to form the passivation layer.

[0099] In step S8, the material and thickness of the first electrode layer are as described above and will not be described again here.

[0100] The method for forming the first electrode layer is similar to the method for forming the second electrode layer.

[0101] The present invention will be further described below by means of specific examples.

[0102] Example 1

[0103] This embodiment provides a gallium oxide-based power device with a double-layer field plate and a variable-k dielectric layer terminal structure, such as Figure 1 As shown, it includes a first electrode layer 1, a gallium oxide substrate 2, and a gallium oxide epitaxial layer 3 stacked in sequence from bottom to top; wherein the first electrode layer includes a Ti layer (thickness of 100nm), a Ni layer (thickness of 300nm) and an Ag layer (thickness of 1μm) stacked in sequence, and the Ti layer side is attached to the gallium oxide substrate; the gallium oxide substrate is 500μm thick, and the gallium oxide substrate is a Sn-doped β-Ga2O3 substrate with an electron concentration of 10 20 cm -3The thickness of the gallium oxide epitaxial layer is 10 μm, and the gallium oxide epitaxial layer is a Si-doped β-Ga2O3 epitaxial layer (relative dielectric constant is 10), and the electron concentration is 10 16 cm -3 .

[0104] The gallium oxide-based power device further comprises:

[0105] The first dielectric layer 4 is located on the surface of the gallium oxide epitaxial layer 3; the material of the first dielectric layer is hafnium oxide (relative dielectric constant of 18.7, breakdown electric field of 5.4 MV / cm), and the thickness of the first dielectric layer is 100 nm;

[0106] The p-type semiconductor layer 5 is continuously located on the surface of the gallium oxide epitaxial layer 3 and on a part of the surface of the first dielectric layer 4. The part of the p-type semiconductor layer 5 located on the part of the surface of the first dielectric layer 4 is the first field plate 51. The thickness of the p-type semiconductor layer is 500nm (that is, the thickness of the second part 52 of the p-type semiconductor layer and the first field plate 51 are both 500nm; the thickness of the part where the second part 52 of the p-type semiconductor layer is connected to the first dielectric layer in the left and right directions is also 500nm). The p-type semiconductor layer is a p-type NiO layer with a hole concentration of 10 18 cm -3 ; The width L1 of the first field plate is 10 μm;

[0107] The second dielectric layer 6 is continuously located on the surface of the first dielectric layer 4 and on a portion of the surface of the first field plate 51; in the left-right direction, the first field plate is connected to a portion of the second dielectric layer located on the surface of the first dielectric layer, the thickness of the portion of the second dielectric layer located on the surface of the first dielectric layer is 700nm, the thickness of the portion of the second dielectric layer located on the partial surface of the first field plate is 350nm, and the material of the second dielectric layer is silicon nitride (the breakdown electric field is 11.6MV / cm).

[0108] The second electrode layer 7 is continuously located on the surface of the p-type semiconductor layer 5 and the partial surface of the second dielectric layer 6. The portion of the second electrode layer 7 located on the partial surface of the second dielectric layer 6 is the second field plate 71. The material of the second electrode layer is a stacked Ni layer and an Al layer. The Ni layer is attached to the surface of the p-type semiconductor layer 5 and the partial surface of the second dielectric layer 6. The maximum thickness of the second electrode layer is 3.2 μm, wherein the thickness of the Ni layer is 200 nm, and the thickness of the Al layer is 3 μm. The rightmost end of the projection of the second electrode layer on the gallium oxide epitaxial layer covers the rightmost end of the projection of the p-type semiconductor layer on the gallium oxide epitaxial layer.

[0109] The passivation layer 8 is located on the surface of the second dielectric layer 6 and part of the surface of the second electrode layer 7; the material of the passivation layer is PI, and the maximum thickness of the passivation layer is 10 μm.

[0110] In gallium oxide-based power devices, the junction terminal extension structure is mainly realized using p-type nickel oxide (p-NiO) materials. By extending part of the p-NiO area beyond the electrode coverage area, when the device withstands voltage, holes are provided through this extended area to assist the expansion of the device depletion layer, suppress the electric field concentration phenomenon in the terminal area, and increase the breakdown voltage of the device, but its electric field balancing effect is limited. In addition, the effect of the uniform electric field of gallium oxide-based power devices with a single-layer field plate structure is also limited (see the introduction in the background technology).

[0111] Therefore, the gallium oxide-based power device with a double-layer field plate and a variable-k dielectric layer terminal structure in Example 1 and the gallium oxide-based power device with a single-layer field plate structure terminal (its structure is as follows Figure 3 As shown, it includes a first electrode layer 1, a gallium oxide substrate 2, a gallium oxide epitaxial layer 3 and a first dielectric layer 4 stacked in sequence from bottom to top, and also includes a second electrode layer 7 located on the surface of the gallium oxide epitaxial layer 3 and a part of the surface of the first dielectric layer 4, a passivation layer 8 located on the surface of the first dielectric layer 4 and the second electrode layer 7, the part of the second electrode layer located on the part of the surface of the first dielectric layer is a field plate, and the materials of each layer are the same as those in Example 1), a gallium oxide-based power device with a junction terminal extension structure terminal (its structure is as shown in Figure 4 As shown in the figure, it includes a first electrode layer 1, a gallium oxide substrate 2, and a gallium oxide epitaxial layer 3 stacked in sequence from bottom to top, and also includes a p-type semiconductor layer 5 located on the gallium oxide epitaxial layer 3, a second electrode layer 7 located on the gallium oxide epitaxial layer 3 and a portion of the surface of the p-type semiconductor layer 5, and a passivation layer 8 located on a portion of the surface of the gallium oxide epitaxial layer 3, the p-type semiconductor layer 5, and the second electrode layer 7. The materials of each layer are the same as those in Example 1. The surface electric field distribution of the drift region during breakdown is tested. The comparison diagram of the surface electric field distribution of the drift region of each device during breakdown is shown in FIG. Figure 5 As shown, it can be seen that the electric field distribution of the single-layer field plate structure terminal and the junction terminal extension structure terminal is uneven, resulting in a lower withstand voltage of the device. The terminal structure in Example 1 can achieve a more uniform electric field distribution, thereby achieving a higher breakdown voltage.

[0112] It should be understood that the application of the present invention is not limited to the above examples. For ordinary technicians in this field, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to the present invention.

Claims

1. A gallium oxide-based power device with a double-layer field plate, characterized in that: The gallium oxide-based power device with a double-layer field plate comprises a first electrode layer, a gallium oxide substrate and a gallium oxide epitaxial layer stacked in sequence from bottom to top; The gallium oxide-based power device with a double-layer field plate further includes: A first dielectric layer, located on the surface of the gallium oxide epitaxial layer; A p-type semiconductor layer is continuously located on the surface of the gallium oxide epitaxial layer and on a portion of the surface of the first dielectric layer, and a portion of the p-type semiconductor layer located on the portion of the surface of the first dielectric layer is a first field plate; A second dielectric layer, continuously disposed on the surface of the first dielectric layer and on a portion of the surface of the first field plate; The second electrode layer is continuously located on the surface of the p-type semiconductor layer and on a portion of the surface of the second dielectric layer. The portion of the second electrode layer located on the portion of the surface of the second dielectric layer is the second field plate.

2. The gallium oxide-based power device with a double-layer field plate according to claim 1, characterized in that: The relative dielectric constant of the first dielectric layer is greater than the relative dielectric constant of the gallium oxide epitaxial layer.

3. The gallium oxide-based power device with a double-layer field plate according to claim 1 or 2, characterized in that: The breakdown electric field of the second dielectric layer is greater than the breakdown electric field of the first dielectric layer.

4. The gallium oxide-based power device with a double-layer field plate according to claim 3, characterized in that: The thickness of the first dielectric layer is 100 nm to 1 μm; the material of the first dielectric layer includes at least one of hafnium oxide, titanium oxide, zirconium oxide, strontium titanate and barium titanate; The thickness of the second dielectric layer is 200 nm to 2 μm; the material of the second dielectric layer includes at least one of silicon oxide, silicon nitride and aluminum oxide.

5. The gallium oxide-based power device with a double-layer field plate according to claim 1, characterized in that: The material of the first electrode layer includes at least one of Ti, Ni, Ag and Au; The material of the second electrode layer includes Ni, Mo, W, Pt, PtO x , Al, Au and Ag.

6. The gallium oxide-based power device with a double-layer field plate according to claim 1, characterized in that: The gallium oxide substrate has a thickness of 50 to 650 μm; The gallium oxide substrate is a highly doped n-type gallium oxide substrate with a doping concentration of 10 18 ~10 20 cm -3 ; The thickness of the gallium oxide epitaxial layer is 2 to 20 μm; The gallium oxide epitaxial layer is a low-doped n-type gallium oxide epitaxial layer with a doping concentration of 10 15 ~10 17 cm -3 .

7. The gallium oxide-based power device with a double-layer field plate according to claim 1, characterized in that: The thickness of the p-type semiconductor layer is 100-600 nm; the p-type semiconductor layer includes at least one of p-type NiO, p-type Cu2O and p-type diamond; The gallium oxide-based power device with a double-layer field plate further includes: A passivation layer is continuously located on the surface of the second dielectric layer and on a portion of the surface of the second electrode layer.

8. The gallium oxide-based power device with a double-layer field plate according to claim 1, characterized in that: When the width of the p-type semiconductor layer is the same as the width of the first dielectric layer in a first direction on the horizontal plane, the width of the first field plate in a direction perpendicular to the first direction on the horizontal plane is greater than or equal to 2 μm.

9. The gallium oxide-based power device with a double-layer field plate according to claim 1, characterized in that: The projection of the second electrode layer on the gallium oxide epitaxial layer covers the projection of the p-type semiconductor layer on the gallium oxide epitaxial layer; or, the projection of the second electrode layer on the gallium oxide epitaxial layer coincides with the projection of the p-type semiconductor layer on the gallium oxide epitaxial layer.

10. A method for preparing a gallium oxide-based power device with a double-layer field plate according to claim 1, characterized in that: The steps include: providing a gallium oxide substrate; forming a gallium oxide epitaxial layer on the surface of the gallium oxide substrate; forming a first dielectric layer on the surface of the gallium oxide epitaxial layer; forming a p-type semiconductor layer on the surface of the gallium oxide epitaxial layer and on a portion of the surface of the first dielectric layer, wherein the portion of the p-type semiconductor layer located on the portion of the surface of the first dielectric layer is a first field plate; forming a second dielectric layer on a surface of the first dielectric layer and on a portion of a surface of the first field plate; forming a second electrode layer on the surface of the p-type semiconductor layer and on a portion of the surface of the second dielectric layer, wherein a portion of the second electrode layer located on the portion of the surface of the second dielectric layer is a second field plate; A first electrode layer is formed on a side of the gallium oxide substrate away from the gallium oxide epitaxial layer to obtain the gallium oxide-based power device with a double-layer field plate.

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