Semiconductor structure, forming method thereof and memory system

Abstract

The invention provides a semiconductor structure, a forming method thereof and a memory system. The semiconductor structure comprises an active layer, an electrostatic protection structure and a bonding pad located on the active layer. The electrostatic protection structure comprises at least one transistor structure, the transistor structure comprises a gate structure, a first electrode region, a channel region and a second electrode region, the first electrode region, the channel region and the second electrode region are located in the active layer and arranged in the first direction, and the gate structure is located on the channel region; the first direction is perpendicular to the second direction; the second direction is the thickness direction of the active layer; and the bonding pad is connected with the first electrode region or the second electrode region of the transistor structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same, and a memory system. Background Art

[0002] With the continuous development of semiconductor chip manufacturing technology, the integration of circuits has been continuously improved, and the voltage resistance of electronic components has been reduced. The harm of electrostatic discharge (ESD) to chips has become more and more significant. Therefore, it is necessary to protect the chip from electrostatic discharge. The commonly used method is to set an electrostatic protection circuit in the chip.

[0003] However, as the requirements for the integration of semiconductor chips continue to increase, how to set up an electrostatic protection circuit to improve the damage of electrostatic discharge to semiconductor chips has become an urgent problem to be solved. Summary of the invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, and a memory system to solve at least one problem existing in the prior art.

[0005] To achieve the above objectives, the technical solution of the embodiment of the present disclosure is implemented as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides a semiconductor structure, comprising an active layer, an electrostatic protection structure, and a pad located on the active layer; wherein:

[0007] The electrostatic protection structure includes at least one transistor structure, the transistor structure includes a gate structure and a first electrode region, a channel region, and a second electrode region located in the active layer and arranged along a first direction, the gate structure is located on the channel region; the first direction is perpendicular to a second direction; the second direction is a thickness direction of the active layer;

[0008] The pad is connected to the first electrode region or the second electrode region of the transistor structure.

[0009] In an optional implementation, the semiconductor structure further includes:

[0010] A power line and a ground line are located on the active layer, and the power line and the ground line are respectively located on two opposite sides of the pad along the first direction.

[0011] In an optional implementation, the electrostatic protection structure includes one of the transistor structures;

[0012] The transistor structure is located between the power line and the pad, the first electrode region and the gate structure of the transistor structure are connected to the power line, and the second electrode region of the transistor structure is connected to the pad;

[0013] or,

[0014] The transistor structure is located between the pad and the ground line, the first electrode region and the gate structure of the transistor structure are connected to the pad, and the second electrode region of the transistor structure is connected to the ground line.

[0015] In an optional implementation, the electrostatic protection structure includes a plurality of transistor structures, which are connected in series and arranged along the first direction; the electrostatic protection structure includes a first end and a second end opposite to each other along the first direction, the first end is close to the power line, and the second end is close to the ground line;

[0016] The electrostatic protection structure is located between the power line and the ground line; the first electrode region and the gate structure of the transistor structure located at the first end are connected to the power line; the second electrode region of the transistor structure located at the second end is connected to the ground line; the pad is connected to the first electrode region and the gate structure of the transistor structure close to the ground line among the two transistor structures closest to the pad in the electrostatic protection structure, and is connected to the second electrode region of the other transistor structure;

[0017] or,

[0018] The electrostatic protection structure is located between the pad and the ground line; the first electrode region and the gate structure of the transistor structure located at the first end are connected to the pad; the second electrode region of the transistor structure located at the second end is connected to the ground line;

[0019] or,

[0020] The electrostatic protection structure is located between the power line and the pad; the first electrode region and the gate structure of the transistor structure located at the first end are connected to the power line; and the second electrode region of the transistor structure located at the second end is connected to the pad.

[0021] In an optional implementation, the first electrode region of the transistor structure is shared with the second electrode region of the transistor structure closer to the power line among the two transistor structures adjacent to the transistor structure;

[0022] The second electrode region of the transistor structure is shared with a first electrode region of a transistor structure closer to the ground line among two transistor structures adjacent to the transistor structure.

[0023] In an optional implementation, the semiconductor structure further includes:

[0024] A conductive line located on the active layer; the conductive line is located between the pad and the power line and / or between the pad and the ground line in the first direction; the conductive line is connected to a first electrode region and a gate structure of a transistor structure.

[0025] In an optional implementation, the gate structure includes a gate layer and a dielectric layer, and the semiconductor structure further includes:

[0026] The isolation layer is located on the active layer; the dielectric layer is located between the isolation layer and the active layer, and the gate layer is located in the isolation layer; the pad, the power line and the ground line are all located on the isolation layer.

[0027] In an optional implementation, the semiconductor structure further includes:

[0028] A plurality of first contact structures penetrating the dielectric layer and the isolation layer along the second direction; one end of the first contact structure along the second direction is connected to the first electrode area or the second electrode area, and the other end of the first contact structure along the second direction is connected to one of the pad, the power line and the ground line.

[0029] In an optional implementation, the semiconductor structure includes a plurality of active layers, each of the active layers extending along the first direction;

[0030] The pad is located on the multiple active layers; each of the active layers has at least one transistor structure.

[0031] In an optional implementation, the semiconductor structure further includes:

[0032] A stacked structure located on one side of the active layer that is away from the pad, on two sides that are opposite to each other along the second direction;

[0033] A plurality of channel structures extending along the second direction and penetrating the stacked structure; the channel structures are connected to the active layer.

[0034] In an optional implementation, the semiconductor structure further includes:

[0035] The peripheral circuit portion is located on one side of the stack structure that is away from the pad, of two sides that are opposite to each other along the second direction.

[0036] In a second aspect, an embodiment of the present disclosure provides a memory system, including:

[0037] At least one semiconductor structure according to any of the preceding embodiments;

[0038] The controller is coupled to the semiconductor structure and configured to control the semiconductor structure.

[0039] In a third aspect, an embodiment of the present disclosure provides a method for forming a semiconductor structure, comprising:

[0040] providing an active layer;

[0041] A solder pad is formed on the active layer, and an electrostatic protection structure is formed; the electrostatic protection structure includes at least one transistor structure, the transistor structure includes a gate structure and a first electrode region, a channel region, and a second electrode region located in the active layer and arranged along a first direction, and the gate structure is located on the channel region; the solder pad is connected to the first electrode region or the second electrode region of the transistor structure; the first direction is perpendicular to the second direction; and the second direction is the thickness direction of the active layer.

[0042] In an optional implementation, the method for forming the semiconductor structure further includes:

[0043] A power line and a ground line are formed on the active layer; the power line and the ground line are respectively located on two opposite sides of the pad along the first direction.

[0044] In an optional implementation, the method for forming the semiconductor structure further includes:

[0045] Conductive lines are formed on the active layer; the conductive lines are located between the pad and the power line and / or between the pad and the ground line in the first direction; each of the conductive lines is connected to a first electrode region and a gate structure of the transistor structure.

[0046] In an optional embodiment, the forming of the electrostatic protection structure includes:

[0047] forming a dielectric layer and an isolation layer on the active layer; the dielectric layer is located between the isolation layer and the active layer;

[0048] A gate layer is formed in the isolation layer; the gate layer and the dielectric layer constitute the gate structure.

[0049] In an optional implementation, the method for forming the semiconductor structure further includes:

[0050] forming a plurality of first contact structures penetrating the dielectric layer and the isolation layer along the second direction; one end of the first contact structure along the second direction is connected to the first electrode region or the second electrode region;

[0051] The step of forming a pad, a power line and a ground line on the active layer comprises:

[0052] The pad, the power line and the ground line are formed on the isolation layer; the other end of the two ends of the first contact structure along the second direction is connected to one of the pad, the power line and the ground line.

[0053] In an optional implementation, the method for forming the semiconductor structure further includes:

[0054] forming a stacking structure stacked along the second direction;

[0055] forming a plurality of channel structures penetrating the stacked structure along the second direction;

[0056] The active layer is formed on one of two opposite sides of the stack structure along the second direction; the active layer is connected to the channel structure.

[0057] In an optional implementation, the method for forming the semiconductor structure further includes:

[0058] A peripheral circuit portion is formed on the other side of the stack structure that is opposite to each other along the second direction.

[0059] In the technical solution provided in the present disclosure, an electrostatic protection structure connected to a pad is provided in a semiconductor structure including an active layer, the electrostatic protection structure includes at least one transistor structure, a first electrode region, a channel region, and a second electrode region of the transistor structure are all provided in the active layer, and a gate structure of the transistor structure is provided on the active layer, and two ends of the electrostatic protection structure are respectively connected to a power line and a ground line, thereby, static electricity generated on the pad can be discharged to a power end or a ground end through the electrostatic protection structure without entering the interior of the semiconductor structure, thereby alleviating the damage caused by high-voltage static electricity to a storage array structure and other circuit structures, and effectively improving the reliability and yield of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Figure 1 A top view of a semiconductor structure provided in an embodiment of the present disclosure Figure 1 ;

[0061] Figure 2 A cross section of a semiconductor structure provided by an embodiment of the present disclosure Figure 1 ;

[0062] Figure 3 A schematic diagram of a circuit structure provided in an embodiment of the present disclosure;

[0063] Figure 4 A cross section of a semiconductor structure provided by an embodiment of the present disclosure Figure 2 ;

[0064] Figure 5 A cross section of a semiconductor structure provided by an embodiment of the present disclosure Figure 3 ;

[0065] Figure 6 A cross section of a semiconductor structure provided by an embodiment of the present disclosure Figure 4 ;

[0066] Figure 7 A cross section of a semiconductor structure provided by an embodiment of the present disclosure Figure 5 ;

[0067] Figure 8 A top view of a semiconductor structure provided in an embodiment of the present disclosure Figure 2 ;

[0068] Fig. 9 A cross section of a semiconductor structure provided by an embodiment of the present disclosure Figure 6 ;

[0069] Fig.10 A schematic diagram of a memory system provided by an embodiment of the present disclosure;

[0070] Fig.11 A schematic diagram of a process for forming a semiconductor structure provided by an embodiment of the present disclosure;

[0071] Fig.12 A schematic diagram of a semiconductor structure forming process according to an embodiment of the present disclosure Figure 1 ;

[0072] Fig.13 A schematic diagram of a semiconductor structure forming process according to an embodiment of the present disclosure Figure 2 ;

[0073] Fig.14 A schematic diagram of a semiconductor structure forming process according to an embodiment of the present disclosure Figure 3 . DETAILED DESCRIPTION

[0074] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0075] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0076] In the drawings, like reference numerals refer to like elements throughout.

[0077] It should be understood that spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial description terms used herein are interpreted accordingly.

[0078] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0079] With the continuous development of semiconductor chip manufacturing technology, the integration of circuits has been continuously improved, and the voltage resistance of electronic components has been reduced. The harm of electrostatic discharge to chips has become more and more significant. Therefore, it is necessary to protect the chip from electrostatic discharge. The commonly used method is to set an electrostatic protection circuit in the chip.

[0080] In some embodiments, for a three-dimensional memory including a peripheral circuit and a memory array structure arranged in a vertical direction, an electrostatic protection circuit is usually provided in the peripheral circuit. However, in the three-dimensional memory, a lead pad is provided on the side of the memory array structure away from the peripheral circuit. When the three-dimensional memory is electrically tested, a probe needs to be used to contact the lead pad to apply an electrical signal to the three-dimensional memory. When the needle tip of the probe contacts the lead pad, electrostatic discharge is easily induced. Since the distance between the probe tip and the electrostatic protection circuit in the peripheral circuit is far, the static electricity cannot be discharged in time, and thus may enter the interior of the three-dimensional memory and damage the memory array structure and other circuit structures, and may even cause the product to be scrapped, thereby reducing production efficiency and product yield.

[0081] Therefore, it is necessary to further optimize the electrostatic protection architecture in the three-dimensional memory. To this end, the present disclosure proposes the following implementation methods.

[0082] The present disclosure provides a semiconductor structure, including an active layer, an electrostatic protection structure, and a pad located on the active layer; wherein the electrostatic protection structure includes at least one transistor structure, the transistor structure includes a gate structure and a first electrode region, a channel region, and a second electrode region located in the active layer and arranged along a first direction, and the gate structure is located on the channel region; the pad is connected to the first electrode region or the second electrode region of the transistor structure; the first direction is perpendicular to the second direction, and the second direction is the thickness direction of the active layer.

[0083] In the embodiment of the present disclosure, the active layer in the semiconductor structure is used as the setting area of ​​the channel region and the electrode region of the transistor structure, and the gate structure of the transistor structure is set on the active layer to form an electrostatic protection structure including at least one transistor structure. The electrostatic protection structure is connected to the pad, so that the static electricity generated at the pad can be discharged, reducing the risk of static electricity generated at the pad entering the interior of the semiconductor structure and causing damage to the storage array structure and other circuit structures, thereby effectively improving the reliability and yield of the semiconductor structure.

[0084] Figure 1 A top view of a semiconductor structure provided by an embodiment of the present disclosure, Figure 2 for Figure 1 Cross-section along line AA', combined with reference Figure 1 and Figure 2The semiconductor structure includes an active layer 101, an electrostatic protection structure 100, and a pad 301 located on the active layer 101; wherein the electrostatic protection structure 100 includes a plurality of transistor structures 200, the transistor structure 200 includes a gate structure 201 and a first electrode region 102, a channel region 103, and a second electrode region 104 located in the active layer 101 and arranged along a first direction, and the gate structure 201 is located on the channel region 103; the pad 301 is connected to the first electrode region 102 or the second electrode region 104 of the transistor structure 200.

[0085] In the embodiment of the present disclosure, the first direction is perpendicular to the second direction, and the second direction is the thickness direction of the active layer 101. Here, the first direction is the X direction, and the second direction is the Z direction.

[0086] In some embodiments, the semiconductor structure further includes: a power line 302 and a ground line 303 located on the active layer 101 , and the power line 302 and the ground line 303 are respectively located on two opposite sides of the pad 301 along the first direction.

[0087] In the embodiment of the present disclosure, the power line 302 is a conductive line coupled to the power end, which can provide a power voltage VCC for the circuit structure connected thereto; the ground line 303 is a conductive line coupled to the ground end, which can provide a ground voltage VSS for the circuit structure connected thereto.

[0088] In a specific example, if Figure 1 As shown, the power line 302 and the ground line 303 both extend along a third direction, where the third direction is the Y direction.

[0089] In the embodiment of the present disclosure, the electrostatic protection structure 100 is composed of a plurality of transistor structures 200, and the plurality of transistor structures 200 are connected in series and arranged along a first direction. The first electrode region 102, the channel region 103, and the second electrode region 104 of the transistor structure 200 are located in the active layer 101, and two adjacent transistor structures 200 share one electrode region. Specifically, the first electrode region 102 of the transistor structure 200 is shared with the second electrode region 104 of the transistor structure 200 that is closer to the power line 302 of the two transistor structures 200 adjacent to the transistor structure 200; the second electrode region 104 of the transistor structure 200 is shared with the first electrode region 102 of the transistor structure 200 that is closer to the ground line 303 of the two transistor structures 200 adjacent to the transistor structure 200. Figure 2 As shown, a transistor structure 200 includes two electrode regions, the electrode region closer to the power line 302 of the two electrode regions is the first electrode region 102 of the transistor structure 200 , and the electrode region closer to the ground line 303 is the second electrode region 104 of the transistor structure 200 .

[0090] In some specific examples, the material of the active layer 101 can be a heavily doped semiconductor material, for example, N-type doped polysilicon. Therefore, the active layer 101 can be used as a high-voltage N-well of the transistor structure 200. The active layer 101 is doped with P-type to form a first electrode region 102 and a second electrode region 104 in the active layer 101.

[0091] It should be noted that, in the embodiment of the present disclosure, the first electrode region 102 is a source region, and the second electrode region 104 is a drain region.

[0092] In the embodiments of the present disclosure, refer to Figure 2 The gate structure 201 of the transistor structure 200 includes a gate layer 202 and a dielectric layer 203 located on the active layer 101, the dielectric layer 203 is located between the active layer 101 and the gate layer 202, one gate structure 201 and two electrode regions located in the active layer 101 constitute one transistor structure 200, and the active layer 101 located between the first electrode region 102 and the second electrode region 104 and directly below the gate structure 201 constitutes the channel region 103 of the transistor structure 200. Here, the electrostatic protection structure 100 includes 6 transistor structures 200 connected in series and arranged along the first direction as an example.

[0093] In some embodiments, the semiconductor structure further includes: an isolation layer 204 located on the active layer 101 , a dielectric layer 203 located between the isolation layer 204 and the active layer 101 , a gate layer 202 located in the isolation layer 204 , and a pad 301 , a power line 302 and a ground line 303 all located on the isolation layer 204 .

[0094] In some embodiments, the semiconductor structure also includes: a plurality of first contact structures 205 penetrating the dielectric layer 203 and the isolation layer 204 along the second direction, one end of the first contact structure 205 along the second direction is connected to the first electrode region 102 or the second electrode region 104, and the other end of the first contact structure 205 along the second direction is connected to one of the pad 301, the power line 302 and the ground line 303.

[0095] In some embodiments, the semiconductor structure also includes: multiple second contact structures (not shown in the figure) penetrating the dielectric layer 203 and the isolation layer 204 along the second direction, and the two ends of the second contact structures along the second direction are respectively connected to the pad 301 and the active layer 101 to achieve the lead-out of the active layer 101.

[0096] In some specific examples, the material of the gate layer 202 can be at least one of a doped semiconductor material (e.g., doped silicon, doped germanium, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a metal material (e.g., tungsten, titanium, tantalum, etc.), and a metal semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.); the material of the dielectric layer 203 can be at least one of silicon oxide, hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium oxide, barium titanium oxide, or strontium tantalum oxide. At least one of the materials selected from the group consisting of strontium titanium, lithium oxide, aluminum oxide, lead scandium tantalum oxide and lead zinc niobate; the material of the isolation layer 204 may be at least one of the materials selected from the group consisting of silicon nitride, silicon oxide, silicon oxynitride and the like; the material of the first contact structure 205 may be at least one of the materials selected from the group consisting of doped semiconductor materials (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metal materials (e.g., tungsten, titanium, tantalum, etc.) and metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0097] In a specific example, the material of the gate layer 202 is titanium nitride, the material of the dielectric layer 203 is silicon oxide, the material of the isolation layer 204 is silicon nitride, and the material of the first contact structure 205 is tungsten.

[0098] In the embodiment of the present disclosure, the electrostatic protection structure 100 is located between the power line 302 and the ground line 303, and the electrostatic protection structure 100 includes a first end and a second end opposite to each other along a first direction, wherein the first electrode region 102 and the gate structure 201 of the transistor structure 200 located at the first end are connected to the power line 302, the second electrode region 104 of the transistor structure 200 located at the second end is connected to the ground line 303, the pad 301 is connected to the first electrode region 102 and the gate structure 201 of the transistor structure 200 close to the ground line 303 among the two transistor structures 200 closest to the pad 301 in the electrostatic protection structure 100, and the second electrode region 104 of the other transistor structure 200 is connected. Here, the two transistor structures 200 closest to the pad 301 share one electrode region, so the electrode regions connected to the pad 301 are the first electrode region 102 of one transistor structure 200 and the second electrode region 104 of the other transistor structure 200.

[0099] In some embodiments, the semiconductor structure also includes a conductive wire 304 located on the active layer 101 , the conductive wire 304 is located between the pad 301 and the power line 302 or between the pad 301 and the ground line 303 in the first direction, and the conductive wire 304 is connected to the first electrode region 102 and the gate structure 201 of a transistor structure 200 .

[0100] In the embodiment of the present disclosure, the first electrode region 102 of the transistor structure 200 is electrically connected to the gate structure 201. Figure 2 As shown, for the transistor structure 200 located at the first end of the electrostatic protection structure 100, its first electrode region 102 and the gate structure 201 are electrically connected through the power line 302 and the first contact structure 205. For the transistor structure 200 close to the ground line 303 among the two transistor structures 200 closest to the pad 301, its first electrode region 102 and the gate structure 201 are electrically connected through the pad 301 and the first contact structure 205. For the other transistor structures 200 in the electrostatic protection structure 100, their first electrode regions 102 and the gate structure 201 are electrically connected through the conductive line 304 and the first contact structure 205.

[0101] In some specific examples, the pad 301, the power line 302, the ground line 303 and the conductive line 304 have the same size in the second direction, and the materials of the pad 301, the power line 302, the ground line 303 and the conductive line 304 may also be the same, and may be at least one of metal materials such as tungsten, copper, nickel, aluminum, silver, gold, titanium, etc.

[0102] In some embodiments, Figure 3 is a schematic diagram of an electrostatic protection circuit corresponding to the semiconductor structure in the above embodiment, such as Figure 3 As shown, the electrostatic protection circuit includes a plurality of PMOS transistors connected in series and coupled between a power supply terminal and a ground terminal, and one PMOS transistor corresponds to one transistor structure 200 in the above embodiment. The current I represents the current flowing from the pad 301 to the inside of the semiconductor structure. The electrostatic protection circuit can be divided into area A and area B with the coupling point of the current I and the electrostatic protection circuit as the dividing point. The coupling point of the current I and the electrostatic protection circuit corresponds to the connection point between the pad 301 and the electrostatic protection structure 100 in the above embodiment.

[0103] In some specific examples, when static electricity is generated on the pad 301, a high voltage is generated in the direction of the current I. When the high voltage is a positive voltage V1 and the difference between the power supply voltage VCC and V1 is less than the sum of the threshold voltages VA of the multiple PMOS transistors in region A, that is, VCC - V1 < VA, the multiple PMOS transistors in region A are turned on, and the static charge can be discharged to the power supply terminal through the circuit in region A. At this time, the multiple PMOS transistors in region B remain in the off state; when the high voltage is a negative voltage V2 and the difference between V2 and the ground voltage VSS is less than the sum of the threshold voltages VB of the multiple PMOS transistors in region B, that is, V2 - VSS < VB, the multiple PMOS transistors in region B are turned on, and the static charge can be discharged to the ground terminal through the circuit in region B. At this time, the multiple PMOS transistors in region A remain in the off state. That is to say, when the magnitude of the voltage V in the direction of the current I satisfies VSS + VB ≤ V ≤ VCC - VA, the electrostatic protection circuit is not triggered. When static electricity is generated on the pad 301, causing the voltage in the direction of the current I to exceed this voltage range, the electrostatic protection circuit will be triggered and the static charge will be discharged to the power supply terminal or the ground terminal to reduce the risk that high voltage enters the interior of the semiconductor structure and causes the internal circuit structure of the semiconductor structure to fail due to high voltage.

[0104] In the embodiments of the present disclosure, the sum of the threshold voltages VA or VB can be changed by changing the number of transistor structures 200 in the electrostatic protection structure 100 or the threshold voltage of a single transistor structure 200, so that the voltage range for triggering the electrostatic protection circuit can be changed. For example, for Figure 1 and Figure 2 the semiconductor structure shown, without changing the threshold voltage of a single transistor structure 200, the voltage range for triggering the electrostatic protection circuit can be changed by increasing or decreasing the number of transistor structures 200, or, without changing the number of transistor structures 200, the voltage range for triggering the electrostatic protection circuit can be changed by changing the thickness of the dielectric layer 203 or the aspect ratio of the channel region 103 in the transistor structure 200. It can be understood that for multiple series-connected transistor structures 200, the more the number of transistor structures 200, the greater the sum of the threshold voltages of the multiple transistor structures 200. For a single transistor structure 200, the thicker its dielectric layer 203 or the smaller the aspect ratio of the channel region 103, the greater its threshold voltage. Here, the aspect ratio of the channel region 103 refers to the ratio of the dimension of the channel region in the Y direction to the dimension of the channel region in the X direction.

[0105] The above embodiments take the electrostatic protection structure 100 including multiple transistor structures 200 located between the power supply line 302 and the ground line 303 as an example. In other embodiments, in order to control the production cost and the area occupied by the electrostatic protection structure 100, the electrostatic protection structure 100 may also include only one transistor structure 200.

[0106] In a specific example, referring to Figure 4 The electrostatic protection structure 100 includes a transistor structure 200 located between a power line 302 and a pad 301 . The first electrode region 102 and the gate structure 201 of the transistor structure 200 are connected to the power line 302 . The second electrode region 104 of the transistor structure 200 is connected to the pad 301 .

[0107] In another specific example, referring to Figure 5 The electrostatic protection structure 100 includes a transistor structure 200 located between a ground line 303 and a pad 301 , a first electrode region 102 and a gate structure 201 of the transistor structure 200 are connected to the pad 301 , and a second electrode region 104 of the transistor structure 200 is connected to the ground line 303 .

[0108] It should be noted that in Figure 4 and Figure 5 In the figure, the transistor structure 200 constitutes the electrostatic protection structure 100, and the marking of the electrostatic protection structure 100 is omitted in the figure.

[0109] In some other embodiments, the electrostatic protection structure 100 includes a plurality of transistor structures 200 located between the pad 301 and the power line 302 , or includes a plurality of transistor structures 200 located between the pad 301 and the ground line 303 .

[0110] In a specific example, referring to Figure 6 The electrostatic protection structure 100 is located between the power line 302 and the pad 301; the first electrode region 102 and the gate structure 201 of the transistor structure 200 at the first end are connected to the power line 302; the second electrode region 104 of the transistor structure 200 at the second end is connected to the pad 301.

[0111] In another specific example, referring to Figure 7 The electrostatic protection structure 100 is located between the pad 301 and the ground line 303; the first electrode region 102 and the gate structure 201 of the transistor structure 200 at the first end are connected to the pad 301; the second electrode region 104 of the transistor structure 200 at the second end is connected to the ground line 303.

[0112] It should be noted that Figures 4 to 7 The semiconductor structure shown can function as Figure 1 and Figure 2 The semiconductor structure shown has similar functions and will not be described in detail here.

[0113] In some embodiments, one pad 301 may be connected to a plurality of active layers 101 , and an electrostatic protection structure 100 is disposed on each active layer 101 .

[0114] In a specific example, referring to Figure 8 The pad 301 is connected to the three active layers 101, and at least one transistor structure 200 is disposed on each active layer 101. Thus, the static electricity generated on the pad 301 can be discharged through the multiple electrostatic protection structures 100, thereby increasing the reliability of electrostatic protection.

[0115] In some embodiments, the semiconductor structure further includes: a stacked structure located on one side of the active layer 101 opposite to each other along the second direction and away from the pad 301; and a plurality of channel structures extending along the second direction and penetrating the stacked structure, and the channel structures are connected to the active layer.

[0116] In some embodiments, the semiconductor structure further includes: a peripheral circuit portion located on one side of the stacked structure that is away from the pad 301 and that is opposite to the other side along the second direction.

[0117] In some specific examples, refer to Fig. 9 The stacked structure 400 is located on one side of the active layer 101 that is away from the pad 301, and the channel structure 401 extends along the second direction and penetrates the stacked structure 400. The stacked structure 400 and the plurality of channel structures 401 constitute a storage array structure. Part of the film layer in the channel structure 401 extends into the active layer 101 and is connected to the active layer 101. The active layer 101 is further connected to the pad 301 to achieve back-side lead-out of the channel structure 401.

[0118] The peripheral circuit portion 501 is located on one side of the stacked structure 400 that is away from the pad 301, and a first wiring layer 402 and a second wiring layer 502 are disposed between the peripheral circuit portion 501 and the stacked structure 400. In a specific example, a hybrid bonding layer is formed between the first wiring layer 402 and the second wiring layer 502.

[0119] like Fig. 9 As shown, the distance between the pad 301 and the peripheral circuit part 501 in the second direction is far, and as the storage density increases, the number of stacking layers in the stacking structure 400 needs to be further increased, and the distance between the pad 301 and the peripheral circuit part 501 in the second direction also increases accordingly. Therefore, when electrostatic discharge is caused by the contact between the needle tip of the test probe and the pad 301, the electrostatic protection circuit set in the peripheral circuit part 501 cannot discharge the static electricity in time.

[0120] In the embodiment of the present disclosure, an electrostatic protection structure 100 connected to the pad 301 is arranged around the pad 301, and the electrostatic protection structure 100 includes at least one transistor structure 200, the first electrode region 102, the channel region 103, and the second electrode region 104 of the transistor structure 200 are arranged in the active layer 101, and the gate structure 201 of the transistor structure 200 is arranged on the active layer 101, the first electrode region 102 and the gate structure 201 of the transistor structure 200 located at the first end of the electrostatic protection structure 100 are connected to the power line 302, and the second electrode region 104 of the transistor structure 200 located at the second end of the electrostatic protection structure 100 is connected to the ground line 303, and the pad 301 is connected to the first electrode region 102 or the second electrode region 104 of the transistor structure 200. Therefore, the static electricity generated on the pad 301 can be discharged to the power end or the ground end through the electrostatic protection structure 100 without entering the interior of the semiconductor structure, thereby reducing the risk of high-voltage static electricity causing damage to the storage array structure and other circuit structures, and effectively improving the reliability and yield of the semiconductor structure.

[0121] In some embodiments, since static electricity is usually generated at the moment when an external power source applies an electrical signal to the inside of the semiconductor structure via the pad 301, after the semiconductor structure enters a normal working state, the connection between the electrostatic protection structure 100 and the power supply terminal and the ground terminal can be disconnected to put the electrostatic protection structure 100 in a shielded state, so as to avoid as much as possible the additional power consumption caused by the electrostatic protection structure 100 being mistakenly triggered under normal working conditions.

[0122] In some specific examples, the peripheral circuit portion 501 may include circuit elements including page buffer sense amplifiers, column decoders / bit line drivers, row decoders / word line drivers, voltage generators, control logic units, registers, interfaces, and data buses.

[0123] In some other specific examples, the semiconductor structure provided by the present disclosure may also include only a storage array structure.

[0124] It should be noted that, in the above embodiment, the storage array structure composed of the stacked structure 400 and the channel structure 401 is a NAND storage array structure, and the memory including the peripheral circuit part 501 is a 3D NAND memory as an example, but the present disclosure is not limited to this, and any other three-dimensional memory obtained by a wafer bonding process may include the semiconductor structure including the electrostatic protection structure 100 provided in the embodiment of the present disclosure.

[0125] Reference Fig.10The present disclosure also provides a memory system 600, comprising: at least one semiconductor structure in any of the above embodiments and a controller 602; the controller 602 is coupled to the at least one semiconductor structure and configured to control the semiconductor structure. Here, the semiconductor structure may be a memory 601.

[0126] In some embodiments, the controller 602 and one or more memories 601 may be integrated into various types of storage devices, that is, the memory system 600 may be implemented and packaged into different types of terminal electronic products.

[0127] In some specific examples, the memory system 600 can be a compact flash card (CFC), a smart media card (SMC), a memory stick (MS), a multimedia card (MMC), such as RS-MMC, MMCmicro, eMMC, etc., a secure digital card (SD card), such as Mini SD card, Micro SD card, SDHC card, etc., a universal flash storage (UFS) card and a solid state drive (SSD).

[0128] In other specific examples, the memory system 600 may be placed in a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having memory therein.

[0129] Based on a concept similar to the semiconductor structure in the above-mentioned embodiment, the embodiment of the present disclosure further provides a method for forming a semiconductor structure. Fig.11 The present invention provides a flow chart of a method for forming a semiconductor structure according to an embodiment of the present invention. The method for forming a semiconductor structure includes the following steps:

[0130] Step S10: providing an active layer;

[0131] Step S20: forming a pad on the active layer and forming an electrostatic protection structure; the electrostatic protection structure includes at least one transistor structure, the transistor structure includes a gate structure and a first electrode region, a channel region, and a second electrode region located in the active layer and arranged along a first direction, and the gate structure is located on the channel region; the pad is connected to the first electrode region or the second electrode region of the transistor structure; the first direction is perpendicular to the second direction; the second direction is the thickness direction of the active layer.

[0132] Figure 12 to Figure 14 This is a schematic diagram of the semiconductor structure formation process. Figure 12 to Figure 14 The formation process of the semiconductor structure is described.

[0133] Reference Fig.12 , providing an active layer 101, and forming a plurality of first electrode regions 102, channel regions 103 and second electrode regions 104 arranged along a first direction in the active layer 101.

[0134] In some embodiments, the material of the active layer 101 can be a heavily doped semiconductor material, for example, N-type doped polysilicon. Therefore, the active layer 101 can be used as a high-voltage N-well of a transistor structure. By performing P-type doping on the active layer 101, a first electrode region 102 and a second electrode region 104 can be formed in the active layer 101.

[0135] In some specific examples, the active layer 101 may be doped by an ion implantation (IMP) process to form a plurality of first electrode regions 102 and second electrode regions 104 arranged along a first direction. The doping elements of the N-type doping may be phosphorus or arsenic, and the doping elements of the P-type doping may be boron or gallium.

[0136] Reference Fig.13 A dielectric layer 203 and an isolation layer 204 are sequentially formed on the active layer 101, and a gate layer 202 located in the isolation layer 204 and a first contact structure 205 penetrating the dielectric layer 203 and the isolation layer 204 along the second direction are formed. The gate layer 202 and the dielectric layer 203 constitute a gate structure 201 of the transistor structure 200, and one of the two opposite ends of the first contact structure 205 along the second direction is connected to the first electrode region 102 or the second electrode region 104.

[0137] In the embodiment of the present disclosure, the first direction is perpendicular to the second direction, and the second direction is the thickness direction of the active layer 101. Here, the first direction is the X direction, and the second direction is the Z direction.

[0138] In some specific examples, the dielectric layer 203 and the isolation layer 204 may be formed by a deposition process, and an opening may be formed in the isolation layer 204 by a photolithography and etching process, and then a conductive material may be filled in the opening by a deposition process to form the gate layer 202. A through hole penetrating the dielectric layer 203 and the isolation layer 204 may be formed by a photolithography and etching process, and a conductive material may be filled in the through hole by a deposition process to form the first contact structure 205.

[0139] In the embodiments of the present disclosure, the deposition process includes but is not limited to chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD) and atomic layer deposition (ALD).

[0140] In some specific examples, the material of the gate layer 202 can be at least one of a doped semiconductor material (e.g., doped silicon, doped germanium, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a metal material (e.g., tungsten, titanium, tantalum, etc.), and a metal semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.); the material of the dielectric layer 203 can be at least one of silicon oxide, hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium oxide, barium titanium oxide, or strontium tantalum oxide. At least one of the materials selected from the group consisting of strontium titanium, lithium oxide, aluminum oxide, lead scandium tantalum oxide and lead zinc niobate; the material of the isolation layer 204 may be at least one of the materials selected from the group consisting of silicon nitride, silicon oxide, silicon oxynitride and the like; the material of the first contact structure 205 may be at least one of the materials selected from the group consisting of doped semiconductor materials (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metal materials (e.g., tungsten, titanium, tantalum, etc.) and metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0141] In some embodiments, the method for forming a semiconductor structure further includes: forming a plurality of second contact structures penetrating the dielectric layer 203 and the isolation layer 204 along the second direction, wherein the second contact structures are used to connect the pads 301 and the active layer 101 to achieve the lead-out of the active layer 101. Furthermore, the second contact structures and the first contact structures 205 may be made of the same material and have the same size in the second direction, so the first contact structures 205 and the second contact structures may be formed simultaneously.

[0142] In some embodiments, in conjunction with reference Fig.13 and Fig.14 The method for forming a semiconductor structure also includes: forming a pad 301, a power line 302, a ground line 303 and a conductive line 304 on the isolation layer 204; the power line 302 and the ground line 303 are respectively located on two opposite sides of the pad 301 along the first direction; the conductive line 304 is located between the pad 301 and the power line 302 and / or between the pad 301 and the ground line 303 in the first direction; each conductive line 304 is connected to the first electrode region 102 and the gate structure 201 of a transistor structure 200; the other end of the first contact structure 205 along the second direction is connected to one of the pad 301, the power line 302, the ground line 303 and the conductive line 304.

[0143] In some specific examples, the materials of the pad 301, the power line 302, the ground line 303 and the conductive line 304 may be the same, and may be at least one of metal materials such as tungsten, copper, nickel, aluminum, silver, gold, titanium, etc. Moreover, the pad 301, the power line 302, the ground line 303 and the conductive line 304 may be formed at the same time. Specifically, an insulating layer (not shown in the figure) may be formed on the isolation layer 204 first, and then openings corresponding to the pad 301, the power line 302, the ground line 303 and the conductive line 304 may be formed in the insulating layer by photolithography and etching processes, and then metal materials may be filled in the openings to form the pad 301, the power line 302, the ground line 303 and the conductive line 304.

[0144] It should be noted that the semiconductor structure can also be formed by a method similar to the method of forming the semiconductor structure in the above embodiment. Figures 4 to 9 The semiconductor structure shown will not be described in detail here.

[0145] In some embodiments, refer back to Fig. 9 The method for forming a semiconductor structure also includes: forming a stacking structure 400 stacked along a second direction; forming a plurality of channel structures 401 penetrating the stacking structure 400 along the second direction; forming an active layer 101 on one side of two opposite sides of the stacking structure 400 along the second direction; and connecting the active layer 101 to the channel structure 401.

[0146] In some embodiments, the method for forming a semiconductor structure further includes: forming a peripheral circuit portion 501 on the other side of the stack structure 400 that is opposite to each other along the second direction.

[0147] In the embodiment of the present disclosure, the active layer 101 as an N-well in the semiconductor structure is used as the formation area of ​​the first electrode region 102, the channel region 103 and the second electrode region 104 of the transistor structure 200, and the gate structure 201 is formed on the active layer 101 to form an electrostatic protection structure 100 including at least one transistor structure 200 connected to the pad 301. Compared with the formation process of the semiconductor structure including the active layer 101 in the related art, the formation method of the semiconductor structure provided by the present disclosure only adds doping of the active layer 101 to form the first electrode region 102 and the second electrode region 104, so as to and related steps for forming the gate structure 201, and the formation process of the first contact structure 205 can be integrated with the formation process of the second contact structure located between the pad 301 and the active layer 101 in the same process step; the formation process of the power line 302, the ground line 303 and the conductive line 304 can be integrated with the formation process of the pad 301 in the same process step, thereby, while the reliability of the semiconductor structure is improved by adding the electrostatic protection structure 100, the additional process cost generated by the addition of the electrostatic protection structure 100 can also be reduced, and the size of the semiconductor structure in the second direction is not increased as much as possible.

[0148] The features disclosed in several device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new device embodiments.

[0149] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0150] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that: It includes an active layer, an electrostatic protection structure, and a pad located on the active layer; wherein, The electrostatic protection structure includes at least one transistor structure, the transistor structure includes a gate structure and a first electrode region, a channel region, and a second electrode region located in the active layer and arranged along a first direction, the gate structure is located on the channel region; the first direction is perpendicular to a second direction; the second direction is a thickness direction of the active layer; The pad is connected to the first electrode region or the second electrode region of the transistor structure.

2. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further comprises: A power line and a ground line are located on the active layer, and the power line and the ground line are respectively located on two opposite sides of the pad along the first direction.

3. The semiconductor structure according to claim 2, characterized in that: The electrostatic protection structure includes a transistor structure; The transistor structure is located between the power line and the pad, the first electrode region and the gate structure of the transistor structure are connected to the power line, and the second electrode region of the transistor structure is connected to the pad; or, The transistor structure is located between the pad and the ground line, the first electrode region and the gate structure of the transistor structure are connected to the pad, and the second electrode region of the transistor structure is connected to the ground line.

4. The semiconductor structure according to claim 2, characterized in that: The electrostatic protection structure comprises a plurality of transistor structures, which are arranged in series and along the first direction; the electrostatic protection structure comprises a first end and a second end opposite to each other along the first direction, the first end is close to the power line, and the second end is close to the ground line; The electrostatic protection structure is located between the power line and the ground line; The first electrode region and the gate structure of the transistor structure at the first end are connected to the power line; The second electrode region of the transistor structure at the second end is connected to the ground line; the pad is connected to the first electrode region and gate structure of the transistor structure close to the ground line among the two transistor structures closest to the pad in the electrostatic protection structure, and the second electrode region of the other transistor structure; or, The electrostatic protection structure is located between the pad and the ground line; the first electrode region and the gate structure of the transistor structure located at the first end are connected to the pad; A second electrode region of the transistor structure located at the second end is connected to the ground line; or, The electrostatic protection structure is located between the power line and the pad; the first electrode region and the gate structure of the transistor structure located at the first end are connected to the power line; The second electrode region of the transistor structure located at the second end is connected to the pad.

5. The semiconductor structure according to claim 4, characterized in that: The first electrode region of the transistor structure is shared with the second electrode region of the transistor structure closer to the power line among the two transistor structures adjacent to the transistor structure; The second electrode region of the transistor structure is shared with a first electrode region of a transistor structure closer to the ground line among two transistor structures adjacent to the transistor structure.

6. The semiconductor structure according to claim 2, characterized in that: The semiconductor structure further comprises: A conductive line located on the active layer; the conductive line is located between the pad and the power line and / or between the pad and the ground line in the first direction; the conductive line is connected to a first electrode region and a gate structure of a transistor structure.

7. The semiconductor structure according to claim 2, characterized in that: The gate structure includes a gate layer and a dielectric layer, and the semiconductor structure also includes: The isolation layer is located on the active layer; the dielectric layer is located between the isolation layer and the active layer, and the gate layer is located in the isolation layer; the pad, the power line and the ground line are all located on the isolation layer.

8. The semiconductor structure according to claim 7, characterized in that: The semiconductor structure further comprises: A plurality of first contact structures penetrating the dielectric layer and the isolation layer along the second direction; one end of the first contact structure along the second direction is connected to the first electrode area or the second electrode area, and the other end of the first contact structure along the second direction is connected to one of the pad, the power line and the ground line.

9. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure includes a plurality of active layers, each of the active layers extending along the first direction; The pad is located on the multiple active layers; each of the active layers has at least one transistor structure.

10. The semiconductor structure according to claim 1, wherein: The semiconductor structure further comprises: A stacked structure located on one side of the active layer that is away from the pad, on two sides that are opposite to each other along the second direction; A plurality of channel structures extending along the second direction and penetrating the stacked structure; the channel structures are connected to the active layer.

11. The semiconductor structure according to claim 10, characterized in that: The semiconductor structure further comprises: The peripheral circuit portion is located on one side of the stack structure that is away from the pad, of two sides that are opposite to each other along the second direction.

12. A memory system, characterized in that: include: At least one semiconductor structure according to claim 10 or 11; The controller is coupled to the semiconductor structure and configured to control the semiconductor structure.

13. A method for forming a semiconductor structure, characterized in that: include: providing an active layer; forming a pad on the active layer and forming an electrostatic protection structure; The electrostatic protection structure includes at least one transistor structure, which includes a gate structure and a first electrode region, a channel region, and a second electrode region located in the active layer and arranged along a first direction, and the gate structure is located on the channel region; the pad is connected to the first electrode region or the second electrode region of the transistor structure; the first direction is perpendicular to the second direction; and the second direction is the thickness direction of the active layer.

14. The method for forming a semiconductor structure according to claim 13, wherein: The method for forming the semiconductor structure further comprises: A power line and a ground line are formed on the active layer; the power line and the ground line are respectively located on two opposite sides of the pad along the first direction.

15. The method for forming a semiconductor structure according to claim 14, wherein: The method for forming the semiconductor structure further comprises: Conductive lines are formed on the active layer; the conductive lines are located between the pad and the power line and / or between the pad and the ground line in the first direction; each of the conductive lines is connected to a first electrode region and a gate structure of the transistor structure.

16. The method for forming a semiconductor structure according to claim 14, wherein: The forming of the electrostatic protection structure comprises: forming a dielectric layer and an isolation layer on the active layer; the dielectric layer is located between the isolation layer and the active layer; A gate layer is formed in the isolation layer; the gate layer and the dielectric layer constitute the gate structure.

17. The method for forming a semiconductor structure according to claim 16, wherein: The method for forming the semiconductor structure further comprises: forming a plurality of first contact structures penetrating the dielectric layer and the isolation layer along the second direction; one end of the first contact structure along the second direction is connected to the first electrode region or the second electrode region; The step of forming a pad, a power line and a ground line on the active layer comprises: The pad, the power line and the ground line are formed on the isolation layer; the other end of the two ends of the first contact structure along the second direction is connected to one of the pad, the power line and the ground line.

18. The method for forming a semiconductor structure according to claim 13, wherein: The method for forming the semiconductor structure further comprises: forming a stacking structure stacked along the second direction; forming a plurality of channel structures penetrating the stacked structure along the second direction; The active layer is formed on one of two opposite sides of the stack structure along the second direction; the active layer is connected to the channel structure.

19. The method for forming a semiconductor structure according to claim 18, wherein: The method for forming the semiconductor structure further comprises: A peripheral circuit portion is formed on the other side of the stack structure that is opposite to each other along the second direction.

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