Semiconductor structure

Abstract

Embodiments of the present disclosure provide embodiments of a semiconductor structure. A semiconductor structure according to an embodiment of the present disclosure includes a first transistor and a second transistor. The first transistor includes a first source feature, a first drain feature, and a first gate structure. The second transistor includes a second source feature, a second drain feature, and a second gate structure. The first source feature is electrically coupled to the second source feature, and the second drain feature is electrically coupled to the first gate structure.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures. Background Art

[0002] The electronics industry has experienced a growing demand for smaller and faster electronic devices that can simultaneously support more increasingly complex and sophisticated functions. Therefore, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance and low-power integrated circuits (ICs). To date, these goals have been achieved to a large extent by reducing semiconductor IC size (e.g., minimum component size) and thereby improving production efficiency and reducing associated costs. However, such scaling has also introduced increased complexity into semiconductor manufacturing processes. Therefore, achieving continuous progress in semiconductor ICs and devices requires similar progress in semiconductor manufacturing processes and technology.

[0003] The manufacture of IC devices includes front-end-of-line (FEOL) processes and back-end-of-line (BEOL) processes. Typically, the FEOL process forms a transistor on a substrate, and the BEOL process forms an interconnect structure above or below the transistor to functionally connect the transistor. The BEOL process includes an etching step that often uses plasma. The use of plasma can generate charges that can accumulate at electrically isolated nodes during the BEOL process. When enough charge is accumulated, energy can be dissipated at a single point in the gate dielectric layer. This may cause breakdown of the gate dielectric layer and permanent damage to the transistor. These damages can be referred to as plasma-induced damage (PID). Several technologies have been proposed to prevent or reduce PID. Summary of the invention

[0004] Some embodiments of the present application provide a semiconductor structure, including: a first transistor, including: a first source component; a first drain component; and a first gate structure; and a second transistor, including: a second source component; a second drain component; and a second gate structure; wherein the first source component is electrically coupled to the second source component, and wherein the second drain component is electrically coupled to the first gate structure.

[0005] Some other embodiments of the present application provide a semiconductor structure, including: a substrate; a first well region and a second well region, located on the substrate; a first transistor and a second transistor, arranged above the first well region; and a third transistor and a fourth transistor, arranged above the second well region, wherein the first transistor includes a first source component, a first drain component and a first gate structure, wherein the second transistor includes a second source component, a second drain component and a second gate structure, wherein the third transistor includes a third source component, a third drain component and a third gate structure, wherein the fourth transistor includes a fourth source component, a fourth drain component and a fourth gate structure, wherein the first source component is electrically coupled to the fourth source component, and wherein the first gate structure is electrically coupled to the fourth drain component.

[0006] Still other embodiments of the present application provide a semiconductor structure comprising: a dielectric layer; a first well region and a second well region, located above the dielectric layer; a first transistor, disposed above the first well region; and a second transistor, disposed above the second well region; wherein the first transistor comprises a first source component, a first drain component and a first gate structure, wherein the second transistor comprises a second source component, a second drain component and a second gate structure, wherein the first source component is electrically coupled to the second source component, and wherein the first gate structure is electrically coupled to the second drain component. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It is emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 is a circuit diagram of a first type PID prevention device according to various aspects of an embodiment of the present disclosure.

[0009] Figure 2 A schematic cross-sectional view of a first PID prevention device implemented with a transistor having isolated source / drain features according to various aspects of embodiments of the present disclosure is shown.

[0010] Figure 3 A schematic cross-sectional view of a first PID prevention device implemented with a transistor having a backside contact structure according to various aspects of an embodiment of the present disclosure is shown.

[0011] Figure 4 is a circuit diagram of a second PID prevention device according to various aspects of an embodiment of the present disclosure.

[0012] Figure 5Schematic cross-sectional views of a second PID prevention device implemented with a transistor having isolated source / drain features according to various aspects of embodiments of the present disclosure are shown.

[0013] Figure 6 A schematic cross-sectional view of a second PID prevention device implemented with a transistor having a backside contact structure according to various aspects of the embodiments of the present disclosure is shown.

[0014] Figure 7 is a circuit diagram of a third PID prevention device according to various aspects of an embodiment of the present disclosure.

[0015] Figure 8 A schematic cross-sectional view of a third PID prevention device implemented with a transistor having isolated source / drain features according to various aspects of embodiments of the present disclosure is shown.

[0016] Fig. 9 A schematic cross-sectional view of a third PID prevention device implemented with a transistor having a backside contact structure according to various aspects of the embodiments of the present disclosure is shown.

[0017] Fig.10 is a circuit diagram of a fourth PID prevention device according to various aspects of the embodiments of the present disclosure.

[0018] Fig.11 A schematic cross-sectional view of a fourth PID prevention device implemented with a transistor having isolated source / drain features according to various aspects of embodiments of the present disclosure is shown.

[0019] Fig.12 A schematic cross-sectional view of a fourth PID prevention device implemented with a transistor having a backside contact structure according to various aspects of the embodiments of the present disclosure is shown.

[0020] Fig.13 is a circuit diagram of a fifth PID prevention device according to various aspects of the embodiments of the present disclosure.

[0021] Fig.14 A schematic cross-sectional view of a fifth PID prevention device implemented with a transistor having isolated source / drain features according to various aspects of embodiments of the present disclosure is shown.

[0022] Fig.15 A schematic cross-sectional view of a fifth PID prevention device implemented with a transistor having a backside contact structure according to various aspects of the embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0023] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0024] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0025] In addition, when "about," "approximately," etc. are used to describe a value or a range of values, as understood by one of ordinary skill in the art, the terms are intended to encompass values ​​within a reasonable range that takes into account variations that inherently occur during manufacturing. For example, based on known manufacturing tolerances associated with manufacturing components having properties associated with the value, a value or range of values ​​encompasses a reasonable range that includes the described value, such as within + / - 10% of the described value. For example, a material layer having a thickness of "about 5 nm" may include a size range from 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with depositing material layers known to one of ordinary skill in the art is + / - 15%.

[0026] The manufacture of IC devices includes a front-end-of-line (FEOL) process and a back-end-of-line (BEOL) process. Typically, the FEOL process forms a transistor on a substrate, and the BEOL process forms an interconnect structure above or below the transistor to functionally connect the transistor. The interconnect structure includes several layers of metal layers, each of which may include metal lines and contact vias. The formation of these metal lines and contact vias may include the use of a plasma-assisted dry etching process. As more and more metal lines and contact vias are formed, they may inevitably act as antennas to collect charges generated by the incidence of plasma. When sufficient charge is accumulated at an electrically isolated node, the charge may cause high field stress to dielectric components (such as a gate dielectric layer). Stress may damage the transistor. For example, when this happens to the gate dielectric layer, the high field stress may cause breakdown of the gate dielectric layer and complete failure of the transistor. This type of damage is generally referred to as plasma-induced damage (PID). Various techniques have been developed to prevent or mitigate PID. In some practices, a conduction path to electrical ground is established for the charge collected by the metal wiring antenna. However, such a conduction path may not be easily available in some cases.

[0027] Embodiments of the present disclosure provide embodiments of PID prevention devices that disperse harmful charge accumulation. The PID prevention devices of the embodiments of the present disclosure include an antenna transistor electrically coupled to a protected device. In some embodiments, the antenna transistor provides a conductive path to release the accumulated charge. In some embodiments, the antenna transistor is positioned similarly to the protected device to share the high field stress caused by the plasma.

[0028] Combination Figures 1 to 15 The following description is provided with the illustrations in FIG. Throughout the disclosure, the same reference numerals refer to the same components and may refer to the same composition or formation process unless otherwise described. Therefore, for simplicity, components with the same reference numerals may be described only once. The X, Y, and Z directions are shown throughout all attached drawings. Figure 1 As used herein, the source / drain region or source / drain feature may be referred to as a source or a drain, either individually or collectively depending on the context.

[0029] First reference Figure 1 , Figure 1 is a circuit diagram of the first PID prevention device 100-1. Figure 1 As shown in , the first PID prevention device 100-1 is configured to protect a protected transistor 10 including a first gate 10G, a first drain 10D, and a first source 10S. The first PID prevention device 100-1 includes an antenna transistor 20 including a second gate 20G, a second drain 20D, and a second source 20S. Figure 1In the embodiment depicted in , the second gate 20G and the second source 20S are electrically coupled to the first source 10S, and the second drain 20D is electrically coupled to the first gate 10G. The first gate 10G and the second drain 20D are electrically coupled to the metal wiring structure 50. The metal wiring structure 50 can be part of the front-side interconnect structure and is located in an appropriate position to accumulate the charge generated by the plasma. When the metal wiring structure 50 is used as an antenna to collect charge, the charge can flow to the first source 10S and the second source 20S via leakage through the first gate 10G and via a leakage path between the second drain 20D and the second source 20S. It can be seen that the leakage path between the second drain 20D and the second source 20S releases the accumulated charge and reduces the high field stress at the first gate 10G. The dispersion of charge reduces the possibility of damage to the protected transistor 10. When the first gate 10G is turned on during operation, the antenna transistor 20 is turned off. Because the antenna transistor 20 is turned off during operation, the first PID prevention device 100-1 is designed to minimize the leakage current (I D ).

[0030] Figure 1 The first PID prevention device 100-1 shown in and other PID prevention devices described herein can be implemented with different types of planar transistors or multi-gate transistors. A multi-gate device generally refers to a device having a gate structure or part thereof disposed above more than one side of a channel region. Fin field effect transistors (FinFETs) and gate-all-around (GAA) transistors are examples of multi-gate devices, which have become popular and promising candidate devices for high-performance and low-leakage applications. FinFETs have an elevated channel wrapped by a gate on more than one side (e.g., a gate wraps the top and sidewalls of a semiconductor material "fin" extending from a substrate). A GAA transistor has a gate structure that can extend partially or entirely around a channel region to provide access to a channel region on two or more sides. Because its gate structure surrounds the channel region, a GAA transistor can also be referred to as a gate-around transistor (SGT). Because the channel region of a GAA transistor can include nanowires or nanosheets, and its configuration is similar to a bridge, a GAA transistor can also be referred to as a multi-bridge channel (MBC) transistor, a nanowire transistor, or a nanosheet transistor. Nanosheets and nanowires can generally be referred to as nanostructures. Figure 1 The first PID prevention device 100-1 shown in FIG. 1 may also be implemented using transistors having a stacked device configuration. For example, it may be implemented using a complementary field effect transistor (C-FET) in which multiple gate transistors are stacked vertically, one above the other. For illustrative purposes, the implementation of the first PID prevention device 100-1 and other PID prevention devices of the present disclosure will be described using a GAA transistor as an example.

[0031] Figure 2 A schematic cross-sectional view of a first PID prevention device 100 - 1 implemented with a GAA transistor having isolated source / drain features is shown. Figure 2 The protected transistor 10 in is a GAA transistor, which includes a first channel component 204 extending between a first source component 208S and a first drain component 208D in the X direction. The first gate structure 206 wraps around each of the first channel components 204. In the depicted embodiment, the protected transistor 10 is an n-type GAA transistor disposed above a first p-type well 202P of the substrate 202. In some instances, the first p-type well 202P may include a p-type dopant, such as boron (B). The first source component 208S and the first drain component 208D include silicon (Si) and an n-type dopant, such as phosphorus (P) or arsenic (As). The first source component 208S and the first drain component 208D of the protected transistor 10 are not in direct contact with the first p-type well 202P. Figure 2 As shown in , each of the first source feature 208S and the first drain feature 208D is insulated from the p-type well 202P by a bottom isolation layer 215. In some examples, the bottom isolation layer 215 can include silicon nitride, silicon oxide, silicon oxynitride, or silicon oxycarbonitride. In one embodiment, the bottom isolation layer 215 includes silicon nitride. A plurality of internal spacer features 230 are interlaced with the first channel member 204 and space the first gate structure 206 from the sidewalls of the first source feature 208S and the first drain feature 208D.

[0032] Although in Figure 2 Although not explicitly shown in the figure, the first gate structure 206 includes a gate dielectric layer and a gate electrode layer. In some embodiments, the gate dielectric layer may include an interface layer and a high-k dielectric layer. Here, the high-k dielectric material as used and described herein includes a dielectric material having a high dielectric constant, for example, a dielectric constant greater than that of thermal silicon oxide (~3.9). The interface layer may include a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride. The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The high-k dielectric layer may include hafnium oxide. Optionally, the high-k dielectric layer may include other high-k dielectric materials, such as titanium oxide (TiO 2 ), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta 2 O 5 ), Hafnium Silicon Oxide (HfSiO 4 ), zirconium oxide (ZrO 2 ), zirconium oxide silicon (ZrSiO 2 ), lanthanum oxide (La 2 O 3 ), aluminum oxide (Al 2 O3 )、ZrO、Yttrium oxide (Y 2 O 3 )、SrTiO 3 (STO), BaTiO 3 (BTO), BaZrO, Hafnium Lanthanum Oxide (HfLaO), Lanthanum Silicon Oxide (LaSiO), Aluminum Silicon Oxide (AlSiO), Hafnium Tantalum Oxide (HfTaO), Hafnium Titanium Oxide (HfTiO), (Ba, Sr)TiO 3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. The high-K gate dielectric layer may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods.

[0033] The gate electrode layer of the first gate structure 206 may include a single layer or optionally a multi-layer structure, such as a metal layer (work function metal layer) having a selected work function to enhance device performance, a liner layer, a wetting layer, an adhesion layer, a metal alloy or various combinations of metal silicides. For example, the gate electrode layer may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals or other suitable metal materials or combinations thereof. In various embodiments, the gate electrode layer may be formed by ALD, PVD, CVD, electron beam evaporation or other suitable processes.

[0034] like Figure 2 As shown in , the first PID prevention device 100-1 includes an antenna transistor 20 that is similar in structure to the protected transistor 10. The antenna transistor 20 is also an n-type GAA transistor disposed on a second p-type well 202P different from the first p-type well 202P. Like the protected transistor 10, the antenna transistor 20 includes a second channel member 214 extending between a second source component 218S and a second drain component 218D in the X direction. A second gate structure 216 wraps around each of the second channel members 214. The second source component 218S and the second drain component 218D are n-type and include silicon (Si) and an n-type dopant, such as phosphorus (P) or arsenic (As).

[0035] exist Figure 2In some embodiments shown in , the second source component 218S is electrically coupled to the first source component 208S, and the second drain component 218D is electrically coupled to the first gate structure 206. In addition, the second gate structure 216 is not kept electrically floating, but is electrically coupled to the second source component 218S and the first source component 208S. The first gate structure 206 and the second drain component 218D are electrically coupled to the front side metal wiring structure group 50F, which can collect the accumulated charge that causes damage to the protected transistor 10. When the Figure 2 When connected in the manner shown in , the accumulated charge can be released through the first gate structure 206 or through the leakage path between the second drain feature 218D and the second source feature 218S. The leakage path of the antenna transistor 20 helps to reduce or eliminate the high field stress at the first gate structure 106.

[0036] The tap cell is common in standard cell designs and can be inserted into IC devices to serve as a way to pull the p-type well 202P to ground voltage (Vss). Although the use of the bottom isolation layer 215 may render the tap cell useless, the tap cell structure may still exist. Figure 2 In some embodiments shown in , the first tap unit transistor 30 shares the same first p-type well 202P with the protected transistor 10, and the second tap unit transistor 40 shares the same second p-type well 202P with the antenna transistor 20. It can be seen that when the bottom isolation layer 215 is not present, the first tap unit transistor 30 serves as an access point to the first p-type well 202P, and the second tap unit transistor 40 serves as an access point to the second p-type well 202P. The first tap unit transistor 30 is similar to a p-type GAA transistor. As shown in FIG. Figure 2As shown in , the first tap unit transistor 30 includes a third channel member 224 extending between the third source / drain components 228 and a third gate structure 226 wrapping each of the third channel member 224. The third source / drain component 228 is p-type and includes silicon germanium (SiGe) and a p-type dopant, such as boron (B). The third gate structure 226 and the third source / drain component 228 are both electrically floating and are not electrically coupled to the protected transistor 10, the antenna transistor 20, or the interconnect structure. The second tap unit transistor 40 is the same way. The second tap unit transistor 40 is similar to a p-type GAA transistor. The second tap unit transistor 40 includes a fourth channel member 234 extending between the fourth source / drain components 238 and a fourth gate structure 236 wrapping each of the fourth channel member 234. The fourth source / drain component 238 is p-type and includes silicon germanium (SiGe) and a p-type dopant, such as boron (B). The fourth gate structure 236 and the fourth source / drain component 238 are both electrically floating and are not electrically coupled to the protected transistor 10, the antenna transistor 20, or the interconnect structure. Because the first tap cell transistor 30 and the second tap cell transistor 40 no longer function as tap cells, they can be referred to as pseudo transistors. In some embodiments, they can be completely omitted to reduce the device footprint and standard cell size. Figure 2 In some embodiments shown in , different transistors may be isolated from each other by isolation features 240. The isolation features 240 may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbonitride.

[0037] Figure 3 A schematic cross-sectional view of a first PID prevention device 100 - 1 implemented with a GAA transistor having a backside contact structure is shown. Figure 3 The protected transistor 10 in FIG. 1 is a GAA transistor including a first channel member 204 extending between a first source feature 208S and a first drain feature 208D. A first gate structure 206 wraps around each of the first channel members 204. In the depicted embodiment, the protected transistor 10 is an n-type GAA transistor disposed above a first p-type well 202P of a substrate 202. Figure 2 Different from the embodiment shown in Figure 3 The GAA transistor in FIG. 1 has a super power rail (SPR) configuration, wherein a backside contact 244 extends through a backside dielectric layer 242 to couple the first source feature 208S to a backside interconnect structure. Figure 3 As shown in FIG. , in the thinning substrate 202 ( Figure 3 After that, a backside dielectric layer 242 is deposited (not explicitly shown) until different well regions (such as the p-type well 202P) are physically and electrically isolated from each other. Due to the SPR structure, there is no common bulk substrate or common well region to serve as an electrical ground.

[0038] like Figure 3 As shown in , the protected transistor 10 includes a first channel member 204 extending between a first source feature 208S and a first drain feature 208D in the X direction. Each of the first source feature 208S and the first drain feature 208D is disposed on the first p-type well 202P. Figure 3 The antenna transistor 20 in the embodiment is similar in structure to the protected transistor 10. The antenna transistor 20 is also an n-type GAA transistor disposed on a second p-type well 202P different from the first p-type well 202P. Like the protected transistor 10, the antenna transistor 20 includes a second channel member 214 extending between a second source feature 218S and a second drain feature 218D in the X direction. A second gate structure 216 wraps around each of the second channel members 214. Figure 2 Details of the first p-type well 202P, the first source feature 208S, the first drain feature 208D, the second source feature 218S, the second drain feature 218D, the first gate structure 206 and the second gate structure 216 have been described and will not be repeated here for brevity.

[0039] exist Figure 3 In some embodiments shown in , the second source component 218S is electrically coupled to the first source component 208S, and the second drain component 218D is electrically coupled to the first drain component 208D. In addition, the second gate structure 216 is not kept electrically floating, but is electrically coupled to the second source component 218S and the first source component 208S. The first gate structure 206 and the second drain component 218D are electrically coupled to the first back metal wiring structure group 50B via the back contact 244. The first back metal wiring structure group 50B can collect accumulated charges that cause damage to the protected transistor 10. The first source component 208S is coupled to the second back metal wiring structure group 60B via the back contact 244. When Figure 3 When connected in the manner shown in , the charge accumulated in the first backside metal wiring structure group 50B can be released to the second backside metal wiring structure group 60B through the first gate structure 206 or through the leakage path between the second drain feature 218D and the second source feature 218S. The leakage path of the antenna transistor 20 helps to reduce or eliminate the high field stress at the first gate structure 106.

[0040] As described above, tap cells are common in standard cell designs and can be inserted into IC devices to serve as a way to pull the p-type well 202P to ground voltage (Vss). Although the use of SPR construction may render the tap cell useless, the tap cell structure may still exist. Figure 3In some embodiments shown in , the first tap unit transistor 30 is disposed above the third p-type well 202P, and the second tap unit transistor 40 is disposed on the fourth p-type well 202P. The first tap unit transistor 30 is similar to a p-type GAA transistor. Figure 3 As shown in , the first tap unit transistor 30 includes a third channel member 224 extending between the third source / drain components 228 and a third gate structure 226 wrapping each of the third channel member 224. The third source / drain component 228 is p-type and includes silicon germanium (SiGe) and a p-type dopant, such as boron (B). The third gate structure 226 and the third source / drain component 228 are both electrically floating and are not electrically coupled to the protected transistor 10, the antenna transistor 20, or the interconnect structure. The second tap unit transistor 40 is the same way. The second tap unit transistor 40 is similar to a p-type GAA transistor. The second tap unit transistor 40 includes a fourth channel member 234 extending between the fourth source / drain components 238 and a fourth gate structure 236 wrapping each of the fourth channel member 234. The fourth source / drain component 238 is p-type and includes silicon germanium (SiGe) and a p-type dopant, such as boron (B). The fourth gate structure 236 and the third source / drain component 238 are both electrically floating and are not electrically coupled to the protected transistor 10, the antenna transistor 20, or the interconnect structure. Because the p-type wells are isolated from each other, the first tap cell transistor 30 and the second tap cell transistor 40 no longer function as tap cells and can be referred to as pseudo transistors. In some embodiments, they can be completely omitted to reduce the device footprint and standard cell size. Figure 3 In some embodiments shown in , different transistors may also be isolated from each other along the X direction by isolation components 240 .

[0041] Reference now Figure 4 , Figure 4 1 is a circuit diagram of the second PID prevention device 100-2. The second PID prevention device 100-2 is similar to the first PID prevention device 100-1, except that the second gate 20G is electrically coupled to the second drain 20D, the first gate 10G and the front metal wiring structure 50F. Since the first PID prevention device 100-1 and the second PID prevention device 100-2 are similar, a detailed description of the circuit diagram of the second PID prevention device 100-2 is omitted for brevity. Figure 4 When the first gate 10G in the embodiment is turned on during operation, the antenna transistor 20 is also turned on. When the second PID prevention device 100-2 is used, the design of the IC device should take into account the leakage current (I D ).

[0042] Figure 5A schematic cross-sectional view of a second PID prevention device 100 - 2 implemented with a GAA transistor having isolated source / drain features is shown. Figure 5 The second PID prevention device 100-2 in is similar to Figure 2 The first PID prevention device 100-1 in FIG. 1 is different in that the second gate structure 216 is electrically coupled to the second drain feature 218D, the first gate structure 206 and the front side metal wiring structure 50F. Figure 2 The first PID prevention device 100-1 and Figure 5 The second PID prevention device 100-2 is similar to that in FIG. 1 and is omitted for brevity. Figure 5 A detailed description of each component in .

[0043] Figure 6 A schematic cross-sectional view of a second PID prevention device 100 - 2 implemented with a GAA transistor having a backside contact structure is shown. Figure 6 The second PID prevention device 100-2 in is similar to Figure 3 The first PID prevention device 100-1 in FIG. 1 is different in that the second gate structure 216 is electrically coupled to the second drain feature 218D, the first gate structure 206 and the first backside metal wiring structure group 50B. Figure 3 The first PID prevention device 100-1 and Figure 6 The second PID prevention device 100-2 is similar to that in FIG. 1 and is omitted for brevity. Figure 6 A detailed description of each component in .

[0044] refer to Figure 7 , Figure 7 is a circuit diagram of a third PID prevention device 100 - 3 . In some embodiments, the drain-to-source leakage path of the antenna transistor 20 may not have sufficient resistance to reduce the leakage current. To address this problem, more than one antenna transistor 20 may be connected in a stacked gate configuration to connect the leakage paths of these antenna transistors 20 in series. Figure 7 In some embodiments shown in FIG. 1 , three antenna transistors 20 including a first antenna transistor 20 - 1 , a second antenna transistor 20 - 2 , and a third antenna transistor 20 - 3 are connected in a stacked gate configuration. Figure 7 3 antenna transistors 20 are shown in FIG. 1 , but more than three antenna transistors 20 may be connected in a stacked gate configuration to serve as the third PID prevention device 100 - 3 . In some examples, the number of antenna transistors in the third PID prevention device 100 - 3 may be between 2 and 1,000.

[0045] Still reference Figure 7. In the stacked gate configuration, the second source 20S of the first antenna transistor 20-1 is electrically coupled to the first source 10S, and the second drain 20D of the first antenna transistor 20-1 is electrically coupled to the second source 20S of the second antenna transistor 20-2. Similarly, the second drain 20D of the second antenna transistor 20-2 is electrically coupled to the second source 20S of the third antenna transistor 20-3. Finally, the second drain 20D of the third antenna transistor 20-3 is electrically coupled to the first gate 10G and the metal wiring structure 50. The second gates 20G of the first antenna transistor 20-1, the second antenna transistor 20-2, and the third antenna transistor 20-3 are electrically coupled to the first source 10S of the protected transistor 10. The metal wiring structure 50 can be part of the front-side interconnect structure and is located in an appropriate position to accumulate charges generated by contact with the plasma. When the metal wiring structure 50 is used as an antenna to collect charges, the charges can flow to the first source 10S and the second source 20S via leakage through the first gate 10G and via the series leakage path between the second drain 20D and the second source 20S of the first antenna transistor 20-1, the second antenna transistor 20-2, and the third antenna transistor 20-3. It can be seen that the series leakage path releases the accumulated charge and reduces the high field stress at the first gate 10G. The dispersion of charge reduces the possibility of damage to the protected transistor 10. In addition, the series leakage path between the antenna transistors 20-1, 20-2, and 20-3 has a greater resistance, which can reduce the leakage current. When Figure 7 When the first gate 10G in the embodiment is turned on during operation, the first antenna transistor 20-1, the second antenna transistor 20-2, and the third antenna transistor 20-3 are turned off. Since the antenna transistors are turned off during operation, the third PID prevention device 100-3 is designed to minimize the leakage current (I D ).

[0046] Figure 8 A schematic cross-sectional view of a third PID prevention device 100 - 3 implemented with a GAA transistor having isolated source / drain features is shown. Figure 8 The protected transistor 10 in FIG. 1 is a GAA transistor including a first channel member 204 extending between a first source member 208S and a first drain member 208D. A first gate structure 206 wraps around each of the first channel members 204. In the depicted embodiment, the protected transistor 10 is an n-type GAA transistor disposed above a first p-type well 202P of a substrate 202. The first source member 208S and the first drain member 208D of the protected transistor 10 are not in direct contact with the first p-type well 202P. Figure 8As shown in FIG. 1 , each of the first source feature 208S and the first drain feature 208D is insulated from the p-type well 202P by the bottom isolation layer 215. A plurality of inner spacer features 230 are interleaved with the first channel member 204 and space the first gate structure 206 from the sidewalls of the first source feature 208S and the first drain feature 208D. A detailed description of the first p-type well 202P, the first source feature 208S, the first drain feature 208D, the first gate structure 206, and the inner spacer features 230 has been provided above and will not be repeated here for the sake of brevity.

[0047] Instead of Figure 2 The first PID prevention device 100-1 in FIG. 1 has a single antenna transistor 20, and the third PID prevention device 100-3 includes a plurality of antenna transistors connected in a stacked gate configuration. For illustration purposes, Figure 8 The third PID prevention device 100-3 in the embodiment includes three antenna transistors-a first antenna transistor 20-1, a second antenna transistor 20-2, and a third antenna transistor 20-3. Each of the three antenna transistors includes a second channel member 214 extending between a second source component 218S and a second drain component 218D. A second gate structure 216 wraps around each of the second channel members 214. In the depicted embodiment, each of the first antenna transistor 20-1, the second antenna transistor 20-2, and the third antenna transistor 20-3 is an n-type GAA transistor disposed on a second p-type well. In some optional embodiments, the first antenna transistor 20-1, the second antenna transistor 20-2, and the third antenna transistor 20-3 can be disposed above different p-type wells.

[0048] exist Figure 8 In some embodiments shown in , the second source component 218S of the first antenna transistor 20-1 is electrically coupled to the first source component 208S. The second drain component 218D of the first antenna transistor 20-1 is electrically coupled to the second source component 218S of the second antenna transistor 20-2. The second drain component 218D of the second antenna transistor 20-2 is electrically coupled to the second source component 218S of the third antenna transistor 20-3. The second drain component 218D of the third antenna transistor 20-3 is electrically coupled to the first gate structure 206 and the front side metal wiring structure group 50F, which can collect accumulated charge that causes damage to the protected transistor 10. In addition, the second gate structures 216 of the first antenna transistor 20-1, the second antenna transistor 20-2, and the third antenna transistor 20-3 are electrically coupled together and electrically coupled to the second source component 218S and the first source component 208S of the first antenna transistor 20-1. When Figure 8When connected in the manner shown in , the accumulated charge can be released through the first gate structure 206 or through the series leakage path between the second drain component 218D of the third antenna transistor 20-3 and the second source component 218S of the first antenna transistor 20-1. The series leakage path of the antenna transistor 20 helps to reduce or eliminate the high field stress at the first gate structure 106.

[0049] The tap cell is common in standard cell designs and can be inserted into IC devices to serve as a way to pull the p-type well 202P to ground voltage (Vss). Although the use of the bottom isolation layer 215 may render the tap cell useless, the tap cell structure may still exist. Figure 8 In some embodiments shown in , the tap unit transistor is omitted. In some alternative embodiments, the tap unit transistor may be inserted between the protected transistor 10 and the first antenna transistor 20-1. The details of the tap unit transistor in these alternative embodiments have been described above and will not be repeated here.

[0050] Fig. 9 A schematic cross-sectional view of a third type PID prevention device 100 - 3 implemented with a GAA transistor having a backside contact structure is shown. Fig. 9 The protected transistor 10 in is a GAA transistor that includes a first channel member 204 extending between a first source member 208S and a first drain member 208D along the X direction. A first gate structure 206 wraps around each of the first channel members 204. A plurality of internal spacer members 230 are interlaced with the first channel members 204 and space the first gate structure 206 from the sidewalls of the first source member 208S and the first drain member 208D. In the depicted embodiment, the protected transistor 10 is an n-type GAA transistor disposed above a first p-type well 202P of the substrate 202. The first source member 208S and the first drain member 208D of the protected transistor 10 are in direct contact with the first p-type well 202P, but the first p-type well 202P is insulated from other well regions. Fig. 9 As shown in , the protected transistor 10 includes an SPR structure in which the substrate is thinned so that neither the bulk substrate nor the common well can be used to connect the two well regions. A backside contact 244 is formed through the backside dielectric layer 242 to couple to source / drain features, such as the first source feature 208S. A detailed description of the first p-type well 202P, the first source feature 208S, the first drain feature 208D, the first gate structure 206, and the internal spacer feature 230 has been provided above, and for the sake of brevity, will not be repeated here.

[0051] Instead of Figure 3 The first PID prevention device 100-1 in the embodiment has a single antenna transistor 20, Fig. 9The third PID prevention device 100-3 in FIG. 1 includes a plurality of antenna transistors connected in a stacked gate configuration. For illustration purposes, Fig. 9 The third PID prevention device 100-3 in the embodiment includes three antenna transistors - a first antenna transistor 20-1, a second antenna transistor 20-2, and a third antenna transistor 20-3. Each of the three antenna transistors includes a second channel member 214 extending between a second source component 218S and a second drain component 218D. A second gate structure 216 wraps around each of the second channel members 214. In the depicted embodiment, each of the first antenna transistor 20-1, the second antenna transistor 20-2, and the third antenna transistor 20-3 is an n-type GAA transistor disposed on a separate p-type well.

[0052] exist Fig. 9 In some embodiments shown in , the second source component 218S of the first antenna transistor 20-1 is electrically coupled to the first source component 208S. The second drain component 218D of the first antenna transistor 20-1 is electrically coupled to the second source component 218S of the second antenna transistor 20-2. The second drain component 218D of the second antenna transistor 20-2 is electrically coupled to the second source component 218S of the third antenna transistor 20-3. The second drain component 218D of the third antenna transistor 20-3 is electrically coupled to the first gate structure 206 and the front side metal wiring structure group 50F, which can collect the accumulated charge that causes damage to the protected transistor 10. In addition, the second gate structures 216 of the first antenna transistor 20-1, the second antenna transistor 20-2, and the third antenna transistor 20-3 are electrically coupled together and electrically coupled to the second source component 218S and the first source component 208S of the first antenna transistor 20-1. The first gate structure 206 and the second drain component 218D of the third antenna transistor 20-3 are electrically coupled to the second source component 218S and the first source component 208S of the first antenna transistor 20-1. The first gate structure 206 and the second drain component 218D of the third antenna transistor 20-3 are electrically coupled to the first back metal wiring structure group 50B via the back contact 244. The first back metal wiring structure group 50B can collect accumulated charges that cause damage to the protected transistor 10. The first source component 208S is coupled to the second back metal wiring structure group 60B via the back contact 244. When Fig. 9When connected in the manner shown in , the charge accumulated in the first backside metal wiring structure group 50B can be released to the second backside metal wiring structure group 60B through the first gate structure 206 or through the series leakage path between the second drain component 218D of the third antenna transistor 20-3 and the second source component 218S of the first antenna transistor 20-1. The series leakage path of the antenna transistor 20 helps to reduce or eliminate the high field stress at the first gate structure 206.

[0053] Tap cells are common in standard cell designs and can be inserted into IC devices to serve as a way to pull the p-type well 202P to ground voltage (Vss). Although the use of SPR construction may render the tap cell useless, the tap cell structure may still exist. Fig. 9 In some embodiments shown in , the tap unit transistor is omitted. In some alternative embodiments, the tap unit transistor may be inserted between the protected transistor 10 and the first antenna transistor 20-1. The details of the tap unit transistor in these alternative embodiments have been described above and will not be repeated here.

[0054] refer to Fig.10 , Fig.10 1 is a circuit diagram of a fourth PID prevention device 100-4. The fourth PID prevention device 100-4 is similar to the third PID prevention device 100-3, except that the second gate 20G of the first antenna transistor 20-1, the second antenna transistor 20-2, and the third antenna transistor 20-3 are electrically coupled to the second drain 20D, the first gate 10G, and the metal wiring structure 50. Since the third PID prevention device 100-3 and the fourth PID prevention device 100-4 are similar, a detailed description of the circuit diagram of the fourth PID prevention device 100-4 is omitted for brevity. Fig.10 When the first gate 10G in the embodiment is turned on during operation, the first antenna transistor 20-1, the second antenna transistor 20-2 and the third antenna transistor 20-3 are also turned on. Therefore, when the fourth PID prevention device 100-4 is adopted, the design of the IC device should take into account the leakage current (I D ).

[0055] Fig.11 A schematic cross-sectional view of a fourth PID prevention device 100 - 4 implemented with a GAA transistor having isolated source / drain features is shown. Fig.11 The fourth PID prevention device 100-4 is similar to Figure 8The third PID prevention device 100-3 in FIG. 1 is different in that the second gate structures 216 of the first antenna transistor 20-1, the second antenna transistor 20-2, and the third antenna transistor 20-3 are electrically coupled to the second drain component 218D of the third antenna transistor, the first gate structure 206, and the front side metal wiring structure group 50F. Fig.11 The fourth PID prevention device 100-4 and Figure 8 The third PID prevention device 100-3 is similar to that in FIG. 1 and is omitted for brevity. Fig.11 A detailed description of each component in .

[0056] Fig.12 A schematic cross-sectional view of a fourth PID prevention device 100 - 4 implemented with a GAA transistor having a backside contact structure is shown. Fig.12 The fourth PID prevention device 100-4 is similar to Fig. 9 The third PID prevention device 100-3 in FIG. 1 is different in that the second gate structure 216 of the first antenna transistor 20-1, the second antenna transistor 20-2, and the third antenna transistor 20-3 is electrically coupled to the second drain component 218D of the third antenna transistor 20-3, the first gate structure 206, and the first backside metal wiring structure group 50B. Fig.12 The fourth PID prevention device 100-4 and Fig. 9 The third PID prevention device 100-3 is similar to that in FIG. 1 and is omitted for brevity. Fig.12 A detailed description of each component in .

[0057] Then refer to Fig.13 , Fig.13 is a circuit diagram of the fifth PID prevention device 100-5. Fig.13 As shown in FIG. 1 , the fifth PID prevention device 100-5 is configured to protect a protected transistor 10 including a first gate 10G, a first drain 10D, and a first source 10S. The fifth PID prevention device 100-5 includes a plurality of antenna transistors connected between the first gate 10G and the first source 10S of the protected transistor 10 in a multi-finger configuration. Although the number of antenna transistors in the fifth PID prevention device 100-5 may be between 2 and 1000, for illustration purposes, the number of antenna transistors in FIG. 100-5 is shown in FIG. Fig.13 Three antenna transistors are shown in FIG. Fig.13 The three antenna transistors in the embodiment include a fourth antenna transistor 20-4, a fifth antenna transistor 20-5, and a sixth antenna transistor 20-6. Each of the fourth antenna transistor 20-4, the fifth antenna transistor 20-5, and the sixth antenna transistor 20-6 includes a second gate 20G, a second drain 20D, and a second source 20S. Fig.13In the embodiment depicted in , the second gate 20G of the fourth antenna transistor 20-4, the fifth antenna transistor 20-5, and the sixth antenna transistor 20-6 is electrically coupled to the first gate 10G and the metal wiring structure 50. All second sources 20S and second drains 20D are electrically coupled to the first source 10S. The metal wiring structure 50 can be part of the front-side interconnect structure and is located in an appropriate position to accumulate the charge generated by contact with the plasma. When the metal wiring structure 50 is used as an antenna to collect charge, the charge can apply a field stress shared by the first gate 10G and all second gates 20G. It can be seen that the distribution or dispersion of high field stress reduces the high field stress at the first gate 10G. It can also be seen that when there are more antenna transistors in the fifth PID prevention device 100-5, the first gate 10G is under less field stress.

[0058] Fig.14 A schematic cross-sectional view of a fifth PID prevention device 100 - 5 implemented with a GAA transistor having isolated source / drain features is shown. Fig.14 The protected transistor 10 in FIG. 1 is a GAA transistor including a first channel member 204 extending between a first source member 208S and a first drain member 208D along the X direction. A first gate structure 206 wraps around each of the first channel members 204. In the depicted embodiment, the protected transistor 10 is an n-type GAA transistor disposed above a first p-type well 202P of the substrate 202. The first source member 208S and the first drain member 208 of the protected transistor 10 are not in direct contact with the first p-type well 202P. Fig.14 As shown in FIG. 1 , each of the first source feature 208S and the first drain feature 208D is insulated from the p-type well 202P by the bottom isolation layer 215. A plurality of inner spacer features 230 are interleaved with the first channel member 204 and space the first gate structure 206 from the sidewalls of the first source feature 208S and the first drain feature 208D. A detailed description of the first p-type well 202P, the first source feature 208S, the first drain feature 208D, the first gate structure 206, and the inner spacer features 230 has been provided above and will not be repeated here for the sake of brevity.

[0059] Fig.14 The fifth PID prevention device 100-5 in includes a plurality of antenna transistors connected in a stacked gate configuration. For illustration purposes, Fig.14The fifth PID prevention device 100-5 in the embodiment includes three antenna transistors - a fourth antenna transistor 20-4, a fifth antenna transistor 20-5, and a sixth antenna transistor 20-6. Each of the three antenna transistors includes a second channel member 214 extending between a second source component 218S and a second drain component 218D. A second gate structure 216 wraps around each of the second channel members 214. In the depicted embodiment, each of the fourth antenna transistor 20-4, the fifth antenna transistor 20-5, and the sixth antenna transistor 20-6 is an n-type GAA transistor disposed on a second p-type well. In some optional embodiments, the fourth antenna transistor 20-4, the fifth antenna transistor 20-5, and the sixth antenna transistor 20-6 can be disposed above different p-type wells.

[0060] exist Fig.14 In some embodiments shown in , the second source component 218S and the second drain component 218D of the fourth antenna transistor 20-4, the fifth antenna transistor 20-5, and the sixth antenna transistor 20-6 are electrically coupled to the first source component 208S. The second gate structure 216 of the fourth antenna transistor 20-4, the fifth antenna transistor 20-5, and the sixth antenna transistor 20-6 is electrically coupled to the first gate structure 206 and the front side metal wiring structure group 50F. Fig.14 When connected in the manner shown in , the accumulated charge from the front metal wiring structure 50F may generate a field stress shared between the first gate structure 206 and the second gate structure 216 of the fourth antenna transistor 20-4, the fifth antenna transistor 20-5, and the sixth antenna transistor 20-6. The distribution of the field stress helps to reduce or eliminate the high field stress at the first gate structure 106.

[0061] The tap cell is common in standard cell designs and can be inserted into IC devices to serve as a way to pull the p-type well 202P to ground voltage (Vss). Although the use of the bottom isolation layer 215 may render the tap cell useless, the tap cell structure may still exist. Fig.14 In some embodiments shown in , the tap unit transistor is omitted. In some alternative embodiments, the tap unit transistor may be inserted between the protected transistor 10 and the fourth antenna transistor 20-4. The details of the tap unit transistor in these alternative embodiments have been described above and will not be repeated here.

[0062] Fig.15 A schematic cross-sectional view of a fifth PID prevention device 100 - 5 implemented with a GAA transistor having a backside contact structure is shown. Fig.15The protected transistor 10 in is a GAA transistor that includes a first channel member 204 extending between a first source member 208S and a first drain member 208D. A first gate structure 206 wraps around each of the first channel members 204. A plurality of internal spacer members 230 are interlaced with the first channel members 204 and space the first gate structure 206 from the sidewalls of the first source member 208S and the first drain member 208D. In the depicted embodiment, the protected transistor 10 is an n-type GAA transistor disposed above a first p-type well 202P of the substrate 202. The first source member 208S and the first drain member 208D of the protected transistor 10 are in direct contact with the first p-type well 202P, but the first p-type well 202P is insulated from other well regions. Fig.15 As shown in , the protected transistor 10 includes an SPR structure in which the substrate is thinned so that neither the bulk substrate nor the common well can be used to connect the two well regions. A backside contact 244 is formed through the backside dielectric layer 242 to couple to source / drain features, such as the first source feature 208S. A detailed description of the first p-type well 202P, the first source feature 208S, the first drain feature 208D, the first gate structure 206, and the internal spacer feature 230 has been provided above, and for the sake of brevity, will not be repeated here.

[0063] Fig.15 The fifth PID prevention device 100-5 in includes a plurality of antenna transistors connected in a stacked gate configuration. For illustration purposes, Fig.15 The fifth PID prevention device 100-5 in the embodiment includes three antenna transistors - a fourth antenna transistor 20-4, a fifth antenna transistor 20-5, and a sixth antenna transistor 20-6. Each of the three antenna transistors includes a second channel member 214 extending between a second source component 218S and a second drain component 218D along the X direction. A second gate structure 216 wraps around each of the second channel members 214. In the depicted embodiment, each of the fourth antenna transistor 20-4, the fifth antenna transistor 20-5, and the sixth antenna transistor 20-6 is an n-type GAA transistor disposed on different p-type wells separated from each other.

[0064] exist Fig.15In some embodiments shown in , the second source component 218S and the second drain component 218D of the fourth antenna transistor 20-4, the fifth antenna transistor 20-5, and the sixth antenna transistor 20-6 are electrically coupled to the first source component 208S. The second gate structure 216 of the fourth antenna transistor 20-4, the fifth antenna transistor 20-5, and the sixth antenna transistor 20-6 is electrically coupled to the first gate structure 206. In addition, the first gate structure 206 is electrically coupled to the first back metal wiring structure group 50B via the back contact 244. The first back metal wiring structure group 50B can collect accumulated charges that cause damage to the protected transistor 10. The first source component 208S is coupled to the second back metal wiring structure group 60B via the back contact 244. When Fig.15 When connected in the manner shown in , the accumulated charge from the first backside metal wiring structure group 50B can generate a field stress shared between the first gate structure 206 and the second gate structure 216 of the fourth antenna transistor 20-4, the fifth antenna transistor 20-5, and the sixth antenna transistor 20-6. The distribution of the field stress helps to reduce or eliminate the high field stress at the first gate structure 106.

[0065] Tap cells are common in standard cell designs and can be inserted into IC devices to serve as a way to pull the p-type well 202P to ground voltage (Vss). Although the use of SPR construction may render the tap cell useless, the tap cell structure may still exist. Fig.15 In some embodiments shown in , the tap unit transistor is omitted. In some alternative embodiments, the tap unit transistor may be inserted between the protected transistor 10 and the fourth antenna transistor 20-4. The details of the tap unit transistor in these alternative embodiments have been described above and will not be repeated here.

[0066] In one exemplary aspect, the present disclosure provides a semiconductor structure. The semiconductor structure includes: a first transistor, the first transistor includes a first source component, a first drain component and a first gate structure; a second transistor, the second transistor includes a second source component, a second drain component and a second gate structure. The first source component is electrically coupled to the second source component. The second drain component is electrically coupled to the first gate structure.

[0067] In some embodiments, the second gate structure is electrically coupled to the second source component. In some embodiments, the second gate structure is electrically coupled to the second drain component. In some embodiments, the first transistor is disposed on a first doped well on the substrate, and each first source component and the first drain component are insulated from the first doped well by a first isolation layer. In some embodiments, the second transistor is disposed on a second doped well on the substrate, and each second source component and the second drain component are insulated from the second doped well by a second isolation layer. In some embodiments, the first doped well is insulated from the second doped well. In some embodiments, the semiconductor structure further includes a bottom dielectric layer. The first transistor and the second transistor are disposed on the bottom dielectric layer. In some instances, the first transistor further includes a plurality of nanostructures extending between the first source component and the first drain component. The first gate structure wraps around each of the plurality of nanostructures.

[0068] Another aspect of the disclosed embodiments relates to a semiconductor structure. The semiconductor structure includes: a substrate; a first well region and a second well region, located on the substrate; a first transistor and a second transistor, arranged above the first well region; and a third transistor and a fourth transistor, arranged above the second well region. The first transistor includes a first source component, a first drain component and a first gate structure. The second transistor includes a second source component, a second drain component and a second gate structure. The third transistor includes a third source component, a third drain component and a third gate structure. The fourth transistor includes a fourth source component, a fourth drain component and a fourth gate structure. The first source component is electrically coupled to the fourth source component, and the first gate structure is electrically coupled to the fourth drain component.

[0069] In some embodiments, the second source component, the second drain component, the third source component, and the third drain component are electrically floating. In some embodiments, the second transistor is not electrically coupled to the third transistor. In some embodiments, the first source component, the first drain component, the second source component, and the second drain component are insulated from the first well region. The third source component, the third drain component, the fourth source component, and the fourth drain component are insulated from the second well region. In some embodiments, the fourth gate structure is electrically coupled to the fourth source component. In some embodiments, the fourth gate structure is electrically coupled to the fourth drain component. In some embodiments, the first transistor further includes a plurality of nanostructures extending between the first source component and the first drain component, and the first gate structure wraps around each of the plurality of nanostructures.

[0070] Another aspect of the disclosed embodiments relates to a semiconductor structure. The semiconductor structure includes: a dielectric layer; a first well region and a second well region, located above the dielectric layer; a first transistor, disposed above the first well region; and a second transistor, disposed above the second well region. The first transistor includes a first source component, a first drain component, and a first gate structure. The second transistor includes a second source component, a second drain component, and a second gate structure. The first source component is electrically coupled to the second source component. The first gate structure is electrically coupled to the second drain component.

[0071] In some embodiments, the second gate structure is electrically coupled to the second source component. In some embodiments, the second gate structure is electrically coupled to the second drain component. In some examples, the semiconductor structure further includes: a third well region and a fourth well region located above the dielectric layer; a third transistor disposed above the third well region; and a fourth transistor disposed above the fourth well region. The first well region, the second well region, the third well region, and the fourth well region are insulated from each other. The third transistor and the fourth transistor are not electrically connected. In some embodiments, the third well region and the fourth well region are disposed between the first well region and the second well region.

[0072] Some embodiments of the present application provide a semiconductor structure, including: a first transistor, including: a first source component; a first drain component; and a first gate structure; and a second transistor, including: a second source component; a second drain component; and a second gate structure; wherein the first source component is electrically coupled to the second source component, and wherein the second drain component is electrically coupled to the first gate structure.

[0073] In some embodiments, the second gate structure is electrically coupled to the second source component. In some embodiments, the second gate structure is electrically coupled to the second drain component. In some embodiments, the first transistor is disposed on a first doped well on a substrate, wherein each of the first source component and the first drain component is insulated from the first doped well by a first isolation layer. In some embodiments, the second transistor is disposed on a second doped well on the substrate, wherein each of the second source component and the second drain component is insulated from the second doped well by a second isolation layer. In some embodiments, the first doped well is insulated from the second doped well. In some embodiments, the semiconductor structure further comprises: a bottom dielectric layer, wherein the first transistor and the second transistor are disposed on the bottom dielectric layer. In some embodiments, the first transistor further comprises a plurality of nanostructures extending between the first source component and the first drain component, wherein the first gate structure wraps around each of the plurality of nanostructures.

[0074] Some other embodiments of the present application provide a semiconductor structure, including: a substrate; a first well region and a second well region, located on the substrate; a first transistor and a second transistor, arranged above the first well region; and a third transistor and a fourth transistor, arranged above the second well region, wherein the first transistor includes a first source component, a first drain component and a first gate structure, wherein the second transistor includes a second source component, a second drain component and a second gate structure, wherein the third transistor includes a third source component, a third drain component and a third gate structure, wherein the fourth transistor includes a fourth source component, a fourth drain component and a fourth gate structure, wherein the first source component is electrically coupled to the fourth source component, and wherein the first gate structure is electrically coupled to the fourth drain component.

[0075] In some embodiments, the second source component, the second drain component, the third source component, and the third drain component are electrically floating. In some embodiments, the second transistor is not electrically coupled to the third transistor. In some embodiments, the first source component, the first drain component, the second source component, and the second drain component are insulated from the first well region, wherein the third source component, the third drain component, the fourth source component, and the fourth drain component are insulated from the second well region. In some embodiments, the fourth gate structure is electrically coupled to the fourth source component. In some embodiments, the fourth gate structure is electrically coupled to the fourth drain component. In some embodiments, the first transistor further includes a plurality of nanostructures extending between the first source component and the first drain component, wherein the first gate structure wraps around each of the plurality of nanostructures.

[0076] Still other embodiments of the present application provide a semiconductor structure comprising: a dielectric layer; a first well region and a second well region, located above the dielectric layer; a first transistor, disposed above the first well region; and a second transistor, disposed above the second well region; wherein the first transistor comprises a first source component, a first drain component and a first gate structure, wherein the second transistor comprises a second source component, a second drain component and a second gate structure, wherein the first source component is electrically coupled to the second source component, and wherein the first gate structure is electrically coupled to the second drain component.

[0077] In some embodiments, the second gate structure is electrically coupled to the second source component. In some embodiments, the second gate structure is electrically coupled to the second drain component. In some embodiments, the semiconductor structure further comprises: a third well region and a fourth well region located above the dielectric layer; a third transistor disposed above the third well region; and a fourth transistor disposed above the fourth well region, wherein the first well region, the second well region, the third well region, and the fourth well region are insulated from each other, wherein the third transistor and the fourth transistor are not electrically connected. In some embodiments, the third well region and the fourth well region are disposed between the first well region and the second well region.

[0078] The features of several embodiments are summarized above. Those skilled in the art will appreciate that they can easily use the disclosed embodiments as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the disclosed embodiments, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the disclosed embodiments.

Claims

1. A semiconductor structure comprising: A first transistor comprising: a first source component; a first drain feature; and a first gate structure; and The second transistor comprises: a second source component; a second drain feature; and a second gate structure; wherein the first source component is electrically coupled to the second source component, Wherein, the second drain component is electrically coupled to the first gate structure.

2. The semiconductor structure according to claim 1, wherein: The second gate structure is electrically coupled to the second source feature.

3. The semiconductor structure according to claim 1, wherein: The second gate structure is electrically coupled to the second drain feature.

4. The semiconductor structure according to claim 1, in, The first transistor is disposed on a first doped well on the substrate, Each of the first source component and the first drain component is insulated from the first doped well by a first isolation layer.

5. The semiconductor structure according to claim 4, in, The second transistor is disposed on a second doped well on the substrate, Each of the second source component and the second drain component is insulated from the second doped well by a second isolation layer.

6. The semiconductor structure according to claim 5, wherein: The first doped well is insulated from the second doped well.

7. The semiconductor structure according to claim 1, further comprising: Bottom dielectric layer, The first transistor and the second transistor are arranged on the bottom dielectric layer.

8. The semiconductor structure according to claim 1, in, The first transistor also includes a plurality of nanostructures extending between the first source feature and the first drain feature, The first gate structure wraps around each of the plurality of nanostructures.

9. A semiconductor structure comprising: substrate; A first well region and a second well region are located on the substrate; A first transistor and a second transistor are disposed above the first well region; as well as A third transistor and a fourth transistor are disposed above the second well region, wherein the first transistor comprises a first source component, a first drain component and a first gate structure, wherein the second transistor comprises a second source component, a second drain component and a second gate structure, The third transistor comprises a third source component, a third drain component and a third gate structure, The fourth transistor comprises a fourth source component, a fourth drain component and a fourth gate structure, wherein the first source component is electrically coupled to the fourth source component, Wherein, the first gate structure is electrically coupled to the fourth drain component.

10. A semiconductor structure comprising: Dielectric layer; A first well region and a second well region, located above the dielectric layer; A first transistor, disposed above the first well region; as well as a second transistor, disposed above the second well region; wherein the first transistor comprises a first source component, a first drain component and a first gate structure, wherein the second transistor comprises a second source component, a second drain component and a second gate structure, wherein the first source component is electrically coupled to the second source component, Wherein, the first gate structure is electrically coupled to the second drain component.

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