N-type TOPCon battery and preparation method thereof

Abstract

The embodiment of the invention provides an N-type TOPCon battery and a preparation method thereof, and the N-type TOPCon battery provided by the invention is characterized in that a first tunneling oxide layer and a boron-doped polycrystalline silicon layer are arranged in a positive electrode projection region, so that the structuring of doped polycrystalline silicon in a positive electrode region of the Topcon battery can be realized on the premise of not increasing shading loss; and the cell conversion efficiency can be effectively improved.

Description

Technical Field

[0001] The present invention relates to the technical field of crystalline silicon solar cell manufacturing, and in particular to an N-type TOPCon cell and a preparation method thereof. Background Art

[0002] Currently, N-type TOPCon cells in crystalline silicon solar cells are widely used due to their small attenuation, obvious advantages in overall cell efficiency and power generation.

[0003] The back of the N-type TOPCon cell is equipped with a passivation contact structure composed of ultra-thin silicon oxide and doped silicon thin layer, which can effectively improve the interface contact resistance and realize the selective passage of carriers. However, it also has a certain light trapping effect, so it cannot be applied to the front area of ​​the cell. As a result, the front of the N-type TOPCon cell is only directly doped with boron, which cannot effectively improve the photoelectric conversion efficiency of the cell. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide an N-type TOPCon cell and a preparation method thereof, so as to solve the problem that the front side of the existing N-type TOPCon cell is only directly doped with boron and the photoelectric conversion efficiency cannot be effectively improved.

[0005] In order to solve the above problems, the present invention is achieved through the following technical solutions:

[0006] The present invention proposes an N-type TOPCon battery, which includes an N-type silicon substrate, a first tunneling oxide layer, a boron-doped polysilicon layer, a boron diffusion layer, a positive electrode, a second tunneling oxide layer, a phosphorus-doped polysilicon layer and a negative electrode;

[0007] The first tunneling oxide layer, the boron-doped polysilicon layer and the positive electrode are sequentially deposited on a first region on the front side of the silicon substrate, and the first region is within the projection range of the positive electrode;

[0008] The boron diffusion layer is deposited on a second region on the front side of the silicon substrate, and the second region is outside the projection range of the positive electrode;

[0009] The second tunneling oxide layer, the phosphorus-doped polysilicon layer and the negative electrode are sequentially deposited on the back side of the silicon substrate.

[0010] Furthermore, in the N-type TOPCon battery, the first tunneling oxide layer is a silicon dioxide layer with a thickness of 1 to 3 nm; and the thickness of the boron-doped polysilicon layer is 100 to 200 nm.

[0011] Furthermore, the N-type TOPCon cell further includes a second tunneling oxide layer, a phosphorus-doped polysilicon layer and a negative electrode which are sequentially deposited on the back side of the silicon substrate.

[0012] Furthermore, in the N-type TOPCon cell, the second tunneling oxide layer is a silicon dioxide layer with a thickness of 1 to 3 nm; and the phosphorus-doped polysilicon layer has a thickness of 100 to 200 nm.

[0013] Furthermore, the N-type TOPCon cell further includes a first passivation film layer and a front anti-reflection film layer sequentially arranged on the front side of the silicon substrate.

[0014] Furthermore, in the N-type TOPCon cell, the front anti-reflection film layer comprises a silicon oxynitride layer, and the thickness is 60 to 80 nm;

[0015] The first passivation film layer is an aluminum oxide layer, and has a thickness of 3-5 nm.

[0016] Furthermore, the N-type TOPCon cell further includes a back-side anti-reflection film layer disposed on the surface of the phosphorus-doped polysilicon layer.

[0017] The present invention also proposes a method for preparing an N-type TOPCon battery, which comprises:

[0018] After the N-type silicon substrate is textured, a first tunneling oxide layer and a boron-doped polysilicon layer are formed on the front side;

[0019] Performing laser ablation on a second area of ​​the silicon substrate, where the second area is an area where the positive electrode is projected outside the front surface of the silicon substrate;

[0020] After laser ablation is performed on the second region, boron diffusion is performed on the front side of the silicon substrate, and a second tunneling oxide layer is formed on the back side, and a phosphorus-doped polysilicon layer is formed on the back side;

[0021] After a phosphorus-doped polysilicon layer is formed on the back side, a passivation film layer, a front anti-reflection film layer, a back anti-reflection film layer and an electrode are formed in sequence.

[0022] Furthermore, in the method for preparing the N-type TOPCon cell, laser ablation is performed on the second region of the boron-doped polysilicon layer, comprising:

[0023] The second area is bombarded with a laser with a laser power of 5 to 15 watts, a frequency of 200 to 300 kHz, and a scanning speed of 15,000 to 20,000 mm / s.

[0024] Furthermore, in the method for preparing the N-type TOPCon cell, a boron-doped polysilicon layer is formed on the front side, comprising:

[0025] A polysilicon layer is formed on the front side of the silicon substrate, and then the polysilicon layer is subjected to boron deposition treatment by thermal decomposition, wherein the boron source includes at least one of boron tribromide and boron trichloride, the temperature is 900-1000° C., and the boron deposition time is 5-7 minutes.

[0026] Furthermore, in the method for preparing the N-type TOPCon cell, the front side of the silicon substrate is subjected to boron diffusion treatment, comprising:

[0027] The front surface is subjected to boron diffusion treatment by thermal decomposition, wherein the boron source comprises at least one of boron tribromide and boron trichloride, the temperature is 900-1200° C., and the boron diffusion time is 60-120 minutes.

[0028] Furthermore, in the method for preparing the N-type TOPCon cell, before the N-type silicon wafer is subjected to texturing treatment, the method further comprises:

[0029] A single crystal N-type silicon wafer is provided as the silicon substrate, wherein the resistivity of the N-type silicon wafer is 0.1Ω·cm-0.8Ω·cm, the minority carrier lifetime is 200-300us, and the thickness is 100-180um.

[0030] Compared with the prior art, the embodiments of the present invention have the following advantages:

[0031] In an embodiment of the present invention, the provided N-type TOPCon cell includes an N-type silicon substrate, a first tunneling oxide layer, a boron-doped polysilicon layer, a boron diffusion layer, a positive electrode, a second tunneling oxide layer, a phosphorus-doped polysilicon layer and a negative electrode; the first tunneling oxide layer, the boron-doped polysilicon layer and the positive electrode are sequentially deposited on the first area on the front side of the silicon substrate, and the first area is within the projection range of the positive electrode; the boron diffusion layer is deposited on the second area on the front side of the silicon substrate, and the second area is outside the projection range of the positive electrode; the second tunneling oxide layer, the phosphorus-doped polysilicon layer and the negative electrode are sequentially deposited on the back side of the silicon substrate. Because the electrode area on the front side of the battery mainly serves the purpose of collecting and transporting carriers, and there is shading loss itself, and the first tunneling oxide layer and the boron-doped polysilicon layer are arranged in the positive electrode projection area, the doped polysilicon structure of the electrode area on the front side of the Topcon battery can be realized without increasing the shading loss, which can effectively improve the battery conversion efficiency.

[0032] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 Schematic diagram of the structure of an N-type TOPCon battery provided by an embodiment of the present invention;

[0034] Figure 2It is a flow chart of a method for preparing an N-type TOPCon battery provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0035] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0036] The applicant of the present invention has found that when preparing an N-type TOPCon cell, it is necessary to prepare an ultra-thin silicon oxide layer on the back of the cell, and then deposit a thin layer of doped polycrystalline silicon. The two together form a passivation contact structure, which can effectively improve the interface contact resistance and realize the selective passage of carriers. However, there is also a certain light trapping effect, so it cannot be applied to the front area of ​​the cell, so that the front of the N-type TOPCon cell is only directly doped with boron, which cannot effectively improve the photoelectric conversion efficiency of the cell.

[0037] In order to solve the above problems, an embodiment of the present invention provides an N-type TOPCon battery, including an N-type silicon substrate 11, a first tunneling oxide layer 12, a boron-doped polysilicon layer 13, a boron diffusion layer 14, a positive electrode 15, a second tunneling oxide layer 16, a phosphorus-doped polysilicon layer 17 and a negative electrode 18; the first tunneling oxide layer 12, the boron-doped polysilicon layer 13 and the positive electrode 15 are sequentially deposited on a first area on the front side of the silicon substrate 11, and the first area is within the projection range of the positive electrode 15; the boron diffusion layer 14 is deposited on a second area on the front side of the silicon substrate 11, and the second area is outside the projection range of the positive electrode 15; the second tunneling oxide layer 16, the phosphorus-doped polysilicon layer 17 and the negative electrode 18 are sequentially deposited on the back side of the silicon substrate 11.

[0038] Among them, the first area is the area on the front side of the silicon substrate 11 not covered by the positive electrode 15, that is, the front area of ​​the silicon substrate 11 outside the positive electrode 15 area; the second area is the area covered by the positive electrode 15, that is, the front area of ​​the silicon substrate 11 in the positive electrode 15 area.

[0039] In the embodiment of the present invention, the electrode area on the front side of the battery is fully utilized mainly for the purpose of collecting and transporting carriers. It itself has the characteristic of shading loss. By arranging a first tunneling oxide layer 12 and a boron-doped polysilicon layer 13 in the electrode area, the doped polysilicon structuring of the electrode area on the front side of the Topcon battery can be achieved without increasing the shading loss, which can effectively improve the battery conversion efficiency.

[0040] Optionally, in one embodiment, the first tunneling oxide layer 12 is a silicon dioxide layer, and the thickness is 1 to 3 nm, for example, it can be in the range of 1 nm, 2 nm, 3 nm or any two of them, which can effectively achieve the tunneling effect.

[0041] Optionally, in one embodiment, the thickness of the boron-doped polysilicon layer 13 is 100-200 nm, for example, it can be in the range of one or any two of 100 nm, 150 nm, and 200 nm, which can effectively ensure the passivation and doping effects.

[0042] Optionally, in one embodiment, the first tunneling oxide layer 12 is a silicon dioxide layer, and the thickness is 1 to 3 nm, for example, it can be in the range of 1 nm, 2 nm, 3 nm or any two of them, which can effectively achieve the tunneling effect.

[0043] Optionally, in one embodiment, the thickness of the phosphorus-doped polysilicon layer 17 is 100-200 nm, for example, it can be one or any two of 100 nm, 150 nm, and 200 nm, which can effectively ensure the passivation and doping effects.

[0044] Optionally, in one embodiment, the N-type TOPCon cell provided in the embodiment of the present invention further includes a first passivation film layer 19 and a front anti-reflection film layer 20 sequentially arranged on the front side of the silicon substrate 11. The first passivation film layer 19 is located between the silicon substrate 11 and the front anti-reflection film layer 20, that is, the first passivation film layer 19 is close to the silicon substrate 11. The above arrangement can effectively reduce the reflectivity of the incident light on the front side of the cell, thereby increasing the absorption of light by the film layer.

[0045] Optionally, in a specific embodiment, the front anti-reflection film layer 20 includes a silicon oxynitride layer, and the thickness is 60 to 80 nm, for example, it can be one or any two of 60 nm, 70 nm, 80 nm, which can effectively ensure the anti-reflection effect.

[0046] Optionally, in a specific embodiment, the first passivation film layer 19 is an aluminum oxide layer, and the thickness is 3 to 5 nm, for example, it can be one or any two of 3 nm, 4 nm, 5 nm, which can effectively achieve the passivation effect.

[0047] Optionally, in one embodiment, the N-type TOPCon cell provided in the embodiment of the present invention further includes a back anti-reflection film layer 21 disposed on the surface of the phosphorus-doped polysilicon layer 17, which is used to reduce the reflectivity of incident light on the back side of the cell, thereby improving the absorption of light by the film layer.

[0048] Optionally, in one embodiment, the N-type TOPCon cell provided in an embodiment of the present invention further includes a second passivation film layer 22 arranged between the phosphorus-doped polysilicon layer 17 and the back anti-reflection film layer 21. The above-mentioned setting can effectively reduce the reflectivity of the incident light on the back side of the cell, thereby improving the absorption of light by the film layer.

[0049] Optionally, in a specific embodiment, the second passivation film layer 22 is an aluminum oxide layer, and the thickness is 3 to 5 nm, for example, it can be one or any two of 3 nm, 4 nm, 5 nm, which can effectively achieve the passivation effect.

[0050] In an embodiment of the present invention, the positive electrode 15 is in contact with the boron-doped polysilicon layer 13, and the positive electrode 15 specifically includes a front mother gate electrode and a front sub-gate electrode, both of which can be silver electrodes, or the front mother gate electrode can be a silver electrode, and the front sub-gate electrode is a silver-aluminum paste electrode.

[0051] In the embodiment of the present invention, the negative electrode 18 is in contact with the phosphorus-doped polysilicon layer 17, and the negative electrode 18 includes a back mother gate electrode and a back sub-gate electrode; wherein the back mother gate electrode and the back sub-gate electrode can both be silver electrodes.

[0052] The present invention also provides a method for preparing an N-type TOPCon battery. Figure 2 As shown, it includes steps 201 to 204:

[0053] Step 201, after the N-type silicon substrate is textured, a first tunneling oxide layer and a boron-doped polysilicon layer are formed on the front side;

[0054] Step 202, performing laser ablation processing on a second area of ​​the silicon substrate, where the second area is an area where the positive electrode is projected outside the front surface of the silicon substrate;

[0055] Step 203: after laser ablation of the second region, perform boron diffusion on the front side of the silicon substrate, form a second tunneling oxide layer on the back side, and form a phosphorus-doped polysilicon layer on the back side;

[0056] Step 204 , after forming a phosphorus-doped polysilicon layer on the back side, a passivation film layer, a front anti-reflection film layer, a back anti-reflection film layer and an electrode are sequentially formed.

[0057] The preparation method of the N-type TOPCon battery provided in the embodiment of the present invention forms a first tunneling oxide layer and a boron-doped polysilicon layer on the front side of the silicon substrate, and then uses laser grooving technology to remove the area where the positive electrode is projected outside the front side of the silicon substrate, that is, the non-metallic gate line boron-doped polysilicon area. This can achieve doped polysilicon structuring in the front electrode area of ​​the Topcon battery without increasing the shading loss, which can effectively improve the battery conversion efficiency. At the same time, the preparation method is compatible with conventional production lines, and the battery manufacturing cost is low.

[0058] In the above step 201, an N-type original silicon wafer of a certain size is selected for texturing treatment, that is, a double-surface pyramid structure is prepared. The resistivity of the N-type original silicon wafer is 0.1Ω·cm-0.8Ω·cm, the minority carrier lifetime is 200-300us, and the thickness is 100-180um.

[0059] In the above step 201, the texturing treatment is to use acid and alkaline solutions to remove the mechanical damage layer and metal ions on the surface of the single crystal N-type original silicon wafer, and at the same time form a "pyramid" appearance on the surface of the battery to improve the light trapping effect of the battery. The texturing treatment specifically includes pre-cleaning, alkaline solution texturing, and post-cleaning; wherein, the pre-cleaning tank is a mixed solution of HCL and H2O2, and the mass percentages of HCL and H2O2 are both 0.2-0.5%. The alkaline solution is NaOH or KOH, and the mass percentage of the solution is 0.4-1.3%, and the post-cleaning is carried out using a HF solution with a mass percentage of 0.1-0.3%; the above texturing treatment time is 50-60 minutes.

[0060] In the above step 201, the textured silicon wafer is sent into a furnace tube, and a first tunneling oxide layer and a polysilicon layer are deposited by low pressure chemical vapor deposition (LPCVD), plasma enhanced vapor deposition (PECVD) or atomic layer deposition (ALD) technology, and then the polysilicon layer is doped with boron by high temperature tubular thermal decomposition technology to form a boron-doped polysilicon layer.

[0061] Optionally, in one embodiment, forming a boron-doped polysilicon layer on the front side includes:

[0062] A polysilicon layer is formed on the front side of the silicon substrate, and then the polysilicon layer is subjected to boron deposition treatment by thermal decomposition, wherein the boron source includes at least one of boron tribromide and boron trichloride, the temperature is 900-1000° C., and the boron deposition time is 5-7 minutes.

[0063] In this embodiment, silane is used as a reactant to form a polysilicon layer on the first tunneling oxide layer on the front side of the silicon substrate, and then at least one of boron tribromide (BBr3) and boron trichloride (BCl3) is used as a boron source, and a high-temperature tubular thermal decomposition technology is used to perform boron doping deposition on the battery, and the deposition temperature is 900-1000°C and the boron deposition time is 5-7 minutes, so that a boron-doped polysilicon layer can be formed. Among them, the deposition temperature can be one of 900°C, 950°C, 1000°C, or any two of the range values; the boron deposition time can be one of 5 minutes, 6 minutes, or 7 minutes, or any two of the range values.

[0064] The thickness of the first tunnel oxide layer is 1-3 nm, and the thickness of the polysilicon layer is 100-200 nm.

[0065] In the above step 202, a laser is used to perform laser ablation on the second area on the front side of the battery, that is, to remove the borosilicate glass layer and the tunnel oxide layer in the non-metal electrode grid line area.

[0066] Optionally, in one implementation, the above step 202 specifically includes:

[0067] The second area is bombarded with a laser with a laser power of 5 to 15 watts, a frequency of 200 to 300 kHz, and a scanning speed of 15,000 to 20,000 mm / s.

[0068] Among them, the laser is preferably a picosecond laser, the laser power can be one of 5 W, 10 W, 15 W or any two of the range values, the laser frequency can be one of 200 KHz, 250 KHz, 300 KHz or any two of the range values, and the scanning rate can be one of 15000 mm / s, 17500 mm / s, 20000 mm / s or any two of the range values.

[0069] In the above step 203, boron diffusion treatment is performed on the entire front side of the battery to form a PN junction on the basis of the N-type silicon substrate at the second region, that is, to form a boron diffusion layer.

[0070] Optionally, in one implementation, the above step 203 specifically includes:

[0071] The front surface is subjected to boron diffusion treatment by thermal decomposition, wherein the boron source comprises at least one of boron tribromide and boron trichloride, the temperature is 900-1200° C., and the boron diffusion time is 60-120 minutes.

[0072] In this embodiment, high-temperature tubular diffusion is used to dope positive trivalent boron elements and form a PN junction with the N-si silicon substrate in the second region. The boron source includes at least one of boron tribromide (BBr3) and boron trichloride (BCl3). The main process of boron diffusion is heating, boron deposition, advancement and oxidation, high-temperature advancement, cooling, etc., wherein the heating rate is 200-300°C / s, the boron deposition temperature is 900-1200°C, the advancement oxidation temperature is 900-1100°C, and the boron diffusion time is 60-120min, thereby achieving effective boron diffusion treatment.

[0073] In the above step 203, after the boron diffusion on the front side and before the tunnel oxide layer is formed on the back side, the back side of the battery needs to be alkaline polished to polish the back side of the battery; wherein the alkaline polishing specifically includes pre-cleaning, alkaline washing, and acid washing; wherein the pre-cleaning solution is a mixed solution of HCL and H2O2, wherein the mass percentages of HCL and H2O2 are both 0.3-0.5%, the alkaline washing solution is a NaOH or KOH solution, wherein the mass percentage of the solution is 4-12%, and the acid washing solution is a HF solution with a mass percentage of 3-10% for cleaning; the above alkaline polishing treatment time is 30-60 minutes;

[0074] In the above step 203, the alkali-polished silicon wafer is sent into a furnace tube, and a second tunneling oxide layer and a polysilicon layer are deposited on the back side by low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD) technology, and then the polysilicon layer is phosphorus-doped by high temperature tubular thermal decomposition technology to form a phosphorus-doped polysilicon layer.

[0075] Optionally, in one embodiment, forming a phosphorus-doped polysilicon layer on the back side includes:

[0076] A polysilicon layer is formed on the front side of the silicon substrate, and then the polysilicon layer is subjected to phosphorus deposition treatment by thermal decomposition, wherein the phosphorus source includes POCl3, the temperature is 600-800°C, and the phosphorus deposition time is 5-7 minutes.

[0077] In this embodiment, silane is used as a reactant to form a polysilicon layer on the second tunnel oxide layer on the front side of the silicon substrate, and then POCl3 is used as a phosphorus source to perform phosphorus doping deposition on the battery using a high-temperature tubular thermal decomposition technique, with a deposition temperature of 600 to 800°C and a phosphorus deposition time of 5 to 7 minutes, thereby forming a phosphorus-doped polysilicon layer. The deposition temperature may be in the range of 600°C, 700°C, 800°C, or any two of them; the phosphorus deposition time may be in the range of 5 minutes, 6 minutes, or 7 minutes, or any two of them.

[0078] The thickness of the second tunnel oxide layer is 1-3 nm, and the thickness of the polysilicon layer is 100-200 nm.

[0079] In the above step 204, before forming the passivation film layer and the anti-reflection film layer on both sides, chain pickling can be performed, and then the front side is textured by wet method to remove the borosilicate glass layer left in the front area of ​​the battery after boron expansion.

[0080] Among them, chain pickling is based on chain cleaning equipment, and the battery is pickled with a high-concentration acid solution. The acid solution includes HF or HNO3, with a mass percentage of 5-15%; the wet method for front texturing uses a tank cleaning equipment to etch the front of the battery. The solution used is an alkaline solution such as NaOH or KOH with a mass percentage of 5-10%, and the time is 40-60 minutes.

[0081] In the above step 204, an aluminum oxide layer is deposited on the surface of the boron-doped polysilicon layer and the phosphorus-doped polysilicon layer by atomic layer deposition technology as the above passivation film layer, the thickness of which can be 3 to 5 nm, the process temperature of which is 200 to 300°C, and the deposition time of which is 7 to 12 min. Then, a layer of silicon oxynitride is deposited on the passivation film layer by PECVD technology, the thickness of which is 60 to 80 nm, the process temperature of which is 600 to 700°C, and the deposition time of which is 5 to 8 min, thereby forming the above front anti-reflection film layer and the back anti-reflection film layer.

[0082] In the above step 204, after forming the front and back anti-reflection layers, the front and back electrodes and electric fields of the battery are prepared using metal slurry as raw materials to achieve the purpose of collecting and transporting carriers, and then sintering is performed to form a positive electrode and a negative electrode respectively, wherein the metal slurry includes: silver, aluminum, and copper; then the battery is subjected to high-temperature sintering annealing treatment at 780-900°C to form a silver-aluminum alloy layer and a good ohmic contact, thereby improving the battery fill factor.

[0083] The present invention is described in detail below by way of examples.

[0084] Example 1

[0085] (1) Select an N-type original silicon wafer with a resistivity of 0.5Ω·cm, a minority carrier lifetime of 260us, and a thickness of 130um as a silicon substrate, and then use a mixed solution of 0.2-0.5% by mass of HCL and H2O2 for pre-cleaning, then use a 0.4% by mass NaOH solution for alkaline cleaning, and then use a 0.2% by mass HF solution for cleaning. The total cleaning time is 60 minutes to complete the texturing process;

[0086] (2) Using LPCVD technology to deposit a 1 nm thick silicon dioxide layer on the front electrode area, and then using silane as a reactant to deposit a 160 nm thick polysilicon layer on the silicon dioxide layer, and then using boron trichloride as a boron source, using high-temperature tubular thermal decomposition technology to perform boron doping deposition on the battery, the deposition temperature is 1000 ° C, the deposition time is 7 minutes, to form a boron-doped polysilicon layer;

[0087] (3) Under the conditions of power of 12 watts, frequency of 290 kHz, and scanning speed of 20,000 mm / s, a laser is used to bombard the area where the positive electrode is projected outside the front surface of the silicon substrate;

[0088] (4) Boron trichloride was used as the boron source and the battery was subjected to boron diffusion treatment using high-temperature tubular thermal decomposition technology, wherein the heating rate was 200°C / s, the boron deposition temperature was 900°C, the advancing oxidation temperature was 980°C, and the boron diffusion time was 90 min;

[0089] (5) After the boron diffusion treatment, the back of the battery is subjected to an alkali polishing treatment, wherein the pre-cleaning solution in the alkali polishing treatment is a mixed solution of HCL and H2O2, wherein the mass percentages of HCL and H2O2 are both 0.3%; the alkali washing solution is NaOH, wherein the mass percentage of the solution is 8%, and the acid washing solution is cleaned using an HF solution having a mass percentage of 8%; the alkali polishing treatment time is 45 minutes;

[0090] (6) The alkali-polished silicon wafer is fed into a furnace tube, and a silicon dioxide layer with a thickness of 1 nm is deposited on the back side by using LPCVD technology. Then, a polysilicon layer with a thickness of 120 nm is deposited on the silicon dioxide layer by using silane as a reactant. Then, POCl3 is used as a phosphorus source, and a high-temperature tubular thermal decomposition technology is used to perform phosphorus doping deposition on the battery. The deposition temperature is 600°C and the deposition time is 7 minutes to form a phosphorus-doped polysilicon layer.

[0091] (7) Use a 12% by mass hydrofluoric acid solution to chain acidify the silicon wafer, and then perform wet front texturing on the silicon wafer. The solution used is an 8% by mass NaOH solution for 50 minutes;

[0092] (8) A 5 nm thick aluminum oxide layer was deposited on the front and back surfaces by atomic layer deposition technology, the process temperature was 300°C, and the deposition time was 7 min; then a 60 nm thick silicon oxynitride layer was deposited on the surface of the aluminum oxide layer by PECVD technology, the process temperature was 600°C, and the deposition time was 8 min;

[0093] (9) Use silver paste to print the front and back gate lines, and then perform high-temperature sintering annealing at 860°C to prepare the front and back metal electrodes.

[0094] The prepared Topcon cell was subjected to an electrical performance IV test, and the results showed that its open circuit voltage was 0.7183V, the short circuit current was 13.918A, the fill factor was 84.63%, and the photoelectric conversion efficiency was 25.21%.

[0095] Compared with the conventional Topcon cell without a tunneling oxide layer / doped polysilicon layer structure on the front side, the overall efficiency of the front tunneling oxide layer Topcon cell prepared by the present invention is increased by about 0.03%, showing a higher efficiency advantage.

[0096] To sum up, in this embodiment, the N-type TOPCon cell provided has a first tunneling oxide layer and a boron-doped polysilicon layer in the positive electrode projection area, which can realize the doped polysilicon structuring of the front electrode area of ​​the Topcon cell without increasing the shading loss, thereby effectively improving the cell conversion efficiency.

[0097] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic creative concept. Therefore, the claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0098] The above is a detailed introduction to an N-type TOPCon battery and a preparation method thereof provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. An N-type TOPCon battery, characterized in that: It includes an N-type silicon substrate, a first tunneling oxide layer, a boron-doped polysilicon layer, a boron diffusion layer, a positive electrode, a second tunneling oxide layer, a phosphorus-doped polysilicon layer and a negative electrode; The first tunneling oxide layer, the boron-doped polysilicon layer and the positive electrode are sequentially deposited on a first region on the front side of the silicon substrate, and the first region is within the projection range of the positive electrode; The boron diffusion layer is deposited on a second region on the front side of the silicon substrate, and the second region is outside the projection range of the positive electrode; The second tunneling oxide layer, the phosphorus-doped polysilicon layer and the negative electrode are sequentially deposited on the back side of the silicon substrate.

2. The N-type TOPCon battery according to claim 1, characterized in that: The first tunneling oxide layer is a silicon dioxide layer with a thickness of 1 to 3 nm; the boron-doped polysilicon layer has a thickness of 100 to 200 nm.

3. The N-type TOPCon battery according to claim 2, characterized in that: The second tunneling oxide layer is a silicon dioxide layer with a thickness of 1 to 3 nm; the phosphorus-doped polysilicon layer has a thickness of 100 to 200 nm.

4. The N-type TOPCon battery according to claim 1, characterized in that: It also includes a first passivation film layer and a front anti-reflection film layer which are sequentially arranged on the front side of the silicon substrate.

5. The N-type TOPCon battery according to claim 4, characterized in that: The front anti-reflection film layer comprises a silicon oxynitride layer, and the thickness is 60 to 80 nm; The first passivation film layer is an aluminum oxide layer, and has a thickness of 3-5 nm.

6. The N-type TOPCon battery according to claim 1, characterized in that: It also includes a back anti-reflection film layer arranged on the surface of the phosphorus-doped polysilicon layer.

7. A method for preparing an N-type TOPCon battery, characterized in that: include: After the N-type silicon substrate is textured, a first tunneling oxide layer and a boron-doped polysilicon layer are formed on the front side; Performing laser ablation on a second area of ​​the silicon substrate, where the second area is an area where the positive electrode is projected outside the front surface of the silicon substrate; After laser ablation is performed on the second region, boron diffusion is performed on the front side of the silicon substrate, and a second tunneling oxide layer is formed on the back side, and a phosphorus-doped polysilicon layer is formed on the back side; After a phosphorus-doped polysilicon layer is formed on the back side, a passivation film layer, a front anti-reflection film layer, a back anti-reflection film layer and an electrode are formed in sequence.

8. The method for preparing an N-type TOPCon battery according to claim 7, characterized in that: Performing laser ablation on the second region of the silicon substrate, comprising: The second area is bombarded with a laser with a laser power of 5 to 15 watts, a frequency of 200 to 300 kHz, and a scanning speed of 15,000 to 20,000 mm / s.

9. The method for preparing an N-type TOPCon battery according to claim 7, characterized in that: A boron-doped polysilicon layer is formed on the front side, comprising: A polysilicon layer is formed on the front side of the silicon substrate, and then the polysilicon layer is subjected to boron deposition treatment by thermal decomposition, wherein the boron source includes at least one of boron tribromide and boron trichloride, the temperature is 900-1000° C., and the boron deposition time is 5-7 minutes.

10. The method for preparing an N-type TOPCon battery according to claim 7, characterized in that: Performing boron diffusion treatment on the front side of the silicon substrate, comprising: The front surface is subjected to boron diffusion treatment by thermal decomposition, wherein the boron source comprises at least one of boron tribromide and boron trichloride, the temperature is 900-1200° C., and the boron diffusion time is 60-120 minutes.

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