A micro-nano satellite payload controller circuit

Abstract

A micro-nano satellite payload controller circuit mainly includes a control circuit, a current sampling circuit, a motor drive circuit, a gas valve drive circuit, a blow valve drive circuit and a ceramic drive circuit. Compared with the traditional drive circuit, the present invention not only realizes the drive control of the micro-nano satellite payload, but also can realize accurate multi-component timing control, realize the flexible and transparent working mode of the micro-nano satellite payload, and can operate in multiple working modes according to the actual working conditions to meet the complex working conditions and reliability of the payload.

Description

Technical Field

[0001] The invention belongs to the technical field of motor control, and in particular relates to a micro-nano satellite payload controller circuit. Background Art

[0002] Micro-nano satellites refer to tiny satellites with a mass of less than 1,000 kg, mostly between 10 kg and 100 kg or even lighter. They have many remarkable features. Their small size and light weight make them easy to launch and deploy. They can often be launched with multiple satellites on one rocket, greatly reducing the launch cost. They have a short development cycle, generally only 1 to 2 years. They are inexpensive, ranging from millions to tens of millions of dollars. Their individual functions are relatively simple, but they can be networked to achieve complex tasks such as distributed observation and communication networking. They play an important role in the fields of communication, earth observation, scientific exploration, and technology verification. With the development of related technologies, their technical performance is constantly improving, networking applications are becoming more and more extensive, and the process of commercialization and industrialization is also accelerating.

[0003] In the process of technology research and development of micro-nano satellites, there are a series of problems that need to be overcome in the field of multi-component timing signal generation and precise control. The motors, air valves, blow valves, piezoelectric ceramics and other components inside micro-nano satellites have different operating characteristics and different requirements for timing signals, such as voltage amplitude, signal waveform and other specific requirements. This requires that when designing FPGA circuits, it is necessary to fully consider how to enable it to generate timing signals that are suitable for various components to ensure that each component can respond accurately and achieve a working state where the start and end time is freely controllable, otherwise the complex functional system of micro-nano satellites will not be realized. At the same time, in order to achieve precise control of the timing of each component, many interference factors must be faced. The space environment where micro-nano satellites are located is extremely harsh, and problems such as circuit noise, signal transmission delay and clock signal jitter are common, which will seriously affect the accuracy of timing signals. Therefore, minimizing these interference effects through advanced circuit optimization technology and precise calibration mechanisms is the key to ensuring the accuracy of micro-nano satellite timing control. In addition, there are close and complex working logic relationships between the many components inside the micro-nano satellite. How to cleverly arrange their timing in the FPGA circuit so that they can operate in an orderly manner according to their respective set start and end times, and achieve efficient coordination at the overall level to avoid working abnormalities caused by mutual interference or timing conflicts between components is undoubtedly an extremely complex technical problem that requires in-depth research and solution.

[0004] There are also many key technical challenges in the precise measurement and control of the working time of micro-nano satellite components based on clock frequency counting. As the core basis for the change of reference time, the stability of clock frequency faces great challenges in the space environment. Space is full of various radiations and extreme temperature changes, which can easily cause clock frequency deviations. Therefore, how to cleverly use technical means such as radiation resistance and temperature compensation to ensure the high stability of clock frequency, and then ensure the accuracy of reference time, has become a technical difficulty that must be solved in micro-nano satellite time measurement and control technology. When combining multi-variable logical combinations and comparing with the start and stop time of multiple components, it is crucial to accurately construct logical relationships. Under different working modes and mission requirements, the variable relationships of multiple components of micro-nano satellites are intricate. It is necessary to conduct in-depth research on how to ensure that the changes of different variables can accurately correspond to the measurement and control of the actual working time of each component, so as to prevent time measurement errors caused by logical errors or incomplete consideration of variables. This urgently requires the establishment of a complete logic design and calibration system. In addition, during the working process of micro-nano satellite components, due to the uncertainty of the space environment, various emergencies may occur, causing the working time to deviate from expectations. Therefore, it is imperative to build a real-time monitoring and dynamic adjustment mechanism, through which the actual working time of each component can be tracked in real time, and the time control can be dynamically adjusted according to the monitoring results with the help of a suitable feedback mechanism, so as to always maintain accurate measurement and control of the working time of micro-nano satellite components.

[0005] There are also many technical points that need to be broken through in the integration and software design of micro-nano satellites to achieve lightweight, miniaturization and high reliability. In the process of integration, many different circuit modules and components are tightly integrated inside micro-nano satellites, and electromagnetic compatibility issues are particularly prominent. Electromagnetic interference is very easy to occur between the various parts, which will seriously affect the normal operation of the entire satellite system. Therefore, how to achieve harmonious coexistence of various parts in the extremely limited space of micro-nano satellites through scientific and reasonable layout design, efficient shielding measures and other electromagnetic compatibility design methods to ensure stable and reliable operation of the system is the key that must be solved in the integrated design stage. For software design, micro-nano satellites must rely on software to achieve rich and diverse functions, and adapt to limited hardware resources in complex space environments, such as storage capacity and computing power. At the same time, it is necessary to ensure that the software itself will not have reliability problems such as freezing and crashing during long-term operation. Therefore, carrying out effective software algorithm optimization, reasonable resource allocation, and building a stable and reliable software architecture and fault-tolerant mechanism have become technical problems that need to be overcome in the software design of micro-nano satellites. In addition, the space environment where micro-nano satellites are located is extremely harsh, with many unfavorable factors such as high vacuum, strong radiation, and extreme temperature changes. While striving to achieve lightweight and miniaturization of micro-nano satellite payload controllers, it is necessary to comprehensively consider multiple dimensions such as material selection, protection design, and redundant backup, and formulate a comprehensive response strategy to ensure that the payload controller can work stably and reliably in such a complex environment for a long time, and ensure the smooth execution of the overall mission of the micro-nano satellite. Summary of the invention

[0006] In order to solve the above technical problems, the present invention provides a micro-nano satellite payload controller circuit. The power converter based on the high-efficiency synchronous rectification circuit connects three groups of switch tubes in parallel on the secondary side of the transformer, i.e., the synchronous rectification end, each group consists of two MOS tubes, thereby increasing the current derating, increasing the current; reducing the conduction internal resistance, improving the efficiency; and preventing the output end voltage from being inverted. In addition, a synchronous rectification drive controller is added to the synchronous rectification circuit to shape the output waveform of the secondary side of the transformer, which is conducive to the conduction of the switch tube; the current at the output end of the transformer is relatively weak, and the current is expanded by adding a synchronous rectification drive controller to enhance the driving capability.

[0007] The present invention is achieved through the following technical solutions.

[0008] The present invention provides a micro-nano satellite payload controller circuit, comprising a control circuit, a current sampling circuit, a motor drive circuit, a gas valve drive circuit and a blow valve drive circuit.

[0009] The motor drive circuit includes a drive chip U4, a comparator U3, resistors R13~R17, capacitors C1~C5 and fuses F3~F4; one end of the resistor R13 is connected to the positive electrode of the power supply, and the other end is connected to one end of the capacitor C1 and the inverting end of the comparator U3, the other end of the capacitor C1 is grounded, one end of the resistor R14 is connected to the positive electrode of the power supply, and the other end is connected to one end of R15 and the in-phase end of the comparator U3, the other end of the resistor R15 is grounded, the output end of the comparator U3 is connected to the 7th pin of the drive chip U4, one end of the resistor R17 is connected to the positive electrode of the power supply, and the other end is connected to the 5th pin of the drive chip U4, one end of the resistor R16 is connected to the positive electrode of the power supply, and the other end is connected to the 6th pin of the drive chip U4, one end of the fuse F3 is connected to the positive electrode of the power supply and one end of the fuse F4, and the other end is connected to the 15th pin of the drive chip U4, 16 pin, the other end of the fuse F4 is connected to one end of the fuse F3 and the 15th and 16th pins of the driver chip U4, the 15th and 16th pins of the driver chip U4 are simultaneously connected to one end of the capacitor C3 and one end of the capacitor C4, the other end of the capacitor C3 is connected to one end of the capacitor C2, the other end of the capacitor C2 is grounded, the other end of the capacitor C4 is connected to one end of the capacitor C5, the other end of the capacitor C5 is connected to the 12th and 13th pins of the driver chip U4, the 12th and 13th pins of the driver chip U4 are simultaneously connected to the motor sampling end of the sampling circuit, the 1st pin of the driver chip U4 is connected to the PWMBH1 signal end, the 2nd pin is connected to the PWMBL1 signal end, the 3rd pin is connected to the PWMAL1 signal end, the 4th pin is connected to the PWMAH1 signal end, the 8th pin is connected to the PWMCL1 signal end, and the 9th pin is connected to the PWMCH1 signal end;

[0010] The gas valve driving circuit comprises a first P-tube driving circuit, a MOS tube V1, diodes D1-D2 and a gas valve; the input end of the first P-tube driving circuit is connected to the input signal QD1, the output end of the first P-tube driving circuit is connected to the gate of the MOS tube V1, the drain of the MOS tube V1 is connected to the positive electrode of the power supply, the source of the MOS tube V1 is connected to the cathode of the diode D1, the anode of the diode D1 is connected to the cathode of the diode D2, the anode of the diode D2 is connected to the gas valve sampling end of the sampling circuit, the drain of the MOS tube V1 is connected to one end of the gas valve, and the other end of the gas valve is connected to the anode of the diode D2;

[0011] The blowing valve driving circuit includes a second P-tube driving circuit, a MOS tube V2, diodes D1-D2 and a blowing valve; the input end of the second P-tube driving circuit is connected to the input signal QD2, the output end of the second P-tube driving circuit is connected to the gate of the MOS tube V2, the drain of the MOS tube V2 is connected to the positive pole of the power supply, the source of the MOS tube V2 is connected to the cathode of the diode D3, the anode of the diode D3 is connected to the cathode of the diode D4, the anode of the diode D4 is grounded, the drain of the MOS tube V2 is connected to one end of the blowing valve, and the other end of the blowing valve is connected to the anode of the diode D4;

[0012] The current sampling circuit includes resistors R1~R12, operational amplifiers U1A, U1B and U2, one end of the resistor R2 is connected to the motor sampling end of the motor drive circuit, and is also connected to one end of the resistor R11, the other end of the resistor R2 is connected to one end of the resistor R1, and is also connected to one end of the resistor R3, one end of the resistor R4, one end of the resistor R7, and one end of the resistor R9, the other end of the resistor R1 is connected to one end of the resistor R5 and is also grounded, the other end of the resistor R3 is connected to one end of the resistor R12 and is also connected to the valve sampling end of the valve drive circuit, the other end of the resistor R4 is connected to the in-phase end of the operational amplifier U1A, and the other end of the resistor R5 is connected to the inverting end of the operational amplifier U1A end, and is connected to one end of a resistor R6, the other end of which is connected to the output end of the operational amplifier U1A and is connected to the output signal Im, the other end of the resistor R11 is connected to the in-phase end of the operational amplifier U1B, the other end of the resistor R7 is connected to the inverting end of the operational amplifier U1B and is connected to one end of a resistor R8, the other end of which is connected to the output end of the operational amplifier U1B and is connected to the output signal Id, the other end of the resistor R12 is connected to the in-phase end of the operational amplifier U2, the other end of the resistor R9 is connected to the inverting end of the operational amplifier U2 and is connected to one end of a resistor R10, the other end of the resistor R10 is connected to the output end of the operational amplifier U2 and is connected to the output signal If;

[0013] The control circuit is provided with input terminals HA, HB, HC, Im, Id, and If, and also with output terminals PWMAH1, PWMAL1, PWMBH1, PWMBL1, PWMCH1, and PWMCL1. The input terminals HA, HB, and HC are respectively connected to the three-phase Hall signals HA, HB, and HC of the motor; the output terminals PWMAH1, PWMAL1, PWMBH1, PWMBL1, PWMCH1, and PWMCL1 of the control circuit are respectively connected to the signal terminals PWMAH1, PWMAL1, PWMBH1, PWMBL1, PWMCH1, and PWMCL1 of the motor drive circuit; the output terminal QD1 signal of the control circuit is connected to the input terminal signal QD1 of the gas valve drive circuit; the output terminal QD2 of the control circuit is connected to the input terminal signal QD2 of the blowing valve drive circuit; the input terminals Im, Id, and If of the control circuit are respectively connected to the output signal Im, the output signal Id, and the output signal If.

[0014] Furthermore, the control circuit is implemented by an FPGA field programmable gate array, using an APA600 series FPGA chip from Microchip Technology.

[0015] Furthermore, it also includes a ceramic drive circuit, which includes a third P-tube drive circuit, an N-tube drive circuit, MOS tubes V3~V4, resistors R19~R20 and piezoelectric ceramics; the control circuit is also provided with output terminals QD3 and QD4, and the output terminals QD3 and QD4 are respectively connected to output signals QD3 and QD4; the input terminal of the third P-tube drive circuit of the ceramic drive circuit is connected to the input signal QD3, the output terminal of the third P-tube drive circuit is connected to the gate of the MOS tube V3, the drain of the MOS tube V3 is connected to one end of the resistor R19, and the other end of the resistor R19 is connected to the positive electrode of the power supply, the input terminal of the N-tube drive circuit is connected to the input signal QD4, the output terminal of the N-tube drive circuit is connected to the gate of the MOS tube V4, the drain of the MOS tube V4 is connected to one end of the resistor R20, and the other end of the resistor R20 is connected to the source of the MOS tube V3, the source of the MOS tube V4 is grounded, the source of the MOS tube V3 is connected to one end of the piezoelectric ceramic, and the other end of the piezoelectric ceramic is connected to the source of the MOS tube V4.

[0016] Furthermore, it also includes a filtering circuit, which is arranged at the signal input end of the motor drive circuit, the electric air valve drive circuit, the solenoid valve drive circuit, and the piezoelectric ceramic drive circuit to filter and resist interference on the signal.

[0017] Furthermore, it also includes a communication circuit, which is connected to the control circuit and inputs a control signal to the control circuit.

[0018] Furthermore, it also includes a power conversion circuit, which is multiple and respectively arranged at the power input ends of the control circuit, the current sampling circuit, the motor drive circuit, the air valve drive circuit and the blowing valve drive circuit.

[0019] Furthermore, it also includes a short-circuit protection circuit, which is multiple and respectively arranged at the power input end of the control circuit, the current sampling circuit, the motor drive circuit, the air valve drive circuit and the blowing valve drive circuit.

[0020] Furthermore, it also includes a surge current suppression circuit, and there are multiple surge current suppression circuits, which are respectively arranged at the power input ends of the control circuit, the current sampling circuit, the motor drive circuit, the air valve drive circuit and the blowing valve drive circuit.

[0021] The beneficial effects of the present invention are as follows: (1) Compared with the traditional control circuit, a micro-nano satellite payload controller circuit is designed with multiple short-circuit protection circuits, and the failure of one circuit does not affect other functional circuits, thereby improving the overall reliability of the controller; (2) The valve drive anti-reverse circuit is composed of two diodes in series, which improves the circuit reliability; (3) A delay circuit is designed at the enable end of the motor drive circuit to effectively prevent the controller from being powered on and outputting a drive signal with no fixed state during the microprocessor configuration, resulting in the upper and lower bridge MOS tubes being directly connected and failing; (4) Current sampling adopts a differential method, and the currents of multiple components can be directly collected, avoiding calculation errors caused by subtraction operations and phase errors; (5) The ceramic drive frequency and dead zone settings are realized by program changes. Compared with analog drive, parameter setting is easier, the influence of component dispersion and temperature drift is significantly reduced, and the consistency and accuracy are improved; (6) The drive control of each component is realized by program control, and the working time and timing control accuracy of each component is accurate to the microsecond level. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is the principle block diagram of the micro-nano satellite payload drive control circuit of the present invention

[0023] Figure 2 is a schematic diagram of a control circuit of the present invention;

[0024] Figure 3 is a schematic diagram of a current sampling circuit of the present invention;

[0025] Figure 4 is a connection diagram of a motor drive circuit of the present invention;

[0026] Figure 5 It is a connection diagram of the gas valve driving circuit of the present invention;

[0027] Figure 6 It is a connection diagram of the blow valve driving circuit of the present invention;

[0028] Figure 7 It is a connection diagram of the piezoelectric ceramic driving circuit of the present invention;

[0029] Figure 8 It is a driving workflow diagram of the present invention. DETAILED DESCRIPTION

[0030] The technical solution of the present invention is further described below, but the scope of protection claimed is not limited to the description.

[0031] like Figure 1 As shown in the figure, the main unit circuits of the micro-nano satellite payload controller include: short-circuit protection circuit, surge current suppression circuit, filter circuit, power conversion circuit, FPGA control circuit, motor drive circuit, electric valve drive circuit, solenoid valve drive circuit, piezoelectric ceramic drive circuit, pressure sampling circuit, and communication circuit. The short-circuit protection circuit is to prevent the internal circuit of the product from short-circuiting. First, it will fuse itself to protect the safety of the upstream power supply system, which is a reliable design. The surge current suppression circuit designs a unit circuit to suppress the current at the moment of power-on startup of the controller to a standard and appropriate range, which is also a protection for the upstream power supply system. The filter circuit performs anti-interference design on the subsequent motor drive circuit, electric valve drive circuit, solenoid valve drive circuit, and piezoelectric ceramic drive circuit to protect the circuit from external interference and also prevent the drive circuit from interfering with the outside world. As the control core, the FPGA control circuit generates timing signals, performs precise timing control, piezoelectric ceramic frequency control, and motor speed control on components such as motors, electric valves, solenoid valves, and piezoelectric ceramics, so that the four components can complete the work tasks under any time combination, and at the same time control the AD conversion circuit, collect pressure, and monitor.

[0032] like Figure 2 As shown, the control circuit input terminals HA, HB, HC are connected to the motor three-phase Hall signals HA, HB, HC; the control circuit output terminals PWMAH1, PWMAL1, PWMBH1, PWMBL1, PWMCH1, PWMCL1 are respectively connected to the input terminals PWMAH1, PWMAL1, PWMBH1, PWMBL1, PWMCH1, PWMCL1 of the motor drive circuit; the control circuit output terminal QD1 signal is connected to the input terminal QD1 of the gas valve drive circuit; the control circuit output terminal QD2 is connected to the input terminal QD2 of the blowing valve drive circuit; the control circuit output terminal outputs QD3, QD4 are respectively connected to the input terminals QD3, QD4 of the ceramic drive circuit.

[0033] The control circuit is implemented based on FPGA processor and adopts APA600 series FPGA chip of Microchip Technology to realize signal acquisition, switch control and motor drive control. The acquired signals include three-phase Hall signals HA, HB and HC, bus current Im, motor current Id, valve current If and two-way pressure signals Ua and Ub. Switch control includes generating valve, blow valve and ceramic drive signals QD1, QD2, QD3 and QD4, and motor drive control signals PWMAH1, PWMAL1, PWMBH1, PWMBL1, PWMCH1 and PWMCL1.

[0034] Since the control circuit is implemented based on the FPGA processor, the multi-functional expansion function can be realized through software without changing or slightly changing the hardware. Therefore, a micro-nano satellite payload controller design is proposed, which is easy to realize multi-component timing control.

[0035] like Figure 3 As shown, one end of the resistor R2 in the current sampling circuit is connected to the motor sampling end of the motor driving circuit, and is connected to one end of the resistor R11 at the same time. The other end of the resistor R2 is connected to one end of the resistor R1, and is connected to one end of the resistor R3, one end of the resistor R4, one end of the resistor R7, and one end of the resistor R9 at the same time. The other end of the resistor R1 is connected to one end of the resistor R5 and is grounded at the same time. The other end of the resistor R3 is connected to one end of the resistor R12 and is connected to the valve sampling end of the valve driving circuit at the same time. The other end of the resistor R4 is connected to the in-phase end (pin 3) of the operational amplifier U1. The other end of the resistor R5 is connected to the inverting end (pin 2) of the operational amplifier U1 and is connected to one end of the resistor R6 at the same time. The other end of resistor R6 is connected to the output end of operational amplifier U1 and to the input end Im of the control circuit. The other end of resistor R11 is connected to the non-inverting end (pin 5) of operational amplifier U1. The other end of resistor R7 is connected to the inverting end (pin 6) of operational amplifier U1 and to one end of resistor R8. The other end of resistor R8 is connected to the output end of operational amplifier U1 and to the input end Id of the control circuit. The other end of resistor R12 is connected to the non-inverting end (pin 3) of operational amplifier U2. The other end of resistor R9 is connected to the inverting end (pin 2) of operational amplifier U2 and to one end of resistor R10. The other end of resistor R10 is connected to the output end of operational amplifier U2 and to the input end If of the control circuit.

[0036] like Figure 4As shown, the motor drive circuit is composed of an integrated circuit U4 and peripheral resistors and capacitors. One end of the resistor R13 is connected to the positive pole of the power supply, and the other end is connected to one end of the capacitor C1 and the inverting end (pin 6) of the comparator U3. The other end of the capacitor C1 is grounded. One end of the resistor R14 is connected to the positive pole of the power supply, and the other end is connected to one end of R15 and the non-inverting end (pin 7) of the comparator U3. The other end of the resistor R15 is grounded. The output end (pin 1) of the comparator is connected to the enable end EN (pin 7) of the integrated circuit U4. One end of the resistor R17 is connected to the positive pole of the power supply, and the other end is connected to the 5th pin of the integrated circuit U4. One end of the resistor R16 is connected to the positive pole of the power supply, and the other end is connected to the 6th pin of the integrated circuit U4. One end of the fuse F3 is connected to the positive pole of the power supply and one end of the fuse F4, and the other end is connected to the 15th and 16th pins of the integrated circuit U4. The other end of the fuse F4 is connected to one end of the fuse F3 and the 15th and 16th pins of the integrated circuit U4. The 15th and 16th pins of the integrated circuit are simultaneously connected to one end of the capacitor C3 and one end of the capacitor C4. The other end of the capacitor C3 is connected to one end of the capacitor C2, and the other end of the capacitor C2 is grounded. The other end of the capacitor C4 is connected to one end of the capacitor C5, and the other end of the capacitor C5 is connected to the 12th and 13th pins of the integrated circuit. The 12th and 13th pins of the integrated circuit are simultaneously connected to the motor sampling end of the sampling circuit.

[0037] like Figure 5-6 As shown, the gas valve and the blow valve are both composed of a solenoid valve drive circuit, which is composed of a MOS tube and its drive circuit. The solenoid valve is provided with an anti-reverse circuit composed of a series diode to eliminate the turn-off peak voltage and protect the MOS tube device. The gas valve drive circuit inputs the QD1 signal to connect the input end of the P tube drive circuit, the output end of the P tube drive circuit is connected to the gate of the MOS tube V1, the drain of the MOS tube V1 is connected to the positive pole of the power supply, the source of the MOS tube V1 is connected to the cathode of the diode D1, the anode of the diode D1 is connected to the cathode of the diode D2, the anode of the diode D2 is connected to the gas valve sampling end of the sampling circuit, the drain of the MOS tube V1 is connected to one end of the gas valve, and the other end of the gas valve is connected to the anode of the diode D2. The blow valve driving circuit inputs a QD2 signal to connect the input end of the P tube driving circuit, the output end of the P tube driving circuit is connected to the gate of the MOS tube V2, the drain of the MOS tube V2 is connected to the positive pole of the power supply, the source of the MOS tube V2 is connected to the cathode of the diode D3, the anode of the diode D3 is connected to the cathode of the diode D4, the anode of the diode D4 is grounded, the drain of the MOS tube V2 is connected to one end of the blow valve, and the other end of the blow valve is connected to the anode of the diode D4.

[0038] like Figure 7As shown, the ceramic drive circuit includes power tubes P tube V1 and N tube V2, a P tube drive circuit and an N tube drive circuit. Two complementary drive signals are output by FPGA to control the gate signals of the P tube and the N tube respectively. The dead time is simple, adjustable and controllable, and easy to implement. The ceramic drive circuit inputs a QD3 signal to connect the input end of the P tube drive circuit, the output end of the P tube drive circuit is connected to the gate of the MOS tube V3, the drain of the MOS tube V3 is connected to one end of the resistor R19, and the other end of the resistor R19 is connected to the positive electrode of the power supply. The input QD4 signal is connected to the input end of the N tube drive circuit, the output end of the N tube drive circuit is connected to the gate of the MOS tube V4, the drain of the MOS tube V4 is connected to one end of the resistor R20, and the other end of the resistor R20 is connected to the source of the MOS tube V3, the source of the MOS tube V4 is grounded, the source of the MOS tube V3 is connected to one end of the piezoelectric ceramic, and the other end of the piezoelectric ceramic is connected to the source of the MOS tube V4.

[0039] like Figure 8 As shown in the figure, it is the control process of the control circuit of the present invention. It can be seen from the figure that the running time of the components such as the motor, electric valve, solenoid valve, piezoelectric ceramics, etc. is set by the start time and the end time, and can be set arbitrarily. When the system starts the running instruction, the components such as the motor, electric valve, solenoid valve, piezoelectric ceramics, etc. strictly operate according to the timing. Only when the end time is greater than the start time, each component will work, and when any component is still in the working state, setting or starting the running instruction again is invalid; only when each component completes the work can it be set or started again.

[0040] After receiving the start command, the controller determines that the start flag (initial value is 0) is 0, and sets the execution parameter completion flag to 1. When the parameter completion flag is 1 in the next clock cycle, the start and end times of the four components are first determined. When the start time is less than the end time, each component can start working, and the start flag is set to 1 at the same time. When the start flag is detected to be 1, the count register running time starts to accumulate counting driven by the clock frequency. When the count value is greater than the component opening time but less than the closing time, the component working flag (motor start flag, gas valve start flag, blow valve start flag, ceramic start flag) is set to 1 and the component starts working. When the count value is greater than the component closing time, the component working flag (motor start flag, gas valve start flag, blow valve start flag, ceramic start flag) is set to 0 and the component stops working. When the component stops working, the corresponding component completion flag (motor stop flag, gas valve closing flag, blow valve closing flag, ceramic closing flag) is set to 1. Only when all four components stop working, the count register running time is set to 1, and the start flag is reset (set to 0) and waits for the next start instruction. As long as one component is still working, the start flag remains 1 and the next start instruction is not executed.

Claims

1. A micro-nano satellite payload controller circuit, characterized in that: It includes a control circuit, a current sampling circuit, a motor drive circuit, a gas valve drive circuit and a blow valve drive circuit. The motor drive circuit includes a drive chip U4, a comparator U3, resistors R13 to R17, capacitors C1 to C5 and fuses F3 to F4; one end of the resistor R13 is connected to the positive electrode of the power supply, and the other end is connected to one end of the capacitor C1 and the inverting end of the comparator U3, the other end of the capacitor C1 is grounded, one end of the resistor R14 is connected to the positive electrode of the power supply, and the other end is connected to one end of R15 and the in-phase end of the comparator U3, the other end of the resistor R15 is grounded, the output end of the comparator U3 is connected to the 7th pin of the drive chip U4, one end of the resistor R17 is connected to the positive electrode of the power supply, and the other end is connected to the 5th pin of the drive chip U4, one end of the resistor R16 is connected to the positive electrode of the power supply, and the other end is connected to the 6th pin of the drive chip U4, one end of the fuse F3 is connected to the positive electrode of the power supply and one end of the fuse F4, and the other end is connected to the 15th pin of the drive chip U4, 16 pin, the other end of the fuse F4 is connected to one end of the fuse F3 and the 15th and 16th pins of the driver chip U4, the 15th and 16th pins of the driver chip U4 are simultaneously connected to one end of the capacitor C3 and one end of the capacitor C4, the other end of the capacitor C3 is connected to one end of the capacitor C2, the other end of the capacitor C2 is grounded, the other end of the capacitor C4 is connected to one end of the capacitor C5, the other end of the capacitor C5 is connected to the 12th and 13th pins of the driver chip U4, the 12th and 13th pins of the driver chip U4 are simultaneously connected to the motor sampling end of the sampling circuit, the 1st pin of the driver chip U4 is connected to the PWMBH1 signal end, the 2nd pin is connected to the PWMBL1 signal end, the 3rd pin is connected to the PWMAL1 signal end, the 4th pin is connected to the PWMAH1 signal end, the 8th pin is connected to the PWMCL1 signal end, and the 9th pin is connected to the PWMCH1 signal end; The gas valve driving circuit comprises a first P-tube driving circuit, a MOS tube V1, diodes D1-D2 and a gas valve; the input end of the first P-tube driving circuit is connected to the input signal QD1, the output end of the first P-tube driving circuit is connected to the gate of the MOS tube V1, the drain of the MOS tube V1 is connected to the positive electrode of the power supply, the source of the MOS tube V1 is connected to the cathode of the diode D1, the anode of the diode D1 is connected to the cathode of the diode D2, the anode of the diode D2 is connected to the gas valve sampling end of the sampling circuit, the drain of the MOS tube V1 is connected to one end of the gas valve, and the other end of the gas valve is connected to the anode of the diode D2; The blow valve driving circuit includes a second P-tube driving circuit, a MOS tube V2, diodes D1-D2 and a blow valve; the input end of the second P-tube driving circuit is connected to the input signal QD2, the output end of the second P-tube driving circuit is connected to the gate of the MOS tube V2, the drain of the MOS tube V2 is connected to the positive pole of the power supply, the source of the MOS tube V2 is connected to the cathode of the diode D3, the anode of the diode D3 is connected to the cathode of the diode D4, the anode of the diode D4 is grounded, the drain of the MOS tube V2 is connected to one end of the blow valve, and the other end of the blow valve is connected to the anode of the diode D4; The current sampling circuit includes resistors R1 to R12, operational amplifiers U1A, U1B and U2, one end of the resistor R2 is connected to the motor sampling end of the motor drive circuit, and is also connected to one end of the resistor R11, the other end of the resistor R2 is connected to one end of the resistor R1, and is also connected to one end of the resistor R3, one end of the resistor R4, one end of the resistor R7, and one end of the resistor R9, the other end of the resistor R1 is connected to one end of the resistor R5 and is also grounded, the other end of the resistor R3 is connected to one end of the resistor R12 and is also connected to the valve sampling end of the valve drive circuit, the other end of the resistor R4 is connected to the in-phase end of the operational amplifier U1A, and the other end of the resistor R5 is connected to the inverting end of the operational amplifier U1A end, and is connected to one end of a resistor R6, the other end of which is connected to the output end of the operational amplifier U1A and is connected to the output signal Im, the other end of the resistor R11 is connected to the in-phase end of the operational amplifier U1B, the other end of the resistor R7 is connected to the inverting end of the operational amplifier U1B and is connected to one end of a resistor R8, the other end of which is connected to the output end of the operational amplifier U1B and is connected to the output signal Id, the other end of the resistor R12 is connected to the in-phase end of the operational amplifier U2, the other end of the resistor R9 is connected to the inverting end of the operational amplifier U2 and is connected to one end of a resistor R10, the other end of the resistor R10 is connected to the output end of the operational amplifier U2 and is connected to the output signal If; The control circuit is provided with input terminals HA, HB, HC, Im, Id, If, and also with output terminals PWMAH1, PWMAL1, PWMBH1, PWMBL1, PWMCH1, PWMCL1, wherein the input terminals HA, HB, HC are respectively connected to the three-phase Hall signals HA, HB, HC of the motor, and the output terminals PWMAH1, PWMAL1, PWMBH1, PWMBL1, PWMCH1, PWMCL1 of the control circuit are respectively connected to the signal terminals PWMAH1, PWMAL1, PWMBH1, PWMBL1, PWMCH1, PWMCL1 of the motor drive circuit; the output terminal QD1 signal of the control circuit is connected to the input terminal signal QD1 of the gas valve drive circuit; the output terminal QD2 of the control circuit is connected to the input terminal signal QD2 of the blowing valve drive circuit; the input terminals Im, Id and If of the control circuit are respectively connected to the output signal Im, the output signal Id and the output signal If; The control circuit is implemented by an FPGA field programmable gate array.

2. The micro-nano satellite payload controller circuit according to claim 1, characterized in that: It also includes a ceramic drive circuit, which includes a third P-tube drive circuit, an N-tube drive circuit, MOS tubes V3-V4, resistors R19-R20 and piezoelectric ceramics; the control circuit is also provided with output terminals QD3 and QD4, and the output terminals QD3 and QD4 are connected to output signals QD3 and QD4 respectively; The input end of the third P-tube driving circuit of the ceramic driving circuit is connected to the input signal QD3, the output end of the third P-tube driving circuit is connected to the gate of the MOS tube V3, the drain of the MOS tube V3 is connected to one end of the resistor R19, and the other end of the resistor R19 is connected to the positive electrode of the power supply, the input end of the N-tube driving circuit is connected to the input signal QD4, the output end of the N-tube driving circuit is connected to the gate of the MOS tube V4, the drain of the MOS tube V4 is connected to one end of the resistor R20, and the other end of the resistor R20 is connected to the source of the MOS tube V3, the source of the MOS tube V4 is grounded, the source of the MOS tube V3 is connected to one end of the piezoelectric ceramic, and the other end of the piezoelectric ceramic is connected to the source of the MOS tube V4.

3. The micro-nano satellite payload controller circuit according to claim 1, characterized in that: It also includes a filter circuit, which is arranged at the signal input end of the motor drive circuit, the electric air valve drive circuit, the solenoid valve drive circuit, and the piezoelectric ceramic drive circuit to filter and resist interference on the signal.

4. The micro-nano satellite payload controller circuit according to claim 1, characterized in that: It also includes a communication circuit, which is connected to the control circuit and inputs a control signal to the control circuit.

5. The micro-nano satellite payload controller circuit according to claim 1, characterized in that: It also includes a power conversion circuit, which is multiple and respectively arranged at the power input ends of the control circuit, the current sampling circuit, the motor drive circuit, the air valve drive circuit and the blowing valve drive circuit.

6. The micro-nano satellite payload controller circuit according to claim 1, characterized in that: It also includes a short-circuit protection circuit. There are multiple short-circuit protection circuits, which are respectively arranged at the power input ends of the control circuit, the current sampling circuit, the motor drive circuit, the air valve drive circuit and the blowing valve drive circuit.

7. The micro-nano satellite payload controller circuit according to claim 1, characterized in that: It also includes a surge current suppression circuit, which is multiple and respectively arranged at the power input ends of the control circuit, the current sampling circuit, the motor drive circuit, the air valve drive circuit and the blowing valve drive circuit.

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