Frequency modulation method of electronic equipment and electronic equipment

Abstract

The invention provides a frequency modulation method of electronic equipment and the electronic equipment, and relates to the field of terminals.The method comprises the steps that a first computing power difference and a first frequency point value of a processor in a first frequency modulation period are obtained, the first computing power difference is in positive correlation with a difference value between a load duty ratio of the processor in the first frequency modulation period and a target load duty ratio; based on the first computing power difference and the first frequency point value, a second frequency point value of the processor in a second frequency modulation period is determined, and the second frequency modulation period is after the first frequency modulation period; and adjusting the frequency point value of the processor based on the second frequency point value in the second frequency modulation period. According to the technical scheme provided by the invention, the flexibility and accuracy of frequency modulation can be improved, on-demand supply of the frequency point values of the processor is realized, the response speed is high, and the problems of over-supply and under-supply of the frequency point values are solved.

Description

[0001] This application claims the priority of the Chinese patent application filed with the State Intellectual Property Office on August 29, 2023, with application number 202311103322.4 and application name “Frequency Modulation Method and Electronic Device for Processor”, all contents of which are incorporated by reference in this application. Technical Field

[0002] The present application relates to the field of terminals, and in particular to a frequency modulation method of an electronic device and the electronic device. Background Art

[0003] Processor frequency modulation is a technology that reasonably configures the frequency value of the processor according to the processor load. Its purpose is to make the processor performance meet the current load requirements without generating unnecessary power consumption.

[0004] In the prior art, one or more frequency-boosting scenarios can be set in advance, such as application cold start, sliding operation, click-to-switch operation, etc. When the electronic device is running, the current business scenario can be identified. When the business scenario is a pre-set frequency-boosting scenario, the frequency value of the processor is increased to a fixed frequency value and continued for a fixed duration. However, under this frequency modulation strategy, since the frequency value of the processor is increased to a fixed frequency value and continued for a fixed duration, and the fixed frequency value and fixed duration do not fully match the current business scenario, the frequency value may be too high and the frequency-boosting time may be too long, which may lead to problems such as excess computing power, waste of power consumption, and heat generation of the processor. The frequency value may also be too low or the frequency-boosting time may be too short, which cannot meet the needs of the current business scenario. For example, the duration of the business scenario exceeds the frequency-boosting duration, resulting in problems such as freezes and loss of response, and poor performance experience. Summary of the invention

[0005] In view of this, the present application provides a frequency modulation method for an electronic device and an electronic device, which can improve the flexibility and accuracy of frequency modulation, realize on-demand supply of frequency point values ​​of the processor, have a fast response speed, and improve the problem of oversupply and undersupply of frequency point values.

[0006] In order to achieve the above-mentioned purpose, in a first aspect, an embodiment of the present application provides a frequency modulation method of an electronic device, comprising:

[0007] Obtain a first computing power difference and a first frequency point value of the processor in a first frequency modulation cycle, wherein the first computing power difference is positively correlated with a difference between a load duty cycle of the processor in the first frequency modulation cycle and a target load duty cycle; determine a second frequency point value of the processor in a second frequency modulation cycle based on the first computing power difference and the first frequency point value, wherein the second frequency modulation cycle is after the first frequency modulation cycle; and in the second frequency modulation cycle, adjust the frequency point value of the processor based on the second frequency point value.

[0008] In an embodiment of the present application, the first computing power difference and the first frequency point value of the processor in the first frequency modulation cycle can be obtained. Since the first computing power difference is positively correlated with the difference between the load duty cycle of the processor in the first frequency modulation cycle and the target load duty cycle, and the load duty cycle can be used as a load measurement value of the processor in the first frequency modulation cycle, the first computing power difference can indicate the difference between the computing power actually provided by the processor in the first frequency modulation cycle and the target computing power. The second frequency point value of the processor in the second frequency modulation cycle is determined by the first computing power difference and the first frequency point value of the processor in the first frequency modulation cycle. In the second frequency modulation cycle, the frequency point value of the processor is adjusted based on the second frequency point value, which can improve the flexibility and accuracy of frequency modulation, realize the on-demand supply of the frequency point value of the processor, and have a fast response speed. It improves the problem of oversupply and undersupply of frequency point values, and does not need to set the frequency increase scenario in advance, and has good generalization.

[0009] In some embodiments, the electronic device includes a single-core processor chip, on which a processor core is packaged, and the processor may refer to the single-core processor chip or a processor core in the single-core processor chip. In some embodiments, the electronic device includes a multi-core processor chip, on which a plurality of processor cores are packaged, and the processor may refer to any processor core in the multi-core processor chip.

[0010] In some embodiments, obtaining the first computing power difference of the processor in the first frequency modulation period includes: obtaining the number of clock cycles consumed by the processor to execute instructions in the first frequency modulation period; determining the load duty cycle of the processor in the first frequency modulation period based on the number of clock cycles; and determining the first computing power difference based on the load duty cycle and the target load duty cycle.

[0011] In some embodiments, obtaining the number of clock cycles consumed by the processor to execute instructions in the first frequency modulation cycle includes: obtaining the number of clock cycles consumed by the processor to execute instructions in the first frequency modulation cycle through a performance monitoring unit (PMU) or a register.

[0012] In some implementations, the PMU may implement counting of performance data through registers.

[0013] Clock cycle, also known as clock_cycle or beat. Clock cycle is the reciprocal of clock frequency. The frequency value of the processor can determine the maximum number of clock cycles that the processor can generate in the same time. In the same time, when the frequency value of the processor is higher, the maximum number of clock cycles that the processor can generate is greater, that is, the processor can complete more instructions under the same efficiency.

[0014] The number of clock cycles consumed by the processor in each frequency modulation cycle is obtained through hardware such as the PMU or a PMU register, so that the load condition of the processor in each frequency modulation cycle can be determined more accurately.

[0015] In some implementations, the frequency modulation cycle can be divided by a time base (tick). The time base is a relative time unit in the operating system, which is derived from the periodic interruption (output pulse) of the timer, and one interruption represents a tick. A time base can be set to the duration of a frequency modulation cycle. In each frequency modulation cycle, the processor register continuously collects the number of clock cycles consumed by the processor and determines whether the time base is reached. If not, the number of clock cycles consumed by the processor continues to be collected. If yes, the subsequent steps are continued.

[0016] In some embodiments, determining the second frequency point value of the processor in the second frequency modulation cycle based on the first computing power difference and the first frequency point value includes: determining the second frequency point value of the processor in the second frequency modulation cycle based on at least one of the first computing power difference and the first frequency point value, and the second computing power difference and the sum of the computing power difference of the processor in at least one historical frequency modulation cycle, the second computing power difference being the computing power difference of the processor in a third frequency modulation cycle, and the third frequency modulation cycle being before the first frequency modulation cycle.

[0017] In some implementations, the at least one historical frequency modulation period may include a first frequency modulation period and a third frequency modulation period.

[0018] In some embodiments, the method also includes: starting from the moment when the first frequency modulation cycle ends, if the second frequency point value of the processor in the second frequency modulation cycle is not determined within a first time period based on the first computing power difference and the first frequency point value, and the second computing power difference and the sum of the computing power difference of the processor in the at least one historical frequency modulation cycle, then deleting the first computing power difference, the first frequency point value, the second computing power difference and the sum of the computing power difference of the processor in the at least one historical frequency modulation cycle.

[0019] In some implementations, the first duration is an integer multiple of the frequency modulation period. For example, the frequency modulation period is 4 ms, and the first duration may be 5 times the frequency modulation period, that is, 20 ms.

[0020] When the second frequency point value of the processor in the second frequency modulation cycle is not determined within the first duration from the moment when the first frequency modulation cycle ends, it means that the second duration from the end of the first frequency modulation cycle to the current time is greater than or equal to the preset first duration, that is, the duration of the first frequency modulation cycle from the current moment is long, and the load condition and business scenario of the electronic device may have changed significantly. Therefore, based on the number of clock cycles, computing power and other data in the historical frequency modulation cycles including the first frequency modulation cycle, it is difficult to very accurately determine the frequency point value of the processor in the frequency modulation cycle after the current moment, so the first computing power difference, the first frequency point value, the second computing power difference and the sum of the computing power difference of the processor in at least one historical frequency modulation cycle can be deleted. Alternatively, it can be understood as initializing the first computing power difference, the first frequency point value, the second computing power difference and the sum of the computing power difference of the processor in at least one historical frequency modulation cycle.

[0021] In some embodiments, determining the second frequency value of the processor in the second frequency modulation period based on the first computing power difference and the first frequency value includes: determining the second frequency value of the processor in the second frequency modulation period based on a closed-loop feedback loop type algorithm, the first computing power difference and the first frequency value, the closed-loop feedback loop type algorithm including proportional control, and at least one of integral control and differential control.

[0022] In some embodiments, the processor can achieve proportional control of the frequency value by using the first computing power difference in the first frequency modulation period. When the first computing power difference is larger, the proportional control effect is larger, and the difference between the second frequency value and the first frequency value is also larger, so that the real computing power of the processor matches the load faster; when the first computing power difference is smaller, the proportional control effect is smaller, and the difference between the second frequency value and the first frequency value is also smaller, avoiding overmodulation.

[0023] In some embodiments, the processor can realize the integral control of the frequency point value by summing the computing power difference in at least one historical frequency modulation cycle before the second frequency modulation cycle. When the sum of the computing power difference is larger, the integral control effect is larger to reduce the static error; when the sum of the computing power difference is smaller, the integral control effect is smaller to avoid integral saturation.

[0024] In some embodiments, the difference between the first computing power difference of the processor in the first frequency modulation cycle and the second computing power difference of the processor in the third frequency modulation cycle can reflect the rate of change of the computing power difference. The third frequency modulation cycle can be before the first frequency modulation cycle. When the rate of change is greater, the differential control effect is greater, and the difference between the first frequency point value and the second frequency point value is also greater, so that the actual computing power of the processor matches the load faster; when the rate of change is smaller, the differential control effect is smaller, and the difference between the first frequency point value and the second frequency point value is also smaller, avoiding overmodulation.

[0025] In some embodiments, the third frequency modulation cycle may be a frequency modulation cycle before the first frequency modulation cycle, the second frequency modulation cycle may be a frequency modulation cycle after the first frequency modulation cycle, and the time interval between the third frequency modulation cycle and the first frequency modulation cycle and the time interval between the first frequency modulation cycle and the second frequency modulation cycle are less than five times the frequency modulation cycle. Exemplarily, the frequency modulation cycle is 4ms, and the time interval between the third frequency modulation cycle and the first frequency modulation cycle and the time interval between the first frequency modulation cycle and the second frequency modulation cycle are both less than 20ms.

[0026] In some implementations, adjusting the frequency value of the processor based on the second frequency value during the second frequency modulation period includes: setting the frequency value of the processor to the second frequency value during the second frequency modulation period.

[0027] In some implementations, the second frequency value may be used as a frequency reference value, and the electronic device may determine whether to set the frequency value of the processor to the second frequency value in the second frequency modulation period by a pre-set decision-making method.

[0028] In a second aspect, an embodiment of the present application provides a frequency modulation method for an electronic device, including: a frequency modulation method for an electronic device, including: identifying a business scenario of the electronic device; in response to the business scenario being a specific scenario, obtaining a first computing power difference and a first frequency point value of the processor in a first frequency modulation cycle, the first computing power difference being positively correlated with a difference between a load duty cycle of the processor in the first frequency modulation cycle and a target load duty cycle; based on the first computing power difference and the first frequency point value, determining a second frequency point value of the processor in a second frequency modulation cycle, the second frequency modulation cycle being after the first frequency modulation cycle; in the second frequency modulation cycle, adjusting the frequency point value of the processor based on the second frequency point value.

[0029] In an embodiment of the present application, the business scenario in which the electronic device is located can be identified, and when the electronic device is in a specific scenario, the frequency value of the processor can be supplied on demand with a fast response speed, thereby improving the problem of oversupply and undersupply of frequency value.

[0030] In some implementations, the specific scenario includes any of the following: launching an application, opening a status bar, switching a display interface, responding to an input operation, displaying an animation effect, and displaying a virtual keyboard.

[0031] Starting an application may include cold starting an application or hot starting an application. When starting an application, there is no process of the application in the background of the electronic device, and the electronic device will recreate a new process and assign it to the application. When hot starting an application, there is already a process of the application in the background, so if there is an existing process, the application can be started from the existing process.

[0032] The status bar can be used to display the operating status of the electronic device, such as network mode, message prompt mode, brightness, volume, etc. The user can query or configure the operating status of the electronic device by opening the status bar.

[0033] Switching the display interface may include switching between any multiple display interfaces of the electronic device. In some implementations, switching the display interface may include switching the display interface within an application, or may include switching the display interface between applications.

[0034] The input operation can be used for a user or other external object to input data into an electronic device. In some embodiments, the input operation can include a click operation or a touch operation on a display screen.

[0035] Displaying animation effects can be used to provide users with a more realistic and dynamic visual experience. In some embodiments, corresponding animation effects can be displayed in response to user operations. For example, dynamic switching effects when switching display interfaces.

[0036] The virtual keyboard can be used to receive text and other data input by the user.

[0037] In a third aspect, an embodiment of the present application provides a frequency modulation device for an electronic device, which has the function of realizing the above-mentioned aspects and the behaviors of the electronic device in the possible implementation methods of the above-mentioned aspects. The functions can be implemented by hardware, or by hardware executing corresponding software implementations. The hardware or software includes one or more modules or units corresponding to the above-mentioned functions. For example, a transceiver module or unit, a processing module or unit, an acquisition module or unit, etc.

[0038] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising: a memory and a processor, the memory being used to store a computer program; the processor being used to execute any one of the methods described in the first aspect above when calling the computer program.

[0039] In a fifth aspect, an embodiment of the present application provides a chip system, which includes a processor, the processor is coupled to a memory, and the processor executes a computer program stored in the memory to implement any method described in the first aspect above.

[0040] The chip system may be a single chip or a chip module composed of multiple chips.

[0041] In a sixth aspect, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the method described in any one of the above-mentioned first aspects is implemented.

[0042] In a seventh aspect, an embodiment of the present application provides a computer program product. When the computer program product is run on an electronic device, the electronic device executes any one of the methods described in the first aspect.

[0043] It can be understood that the beneficial effects of the third to seventh aspects mentioned above can be found in the relevant descriptions in the first or second aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0045] Figure 2 A schematic diagram of a load following curve provided in an embodiment of the present application;

[0046] Figure 3 A flow chart of a frequency modulation method of an electronic device provided in an embodiment of the present application;

[0047] Figure 4 A flow chart of another frequency modulation method of an electronic device provided in an embodiment of the present application;

[0048] Figure 5 A flow chart of another frequency modulation method of an electronic device provided in an embodiment of the present application;

[0049] Figure 6 A flow chart of another frequency modulation method of an electronic device provided in an embodiment of the present application;

[0050] Figure 7 A schematic diagram of another load following curve provided in an embodiment of the present application. DETAILED DESCRIPTION

[0051] The frequency modulation method of the processor provided in the embodiment of the present application can be applied to electronic devices such as mobile phones, tablet computers, wearable devices, vehicle-mounted devices, augmented reality (AR) / virtual reality (VR) devices, laptop computers, ultra-mobile personal computers (UMPC), netbooks, personal digital assistants (PDA), etc. The embodiment of the present application does not impose any restrictions on the specific types of electronic devices.

[0052] Figure 1 1 is a schematic diagram of the structure of an electronic device 100 provided in an embodiment of the present application. The electronic device 100 may include a processor 110, a memory 120, a communication module 130, and the like.

[0053] The memory 120 is used to store program codes and data. In an embodiment of the present application, the processor 110 can execute computer-executable instructions stored in the memory 120 to control and manage the actions of the electronic device 100. The frequency value (also called frequency) of the processor 110 is the number of times the processor 110 clock cycle runs in one second. The processor 110 can run an operation in each clock cycle, so the larger the frequency value of the processor 110, the faster the operation speed of the processor 110, the better the performance, and the higher the power consumption. In some embodiments, the electronic device 100 may include one or more processors 110. In some embodiments, the electronic device 100 may include one or more frequency modulation strategies, and the electronic device 100 may adjust the frequency value of one or more processors 110 based on these frequency modulation strategies to achieve the purpose of balancing the power consumption and performance of the electronic device 100. In some embodiments, the electronic device 100 includes a single-core processor chip, and a processor core (core) is encapsulated on the single-core processor chip. The processor 110 may refer to a single-core processor chip or a processor core in the single-core processor chip. In some embodiments, the electronic device 100 includes a multi-core processor chip on which multiple processor cores are packaged, and the processor 110 may refer to any processor core in the multi-core processor chip.

[0054] The communication module 130 can be used for communication between various internal modules of the electronic device 100, or communication between the electronic device 100 and other external electronic devices. Exemplarily, if the electronic device 100 communicates with other electronic devices via a wired connection, the communication module 130 may include an interface, such as a USB interface. The USB interface may be an interface that complies with USB standard specifications, specifically a Mini USB interface, a Micro USB interface, a USB Type C interface, etc. The USB interface can be used to connect a charger to charge the electronic device 100, and can also be used to transmit data between the electronic device 100 and peripheral devices. It can also be used to connect headphones to play audio through the headphones. The interface can also be used to connect other electronic devices, such as AR devices.

[0055] Alternatively, the communication module 130 may include an audio device, a radio frequency circuit, a Bluetooth chip, a wireless fidelity (Wi-Fi) chip, a near-field communication technology (NFC) module, etc., and can achieve interaction between the electronic device 100 and other electronic devices in a variety of different ways.

[0056] Optionally, the electronic device 100 may further include a performance detection unit 140. The performance detection unit may directly collect corresponding events from various hardware such as a processor, and may also be associated with software to optimize the hardware or operating system. The performance detection unit 140 may include a register 141, which may be used to record original hardware events. In some embodiments, the register 141 may record the number of clock cycles consumed by the processor 110. In some embodiments, the performance detection unit 140 may further include a counter, and when the register 141 detects original hardware events, the register 141 may specifically count the number of a certain type of original detection event through the counter. In some embodiments, the register 141 may also be referred to as a PMU register.

[0057] Optionally, the electronic device 100 may further include a display screen 150 , and the display screen 150 may display images or videos in a human-computer interaction interface.

[0058] Optionally, the electronic device 100 may further include a peripheral device 160 , such as a mouse, a keyboard, a speaker, a microphone, etc.

[0059] It should be understood that, in addition to Figure 1 In addition to the various components or modules listed in the figure, the embodiment of the present application does not specifically limit the structure of the electronic device 100. In other embodiments of the present application, the electronic device 100 may also include more or fewer components than shown in the figure, or combine some components, or split some components, or arrange the components differently. The components shown in the figure can be implemented in hardware, software, or a combination of software and hardware.

[0060] In order to facilitate understanding of the technical solutions in the embodiments of the present application, the application scenarios of the embodiments of the present application are first introduced below.

[0061] The frequency point value of the processor, also known as the frequency, is the clock frequency of the processor, which can be understood as the operating frequency of the processor during operation. The higher the frequency point value, the faster the processor's operation speed.

[0062] Clock cycle, also known as clock_cycle or beat. Clock cycle is the reciprocal of clock frequency. Clock cycle is the basic time unit in electronic devices. In one clock cycle, electronic devices can only complete one "micro-operation" or several compatible "micro-operations" (no conflict or mutual interference on the data path). A collection of multiple "micro-operations" can constitute an instruction. The frequency value of the processor can determine the maximum number of clock cycles that the processor can generate in the same time, and in the same time, when the frequency value of the processor is higher, the maximum number of clock cycles that the processor can generate is larger, that is, the processor can complete more instructions under the same efficiency. However, it can be understood that the number of clock cycles actually consumed by the processor to execute instructions in the same time can be positively correlated with the load of the processor, and the actual number of clock cycles consumed is less than the maximum number of clock cycles that can be generated. For example, the frequency value of the processor is 2GHz, and a maximum of 2,000,000 clock cycles can be generated in 1ms, but the clock cycles actually consumed by the processor to execute instructions in 1ms can be less than 2,000,000.

[0063] Processor frequency modulation is a technology that reasonably configures the frequency value of the processor according to the processor load. Its purpose is to make the processor performance meet the current load requirements without generating unnecessary power consumption.

[0064] The following will be combined Figure 2 The load following curve diagram of the processor is shown in FIG. 1 , and several frequency increasing strategies of the example are introduced. Figure 2 In FIG. 1 , curve 1 is a load curve of a processor, curve 2 is a frequency point value curve corresponding to frequency modulation strategy 1, and curve 3 is a frequency point value curve corresponding to frequency modulation strategy 2.

[0065] In some frequency modulation strategies (i.e., frequency modulation strategy one), one or more frequency increase scenarios (e.g., boost scenarios) can be set in advance, such as application cold start, sliding operation, click switching operation, etc. When the electronic device is running, the current business scenario can be identified. When the business scenario is a pre-set frequency increase scenario, the frequency value of the processor is increased to a fixed frequency value and lasts for a fixed duration. However, under this frequency modulation strategy, since the frequency value of the processor is increased to a fixed frequency value and lasts for a fixed duration, and the fixed frequency value and fixed duration do not completely match the current business scenario, the frequency value may be too high and the frequency increase time may be too long (i.e., oversupply), which may lead to problems such as excess processor computing power, waste of power consumption, and heat generation. The frequency value may also be too low or the frequency increase time may be too short, which cannot meet the needs of the current business scenario (i.e., undersupply). For example, if the duration of the business scenario exceeds the frequency increase duration, problems such as freeze and loss of response may occur, and the performance experience is poor. In addition, long-term use of this frequency modulation strategy may also cause severe heat generation in electronic devices, leading to more serious problems such as frequency reduction, reduced display resolution, lower refresh rate, lower brightness, and loosening of the bonding structure between components, further affecting the user experience.

[0066] In some frequency modulation strategies (i.e., frequency modulation strategy 2), the processor load can be determined through the window-assisted load tracking algorithm (WALT). When the processor load reaches a preset value, the processor frequency value is increased. WALT can predict the processor load in the next window and output the frequency value based on the load of N windows in the processor history in units of time length windows. The default window used by the open source community is currently 20ms (milliseconds). However, the response speed of this frequency modulation strategy is very slow. In the case of sudden high load, the processor frequency cannot be increased in time, resulting in insufficient processor computing power and poor performance experience. After the load decreases, the frequency cannot be reduced in time, resulting in a waste of power consumption.

[0067] In order to solve at least some of the above technical problems, the present application provides a frequency modulation method for an electronic device. The frequency modulation strategy adopted by the frequency modulation method can be called frequency modulation strategy three. Frequency modulation strategy three can determine the frequency point value of the processor through closed-loop feedback loop algorithms such as PID (composite control of proportional, integral and differential superposition), PI (proportional integral control), and PD (proportional differential control), improve the flexibility and accuracy of frequency modulation, and realize the on-demand supply of the frequency point value of the processor, with fast response speed, improve the problem of oversupply and undersupply of the frequency point value, and do not need to identify the frequency increase scenario in advance to set the corresponding frequency modulation strategy, which has good generalization. Frequency modulation strategy three can determine the load of the processor by obtaining the number of clock cycles consumed by the processor to execute instructions through the PMU, improve the accuracy of the processor load measurement, and thus improve the accuracy of frequency modulation of the processor. The technical solution of the present application is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

[0068] Please refer to Figure 3 , is a flow chart of a frequency modulation method of an electronic device provided in an embodiment of the present application. The method can be used for an electronic device to modulate the frequency of a processor in a single frequency modulation cycle. It should be noted that the method is not based on Figure 3 The specific order described below is a limitation, and it should be understood that in other embodiments, the order of some steps in the method can be interchanged according to actual needs, or some steps can be omitted or deleted. The method includes the following steps:

[0069] S301, a processor register collects the number of clock cycles consumed by the processor.

[0070] A processor is any processor in an electronic device.

[0071] During operation, the processor can execute one or more instructions, and each instruction can be decomposed into multiple "micro-operations". Each time the processor executes a "micro-operation", it consumes one clock cycle. It is understandable that the greater the load on the processor, the more instructions the processor executes, and accordingly, the greater the number of clock cycles consumed.

[0072] In some embodiments, the register of the processor may be a storage area for storing data of the processor, and may be used to temporarily store data involved in the operation and the result of the operation as well as some information required for the operation of the processor. In some embodiments, the register may be a PMU register. The number of clock cycles consumed by the processor is collected through the register, that is, the load of the processor may be evaluated through hardware information.

[0073] S302, the electronic device determines whether the first frequency modulation period is finished, if so, executes S303, otherwise returns to S301.

[0074] If the first frequency modulation cycle has not ended, S301 can be executed again, that is, the number of clock cycles consumed by the processor can be continuously collected. If the first frequency modulation cycle ends, it means that the number of clock cycles consumed by the processor in the first frequency modulation cycle has been counted, so that the subsequent steps can be continued.

[0075] In some implementations, the duration of the frequency modulation cycle can be obtained by presetting. For example, a frequency modulation cycle can be 4 ms. Of course, in practical applications, the duration of the frequency modulation cycle can also be other values, and the embodiment of the present application does not limit the method of setting the frequency modulation cycle and the specific duration of the frequency modulation cycle.

[0076] In some implementations, the frequency modulation cycle can be divided by a time base (tick). The time base is a relative time unit in the operating system, which is derived from the periodic interruption (output pulse) of the timer. One interruption represents a tick, also known as a "clock tick" or a time scale. A time base can be set to the duration of a frequency modulation cycle. In each frequency modulation cycle, the processor's register continuously collects the number of clock cycles consumed by the processor and determines whether the time base is reached. If not, the processor continues to collect the number of clock cycles consumed by the processor. If yes, the subsequent steps are continued.

[0077] S303: The electronic device obtains and stores the number of clock cycles consumed by the processor in the first frequency modulation period.

[0078] In some implementations, the electronic device may obtain the number of clock cycles consumed by the processor in the first frequency modulation period through the PMU or a PMU register.

[0079] Through S301-S303, the number of clock cycles consumed by the processor in each frequency modulation cycle is obtained through hardware, so that the load of the processor in each frequency modulation cycle can be determined more accurately. And it can be understood that in actual applications, the number of clock cycles consumed by the processor in each frequency modulation cycle can also be obtained by other methods, or the load of the processor in each frequency modulation cycle can be determined by other methods.

[0080] S304, the electronic device determines whether to update the frequency point value of the processor in the second frequency modulation period. If yes, S305 can be executed, otherwise S308 can be executed.

[0081] In some examples, the second frequency modulation period may be after the first frequency modulation period. In some implementations, the second frequency modulation period may be the next frequency modulation period of the first frequency modulation period.

[0082] Since adjusting the frequency value of the processor will affect the performance and power consumption of the processor, for example, when the frequency value is increased, the processor will have higher performance, but it will also bring higher power consumption. Therefore, when the electronic device enters each frequency modulation cycle, it can determine whether to update the frequency value of the processor in the frequency modulation cycle based on the pre-set power consumption strategy. For example, when the electronic device is in energy-saving mode, or the current remaining power of the electronic device is low, the processor can be frequency-free to improve the endurance of the electronic device.

[0083] It is understandable that in actual applications, the electronic device may also determine whether to update the frequency value of the processor for the next frequency modulation cycle for other reasons and through other methods. The embodiment of the present application does not limit the reasons for determining whether to update the frequency value of the processor for the next frequency modulation cycle and the specific determination method.

[0084] In some implementations, S304 may be omitted or skipped. That is, the electronic device may always update the frequency point value of the processor in each frequency modulation cycle.

[0085] S305: The electronic device determines a load duty cycle of the processor in the first frequency modulation period based on the number of clock cycles consumed by the processor in the first frequency modulation period.

[0086] In some examples, the load duty cycle of the processor may indicate how busy the processor is during a period of time, or the load duty cycle may be used as a load measurement value of the processor during the period of time. The load duty cycle may be expressed as a percentage.

[0087] When the load duty cycle of the processor in the first frequency modulation period is larger, it can be said that the processor is busier in the first frequency modulation period, that is, the load is higher. As can be seen from the above, by obtaining the number of clock cycles consumed by the processor in the first frequency modulation period through hardware, the load of the processor in the first frequency modulation period can be determined more accurately. Therefore, based on the number of clock cycles consumed by the processor in the first frequency modulation period, the load duty cycle of the processor in the first frequency modulation period can also be determined more accurately.

[0088] In some implementations, the load duty cycle of the processor in the first frequency modulation period may be determined by the following formula 1.

[0089] cpu_usage=clock_cycles*1024 / avg_freq (Formula 1)

[0090] In some examples, cpu_usage represents the load duty cycle of the processor in the first frequency modulation cycle; clock_cycles represents the number of clock cycles consumed by the processor in the first frequency modulation cycle; avg_freq represents the average frequency value of the processor in the first frequency modulation cycle. Since the electronic device may adjust the frequency value of the processor based on other reasons (such as other frequency modulation strategies) during the operation of the processor, avg_freq may be different from the first frequency value of the processor in the first frequency modulation cycle.

[0091] It is understandable that the load duty cycle of the processor in the first frequency modulation period may also be determined in other ways.

[0092] S306: The electronic device determines a first computing power difference of the processor in the first frequency modulation period based on the load duty cycle of the processor in the first frequency modulation period and the target load duty cycle.

[0093] In some embodiments, the target load duty cycle can be obtained by presetting. For example, the target load duty cycle can be 75%, that is, targetload is 1024*75%. It is understandable that in practical applications, the target load duty cycle can also be set by other methods, and the target load duty cycle can also be other values. The embodiment of the present application does not limit the method of setting the target load duty cycle and the specific value of the target load duty cycle.

[0094] In some implementations, the first computing power difference of the processor in the first frequency modulation period may be determined by the following formula 2.

[0095] error=compu*cpu_usage / targetload-compu (Formula 2)

[0096] In some examples, error represents the first computing power difference; compu represents the actual computing power of the processor in the first frequency modulation cycle, and compu can be determined based on the first frequency point value of the processor in the first frequency modulation cycle; compu*cpu_usage / targetload can represent the target computing power. As can be seen from Formula 2, the first computing power difference is positively correlated with the difference between the load duty cycle of the processor in the first frequency modulation cycle and the target load duty cycle.

[0097] In some embodiments, a load duty cycle difference between a load duty cycle of the processor in a first frequency modulation period and a target load duty cycle can be determined, and based on the load duty cycle difference, a first computing power difference can be determined from a stored mapping relationship between the load duty cycle difference and the computing power difference.

[0098] In some embodiments, the electronic device may obtain and store the mapping relationship between the load duty cycle difference and the computing power difference. The mapping relationship may be expressed in a table, for example, the mapping relationship may include multiple load duty cycle differences and the computing power difference corresponding to each load duty cycle difference. In some embodiments, the mapping relationship may be expressed in a function, for example, computing power difference = A*(load duty cycle difference), where A may be a predetermined parameter. It is understandable that in actual applications, the electronic device may also obtain the mapping relationship between the load duty cycle difference and the computing power difference in other ways, and the mapping relationship between the load duty cycle difference and the computing power difference may also be expressed in other ways.

[0099] It is understandable that, in practical applications, the first computing power difference of the processor in the first frequency modulation period may also be determined in other ways.

[0100] As can be seen from the above, the load duty cycle of the processor can indicate the busyness of the processor over a period of time, and the first computing power difference is positively correlated with the difference between the load duty cycle of the processor in the first frequency modulation cycle and the target load duty cycle. When the load duty cycle of the processor in the first frequency modulation cycle is greater than the target load duty cycle, the first computing power difference is greater than 0, which can indicate that the actual computing power of the processor in the first frequency modulation cycle is insufficient and cannot meet the load requirements. When the load duty cycle of the processor in the first frequency modulation cycle is less than the target load duty cycle, the first computing power difference is less than 0, which can indicate that the actual computing power of the processor in the first frequency modulation cycle overflows and can meet the load requirements, and the overflow computing power may waste part of the power consumption.

[0101] S307, the electronic device determines a second frequency point value in a second frequency modulation period based on a closed-loop feedback loop algorithm and the first computing power difference.

[0102] The closed-loop feedback loop type algorithm may include three parts: proportional control (p), integral control (i) and differential control (d), and these three parts may be used alone or in combination. The proportional control part may produce a control effect by adjusting the error between the system input and the set value. The integral control part may produce a control effect according to the cumulative error between the system output and the set value. The differential control part may produce a control effect according to the rate of change of the system output. The combination of the three parts of proportional control, integral control and differential control may achieve precise control of the system. Closed-loop control refers to a control method that uses the system output as a feedback signal and compares it with the set value and then adjusts it. It may continuously provide feedback on the system output, thereby correcting the deviation in time and enabling the system to better use the change. In some embodiments, the closed-loop feedback loop type algorithm may include proportional control (p), and may also include at least one of proportional integral control (i) and proportional differential control (d). In some embodiments, the closed-loop feedback loop type algorithm may include proportional integral differential compound control (pid), proportional integral control (pi) or proportional differential control (pd). In some embodiments, the proportional integral differential compound control may specifically be a position proportional integral differential compound control.

[0103] In some embodiments, the frequency value of the processor can be controlled by a closed-loop feedback loop based on the first computing power difference of the processor in the first frequency modulation cycle, or in combination with the computing power difference or the sum of the computing power differences of more frequency modulation cycles before the second frequency modulation cycle, so as to obtain the second frequency value of the processor in the second frequency modulation cycle, thereby improving the flexibility and accuracy of the frequency modulation, realizing on-demand supply of the frequency value of the processor, and having a fast response speed, improving the problem of oversupply and undersupply of the frequency value, and not requiring the frequency increase scenario to be set in advance, and having good generalization.

[0104] In some embodiments, the processor can achieve proportional control of the frequency value by using the first computing power difference in the first frequency modulation period. When the first computing power difference is larger, the proportional control effect is larger, and the difference between the second frequency value and the first frequency value is also larger, so that the real computing power of the processor matches the load faster; when the first computing power difference is smaller, the proportional control effect is smaller, and the difference between the second frequency value and the first frequency value is also smaller, avoiding overmodulation.

[0105] In some embodiments, the processor can realize the integral control of the frequency point value by summing the computing power difference in at least one historical frequency modulation cycle before the second frequency modulation cycle. When the sum of the computing power difference is larger, the integral control effect is larger to reduce the static error; when the sum of the computing power difference is smaller, the integral control effect is smaller to avoid integral saturation.

[0106] In some embodiments, the difference between the first computing power difference of the processor in the first frequency modulation cycle and the second computing power difference of the processor in the third frequency modulation cycle can reflect the rate of change of the computing power difference. The third frequency modulation cycle can be before the first frequency modulation cycle. When the rate of change is greater, the differential control effect is greater, and the difference between the first frequency point value and the second frequency point value is also greater, so that the actual computing power of the processor matches the load faster; when the rate of change is smaller, the differential control effect is smaller, and the difference between the first frequency point value and the second frequency point value is also smaller, avoiding overmodulation.

[0107] In addition, the manner in which the electronic device determines the second frequency point value in the second frequency modulation period based on the closed-loop feedback loop algorithm and the first computing power difference can also be referred to in detail in the following embodiments.

[0108] S308, the electronic device decides whether to adjust the frequency.

[0109] In some implementations, if the electronic device determines through S304 not to update the frequency value of the processor in the second frequency modulation period, then the frequency value of the processor may not be adjusted in the second frequency modulation period.

[0110] In some embodiments, if the electronic device determines the second frequency value of the processor in the second frequency modulation period through S305-S307, the frequency value of the processor can be adjusted based on the second frequency value during the second frequency modulation period. In some embodiments, the electronic device can set the frequency value of the processor to the second frequency value during the second frequency modulation period.

[0111] In some embodiments, the second frequency point value can be used as a frequency point reference value, and the electronic device can determine whether to set the frequency point value of the processor to the second frequency point value in the second frequency modulation period through a pre-set decision-making method. Exemplarily, the electronic device includes multiple processors, and the frequency point values ​​of the multiple processors in the second frequency modulation period are determined in the same or similar manner as the aforementioned S301-S307. The electronic device can obtain the maximum frequency point value from the multiple frequency point values, and set the frequency point values ​​of the multiple processors to the maximum frequency point value in the second frequency modulation period.

[0112] In some embodiments, the third frequency modulation cycle may be a frequency modulation cycle before the first frequency modulation cycle, the second frequency modulation cycle may be a frequency modulation cycle after the first frequency modulation cycle, and the time interval between the third frequency modulation cycle and the first frequency modulation cycle and the time interval between the first frequency modulation cycle and the second frequency modulation cycle are less than five times the frequency modulation cycle. Exemplarily, the frequency modulation cycle is 4ms, and the time interval between the third frequency modulation cycle and the first frequency modulation cycle and the time interval between the first frequency modulation cycle and the second frequency modulation cycle are both less than 20ms.

[0113] In the embodiment of the present application, the second frequency point value of the processor in the second frequency modulation cycle can be determined by a closed-loop feedback loop algorithm, the first computing power difference of the processor in the first frequency modulation cycle, and the first frequency point value, thereby improving the flexibility and accuracy of frequency modulation, realizing on-demand supply of the frequency point value of the processor, and having a fast response speed, improving the problem of oversupply and undersupply of the frequency point value, and not requiring the frequency increase scenario to be set in advance, and having good generalization. It is also possible to obtain the number of clock cycles of the processor from the register, and then determine the first computing power difference of the processor based on the number of clock cycles, thereby improving the accuracy of determining the load condition of the processor, and thereby improving the accuracy of frequency modulation of the processor.

[0114] Please refer to Figure 4 , is a flow chart of a frequency modulation method of an electronic device provided in an embodiment of the present application. Figure 4 As shown, the electronic device may include a frequency modulation strategy service and a closed-loop feedback frequency modulation service, and the frequency modulation method may be implemented through the interaction between these two services.

[0115] The frequency modulation policy service can be an upper-level entry for providing frequency modulation services to electronic devices. The frequency modulation policy service can obtain multiple data related to the processor (such as the processor identifier, the number of processor clock cycles, etc.), and provide these data to one or more frequency modulation services to obtain the frequency point value corresponding to the processor from the one or more frequency modulation services.

[0116] The closed-loop feedback frequency modulation service may be one of the one or more frequency modulation services. The closed-loop feedback frequency modulation service may obtain multiple data related to the processor from the frequency modulation strategy service, determine the frequency point value corresponding to the processor based on the closed-loop feedback loop type algorithm and the multiple data, and return the frequency point value to the frequency modulation strategy service. In some embodiments, the closed-loop feedback frequency modulation service may include multiple computing interfaces, each of which may be used to implement a type of calculation. Exemplarily, the closed-loop feedback frequency modulation service may include a load duty cycle interface, a computing power difference interface, and a frequency point value interface, the load duty cycle interface may be used to calculate the load duty cycle of the processor, the computing power difference interface may be used to calculate the computing power difference of the processor, and the frequency point value interface may be used to calculate the frequency point value corresponding to the processor based on the closed-loop feedback loop type algorithm.

[0117] The following will specifically describe the method for implementing the frequency modulation method of the processor through the frequency modulation strategy service and the closed-loop feedback frequency modulation service. It can be understood that in actual applications, the implementation of this method is not limited to the following. Figure 4 It should also be noted that this method does not Figure 4The specific order described below is a limitation, and it should be understood that in other embodiments, the order of some steps in the method can be interchanged according to actual needs, or some steps can be omitted or deleted. The method includes the following steps:

[0118] S401, the frequency modulation strategy service calls the closed-loop feedback frequency modulation service, and inputs the processor identifier (cpu_id), the frequency modulation strategy identifier (flags), and the number of clock cycles (clock_cycles) consumed by the processor in the first frequency modulation cycle.

[0119] In some examples, the processor identification and frequency scaling strategy identification may be omitted.

[0120] The processor identifier is used to indicate the identity of the processor. When an electronic device includes multiple processors, different processors can be distinguished by the processor identifier. The processor identifier may include a character or a string. In some embodiments, the processor identifier may be set by the manufacturer of the processor, or may be configured by a user or other relevant technicians.

[0121] The frequency modulation strategy identifier can be used to indicate a frequency modulation strategy. When the electronic device includes multiple frequency modulation strategies, the different frequency modulation strategies can be distinguished by the frequency modulation strategy identifier. The frequency modulation strategy identifier can include characters or strings. For example, in addition to the closed-loop feedback frequency modulation service, the electronic device also includes two other frequency modulation services. These three frequency modulation services correspond to a frequency modulation strategy respectively. Then, flags=1, flags=2 and flags=3 can be used to indicate these three frequency modulation services respectively. If flags=1 indicates the closed-loop feedback frequency modulation service, the frequency modulation strategy service can call the closed-loop feedback frequency modulation service by setting flags to 1.

[0122] It should be noted that the manner in which the frequency modulation policy service obtains the number of clock cycles consumed by the processor in the first frequency modulation period can be referred to the relevant description in the aforementioned S301-S303.

[0123] S402, the closed-loop feedback frequency modulation service is started, and the processor identifier (cpu_id), the number of clock cycles (clock_cycles) consumed by the processor in the first frequency modulation period, and the second time length from the end of the first frequency modulation period to the current period are transmitted to the load duty cycle interface.

[0124] In some examples, the processor identifier and the second duration from the end of the first frequency modulation cycle to the present time may be omitted.

[0125] In some embodiments, when the second duration from the end of the first frequency modulation cycle to the current time is less than the preset first duration, the subsequent steps can be continued. When the second duration from the end of the first frequency modulation cycle to the current time is greater than or equal to the preset first duration, it means that the duration of the first frequency modulation cycle from the current moment is long, and the load condition and business scenario of the electronic device may have changed significantly. Therefore, based on the number of clock cycles, computing power and other data in the historical frequency modulation cycles including the first frequency modulation cycle, it is difficult to very accurately determine the frequency point value of the frequency modulation cycle of the processor after the current moment, so the subsequent steps can be stopped.

[0126] In some embodiments, when the first frequency modulation cycle ends and the current second duration is greater than or equal to the preset first duration, at least part of the relevant data used to determine the frequency point value of the processor can be initialized. In some embodiments, from the moment when the first frequency modulation cycle ends, if the second frequency point value of the processor in the second frequency modulation cycle is not determined within the first duration based on at least one of the closed-loop feedback loop algorithm, the first computing power difference and the first frequency point value, and the second computing power difference and the sum of the computing power difference of the processor in at least one historical frequency modulation cycle, the first computing power difference, the first frequency point value, the second computing power difference, and the sum of the computing power difference of the processor in at least one historical frequency modulation cycle are deleted. Among them, the at least one historical frequency modulation cycle may include the first frequency modulation cycle and the third frequency modulation cycle, the second computing power difference is the computing power difference of the processor in the third frequency modulation cycle, and the third frequency modulation cycle is before the first frequency modulation cycle.

[0127] In some embodiments, the first duration may be an integer multiple of the frequency modulation period. For example, the frequency modulation period is 4 ms, and the first duration may be 5 times the frequency modulation period, that is, 20 ms. It is understandable that in practical applications, the first duration may also be other values.

[0128] In some implementations, the closed-loop feedback frequency modulation service may also transmit the current time and the frequency modulation period to the load duty cycle interface, and the load duty cycle interface determines the second duration from the end of the first frequency modulation period to the present based on the current time and the frequency modulation period.

[0129] S403, the load duty cycle interface returns the load duty cycle (cpu_usage) to the closed-loop feedback frequency modulation service according to the average frequency value (avg_freq) of the processor in the first frequency modulation period and the number of clock cycles (clock_cycles) consumed by the processor in the first frequency modulation period.

[0130] In some examples, the load duty cycle interface may determine the load duty cycle of the processor in the first frequency modulation period based on the number of clock cycles consumed by the processor in the first frequency modulation period. It should be noted that the load duty cycle interface determines the load duty cycle of the processor in the first frequency modulation period based on the number of clock cycles consumed by the processor in the first frequency modulation period, as described in detail in the aforementioned S305.

[0131] S404, the closed-loop feedback frequency modulation service transmits the processor identifier (cpu_id), load duty cycle (cpu_usage) and target load duty cycle (targetload) to the computing power difference interface.

[0132] In some examples, the identification of the processor may be omitted.

[0133] S405, the computing power difference interface returns the first computing power difference (error) of the processor in the first frequency modulation cycle to the closed-loop feedback frequency modulation service based on the load duty cycle (cpu_usage) and the target load duty cycle (targetload).

[0134] In some examples, the computing power difference interface can determine the first computing power difference of the processor in the first frequency modulation period based on the target load duty cycle and the load duty cycle. It should be noted that the computing power difference interface determines the first computing power difference of the processor in the first frequency modulation period based on the target load duty cycle and the load duty cycle, which can be referred to the detailed description in the aforementioned S306.

[0135] S406: The closed-loop feedback frequency modulation service transmits the closed-loop feedback parameter and the first computing power difference (error) to the frequency point value interface.

[0136] In some examples, the closed-loop feedback parameters may be omitted.

[0137] As can be seen from the above, the closed-loop feedback loop algorithm can include three parts: proportional control (p), integral control (i) and differential control (d). Therefore, the closed-loop feedback parameters can include at least one of the proportional adjustment coefficient (kp), the integral adjustment coefficient (ki) and the differential adjustment coefficient (kd). The proportional adjustment coefficient can speed up the response speed of the system, improve the adjustment accuracy of the system, and quickly adjust the error. The integral adjustment coefficient can eliminate the residual and adjust the steady-state time. The differential adjustment coefficient can improve the dynamic performance of the system, predict the error trend, and correct the error in advance.

[0138] It should be noted that the proportional adjustment coefficient, the integral adjustment coefficient and the differential adjustment coefficient may be pre-set values. It is also understandable that the proportional adjustment coefficient, the integral adjustment coefficient and the differential adjustment coefficient may be configured and updated by the user, and the embodiment of the present application does not limit the manner of setting the proportional adjustment coefficient, the integral adjustment coefficient and the differential adjustment coefficient, and the specific values ​​of the proportional adjustment coefficient, the integral adjustment coefficient and the differential adjustment coefficient.

[0139] S407, the frequency point value interface returns the second frequency point value (pid_freq) of the processor in the second frequency modulation period to the closed-loop feedback frequency modulation service based on the closed-loop feedback loop algorithm and the first computing power difference (error).

[0140] The frequency point value interface can determine the second frequency point value of the processor in the second frequency modulation period based on a closed-loop feedback loop algorithm and the first computing power difference.

[0141] In some implementations, the second frequency point value of the processor in the second frequency modulation period may be determined by the following formula 3.

[0142] pid_freq=last_pid_freq+p_freq+i_freq+d_freq (Formula 3)

[0143] In some examples, pid_freq represents the second frequency point value of the processor in the second frequency modulation cycle; last_pid_freq represents the first frequency point value of the processor in the first frequency modulation cycle; p_freq represents the calculation component of proportional control, p_freq = kp*error; i_freq represents the calculation component of integral control, i_freq = ki*error_sum, error_sum represents the sum of the computing power difference of the processor in at least one historical frequency modulation cycle; d_freq represents the calculation component of differential control, d_freq = kd*(error-last_error), last_error represents the second computing power difference of the processor in the third frequency modulation cycle; at least one of i_freq and d_freq can be omitted.

[0144] It can be seen from Formula 3 that the closed-loop feedback loop algorithm can proportionally control the frequency value of the processor through the first computing power difference of the processor in the first frequency modulation period, integrally control the frequency value of the processor through the sum of the computing power differences of the processor in at least one historical frequency modulation period, and differentially control the frequency value of the processor through the difference between the first computing power difference of the processor in the first frequency modulation period and the second computing power difference of the processor in the third frequency modulation period. Combined with the fast response and anti-oscillation characteristics of the closed-loop feedback loop algorithm, the actual computing power provided by the processor in the second frequency modulation period is more matched with the computing power required by the load.

[0145] In some embodiments, if the sum of the computing power differences of the processor in at least one historical frequency modulation cycle is greater than or equal to a preset numerical range, the sum of the computing power differences can be scaled to the numerical range to improve the problem of integral saturation and inaccurate frequency modulation caused by the excessive sum of the computing power differences. Exemplarily, the numerical range can be 1-1024. Of course, in practical applications, the numerical range can also be a range of other sizes.

[0146] S408, the frequency modulation strategy service obtains the second frequency point value (pid_freq) from the closed-loop feedback frequency modulation service and makes a decision.

[0147] When the frequency modulation strategy service obtains the second frequency value, a decision may be made based on the second frequency value to determine whether to use the second frequency value as the final frequency value of the processor in the second frequency modulation period.

[0148] In some implementations, the frequency modulation policy service may determine the second frequency point value as the final frequency point value of the processor in the second frequency modulation cycle.

[0149] In some embodiments, the second frequency value can be used as a frequency reference value, and the frequency modulation strategy service can also determine more frequency reference values ​​of the processor in the second frequency modulation cycle through other frequency modulation strategies, and select the largest frequency reference value from multiple frequency reference values ​​as the final frequency value of the processor in the second frequency modulation cycle.

[0150] In an embodiment of the present application, the frequency modulation algorithm of the processor can be implemented through multiple services and computing interfaces. The closed-loop feedback frequency modulation service can initialize these historical data such as the first computing power difference of the processor in the first frequency modulation cycle when the accumulation time is long, and no longer determine the second frequency point value of the processor in the second frequency modulation cycle based on these historical data, thereby improving the accuracy of determining the second frequency point value of the processor in the second frequency modulation cycle. The load duty cycle interface can determine the load duty cycle of the processor in the first frequency modulation cycle based on the number of clock cycles of the processor in the first frequency modulation cycle. The computing power interface can accurately determine the first computing power difference of the processor in the first frequency modulation cycle based on the load duty cycle. Since the number of clock cycles is obtained from the register of the processor, the load duty cycle can more accurately reflect the load of the processor, and the first computing power difference can also more accurately reflect the difference between the computing power actually provided by the processor in the first frequency modulation cycle and the computing power required by the load. The frequency point value interface can combine the fast response and anti-oscillation characteristics of the closed-loop feedback loop algorithm to determine the second frequency point value of the second frequency modulation period, so that the actual computing power provided by the processor in the second frequency modulation period is more matched with the computing power required by the load, thereby realizing on-demand supply of processor computing power.

[0151] Please refer to Figure 5, is a flow chart of a frequency modulation method of an electronic device provided in an embodiment of the present application. The method can be used for an electronic device to modulate the frequency of a processor in a single frequency modulation cycle. It should be noted that the method is not based on Figure 5 The specific order described below is a limitation, and it should be understood that in other embodiments, the order of some steps in the method can be interchanged according to actual needs, or some steps can be omitted or deleted. The method includes the following steps:

[0152] S501, the electronic device obtains a first computing power difference and a first frequency point value of the processor in a first frequency modulation period, where the first computing power difference is positively correlated with a difference between a load duty cycle of the processor in the first frequency modulation period and a target load duty cycle.

[0153] In some examples, the manner in which the electronic device obtains the first computing power difference and the first frequency point value of the processor in the first frequency modulation period can refer to the relevant description in the aforementioned S301-S306.

[0154] S502: The electronic device determines, based on the first computing power difference and the first frequency value, a second frequency value of the processor in a second frequency modulation period, where the second frequency modulation period is after the first frequency modulation period.

[0155] In some examples, the electronic device determines the second frequency value of the processor in the second frequency modulation period based on the first computing power difference and the first frequency value, which can be referred to the relevant description in the aforementioned S307, or the relevant description in the aforementioned S401-S408.

[0156] S503: The electronic device adjusts the frequency value of the processor based on the second frequency value in the second frequency modulation period.

[0157] In some examples, the manner in which the electronic device adjusts the frequency value of the processor based on the second frequency value in the second frequency modulation period can refer to the related descriptions in the aforementioned S308 and S408.

[0158] In an embodiment of the present application, the first computing power difference and the first frequency point value of the processor in the first frequency modulation cycle can be obtained. Since the first computing power difference is positively correlated with the difference between the load duty cycle of the processor in the first frequency modulation cycle and the target load duty cycle, and the load duty cycle can be used as a load measurement value of the processor in the first frequency modulation cycle, the first computing power difference can indicate the difference between the computing power actually provided by the processor in the first frequency modulation cycle and the target computing power. The second frequency point value of the processor in the second frequency modulation cycle is determined by the first computing power difference and the first frequency point value of the processor in the first frequency modulation cycle. In the second frequency modulation cycle, the frequency point value of the processor is adjusted based on the second frequency point value, which can improve the flexibility and accuracy of frequency modulation, realize the on-demand supply of the frequency point value of the processor, and have a fast response speed. It improves the problem of oversupply and undersupply of frequency point values, and does not need to set the frequency increase scenario in advance, and has good generalization.

[0159] Please refer to Figure 6 , is a flow chart of a frequency modulation method of an electronic device provided in an embodiment of the present application. The method can be used for an electronic device to modulate the frequency of a processor in a single frequency modulation cycle. It should be noted that the method is not based on Figure 6 The specific order described below is a limitation, and it should be understood that in other embodiments, the order of some steps in the method can be interchanged according to actual needs, or some steps can be omitted or deleted. The method includes the following steps:

[0160] S601, the electronic device identifies the current business scenario.

[0161] Electronic devices can determine business scenarios based on their current operating status. For example, electronic devices can detect the start, run, and end of applications; detect user input operations from input devices such as keyboards and touch screens, and further identify the type of input operation (such as click operation or touch operation), and detect the operation object of the input operation (such as starting an application, pulling down the status bar, switching the display interface, etc.) in combination with the input operation and the display interface on the display screen.

[0162] It should be noted that the embodiments of the present application do not limit the manner in which the electronic device identifies the business scenario.

[0163] S602, in response to the business scenario being a specific scenario, the electronic device obtains a first computing power difference and a first frequency point value of the processor in a first frequency modulation cycle, and the first computing power difference is positively correlated with a difference between a load duty cycle of the processor in the first frequency modulation cycle and a target load duty cycle.

[0164] In some embodiments, the electronic device may obtain a specific scenario configured by the user. In some embodiments, the specific scenario includes one or more of starting an application, opening a status bar, switching a display interface, responding to an input operation, displaying an animation effect, and displaying a virtual keyboard. It is understandable that the specific scenario may also include more business scenarios.

[0165] Starting an application may include cold starting an application or hot starting an application. When starting an application, there is no process of the application in the background of the electronic device, and the electronic device will recreate a new process and assign it to the application. When hot starting an application, there is already a process of the application in the background, so if there is an existing process, the application can be started from the existing process.

[0166] The status bar can be used to display the operating status of the electronic device, such as network mode, message prompt mode, brightness, volume, etc. The user can query or configure the operating status of the electronic device by opening the status bar.

[0167] Switching the display interface may include switching between any multiple display interfaces of the electronic device. In some implementations, switching the display interface may include switching the display interface within an application, or may include switching the display interface between applications.

[0168] The input operation can be used for a user or other external object to input data into an electronic device. In some embodiments, the input operation can include a click operation or a touch operation on a display screen.

[0169] Displaying animation effects can be used to provide users with a more realistic and dynamic visual experience. In some embodiments, corresponding animation effects can be displayed in response to user operations. For example, dynamic switching effects when switching display interfaces.

[0170] The virtual keyboard can be used to receive text and other data input by the user.

[0171] In some implementations, if the business scenario is a specific scenario, the electronic device may not execute the steps.

[0172] In some examples, the manner in which the electronic device obtains the first computing power difference and the first frequency point value of the processor in the first frequency modulation period can refer to the relevant description in the aforementioned S301-S306.

[0173] S603, the electronic device determines a second frequency value of the processor in a second frequency modulation period based on the first computing power difference and the first frequency value, and the second frequency modulation period is after the first frequency modulation period.

[0174] In some examples, the electronic device determines the second frequency value of the processor in the second frequency modulation period based on the first computing power difference and the first frequency value, which can be referred to the relevant description in the aforementioned S307, or the relevant description in the aforementioned S401-S408.

[0175] S604: The electronic device adjusts the frequency value of the processor based on the second frequency value in the second frequency modulation period.

[0176] In some examples, the manner in which the electronic device adjusts the frequency value of the processor based on the second frequency value in the second frequency modulation period can refer to the related descriptions in the aforementioned S308 and S408.

[0177] In an embodiment of the present application, the business scenario in which the electronic device is located can be identified, and when the electronic device is in a specific scenario, the frequency value of the processor can be supplied on demand with a fast response speed, thereby improving the problem of oversupply and undersupply of frequency value.

[0178] The beneficial effects of the frequency modulation method provided by the implementation of this application will be described below with reference to specific examples.

[0179] Exemplarily, the computing power and power consumption levels of electronic devices are shown in Table 1 below.

[0180] Table 1

[0181]

[0182] As shown in Table 1, when the frequency value of the processor is 1172000, the computing power of the processor is 1397, the power consumption is 148, and the energy efficiency value is 0.11908; when the frequency value of the processor is 1882000, the computing power of the processor is 2224, the power consumption is 340, and the energy efficiency value is 0.16807.

[0183] If the processor runs at 1172000 and 1882000 for 5ms each, the computing power achieved by the processor = 1397*5+2224*5=18105, and the power consumed = 148*5+340*5=2440. If the processor runs at 1517000 for 10ms, the computing power of the processor = 1809*10=18090, and the power consumed by the processor = 226*10=2260. By comparison, it can be seen that the computing power achieved by the processor when the processor runs at 1517000 for 10ms is similar to that when the processor runs at 1172000 and 1882000 for 5ms each, but the power consumption is reduced by 7.4%.

[0184] Please refer to Figure 7 , is a schematic diagram of a load following curve of a processor provided in an embodiment of the present application. Figure 7In the figure, curve 4 is a frequency point value curve corresponding to frequency modulation strategy 3 (ie, the frequency modulation method of the processor provided in this application). Figure 2 Compared with curves 2 and 3 in the figure, curve 4 has a higher degree of overlap with curve 1, that is, the frequency modulation method of the processor provided in the present application has high flexibility and accuracy in frequency modulation, realizes the on-demand supply of the frequency point value of the processor, has a fast response speed, and improves the problem of over-supply and under-supply of the frequency point value. For example, compared with Figure 2 In the under-supplied area, curve 4 can increase the frequency value of the processor to provide higher computing power, thus making the processor have higher performance. Figure 2 In the oversupply area, curve 4 can reduce the frequency value of the processor to provide lower computing power, thereby reducing power waste.

[0185] Based on the same inventive concept, as an implementation of the above method, an embodiment of the present application provides a frequency modulation device for an electronic device. The device embodiment corresponds to the above method embodiment. For ease of reading, the device embodiment will no longer repeat the details of the above method embodiment one by one, but it should be clear that the device in this embodiment can correspond to all the contents of the above method embodiment.

[0186] In a possible implementation, the device may correspond to the processor in the above method embodiment, for example, it may be a processor chip or a processor core in a processor chip. The device may have the function of executing each step or process corresponding to the frequency modulation method of the electronic device in the above method. The function may be implemented by hardware, or by hardware executing corresponding software implementation.

[0187] Based on the same inventive concept, an embodiment of the present application further provides an electronic device. The electronic device comprises: a memory and a processor, wherein the memory is used to store a computer program; and the processor is used to execute the method described in the above method embodiment when calling the computer program.

[0188] The electronic device provided in this embodiment can execute the above method embodiment, and its implementation principle and technical effect are similar, which will not be repeated here.

[0189] Based on the same inventive concept, an embodiment of the present application further provides a chip system, which includes a processor coupled to a memory, and the processor executes a computer program stored in the memory to implement the method described in the above method embodiment.

[0190] In some examples, the chip system may be a single chip, or a chip module composed of multiple chips.

[0191] The embodiment of the present application also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the method described in the above method embodiment is implemented.

[0192] The embodiment of the present application also provides a computer program product. When the computer program product is run on an electronic device, the electronic device implements the method described in the above method embodiment when executing the computer program product.

[0193] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable storage medium may include at least: any entity or device capable of carrying the computer program code to an electronic device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electric carrier signal, a telecommunication signal, and a software distribution medium. For example, a USB flash drive, a mobile hard disk, a disk or an optical disk.

[0194] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0195] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0196] In the embodiments provided in the present application, it should be understood that the disclosed devices / equipment and methods can be implemented in other ways. For example, the device / equipment embodiments described above are merely schematic, for example, the division of the modules or units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0197] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0198] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0199] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0200] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0201] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0202] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A frequency modulation method for an electronic device, characterized in that: include: Acquire a first computing power difference and a first frequency point value of the processor in a first frequency modulation period, wherein the first computing power difference is positively correlated with a difference between a load duty cycle of the processor in the first frequency modulation period and a target load duty cycle; Determining, based on the first computing power difference and the first frequency point value, a second frequency point value of the processor in a second frequency modulation period, where the second frequency modulation period is after the first frequency modulation period; In the second frequency modulation period, the frequency value of the processor is adjusted based on the second frequency value.

2. The method according to claim 1, characterized in that: The obtaining of a first computing power difference of the processor in a first frequency modulation period includes: Obtaining the number of clock cycles consumed by the processor to execute instructions in the first frequency modulation cycle; Determining the load duty cycle of the processor in the first frequency modulation period based on the number of clock cycles; The first computing power difference is determined based on the load duty cycle and the target load duty cycle.

3. The method according to claim 2, characterized in that The obtaining the number of clock cycles consumed by the processor to execute instructions in the first frequency modulation cycle includes: The number of clock cycles consumed by the processor to execute instructions within the first frequency modulation cycle is obtained through a performance monitoring unit PMU or a register.

4. The method according to any one of claims 1 to 3, characterized in that: The determining, based on the first computing power difference and the first frequency value, a second frequency value of the processor in a second frequency modulation period includes: The second frequency point value of the processor in the second frequency modulation cycle is determined based on at least one of the first computing power difference and the first frequency point value, and the second computing power difference and the sum of the computing power difference of the processor in at least one historical frequency modulation cycle, where the second computing power difference is the computing power difference of the processor in a third frequency modulation cycle, and the third frequency modulation cycle is before the first frequency modulation cycle.

5. The method according to claim 4, characterized in that The method further comprises: From the moment when the first frequency modulation cycle ends, if the second frequency point value of the processor in the second frequency modulation cycle is not determined within the first time period based on the first computing power difference and the first frequency point value, and the second computing power difference and the sum of the computing power difference of the processor in the at least one historical frequency modulation cycle, then the first computing power difference, the first frequency point value, the second computing power difference and the sum of the computing power difference of the processor in the at least one historical frequency modulation cycle are deleted.

6. The method according to claim 5, characterized in that The first duration is an integer multiple of the frequency modulation period.

7. The method according to any one of claims 1 to 6, characterized in that: The determining, based on the first computing power difference and the first frequency value, a second frequency value of the processor in a second frequency modulation period includes: Based on a closed-loop feedback loop type algorithm, the first computing power difference and the first frequency point value, the second frequency point value of the processor in the second frequency modulation period is determined, and the closed-loop feedback loop type algorithm includes proportional control, and at least one of integral control and differential control.

8. The method according to any one of claims 1 to 7, characterized in that: The step of adjusting the frequency value of the processor based on the second frequency value during the second frequency modulation period includes: In the second frequency modulation period, the frequency point value of the processor is set to the second frequency point value.

9. A frequency modulation method for an electronic device, characterized in that: include: Identify business scenarios of electronic devices; In response to the business scenario being a specific scenario, obtaining a first computing power difference and a first frequency point value of the processor in a first frequency modulation period, wherein the first computing power difference is positively correlated with a difference between a load duty cycle of the processor in the first frequency modulation period and a target load duty cycle; Determining, based on the first computing power difference and the first frequency point value, a second frequency point value of the processor in a second frequency modulation period, where the second frequency modulation period is after the first frequency modulation period; In the second frequency modulation period, the frequency value of the processor is adjusted based on the second frequency value.

10. The method according to claim 9, characterized in that The specific scenario includes any of the following: starting an application, opening a status bar, switching a display interface, responding to an input operation, displaying an animation effect, and displaying a virtual keyboard.

11. An electronic device, characterized in that: include: A memory and a processor, wherein the memory is used to store a computer program; and the processor is used to execute the method according to any one of claims 1 to 8 when calling the computer program, or to execute the method according to claim 9 or 10.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 8 is implemented, or the method according to claim 9 or 10 is implemented.

13. A computer program product, characterized in that When the computer program product runs on an electronic device, the electronic device executes the method according to any one of claims 1 to 8, or executes the method according to claim 9 or 10.

Images