Miniature PNT system high-reliability clock synchronization method based on CSAC

Abstract

The invention provides a CSAC-based miniature PNT system high-reliability clock synchronization method, and the method comprises the steps: firstly, obtaining a 1pps signal of a CSAC and a 1pps signal of a GNSS in real time, and calculating a clock difference signal; under the condition that the GNSS signal is effective, whether the clock difference signal is larger than a preset threshold value or not is judged, and if the clock difference signal is larger than the threshold value, a coarse adjustment function of the chip-level atomic clock is started; otherwise, performing the following fine adjustment operation; and if the 1pps signal of the GNSS fails, the system automatically starts a clock holding function, and the time precision of the CSAC is predicted and maintained through an extended Kalman filtering method, so that the relatively high time synchronization precision can still be maintained during the loss of the GNSS signal. Once the GNSS signal recovers, the system will exit the clock hold mode and perform time synchronization with the GNSS again. According to the invention, the clock synchronization problem between the CSAC and the GNSS is solved, so that the high-precision time synchronization of the system is ensured, and the reliability of the system is remarkably enhanced.

Description

Technical Field

[0001] The invention relates to the field of aviation navigation, and in particular to a high-reliability clock synchronization method for a micro PNT system based on CSAC. Background Art

[0002] The application value of atomic clock timing technology in the fields of positioning, communication and navigation is becoming increasingly prominent. Among them, the chip-scale atomic clock (CSAC), as the core of the micro PNT system, has gradually become the key technical support for various application scenarios due to its small size, low power consumption and high precision.

[0003] In recent years, China has been continuously promoting the development of positioning and timing technologies based on high-precision atomic clocks in the process of building and improving the Beidou Satellite Navigation System (BDS). Especially in complex environments, such as drones, autonomous driving, and communication systems, where high-precision and continuous timing are urgently needed, the CSAC-assisted GNSS system has shown significant advantages. Compared with traditional crystal oscillators, atomic clocks have extremely high long-term stability and short-term accuracy, which effectively improves the reliability and continuity of positioning and time synchronization when satellite navigation signals are poor or intermittent.

[0004] In this context, domestic research institutes and enterprises have gradually accelerated the research and breakthroughs of micro-PNT related technologies. By using the GNSS system to calibrate and synchronize CSAC, combined with a variety of clock calibration algorithms, such as Kalman filtering and adaptive algorithms, the long-term stability problems caused by the frequency deviation of the atomic clock itself can be effectively eliminated. At the same time, in view of the situation where GNSS signals cannot continuously and stably provide time references in complex environments, a series of adaptive time retention and synchronization algorithms are designed, so that CSAC can still maintain a high time accuracy when GNSS fails, thereby ensuring the continuity of the timing system.

[0005] Therefore, designing and implementing an adaptive time synchronization method based on atomic clocks not only meets the urgent domestic demand for high-precision timing technology, but also provides technical support and solutions for the development of future Micro-PNT systems. Summary of the invention

[0006] The purpose of the present invention is to provide a high-reliability clock synchronization method for a micro PNT system based on CSAC to solve the clock synchronization problem between CSAC and GNSS, ensure high-precision time synchronization of the system, and improve the reliability of the system to achieve the purpose of accurate time synchronization.

[0007] To achieve the above object, the present invention provides a high-reliability clock synchronization method for a micro PNT system based on CSAC.

[0008] Therefore, the present invention adopts the above-mentioned high-reliability clock synchronization method of a micro PNT system based on CSAC, and the technical effects are as follows:

[0009] (1) The method provided by the present invention comprehensively considers the method of adjusting the clock signal of CSAC under different conditions, and can predict the clock difference between CSAC and GNSS when the GNSS signal fails, and perform time synchronization according to the predicted clock difference value, which greatly improves the robustness of the system and ensures the high accuracy of time synchronization.

[0010] (2) The present invention designs a high-reliability clock synchronization method for a micro PNT system based on CSAC, which can predict the CSAC clock error data in combination with the historical data characteristics of CSAC, so that when the time source changes, the system can still maintain high-precision synchronization performance, effectively improving the reliability and stability of the synchronization system.

[0011] (3) The present invention adopts a dynamic adjustment strategy. When GNSS fails or is unavailable, it uses the high precision and short-term retention capability of the atomic clock to reduce the impact of clock source frequency drift, thereby ensuring that the system can still maintain a high time synchronization accuracy when not relying on external timing signals.

[0012] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is an architecture diagram of a high-reliability clock synchronization method for a micro PNT system based on CSAC of the present invention;

[0014] Figure 2 These are the three situations corresponding to the CASC clock error change trend in the fine adjustment mode of the present invention. Figure 2 (A) The absolute value of the CSAC clock error measurement is greater than 1ns, and the clock error change trend is approaching 0ns; Figure 2 (B) The measured value of the CSAC clock error is between ±1ns, and the absolute value of the relative frequency deviation of the CSAC is greater than 1×10 -11 s / s; Figure 2 (C) The absolute value of the CSAC clock error measurement is greater than 1ns, and the clock error change trend is away from 0ns;

[0015] Figure 3 This is a flow chart of the clock holding algorithm in the present invention. DETAILED DESCRIPTION

[0016] The technical solution of the present invention is further described below through the accompanying drawings and embodiments.

[0017] Unless otherwise defined, technical or scientific terms used in the present invention shall have the common meanings understood by one having ordinary skills in the field to which the present invention belongs.

[0018] TDC-AS6500, or AS6500, is a high-performance time-to-digital conversion chip produced by ScioSense.

[0019] The MAX913 is a single high-speed, low-power comparator produced by Maxim Integrated.

[0020] CSAC is an innovative chip-scale atomic clock, which has an important position and significance in the field of atomic clocks. With its small size, low power consumption and relatively high accuracy, chip-scale atomic clocks have broad application prospects in many fields.

[0021] Embodiment 1

[0022] The present invention provides a high-reliability clock synchronization method for a micro PNT system based on CSAC, comprising the following steps:

[0023] S1, initialize each part of the microcontroller, especially initialize the time digital converter (TDC), and send relevant instructions;

[0024] The initialization of TDC includes:

[0025] S11, initialize the TDC-AS6500 time interval measurement chip and the MAX913 comparator chip, use the 10MHz signal output by the CSAC as the external reference clock, and the MAX913 is used to shape the clock signal;

[0026] S12. TDC-AS6500 communicates with STM32H743IIT6 microcontroller through SPI serial port to transmit control commands and clock error measurement results. SPI bus uses the instruction format of "0b100X_XXXX" to send the corresponding initialization parameters, where X represents the binary form of the register address. These parameters include INTERRUPT pin, REFCLK pin, DISABLE pin and RSTIDX pin;

[0027] S13, TDC-AS6500 identifies measurement events and triggers data acquisition by monitoring the level changes of its INTERRUPT pin. The chip adopts an edge-triggered event timing method, taking the start pulse of each cycle of the reference clock as the time reference point. In each trigger event, it accurately measures and calculates the time interval of the measurement channel signal relative to the rising edge of the reference clock signal in the previous cycle. The measurement results are subdivided into two key parameters: the count value (REFID) within the reference clock cycle and the clock error precision measurement value (TSTOP). These parameters are recorded and stored in the dedicated registers of CHANNELx for subsequent processing and analysis;

[0028] S2. Use TDC to monitor and record in real time the 1pps signal sent by CSAC to channel STOP1 and the 1pps signal sent by the GNSS receiver to channel STOP2, and calculate the clock difference Δt between the two 1pps signals. 12 , thereby obtaining clock error data;

[0029] In each trigger event, accurately measure and calculate the time interval of the measurement channel signal relative to the rising edge of the reference clock signal in the previous cycle. The specific steps are as follows:

[0030] Time interval calculation: Calculate the time intervals of channel STOP1 and channel STOP2. The specific formula is as follows:

[0031] t stop =TSTOP+REF_DIV×REFID;

[0032] In the formula, t stop It represents the time interval of a single channel, and REF_DIV represents the frequency division coefficient.

[0033] Time interval difference calculation: Calculate the time interval difference Δt between channel STOP1 and channel STOP2 12 , the calculation formula is as follows:

[0034] Δt 12 =t stop1 -t stop2 ;

[0035] In the formula, t stop1 Indicates the time interval of the first channel, t stop2 Indicates the time interval of the second channel.

[0036] S3. Determine whether the GNSS signal is disconnected. The 1pps signal output by the GNSS receiver is connected to the STOP2 channel of the TDC chip. The measurement result of STOP2 is used to determine whether the 1pps signal of the GNSS receiver is disconnected. If the measurement result of STOP2 is 0, it means that the 1pps signal of the GNSS is disconnected, and the process goes to step S8; otherwise, the process goes to step S4 to step S7;

[0037] S4. After executing steps S1 to S3 without failure for 100 times, the system is considered to be in a stable state and adjustment judgment is started. In order to avoid discussing the positive and negative conditions of the clock error data, the clock error value is converted into its absolute value;

[0038] S5, determine whether the clock difference value is greater than 100ns, if so, proceed to step S6; otherwise, proceed to step S7;

[0039] S6, the system enters the coarse adjustment mode. If the clock error value is greater than 100ns, coarse synchronization is performed through the 1pps synchronization function of the CSAC to reduce the clock error between the CSAC and the GNSS system time to within 100ns, and then returns to step S5;

[0040] S7, the system enters the fine adjustment mode, in which the microcontroller uses the clock control algorithm based on the ping-pong method to accurately adjust the clock. First, the clock error historical data is fitted based on the traditional quadratic clock error model; second, the clock control adjustment amount S is calculated based on the fitting result. n (n=1,2,3); Finally, the CASC is frequency modulated in the opposite direction according to the clock control adjustment amount;

[0041] In the fine adjustment mode, the microcontroller uses the ping-pong method to fit the secondary clock error model. The model construction provides a key basis for subsequent precise adjustment, as follows:

[0042] During the effective period of the reference signal, the ping-pong method keeps the CSAC in a free-running state and collects the clock difference between the CSAC and the GNSS in real time. When the running time reaches the preset clock control period, the least squares estimation method is used to analyze and process the historical clock difference data during this period, and then the estimated values ​​of the parameters of the secondary clock difference model are obtained;

[0043] The secondary clock error model is as follows:

[0044]

[0045] In this model, b0, b1 and b2 are the clock error model parameters to be fitted, which represent the CSAC initial phase deviation, CSAC initial frequency deviation and CSAC frequency drift rate respectively, t0 is the reference time point, ε x is the random noise term;

[0046] In the fine adjustment mode, the microcontroller uses a clock control algorithm based on the ping-pong method to accurately adjust the clock. This method divides different situations according to the clock error change trend reflected by the CSAC model, and determines the corresponding clock control adjustment amount accordingly, as follows:

[0047] When the absolute value of the CSAC clock error measurement is greater than 1ns, and the clock error change trend is approaching 0ns, the clock control adjustment amount is set to S1, and the formula is as follows:

[0048]

[0049] Where x is the clock difference measurement value between CSAC and GNSS system time at the time of clock control operation, T is the control time constant, and β is the attenuation factor;

[0050] When the absolute value of the CSAC clock error measurement is greater than 1ns, and the clock error change trend is moving away from 0ns, the clock control adjustment amount is set to S2, and the formula is as follows:

[0051]

[0052] Where α1 is the relative frequency deviation of CSAC in the current driving cycle;

[0053] When the clock error measurement value of CSAC is between ±1ns and the absolute value of the relative frequency deviation of CSAC is greater than 1×10 - 11 When s / s, the clock control adjustment amount is set to S3, and the formula is as follows:

[0054]

[0055] When the clock error measurement value of CSAC is between ±1ns and the absolute value of the relative frequency deviation of CSAC is not greater than 1×10 -11 When the frequency is s / s, no control operation is performed to reduce the frequency adjustment of CSAC, that is, the clock control adjustment amount is set to 0;

[0056] The CSAC is adjusted using the obtained clock control adjustment; the relevant data is sorted and stored.

[0057] S8, when the GNSS signal is disconnected, the system enters the clock holding mode, in which the microcontroller uses the clock holding algorithm to adjust the clock;

[0058] Firstly, according to the historical clock error data, the phase deviation, frequency deviation and frequency drift rate of CSAC are used as state quantities, and the clock error model parameters are estimated with the help of the extended Kalman filter (EKF) algorithm, so as to obtain the CSAC nonlinear clock error model; then, the model is used to predict the clock error at the next moment; finally, the clock keeping condition is established based on the CSAC nonlinear clock error model and its predicted value, and the necessary clock steering operation is performed based on this;

[0059] According to the high-reliability clock synchronization method of a micro PNT system based on CSAC in claim 1, it is characterized in that the clock holding condition is established based on the CSAC nonlinear clock error model and its predicted value, and the necessary clock driving operation is performed based on this, and the specific operations are as follows:

[0060] Clock holding condition judgment: If the absolute value of the clock error prediction value is less than 10ns, and the relative frequency deviation is less than |4×10-11|s / s, and the clock error prediction value shows a decreasing trend (approaching 0ns), then no clock steering operation is performed on the CSAC, allowing it to converge slowly under autonomous operation, ensuring that the clock error of the CSAC converges slowly to near 0ns in the subsequent control cycle;

[0061] When the absolute value of the clock error prediction value is not less than 10ns, or the relative frequency deviation is not less than |4×10-11|s / s, or the clock error prediction value is divergent (away from the 0ns direction), it is necessary to perform necessary clock steering operations: using the 10,000-second frequency stability of CSAC as a reference, make small adjustments to it, so that the clock error of CSAC gradually returns to near 0ns;

[0062] After each cycle, the current clock error data is stored and used to update the extended Kalman filter model of the next cycle; if the GNSS signal returns to normal, the system will exit the clock hold mode and continue to use GNSS for 1pps calibration synchronization.

[0063] In the clock keeping process, the EKF algorithm is used to estimate the clock error model parameters, thereby obtaining the CSAC nonlinear clock error model, whose mathematical form is as follows:

[0064]

[0065] Where x(t) is the clock error of the atomic clock; t is the time difference between the current measurement time and the initial measurement time; a0 is the CSAC initial phase deviation; a1 is the CSAC initial frequency deviation; a2 is the CSAC frequency drift rate, also known as the aging rate; ε x (t) is the CSAC random noise, a0, a1 and a2 are the deterministic time components that affect the atomic clock error, and ε x (t) is the random variation component that affects the atomic clock error.

[0066] The system conducts the EKF process based on historical data, that is, determining the system equations and initialization, prediction and updating, and repeated iteration and prediction, and gradually calculates the current system state. Then, the nonlinear clock error model of CSAC is constructed based on the current system state, and based on the rigorous nonlinear clock error model, the CSAC clock error prediction value at the current moment is accurately obtained.

[0067] S9. After each adjustment, the system will form an entry with the forecast value obtained in step S7 and the corresponding time, 1pps signal, clock error information and other information, and store the entry additionally and persistently in the historical data list, save the relevant results in the SD card or transfer them to the upper computer software, until the reference signal is restored and the clock hold mode is exited, CSAC quickly resynchronizes with the GNSS system time and returns to S2; among them, the persistent historical data serves as a log to help users analyze and troubleshoot problems when a fault occurs; on the other hand, the historical data serves as a data set for S8 and is used as a reference for prediction when system data is missing.

[0068] Therefore, the present invention adopts the above-mentioned high-reliability clock synchronization method of a micro PNT system based on CSAC to solve the clock synchronization problem between CSAC and GNSS, ensure high-precision time synchronization of the system, and improve the reliability of the system to achieve the purpose of accurate time synchronization.

[0069] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that they can still modify or replace the technical solution of the present invention with equivalents, and these modifications or equivalent replacements cannot cause the modified technical solution to deviate from the spirit and scope of the technical solution of the present invention.

Claims

1. A high-reliability clock synchronization method for a micro PNT system based on CSAC, characterized in that: The following steps are involved: S1, initializing each part of the microcontroller, especially initializing the time digital converter TDC, and sending relevant instructions; S2. Use TDC to monitor and record in real time the 1pps signal sent by CSAC to channel STOP1 and the 1pps signal sent by the GNSS receiver to channel STOP2, and calculate the clock difference Δt between the two 1pps signals. 12 , thereby obtaining clock error data; S3, judging whether the GNSS signal is disconnected, the 1pps signal output by the GNSS receiver is connected to the STOP2 channel of the TDC chip, and judging whether the 1pps signal of the GNSS receiver is disconnected by the measurement result of STOP2; if the measurement result of STOP2 is 0, it means that the 1pps signal of the GNSS is disconnected, and the process goes to step S8; otherwise, the process goes to step S4 to step S7; S4. After executing steps S1 to S3 without failure for 100 times, the system enters a stable state, and adjustment begins at this time. In order to avoid discussing the positive and negative situations of the clock error data, the clock error value is converted into its absolute value; S5, determine whether the clock difference value is greater than 100ns, if so, proceed to step S6; otherwise, proceed to step S7; S6, the system enters the coarse adjustment mode, the 1pps coarse synchronization function of the atomic clock is started, the atomic clock automatically adjusts the clock error, and then returns to step S4; S7, the system enters the fine adjustment mode. In this mode, the microcontroller uses a clock control algorithm based on the ping-pong method to accurately adjust the clock. First, the clock error historical data is fitted based on the traditional quadratic clock error model. Second, the clock control adjustment amount S is calculated based on the fitting result. n n=1,2,3; finally, the CASC is frequency modulated in the opposite direction according to the clock control adjustment amount; S8, when the GNSS signal is disconnected, the clock holding mode is entered. In this mode, the microcontroller uses the clock holding algorithm to adjust the clock. First, based on the clock error historical data, the extended Kalman filter EKF algorithm is used to estimate the clock error model parameters, thereby obtaining the CSAC nonlinear clock error model; Then, the CSAC nonlinear clock error model is used to predict the clock error at the next moment; Finally, the clock keeping conditions are established based on the CSAC nonlinear clock error model and its predicted value, and the necessary clock steering operations are performed based on this. S9. After each adjustment, the system will combine the obtained forecast value and the corresponding time, 1pps signal, clock error information and other information into an entry, and store the entry additionally and persistently in the historical data list, save the relevant results in the SD card or transfer them to the upper computer software, and then the system exits the clock hold mode, CSAC quickly resynchronizes with the GNSS system time, and returns to S2; among them, the persistent historical data serves as a log to help users analyze and troubleshoot problems when a fault occurs; on the other hand, the historical data is used as a data set of S8 and is used as a reference for prediction when system data is missing.

2. According to claim 1, a high-reliability clock synchronization method for a micro PNT system based on CSAC is characterized in that: The initialization of TDC includes: S11, initialize the TDC-AS6500 time interval measurement chip and the MAX913 comparator chip, use the 10MHz signal output by the CSAC as the external reference clock, and the MAX913 is used to shape the clock signal; S12. TDC-AS6500 communicates with STM32H743IIT6 microcontroller through SPI serial port to transmit control commands and clock error measurement results. SPI bus uses the instruction format of "0b100X_XXXX" to send the corresponding initialization parameters, where X represents the binary form of the register address. These parameters include INTERRUPT pin, REFCLK pin, DISABLE pin and RSTIDX pin; S13. TDC-AS6500 identifies measurement events and triggers data acquisition by monitoring the level changes of its INTERRUPT pin. TDC-AS6500 adopts edge-triggered event timing method, taking the start pulse of each cycle of the reference clock as the time reference point. In each trigger event, the time interval of the measurement channel signal relative to the rising edge of the reference clock signal in the previous cycle is accurately measured and calculated. The measurement result is subdivided into two key parameters: the count value REFID within the reference clock cycle and the clock error precision measurement value TSTOP. The two key parameters are recorded and stored in the dedicated registers of CHANNELx for subsequent processing and analysis.

3. The adaptive time synchronization method based on chip-level atomic clock driving according to claim 2 is characterized in that: In each trigger event, accurately measure and calculate the time interval of the measurement channel signal relative to the rising edge of the reference clock signal in the previous cycle. The specific steps are as follows: Time interval calculation: Calculate the time intervals of channel STOP1 and channel STOP2. The specific formula is as follows: t stop =TSTOP+REF_DIV×REFID; Where, t stop Represents the time interval of a single channel, REF_DIV represents the frequency division coefficient; Time interval difference calculation: Calculate the time interval difference Δt between channel STOP1 and channel STOP2 12 The calculation formula is as follows: Δt 12 =t stop1 -t stop2 ; Where, t stop1 Indicates the time interval of the first channel, t stop2 Indicates the time interval of the second channel.

4. The adaptive time synchronization method based on chip-level atomic clock driving according to claim 1, characterized in that: The historical clock error data is fitted based on the traditional quadratic clock error model, as follows: During the effective period of the reference signal, the ping-pong method keeps the CSAC in a free-running state and collects the clock difference between the CSAC and the GNSS in real time. When the running time reaches the preset clock control period, the least squares estimation method is used to analyze and process the historical clock difference data during this period, and then the estimated values ​​of the parameters of the secondary clock difference model are obtained; The secondary clock error model is as follows: In this model, b0, b1 and b2 are the clock error model parameters to be fitted, which represent the CSAC initial phase deviation, CSAC initial frequency deviation and CSAC frequency drift rate respectively, t0 is the reference time point, ε x is a random noise term.

5. The adaptive time synchronization method based on chip-level atomic clock driving according to claim 1, characterized in that: The clock control adjustment amount is calculated according to the fitting results, as follows: When the absolute value of the CSAC clock error measurement is greater than 1ns, and the clock error change trend is approaching 0ns, the clock control adjustment amount is set to S1, and the formula is as follows: Where x is the clock difference measurement value between CSAC and GNSS system time at the time of clock control operation, T is the control time constant, and β is the attenuation factor; When the absolute value of the CSAC clock error measurement is greater than 1ns, and the clock error change trend is moving away from 0ns, the clock control adjustment amount is set to S2, and the formula is as follows: Where α1 is the relative frequency deviation of CSAC in the current driving cycle; When the clock error measurement value of CSAC is between ±1ns and the absolute value of the relative frequency deviation of CSAC is greater than 1×10 -11 When s / s, the clock control adjustment amount is set to S3, and the formula is as follows: When the clock error measurement value of CSAC is between ±1ns and the absolute value of the relative frequency deviation of CSAC is not greater than 1×10 -11 When the frequency is s / s, no control operation is performed to reduce the frequency adjustment of CSAC, that is, the clock control adjustment amount is set to 0; The CSAC is adjusted using the obtained clock control adjustment; the relevant data is sorted and stored.

6. The high-reliability clock synchronization method for a micro PNT system based on CSAC according to claim 1, characterized in that: The clock maintenance conditions are established based on the CSAC nonlinear clock error model and its predicted value, and the necessary clock steering operations are performed based on this. The specific operations are as follows: If the absolute value of the clock error prediction value is less than 10ns and the relative frequency deviation is less than 4×10 -11 s / s, and the clock error prediction value shows a decreasing trend, then, no clock steering operation is performed on CSAC, allowing it to converge slowly under autonomous operation, ensuring that the clock error of CSAC converges slowly to around 0ns in the subsequent control cycle; When the absolute value of the clock error prediction value is not less than 10ns, or the relative frequency deviation is not less than 4×10 -11 s / s, or the predicted clock error value shows a divergent state, it is necessary to perform necessary clock steering operations: using the 10,000-second frequency stability of CSAC as a reference, make small adjustments to it, so that the clock error of CSAC gradually returns to around 0ns.

7. The high-reliability clock synchronization method for a micro PNT system based on CSAC according to claim 1, characterized in that: The EKF algorithm is used to estimate the clock error model parameters, thereby obtaining the CSAC nonlinear clock error model, whose mathematical form is as follows: Where xt is the clock error of CSAC; t is the time difference between the current measurement time and the initial measurement time; a0 is the initial phase deviation of CSAC; a1 is the initial frequency deviation of CSAC; a2 is the frequency drift rate of CSAC, also known as the aging rate; ε x t is the CSAC random noise, a0, a1 and a2 are the deterministic time components affecting the CSAC clock error, and ε x t is the random variation component that affects the CSAC clock error.

8. The high-reliability clock synchronization method for a micro PNT system based on CSAC according to claim 7, characterized in that: The CSAC nonlinear clock error model is used to predict the clock error at the next moment, as follows: The system conducts the EKF process based on historical data, i.e., determines the system equations and initialization, prediction and update, and repeats the iteration and prediction steps, and gradually calculates the system state at the current moment; then, the nonlinear clock error model of CSAC is constructed based on the system state at the current moment, and based on the constructed nonlinear clock error model, the predicted value of CSAC clock error at the current moment is obtained; After each cycle, the current clock error data is stored and applied to the model update of the next cycle.

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