Data processing method, device, equipment and medium of single-port RAM based on BHT

Abstract

The present application provides a data processing method, device, equipment and medium of a single-port RAM based on BHT, which is applied to a pipeline structure. The method includes: when there are multiple branch jump instructions in the pipeline structure, obtaining the update source of the branch history table BHT data of the pipeline structure; caching the update data of BHT through the FIFO queue according to the first-in-first-out FIFO queue writing port rule and the update source; reading the target data through the FIFO queue and writing it into RAMs according to the FIFO queue writing rule; RAMs include multiple single-port RAMs of the same size; when a valid read operation is performed on RAMs, the direction of the branch jump instruction is predicted according to the read address of the valid read operation, the FIFO queue and the cached valid BHT update data address; a valid read operation refers to a read operation that meets preset conditions. This scheme realizes the accurate prediction of the direction of the branch jump instruction, avoids the pollution of the branch history table, thereby improving the accuracy of branch prediction, and further improving the performance of the processor.

Description

Technical Field

[0001] The present application relates to the field of processor technology, and in particular to a data processing method, device, equipment and medium of a single-port RAM based on BHT. Background Art

[0002] With the continuous development of computer technology, branch prediction, as an optimization technology, has been widely used in processor architectures because it can improve the efficiency of the instruction pipeline and reduce the performance loss caused by branch instructions. It can predict the jump direction of the branch instruction before the jump result of the branch instruction is generated. In the branch prediction process, the branch history table (branch target table, BHT) also came into being. It is a structural unit used to record branch jump history information. By using the program counter (Program Counter, PC) as the index of the branch history table BHT, the corresponding two prediction status bits in the branch history table are read out to obtain the prediction result.

[0003] At present, in the related art, a pattern history table (PHT) is generated in sequence through multiple input branch jump histories to predict whether a branch will jump. However, in actual situations, the input branch jump history is generated by a part of the bits of the PC. This part of the PC of multiple jump instructions may conflict and cause the same PHT address to be occupied. Since multiple different branch instructions correspond to the same address in the PHT, confusion and errors will occur when predicting these branch instructions; and there are branches with completely different behaviors corresponding to the same index. At this time, the read prediction information is not applicable to the new branch, and since the new branch updates and rewrites the branch history table, it is a kind of pollution for the previous branch corresponding to the index, thereby affecting the performance of the processor. Summary of the invention

[0004] The embodiments of the present application provide a data processing method, apparatus, device and medium for a single-port RAM based on BHT.

[0005] According to a first aspect of an embodiment of the present application, a data processing method of a single-port RAM based on BHT is provided, wherein the data processing method of the single-port RAM based on BHT is applied to a pipeline structure, wherein the pipeline structure comprises: an operand buffer, a plurality of execution units, and a plurality of arithmetic logic units connected in sequence; comprising:

[0006] When there are multiple branch jump instructions in the pipeline structure, obtaining the update source of the branch history table BHT data of the pipeline structure;

[0007] According to a first-in-first-out (FIFO) queue writing port rule and the update source, the update data of the BHT is cached through the FIFO queue;

[0008] According to the FIFO queue writing rule, the target data is read from the FIFO queue and written into the RAMs; the RAMs include multiple single-port RAMs of the same size;

[0009] When a valid read operation is performed on the RAMs, a branch jump instruction direction is predicted based on the read address of the valid read operation, the FIFO queue and the cached valid BHT update data address; the valid read operation refers to a read operation that meets preset conditions.

[0010] In an optional embodiment of the present application, each of the arithmetic logic units includes a first input channel and a second input channel; the update sources of the branch history table BHT data of the pipeline structure include: a first update source, a second update source and a third update source;

[0011] The first update source refers to the branch jump instruction of the first input channel of the last delivery stage of the pipeline; the second update source refers to the branch jump instruction of the second input channel of the last delivery stage of the pipeline; the third update source refers to the branch jump instruction that generates a request to flush the pipeline structure and is executed first in the pipeline structure.

[0012] In an optional embodiment of the present application, the FIFO queue includes two write ports and one read port, and according to the FIFO queue write port rule and the update source, the BHT update data is cached through the FIFO queue, including:

[0013] When the third update source is valid and the data address of the BHT update data does not match the first update source and the second update source, the first write port in the FIFO queue caches the data of the third update source; otherwise, the first write port in the FIFO queue caches the data of the first update source;

[0014] When the third update source is valid, the data address of the BHT update data does not match the first update source and the second update source, and the first update source is valid, the second write port in the FIFO queue caches the data of the first update source; otherwise, the second write port in the FIFO queue caches the data of the second update source.

[0015] In an optional embodiment of the present application, caching the update data of the BHT by the FIFO queue includes:

[0016] When the data address of the BHT update data to be cached in the FIFO queue matches the data address of the valid BHT data cached in the FIFO queue, the data address matching the valid BHT data is used as the target data address;

[0017] The BHT update data to be cached is merged into the valid BHT data corresponding to the target data address.

[0018] In an optional embodiment of the present application, according to the FIFO queue writing rule, the target data is read from the FIFO queue and written into the RAMs, including:

[0019] At each clock cycle, obtain the BHT read address and check the BHT update address at the top of the FIFO queue;

[0020] When the BHT update address conflicts with the BHT read address, a data is read from the FIFO queue as the target data and written into the RAMs.

[0021] In an optional embodiment of the present application, the low-order index of the write address is used as the chip select enable of the single-port RAM, and the high-order index of the write address is used as the access address of the single-port RAM.

[0022] In an optional embodiment of the present application, when a valid read operation is performed on the RAMs, a branch jump instruction direction is predicted according to a read address of the valid read operation, the FIFO queue and a cached valid BHT update data address, including:

[0023] When a valid read operation is performed on the RAMs, a register is used to store the lower bits of the read address; the lower bits of the read address are used to select a single-port RAM to return read data from the RAMs;

[0024] Sending the read address of the valid read operation to the FIFO queue and comparing it with the data address of the cached valid BHT update data;

[0025] If BHT update data matching the read address is found in the FIFO queue, selecting valid BHT data cached in the FIFO;

[0026] The jump direction of the branch jump instruction is predicted according to the valid BHT data.

[0027] A second aspect of the embodiment of the present application provides a data processing device of a single-port RAM based on BHT, including:

[0028] An acquisition module, used for acquiring an update source of branch history table BHT data of the pipeline structure when there are multiple branch jump instructions in the pipeline structure;

[0029] A cache module, configured to cache the update data of the BHT through the FIFO queue according to a first-in-first-out FIFO queue writing port rule and the update source;

[0030] A writing module, used for reading target data from the FIFO queue and writing the target data into RAMs according to the FIFO queue writing rule; the RAMs include multiple single-port RAMs of the same size;

[0031] The prediction module is used to predict the direction of the branch jump instruction according to the read address of the effective read operation, the FIFO queue and the cached effective BHT update data address when a valid read operation is performed on the RAMs; the effective read operation refers to a read operation that meets the preset conditions.

[0032] According to a third aspect of an embodiment of the present application, a computer device is provided, comprising: a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of any of the above methods when executing the computer program.

[0033] A fourth aspect of an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the steps of any of the above methods when executed by a processor.

[0034] In an embodiment of the present application, a data processing method for a single-port RAM based on BHT is provided, which is applied to a pipeline structure, wherein the pipeline structure includes: an operand buffer, multiple execution units, and multiple arithmetic logic units connected in sequence; the method includes: when there are multiple branch jump instructions in the pipeline structure, obtaining the update source of the branch history table BHT data of the pipeline structure; caching the update data of the BHT through the FIFO queue according to the first-in-first-out FIFO queue writing port rule and the update source; reading the target data from the FIFO queue and writing it into RAMs according to the FIFO queue writing rule; the RAMs include multiple single-port RAMs of the same size; when a valid read operation is performed on the RAMs, predicting the direction of the branch jump instruction according to the read address of the valid read operation, the FIFO queue, and the cached valid BHT update data address; the valid read operation refers to a read operation that meets preset conditions. The technical solution in the present application sets a queuing mechanism when multiple branch jump instructions arrive at the same time, caches the update data of the BHT through the FIFO queue, and can read the target data through the FIFO queue and write it into a single-port RAM of the same size in the RAMs according to the FIFO queue writing rule, thereby solving the problem of conflict in the simultaneous reading and writing of BHT addresses by multiple branch jump instructions, and comprehensively considering the factors of the read address, FIFO queue and cached effective BHT update data address, so as to accurately predict the direction of the branch jump instruction, avoid the pollution of the branch history table, thereby improving the accuracy of branch prediction, and further improving the performance of the processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0036] Figure 1 A schematic diagram of the structure of a mode history table PHT provided in one embodiment of the present application;

[0037] Figure 2 A flowchart of a bit splicing method in global history branch prediction provided by one embodiment of the present application;

[0038] Figure 3 A schematic diagram of the structure of a single input mode history table PHT provided in one embodiment of the present application;

[0039] Figure 4 A schematic diagram of the structure of an ideal multi-input mode history table PHT provided by an embodiment of the present application;

[0040] Figure 5 A schematic diagram of the structure of a multi-input preemptive PHT address provided in another embodiment of the present application;

[0041] Figure 6 A schematic diagram of the structure of a computer device provided in one embodiment of the present application;

[0042] Figure 7 A schematic diagram of a data processing process of a single-port RAM based on BHT provided in one embodiment of the present application;

[0043] Figure 8 A schematic diagram of a multi-pipeline dual-issue three-level branch jump instruction structure provided by an embodiment of the present application;

[0044] Fig. 9 A flowchart of a method for merging BHT update data to be cached into address-matched and valid BHT data provided by one embodiment of the present application;

[0045] Fig.10 A schematic diagram of the structure of a data processing device based on a single-port RAM of BHT provided in one embodiment of the present application. DETAILED DESCRIPTION

[0046] In the process of implementing the present application, the inventors found that in the traditional multi-stage pipeline configurable emission CPU pipeline structure, multiple branch jump instructions updating the BHT at the same time will cause BHT address conflict problems, thereby affecting processor performance.

[0047] In order to make the technical solutions and advantages in the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0048] As mentioned in the background technology, the traditional BHT usually uses the partial bit information of the current conditional branch instruction and the jump information of the previous conditional branch instruction of the current conditional branch instruction as an index to retrieve the information that determines the jump direction of the conditional jump instruction from the BHT. With the rapid development of branch prediction, dynamic branch prediction has become more and more popular. It can not only implement branch prediction without changing the instruction set architecture or pre-existing binary files, but also closely track branch behavior at runtime, and has a certain degree of adaptability.

[0049] Exemplarily, taking the dynamic branch predictor as a 2-bit predictor as an example, a simple dynamic branch predictor uses the program counter (PC) of the current branch instruction as the index of the branch history table BHT, reads out the corresponding two prediction status bits in the branch history table, and takes the highest bit of the two prediction status bits as the prediction result. The prediction result includes 0 and 1. When the prediction result is 1, it indicates a predicted jump; when the prediction result is 0, it indicates no prediction of a jump.

[0050] In the dynamic branch prediction process, a "two-bit saturated counter" can be used to predict the behavior of branch instructions. Multiple "two-bit saturated counters" are organized into a pattern history table PHT. PHT uses the history information of branch jumps as an index. It is a table used to store branch prediction information in the branch prediction mechanism. Use branch jump history (BranchHistory) as the index of PHT, see Figure 1 The schematic diagram of the structure of the pattern history table PHT shown in FIG. Assuming that n bits are used to record the branch history, since each bit has two values ​​of 0 or 1, a total of 2 to the power of n table entries can be indexed. Among them, the n-bit recorder history can include 1 and 0, 1 represents taken, and 0 represents not-taken. When the branch instruction is executed, the state of the counter is updated according to the actual result. If the branch is taken, the counter is more inclined to move in the direction of "taken", and if the branch is not taken, the counter is more inclined to move in the direction of "not-aken". This branch prediction structure can be called a local branch predictor, which only considers the limitations of each instruction, without considering the correlation between the branch instructions. Subsequently, global branch prediction appeared, and its structure is a global branch history register (Global History Register, GHR) or a branch history register (Branch History Register, BHR). This structure can achieve better prediction of branch structures with correlation. The predictor that can predict branch instructions with correlation is called a correlation predictor.

[0051] Taking the Gselect structure of the typical correlation predictor as an example, the branch instruction address is used as local information, and the local information and global history information are combined to index the branch history table. The predictor is indexed by bit-joining the global branch history register GHR and the program counter PC of the branch instruction, and the two prediction status bits are read out.

[0052] Specifically, see Figure 2 As shown, Figure 2The schematic diagram of the structure of the bit splicing method in the global history branch prediction method is shown in Figure 1. After obtaining the program counter PC, the PC is used to store the address of the next instruction to be executed. The PC is hashed to obtain a hash result, and the hash result is bit-spliced ​​with the global branch history register GHR to obtain a splicing result. The splicing result is then used as the index of the pattern history table PHT, and the corresponding table entry is searched in the PHT according to the index, and the two prediction status bits are read out as the prediction result, thereby determining whether the next instruction will branch or not.

[0053] See also Figure 3 As shown in the figure, for a single pipeline fetch and single issue, assume that n bits record the branch jump history and use it as the index of the PHT, read the prediction result prediction of the PHT, the update of the PHT is only affected by a single input, and the prediction is only generated by a single input. The PHT generated by a single output will not cause multiple instructions to update the PHT or the address conflict of reading and writing the PHT. As the pipeline increases, multiple inputs will be generated to generate the PHT. See Figure 4 As shown in the figure, in an ideal state, multiple inputs generate PHT in sequence, and the multiple inputs are branch history 1, branch history 2, and branch history 3. However, in actual situations, the input branch history itself is generated by a part of the bits of the PC, and this part of the PC of multiple jump instructions may be the same, that is, different jump instructions may generate the same Branch history because of the same part of their PC bits. This leads to the situation that multiple inputs may occupy the same PHT address. Since multiple different branch instructions correspond to the same address in the PHT, when these branch instructions are predicted, confusion and errors will occur. This situation is called the problem of branch aliasing. See Figure 5 As shown, for example, branch history 2 and branch history 3 both correspond to the same address of PHT, causing confusion and errors.

[0054] In the branch prediction mechanism of the processor, Gshare prediction is a commonly used method. It uses the information of the program controller PC and the global history register GHR to predict whether the branch will jump. As the size of the processor program becomes larger and larger, due to the limitation of hardware resources (such as chip area, power consumption, etc.), the hardware cannot implement a large enough branch history table to record the branch jump information of all branch instructions. In the Gshare predictor, the PC and GHR involved in the search only contain part of the branch address information and global history information. For example, the PC may only take its low-order part, and the GHR may only take the most recent branch history. Because only part of the information is used, it is entirely possible that different branch instructions generate the same index after processing, but the actual jump behavior of these branches (i.e., whether the branch will jump) is completely different. When the above situation occurs, the prediction information read from the branch history table is based on the behavior of the previous branch with the same index. However, although the index of this new branch is the same, the behavior is different, so the prediction information read is no longer applicable to this new branch. When a new branch is executed, it updates the branch history table according to its actual jump behavior. This update is a pollutant for the previous branch with the same index but different behavior, because the prediction information of the previous branch is incorrectly modified. The next time the previous branch is encountered, the prediction will be wrong. If the branch prediction is wrong, the processor may execute unnecessary instructions, causing the pipeline to empty and refill, wasting a lot of clock cycles, and seriously affecting the performance of the processor.

[0055] Based on the above defects, the present application provides a data processing method of a single-port RAM based on BHT. Compared with the related art, the technical solution in the present application sets a queuing mechanism when multiple branch jump instructions arrive at the same time, caches the update data of the BHT through the FIFO queue, and can read the target data through the FIFO queue and write it into a single-port RAM of the same size in RAMs according to the FIFO queue writing rule, thereby solving the problem of conflict in reading and writing BHT addresses when multiple branch jump instructions are read and written at the same time, and comprehensively considering the factors of read address, FIFO queue and cached effective BHT update data address, to achieve accurate prediction of the direction of branch jump instructions, avoid pollution of the branch history table, thereby improving the accuracy of branch prediction, and further improving the performance of the processor.

[0056] The solutions in the embodiments of the present application may be implemented using various computer languages, such as the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0057] See also Figure 6 , a schematic diagram of a computer device provided in an embodiment of the present application. Figure 6As shown, the computer device includes a processor, a memory, a network interface, a display screen and an input device connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium can be, for example, a disk. The non-volatile storage medium stores files (which can be files to be processed or processed files), operating systems, computer programs, etc. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a data processing method of a single-port RAM based on BHT is implemented. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covered on the display screen, or a key, trackball or touchpad set on the computer device housing, or an external keyboard, touchpad or mouse, etc.

[0058] See also Figure 7 The following embodiments take the above-mentioned computer device as the execution subject, and apply the data processing method of the single-port RAM based on BHT provided in the embodiment of the present application to the above-mentioned computer device to perform instruction processing as an example for specific description. The data processing method of the single-port RAM based on BHT provided in the embodiment of the present application is applied to a pipeline structure, and the pipeline structure includes: an operand buffer, multiple execution units, and multiple arithmetic logic units connected in sequence, including the following steps 201-204:

[0059] Step 201: When there are multiple branch jump instructions in the pipeline structure, obtain the update source of the branch history table BHT data of the pipeline structure.

[0060] It should be noted that the above pipeline structure can be a CPU pipeline structure, which is a multi-stage pipeline configurable launch CPU pipeline structure, which can complete multiple branch jump instructions at the same time. In the embodiment of the present application, a multi-pipeline dual-launch simultaneously completes six instructions as a sample structure, see Figure 8 As shown, Figure 8 A schematic diagram of a multi-pipeline dual-issue three-stage branch jump instruction structure provided in an embodiment of the present application. In the pipeline structure of the CPU, an operand buffer, multiple execution units and multiple arithmetic logic units connected in sequence are included.

[0061] It can be understood that the operand buffer can be opBuf, which is responsible for storing and providing operands. Ex is an execution unit, which is responsible for performing specific operations; the ALU unit is an arithmetic logic unit, which is responsible for performing arithmetic and logical operations. Data flows between such modules to gradually complete the execution process of instructions. The multiple execution units are: a first execution unit Ex1, a second execution unit Ex2, a third execution unit Ex3, and a third execution unit Ex4. The multiple arithmetic logic units are: a first arithmetic logic unit ALU1, a second arithmetic logic unit ALU2, and a third arithmetic logic unit ALU3. The pipeline structure includes a multi-stage pipeline, each stage has a specific function, and data is transmitted in sequence between each stage to achieve parallel processing, thereby improving the execution efficiency of the processor. Among them, the first arithmetic logic unit ALU1 of the first level receives data from opBuf and processes it to obtain a first result, which may include a branch jump instruction. When the branch jump instruction predicts the execution of the next step, the first result is transmitted to the second arithmetic logic unit ALU2. At the same time, the second arithmetic logic unit ALU2 receives data from the second execution unit Ex2 and processes the first result to obtain a second result. When the next step is executed, the second result is transmitted to the third arithmetic logic unit ALU3. At the same time, the third arithmetic logic unit ALU3 receives data from the fourth execution unit Ex4 and processes the third result to obtain a fourth result.

[0062] In the pipeline structure of the CPU, multiple arithmetic logic units (such as ALU1, ALU2, and ALU3) are involved, and these arithmetic logic units are related to branch jump instructions and branch history tables (BHT) during the execution of instructions. ALU1 and ALU2 both have the possibility of generating jumps when executing corresponding instructions. Once they generate a jump, they will "flush" the current pipeline segment. The so-called "flush" is to clean up the subsequent instructions that have been partially or accurately executed in the pipeline, and to obtain and execute instructions again according to the new jump target. In addition, when ALU1 and ALU2 generate such a jump and flush the pipeline, the BHT needs to be updated immediately, so that the BHT can record the latest branch jump situation in time, so as to make more accurate predictions of branch instructions later.

[0063] In this embodiment, ALU1, ALU2 and ALU3 include two ports, namely I0 and I1. The I0 and I1 ports can be understood as different data input channels, and each input channel has multiple instructions circulating in the pipeline. When there are six instructions in total, namely, I0 and I1 ports of ALU1, ALU2 and ALU3, and one of them is issued to flush the pipeline, an arbitration operation is required. The purpose of arbitration is to select the branch jump instruction that has issued a pipeline flush request and is the oldest branch jump instruction from the six branch jump instructions. Then the result of the selected instruction is used to update the BHT. This is done to ensure that the data updated by the BHT conforms to the pipeline execution order and the actual occurrence of the branch jump, so that the BHT can accurately reflect the first valid branch jump information in the entire pipeline.

[0064] Among them, the update sources of the branch history table BHT data of the above-mentioned pipeline structure include multiple sources. The branch jump instruction of the I0 channel of the last delivery stage of the pipeline can be used as the update source, the branch jump instruction of the I1 channel of the last delivery stage of the pipeline can be used as the update source, and the branch jump instruction that occurs a flush pipeline request and enters the pipeline earliest can also be used as the update source.

[0065] Step 202: According to the FIFO queue writing port rule and the update source, the BHT update data is cached through the FIFO queue.

[0066] It should be noted that the above-mentioned first-in-first-out FIFO queue write port rule can be pre-defined according to actual needs. The FIFO queue includes two write ports and one read port. The single-port RAM organizational structure of the BHT in the embodiment of the present application is based on the FIFO queue including two write ports and one read port to cache BHT data with multiple update sources.

[0067] Specifically, the FIFO queue write port rule includes multiple conditions, and each condition corresponds to different cached data. After obtaining the update source, it can be determined whether the update source meets the conditions in the FIFO queue write port rule according to the FIFO queue write port rule and the update source, and the data of the corresponding condition is cached when the corresponding condition is met.

[0068] Step 203: According to the FIFO queue writing rule, the target data is read from the FIFO queue and written into the RAMs; the RAMs include multiple single-port RAMs of the same size.

[0069] It should be noted that the above FIFO queue write rules can be pre-defined according to actual needs. The target data refers to the data that needs to be written into the RAMs. When a write operation needs to be performed, the target data needs to be read from the FIFO queue and written into the RAMs according to the FIFO queue write rules.

[0070] It is understandable that RAMs means multiple random access memories, and single-port RAM (Random-AccessMemory) is a single-port random access memory. It can only perform one read operation or one write operation at the same time because it has only one set of address lines, data lines and control lines. For example, when a single-port RAM is performing a read operation, it cannot perform a write operation at the same time, and vice versa.

[0071] The above-mentioned single-port RAMs of the same size refer to RAMs with the same storage capacity, that is, each single-port RAM has the same number of storage units. During data processing, these single-port RAMs can work in parallel. For example, in one clock cycle, different single-port RAMs can perform read operations or write operations respectively, thereby improving the data throughput rate of the entire storage system. Moreover, since they are single-port RAMs, they will not interfere with each other when they are operating separately.

[0072] Step 204: when a valid read operation is performed on the RAMs, the direction of the branch jump instruction is predicted according to the read address of the valid read operation, the FIFO queue and the cached valid BHT update data address; a valid read operation refers to a read operation that meets preset conditions.

[0073] In this embodiment, when a valid read operation is performed on RAMs, since there are multiple RAMs in the RAMs, it is necessary to determine which RAM to read data from. A valid read operation refers to a read operation that meets certain conditions, such as a read operation performed in a specific clock cycle or instruction execution phase. When the number of RAMs in the RAMs is greater than 1, each time a valid read operation is initiated, a register is used to save the low bit of the read address for selecting the returned RAMs read data.

[0074] When data needs to be read from RAMs, the read address of the effective read operation, the FIFO queue and the cached effective BHT update data address are obtained, and the read address and the BHT update data address can be compared. According to the comparison result, the branch jump reverse prediction is performed.

[0075] In an embodiment of the present application, a data processing method for a single-port RAM based on BHT is provided, which is applied to a pipeline structure, wherein the pipeline structure includes: an operand buffer, multiple execution units, and multiple arithmetic logic units connected in sequence; the method includes: when there are multiple branch jump instructions in the pipeline structure, obtaining the update source of the branch history table BHT data of the pipeline structure; caching the update data of the BHT through the FIFO queue according to the first-in-first-out FIFO queue writing port rule and the update source; reading the target data from the FIFO queue and writing it into RAMs according to the FIFO queue writing rule; the RAMs include multiple single-port RAMs of the same size; when a valid read operation is performed on the RAMs, predicting the direction of the branch jump instruction according to the read address of the valid read operation, the FIFO queue, and the cached valid BHT update data address; the valid read operation refers to a read operation that meets preset conditions. The technical solution in the present application sets a queuing mechanism when multiple branch jump instructions arrive at the same time, caches the update data of the BHT through the FIFO queue, and can read the target data through the FIFO queue and write it into a single-port RAM of the same size in the RAMs according to the FIFO queue writing rule, thereby solving the problem of conflict in the simultaneous reading and writing of BHT addresses by multiple branch jump instructions, and comprehensively considering the factors of the read address, FIFO queue and cached effective BHT update data address, so as to accurately predict the direction of the branch jump instruction, avoid the pollution of the branch history table, thereby improving the accuracy of branch prediction, and further improving the performance of the processor.

[0076] In an optional embodiment of the present application, each arithmetic logic unit includes a first input channel and a second input channel; the update sources of the branch history table BHT data of the pipeline structure include: a first update source, a second update source and a third update source.

[0077] The first update source refers to the branch jump instruction of the first input channel of the last delivery stage of the pipeline; the second update source refers to the branch jump instruction of the second input channel of the last delivery stage of the pipeline; the third update source refers to the branch jump instruction that generates a request to flush the pipeline structure and is executed first in the pipeline structure.

[0078] It should be noted that in the above pipeline structure, there are three update sources for BHT data, namely the first update source, the second update source and the third update source. For the arithmetic logic unit, the first input channel may be the I0 channel, and the second input channel may be the I1 channel.

[0079] As an implementable method, the first source S1 is the branch jump instruction of the I0 channel of the last delivery stage of the pipeline. Under the normal process of pipeline structure execution, that is, when the above-mentioned instant flushing of the pipeline caused by ALU does not occur, when the branch jump instruction flows along the pipeline to the last delivery stage, and the branch jump instruction comes through the I0 channel, it will be called a source for updating BHT, that is, the first update source. In other words, the result after the execution of this instruction can be used to update the relevant information in BHT, so that BHT can record the execution status of the branch at this stage.

[0080] As another possible implementation, the second source S2 is the branch jump instruction of the last delivery stage I1 channel of the pipeline. Similar to the first input channel (I0 channel), if the branch jump instruction finally reaches the delivery stage in the normal pipeline and comes through the I1 channel, it will also serve as a source for BHT update, and its execution result will also be used to update the BHT to improve the record of branch jumps in different channels in the BHT.

[0081] As another possible implementation, the third source S3 is the oldest branch jump instruction that has a pipeline flush request. When a pipeline flush request appears in instructions related to multiple computing units, the oldest branch jump instruction selected through arbitration is another source of BHT updates, which can promptly respond to pipeline changes caused by jumps and ensure the timeliness and accuracy of BHT information. Here, "oldest" means that this instruction enters the pipeline earliest, and is determined according to the order of execution of the pipeline.

[0082] In this embodiment, by setting the first update source, the second update source and the third update source, the relevant information of the branch jump instruction can be recorded more comprehensively, which is convenient for comprehensively capturing the branch information. Moreover, through three different update sources, the information of the branch instruction at different stages can be integrated into the BHT, providing more comprehensive data support for branch prediction, which helps to more accurately predict whether the branch will jump, reduce the probability of prediction errors, and thus improve the performance of the processor.

[0083] In an optional embodiment of the present application, the FIFO queue includes two write ports and one read port. According to the FIFO queue write port rule and update source, the BHT update data is cached through the FIFO queue, including the following method steps:

[0084] When the third update source is valid and the data address of the BHT update data does not match the first update source and the second update source, the first write port in the FIFO queue caches the data of the third update source; otherwise, the first write port in the FIFO queue caches the data of the first update source;

[0085] When the third update source is valid, the data address of the BHT update data does not match the first update source and the second update source, and the first update source is valid, the second write port in the FIFO queue caches the data of the first update source; otherwise, the second write port in the FIFO queue caches the data of the second update source.

[0086] It should be noted that the FIFO includes two write ports and one read port, and the two write ports include a first write port and a second write port. The two write ports represent that data can be written to the FIFO queue from two different data sources at the same time. The two write ports are used to cache data from different update sources. For example, according to specific rules, data from different update sources of BHT update data can be written to the FIFO queue respectively through the two write ports.

[0087] A read port means that when data is read out, data can only be read from one port at a time. In the application scenario in this article, in each clock cycle, when certain conditions are met (such as the top BHT update address of the FIFO does not conflict with the BHT read address), a data will be read from this read port and written to the RAMs (random access memory).

[0088] As an implementable method, after obtaining three update sources, it is determined whether the third update source S3 is valid, and whether the data address of the BHT update data matches the first update source S1 and the second update source S2. When the third update source S3 is valid and the update address does not match the first update source S1 and the second update source S2 of the BHT data, the first write port of the FIFO queue selects to cache the data of the BHT third update source S3; when the third update source S3 is invalid, or when the data address matches any one of the first update source S1 and the second update source S2 of the BHT data, the data of the first update source S1 is cached through the first write port of the FIFO queue.

[0089] As another implementable manner, when the third update source S3 is valid, it is determined whether the data address of the BHT update data matches the first update source and the second update source, and whether the first update source S1 is valid; when the third update source S3 is valid, the data address of the BHT update data does not match both the first update source and the second update source, and the first update source S1 is valid, the second write port in the FIFO queue caches the data of the first update source S1; when the third update source S3 is invalid, or when the data address matches any one of the first update source S1 and the second update source S2 of the BHT data, or the first update source S1 is invalid, the second write port in the FIFO queue caches the data of the second update source S2.

[0090] In this embodiment, a two-write and one-read FIFO queue is used to cache the update data of the BHT. Data from different sources are received through two write ports, which can efficiently cache the update data, and select and flow data from different sources according to different rules, so as to facilitate flexible processing of data from different sources. In addition, data can be written in parallel through the two write ports, which can significantly improve the speed of data caching when data from multiple sources are frequently updated.

[0091] In an optional embodiment of the present application, see Fig. 9 As shown, the above-mentioned caching of BHT update data through the FIFO queue includes the following method steps:

[0092] Step 301 : When the data address of the BHT update data to be cached in the FIFO queue matches the data address of the valid BHT data cached in the FIFO queue, the data address that matches the valid BHT data is used as the target data address.

[0093] Step 302: merge the BHT update data to be cached into the valid BHT data corresponding to the target data address.

[0094] It should be noted that the above-mentioned BHT update data to be cached is the BHT update data to be cached in the FIFO. The target data address is a data address matched by valid BHT data, and the number of the target data address may be one.

[0095] In this embodiment, after obtaining the data address of the BHT update data to be cached in the FIFO queue, the data address of the BHT update data to be cached in the FIFO queue is matched with the data address of the valid BHT data cached in the FIFO queue to determine whether they match consistently. If they match consistently, no new data is written, but the data address in the valid FIFO queue that matches consistently is used as the target data address. Then, the BHT update data to be cached is merged into the valid BHT data corresponding to the target data address.

[0096] In this embodiment, by matching the data address of the BHT update data to be cached in the FIFO queue with the data address of the valid BHT data cached in the FIFO queue, it is convenient to accurately determine the target data address, avoid repeated storage of data with the same address, ensure that the branch history data corresponding to each address is the latest and unique, and ensure data consistency. In addition, once new update data matches the cached data address, the new data will be merged in, and the branch history information corresponding to the address will be updated in time, ensuring the timeliness of the updated data.

[0097] In an optional embodiment of the present application, the method of reading target data from the FIFO queue and writing it into RAMs according to the FIFO queue writing rule includes the following method steps:

[0098] At each clock cycle, the BHT read address is obtained and the BHT update address at the top of the FIFO queue is checked.

[0099] When a conflict occurs between the BHT update address and the BHT read address, a data is read from the FIFO queue as the target data and written into the RAMs.

[0100] It should be noted that RAM (Random Access Memory) is composed of multiple storage units. In order to access these storage units, addresses are needed to locate them. Each storage unit has a unique address. When data needs to be written to or read from RAM, this address is used to specify the specific storage unit. The FIFO queue write rule is customized according to actual needs and can be flexibly adjusted. The BHT update address and BHT read address are both identifiers pointing to storage units in the BHT.

[0101] Specifically, in each clock cycle, the BHT read address is obtained and the BHT update address at the top of the FIFO queue is obtained, and then it is determined whether the BHT update address and the BHT read address conflict, which can be determined by a conflict judgment rule. The conflict judgment rule can, for example, compare whether the value of the BHT update address and the value of the BHT read address are the same. If they are the same, it indicates that a conflict occurs; if they are different, it indicates that no conflict occurs.

[0102] When the BHT update address and the BHT read address conflict, a data is read from the FIFO queue as the target data, and the target data is written into the RAMs through the read port of the FIFO queue. The RAMs include multiple single-port RAMs of the same size, the number of which can be customized according to actual needs, and the storage space of each single-port RAM is the same.

[0103] In this embodiment, by judging whether the BHT update address conflicts with the BHT read address according to the FIFO queue writing rule, it is convenient to timely discover possible data inconsistency. When the BHT update address conflicts with the read address, the data is read from the FIFO queue and written to the RAMs to ensure that the updated data is used first in the event of a conflict. By timely updating the data stored in the RAMs, branch prediction errors caused by reading outdated data can be avoided, thereby improving the accuracy of branch prediction.

[0104] In an optional embodiment of the present application, the above method includes the following steps:

[0105] The low-order index of the write address is used as the chip select enable of the single-port RAM, and the high-order index of the write address is used as the access address of the single-port RAM.

[0106] It is understandable that in a system including multiple RAMs, the chip select enable signal is used to select a specific RAM for operation, and only when the enable operation is performed can the corresponding RAM be accessed.

[0107] Please refer to the following Table 1, which shows the chip select enable of RAMs provided in the embodiment of the present application. It is configured with four RAMs, namely RAM0, RAM1, RAM2 and RAM3.

[0108] Table 1: Chip select enable for RAMs

[0109]

[0110] Among them, for each RAM, there is a corresponding conditional expression when executing chip select enable, for example, the conditional expression for RAM0 chip select enable is addr[1:0]=2'b00, the conditional expression for RAM1 chip select enable is addr[1:0]=2'b01, the conditional expression for RAM2 chip select enable is addr[1:0]=2'b10, and the conditional expression for RAM3 chip select enable is addr[1:0]=2'b1.

[0111] It should be noted that addr[1:0] in these conditional expressions represents a two-bit address signal, and 2'bxx is an expression of a binary number, where b represents binary and xx is a specific two-bit binary value. For example, when the value of addr[1:0] is 00, RAM0 is chip-enabled; when the value of addr[1:0] is 01, RAM1 is chip-enabled; when the value of addr[1:0] is 10, RAM2 is chip-enabled; when the value of addr[1:0] is 11, RAM3 is chip-enabled.

[0112] In this embodiment, different RAMs are selected by the low bit of the address signal, so that the storage capacity can be expanded within a limited hardware space, meeting the needs of large-capacity storage, and the number and capacity of RAM can be flexibly configured according to actual applications. For example, in different projects or application scenarios, the appropriate number and size of RAM can be selected by adjusting the logic of chip select enable, without redesigning the entire storage system architecture. In addition, the chip select enable mechanism can realize the rapid selection and access to specific RAMs. In a multi-tasking environment, different tasks may correspond to different storage areas (i.e., different RAMs). Through chip select enable, the required data storage location can be quickly located, reducing data access time and improving the overall operation efficiency of the system.

[0113] In an optional embodiment of the present application, when a valid read operation is performed on RAMs, a branch jump instruction direction is predicted according to a read address of the valid read operation, a FIFO queue, and a cached valid BHT update data address, including the following steps:

[0114] When a valid read operation is performed on RAMs, a register is used to save the low bits of the read address; the low bits of the read address are used to select a single-port RAM to return read data from the RAMs; the read address of the valid read operation is sent to the FIFO queue and compared with the data address of the cached valid BHT update data; if BHT update data matching the read address is found in the FIFO queue, the valid BHT data cached from the FIFO is selected; and the jump direction of the branch jump instruction is predicted based on the valid BHT data.

[0115] Specifically, when performing a valid read operation on RAMs, since there are multiple RAMs, it is necessary to determine which RAM to read the data from. The above-mentioned valid read operation refers to a read operation that meets certain conditions, such as a read operation performed in a specific clock cycle or instruction execution phase. To this end, the system uses a register to save the low bit of the read address, which is used to select which RAM to return the read data from. For example, if there are four RAMs (numbered 0-3 in sequence), the low bit of the read address (assuming it is 2 bits) can be 00, 01, 10, 11, corresponding to RAM0, RAM1, RAM2 and RAM3 respectively.

[0116] In this embodiment, when a read operation is initiated on the RAM, the read address of the valid read operation will be sent to the FIFO queue, which caches the valid BHT update data. The read address is compared with the data address of the BHT update data; this is because the BHT data may have been updated, and these updated data may better reflect the jump direction of the current branch instruction.

[0117] If the BHT update data matching the read address is found in the FIFO queue, the system will abandon the read data returned from the RAM and select the valid BHT data cached in the FIFO queue as the target data to predict the jump direction of the branch instruction. This is to ensure that the latest BHT data is used for prediction, improve the accuracy of branch prediction, and thus optimize the performance of the processor.

[0118] In this embodiment, when a valid read operation is performed on the RAMs, the read address of the valid read operation, the FIFO queue and the cached valid BHT update data address are compared, ensuring that when there are multiple RAMs, the source of the read data can be correctly selected, and when the BHT data is updated, the updated data is used first for branch prediction, avoiding the problem of inaccurate prediction caused by using outdated RAM data, and improving the accuracy of branch jump instruction prediction.

[0119] It should be understood that, although the various steps in the flow chart are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0120] In another embodiment provided in the present application, a data processing device based on a single-port RAM of BHT is also provided. Fig.10 As shown, the device comprises:

[0121] The acquisition module 810 is used to acquire the update source of the branch history table BHT data of the pipeline structure when there are multiple branch jump instructions in the pipeline structure;

[0122] The cache module 820 is used to cache the update data of the BHT through the FIFO queue according to the FIFO queue writing port rule and the update source;

[0123] The writing module 830 is used to read the target data from the FIFO queue and write it into the RAMs according to the FIFO queue writing rule; the RAMs include multiple single-port RAMs of the same size;

[0124] The prediction module 840 is used to predict the direction of the branch jump instruction when a valid read operation is performed on the RAMs according to the read address of the valid read operation, the FIFO queue and the cached valid BHT update data address; the valid read operation refers to the read operation that meets the preset conditions.

[0125] Optionally, the update sources of the branch history table BHT data of the above pipeline structure include: a first update source, a second update source and a third update source;

[0126] The first update source refers to the branch jump instruction of the first input channel of the last delivery stage of the pipeline; the second update source refers to the branch jump instruction of the second input channel of the last delivery stage of the pipeline; the third update source refers to the branch jump instruction that generates a request to flush the pipeline structure and is executed first in the pipeline structure.

[0127] Optionally, the cache module 820 is specifically used for:

[0128] When the third update source is valid and the data address of the BHT update data does not match the first update source and the second update source, the first write port in the FIFO queue caches the data of the third update source; otherwise, the first write port in the FIFO queue caches the data of the first update source;

[0129] When the third update source is valid, the data address of the BHT update data does not match the first update source and the second update source, and the first update source is valid, the second write port in the FIFO queue caches the data of the first update source; otherwise, the second write port in the FIFO queue caches the data of the second update source.

[0130] Optionally, the cache module 820 is further configured to:

[0131] When the data address of the BHT update data to be cached in the FIFO queue matches the data address of the valid BHT data cached in the FIFO queue, the data address that matches the valid BHT data is used as the target data address;

[0132] The BHT update data to be cached is merged into the valid BHT data corresponding to the target data address.

[0133] Optionally, the writing module 830 is specifically used for:

[0134] At each clock cycle, get the BHT read address and check the BHT update address at the top of the FIFO queue;

[0135] When a conflict occurs between the BHT update address and the BHT read address, a data is read from the FIFO queue as the target data and written into the RAMs.

[0136] Optionally, the above device is also used for:

[0137] The low-order index of the write address is used as the chip select enable of the single-port RAM, and the high-order index of the write address is used as the access address of the single-port RAM.

[0138] Optionally, the prediction module 840 is specifically used for:

[0139] When a valid read operation is performed on RAMs, a register is used to store the lower bits of the read address; the lower bits of the read address are used to select the single-port RAM to return the read data from the RAMs;

[0140] Send the read address of the valid read operation to the FIFO queue and compare it with the data address of the cached valid BHT update data;

[0141] If the BHT update data matching the read address is found in the FIFO queue, select the valid BHT data cached from the FIFO;

[0142] The jump direction of the branch jump instruction is predicted based on the valid BHT data.

[0143] For the specific definition of the above-mentioned single-port RAM data processing device based on BHT, please refer to the definition of the single-port RAM data processing method based on BHT above, which will not be repeated here. Each module in the above-mentioned single-port RAM data processing device based on BHT can be implemented in whole or in part by software, hardware and a combination thereof. Each of the above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory in the computer device in the form of software, so that the processor can call and execute the operations corresponding to each of the above modules.

[0144] In one embodiment, a computer device is provided, the internal structure diagram of which can be as follows: Figure 6 As shown. The computer device includes a processor, a memory, a network interface and a database connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a data processing method of a single-port RAM based on BHT as described above is implemented. It includes: a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, any step in the data processing method of a single-port RAM based on BHT as described above is implemented.

[0145] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, any step in the above-mentioned data processing method of a single-port RAM based on BHT can be implemented.

[0146] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0147] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0148] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0149] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0150] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0151] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A data processing method of a single-port RAM based on BHT, characterized in that: The data processing method of the single-port RAM of the BHT is applied to a pipeline structure, wherein the pipeline structure comprises: an operand buffer, a plurality of execution units and a plurality of arithmetic logic units connected in sequence; the method comprises: When there are multiple branch jump instructions in the pipeline structure, obtaining the update source of the branch history table BHT data of the pipeline structure; According to a first-in-first-out (FIFO) queue writing port rule and the update source, the update data of the BHT is cached through the FIFO queue; According to the FIFO queue writing rule, the target data is read from the FIFO queue and written into the RAMs; the RAMs include multiple single-port RAMs of the same size; When a valid read operation is performed on the RAMs, a branch jump instruction direction is predicted according to a read address of the valid read operation, the FIFO queue and a cached valid BHT update data address; the valid read operation refers to a read operation that meets a preset condition; Each of the arithmetic logic units includes a first input channel and a second input channel; the update sources of the branch history table BHT data of the pipeline structure include: a first update source, a second update source and a third update source; The first update source refers to the branch jump instruction of the first input channel of the last delivery stage of the pipeline; the second update source refers to the branch jump instruction of the second input channel of the last delivery stage of the pipeline; the third update source refers to the branch jump instruction that generates a request to flush the pipeline structure and is executed first in the pipeline structure; The FIFO queue includes two write ports and one read port. According to the FIFO queue write port rule and the update source, the BHT update data is cached through the FIFO queue, including: When the third update source is valid and the data address of the BHT update data does not match the first update source and the second update source, the first write port in the FIFO queue caches the data of the third update source; otherwise, the first write port in the FIFO queue caches the data of the first update source; When the third update source is valid, the data address of the BHT update data does not match the first update source and the second update source, and the first update source is valid, the second write port in the FIFO queue caches the data of the first update source; otherwise, the second write port in the FIFO queue caches the data of the second update source.

2. The method according to claim 1, characterized in that Cache the update data of the BHT by the FIFO queue, including: When the data address of the BHT update data to be cached in the FIFO queue matches the data address of the valid BHT data cached in the FIFO queue, the data address matching the valid BHT data is used as the target data address; The BHT update data to be cached is merged into the valid BHT data corresponding to the target data address.

3. The method according to claim 1, characterized in that: According to the FIFO queue writing rule, the target data is read from the FIFO queue and written into the RAMs, including: At each clock cycle, obtain the BHT read address and check the BHT update address at the top of the FIFO queue; When the BHT update address conflicts with the BHT read address, a data is read from the FIFO queue as the target data and written into the RAMs.

4. The method according to claim 1, characterized in that: The method further comprises: The low-order index of the write address is used as the chip select enable of the single-port RAM, and the high-order index of the write address is used as the access address of the single-port RAM.

5. The method according to claim 1, characterized in that When a valid read operation is performed on the RAMs, a branch jump instruction direction is predicted according to a read address of the valid read operation, the FIFO queue and a cached valid BHT update data address, including: When a valid read operation is performed on the RAMs, a register is used to store the lower bits of the read address; the lower bits of the read address are used to select a single-port RAM to return read data from the RAMs; Sending the read address of the valid read operation to the FIFO queue and comparing it with the data address of the cached valid BHT update data; If BHT update data matching the read address is found in the FIFO queue, selecting valid BHT data cached in the FIFO; The jump direction of the branch jump instruction is predicted according to the valid BHT data.

6. A computer device comprising: A memory and a processor, wherein the memory stores a computer program, wherein the processor implements the steps of the data processing method of the single-port RAM based on BHT according to any one of claims 1 to 5 when executing the computer program.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the data processing method of the single-port RAM based on BHT according to any one of claims 1 to 5 are implemented.

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