Temperature-based storage system organization

Abstract

The invention relates to a temperature-based storage system organization. The disclosed systems, devices and methods include receiving temperature information corresponding to a write temperature of at least one of a plurality of pages of non-volatile memory cells of a group of non-volatile memory cells; determining a statistical measure of temperature information for the group of non-volatile memory cells using the received temperature information; and storing the determined statistical measure of temperature information for the group of non-volatile memory cells. The determined statistical measure of the storage of temperature information may be used to optimize or improve one or more storage system operations.

Description

[0001] Information about divisional applications

[0002] This case is a divisional application. The parent case of the divisional application is an invention patent application with an application date of April 16, 2020, application number 202010300443.8, and invention name “Temperature-based storage system organization”. Technical Field

[0003] The present invention relates to the field of semiconductors, and more particularly, to memory devices. Background Art

[0004] A memory device is a semiconductor circuit that provides electronic storage of data for a host system (e.g., a computer or other electronic device). A memory device may be volatile or non-volatile. Volatile memory requires power to maintain data, and includes devices such as random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), or synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can retain stored data when not powered, and includes devices such as flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), resistance variable memory, such as phase change random access memory (PCRAM), resistance random access memory (RRAM), or magnetoresistive random access memory (MRAM), among others.

[0005] The host system typically includes a host processor, a first amount of main memory (e.g., typically volatile memory such as DRAM) to support the host processor, and one or more storage systems (e.g., typically non-volatile memory such as flash memory) that provide additional storage for retaining data in addition to or separate from the main memory.

[0006] A storage system such as a solid state drive (SSD) may include a memory controller and one or more memory devices, including several (e.g., multiple) dies or logical units (LUNs). In some instances, each die may include several memory arrays and peripheral circuitry thereon, such as die logic or a die processor. The memory controller may include an interface circuitry configured to communicate with a host device (e.g., a host processor or interface circuitry) via a communication interface (e.g., a bidirectional parallel or serial communication interface). The memory controller may receive commands or operations associated with memory operations or instructions from the host system, such as read or write operations to transfer data (e.g., user data and associated integrity data, such as error data or address data, etc.) between the memory device and the host device, erase operations to erase data from the memory device, perform drive management operations (e.g., data migration, garbage collection, block deregistration), etc.

[0007] Software (e.g., programs), instructions, operating systems (OS), and other data are typically stored on storage systems and accessed by main memory for use by a host processor. Main memory (e.g., RAM) is typically a faster, more expensive, and different type of memory device (e.g., volatile) than most memory devices of the storage system (e.g., non-volatile, such as SSDs, etc.). In addition to main memory, a host system may also include different levels of volatile memory, such as a group of static memories (e.g., cache memories, typically SRAM), which are typically faster than main memory and, in some instances, are configured to operate at speeds approaching or exceeding the speed of the host processor, but with lower density and higher cost. Summary of the invention

[0008] In one aspect, the present application provides a storage system comprising: a first group of non-volatile memory cells, the first group comprising multiple pages of memory cells; a control circuit system configured to: receive temperature information corresponding to a write temperature of at least one page of the first group of non-volatile memory cells; determine a statistical measure of the temperature information for the first group of non-volatile memory cells using the received temperature information; and store the determined statistical measure of the temperature information for the first group of non-volatile memory cells.

[0009] In another aspect, the present application further provides a method comprising: receiving, using a control circuit system of a storage system, temperature information corresponding to a write temperature of at least one of a plurality of pages of nonvolatile memory cells for each of a plurality of groups of nonvolatile memory cells; determining, using the control circuit system, a statistical measure of the temperature information for each of the plurality of groups of nonvolatile memory cells using the received temperature information; and storing, using the control circuit system, the determined statistical measure of the temperature information for each of the plurality of groups of nonvolatile memory cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In the drawings, which are not necessarily drawn to scale, like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different instances of similar components. The drawings generally illustrate various embodiments discussed in this document by way of example and not limitation.

[0011] Figure 1 An example host system including a host device and a storage system is described.

[0012] Figure 2 Describes instance storage configuration for a user and auxiliary data in groups or subgroups of memory cells.

[0013] Figure 3 Example write (program) distributions at different tiers and write temperatures are illustrated.

[0014] Figures 4 to 6 Example methods for improving operation of one or more storage systems are described.

[0015] Figure 7 Schematic diagram illustrating an example of a 3D NAND architecture semiconductor memory array.

[0016] Figure 8 An example block diagram illustrating a memory module.

[0017] Fig. 9 An example block diagram illustrating an information handling system. DETAILED DESCRIPTION

[0018] Data errors occur when data stored in a memory device falls outside of an expected distribution. Error correction code (ECC) may be implemented by one or more system components, such as a memory controller, device controller, host processor, or other controller or circuit, to correct such data errors.

[0019] When the write and read temperatures for memory cells of a memory device are significantly different, the read levels may not be centered in the distribution valleys on the memory cells, typically resulting in failed read operations (e.g., uncorrectable ECC (UECC), etc.) and further read recovery operations. For example, a write temperature, such as the temperature of a memory device, may be recorded during a programming operation of the memory device. In other instances, the write temperature may include a temperature of a group of memory cells that is close to that during a programming operation of such memory cells. When an error is detected, the memory device (e.g., firmware (FW) in the memory device) may retrieve the recorded write temperature and adjust one or more read levels or recovery operations, such as using information from one or more lookup tables associated with this write temperature, such as, for example, compared to a current read temperature, etc. However, such recovery flows are only available after the first read operation. In some instances, the temperature information itself may not be readable or recoverable, and thus the metadata is affected by the same issues that affect the data in a failed read operation. In contrast, saving complete temperature information using, for example, a system table is expensive both in terms of space and overhead required for loading, saving, and folding, etc., since the temperature information further affects garbage collection and external memory device maintenance beyond the scope of read operations, and therefore, maintaining write performance.

[0020] The inventors have recognized, among other things, systems, methods, and apparatus for managing temperature information in a storage system that include a memory controller and one or more memory devices. For example, in real-world use cases and many test environments, extreme and sudden changes in temperature are unlikely to occur. As discussed further below, storage of monitored temperature data may be implemented, however such operations may be space intensive and may require more time to access in some cases and than would be preferred. As described herein, in many example systems, memory operations may be effectively managed with reference to measurements about monitored temperature data, instead of the temperature data itself (e.g., individual temperature measurements for each memory operation).

[0021] Thus, tracking a statistical measure of temperature information (e.g., one or more determined measures, including one or more of maximum, minimum, mean, variance, standard deviation, coefficient of variation, distribution, etc., which, in certain instances, are distinct from the individual temperature measurements themselves) across a group of memory cells, such as at a block, superblock, or window level, may provide an adequate temperature compensation mechanism across the group so that the memory system can determine memory operating parameters based on the statistical measure of temperature information (e.g., a range of the statistical measure, etc.). As discussed herein, "temperature" refers to a measure of heat, and does not refer to the frequency of use of such information (e.g., "hot" or "cold" in the context of read or write frequency).

[0022] In an example, multiple zones (e.g., subgroups of memory cells, or one or more groups of memory cells from a block, superblock, window, plane, a memory device, etc.) may be determined based on temperature uniformity such that operations in a particular zone or range of zones may be performed with a higher degree of uniformity such that a single (smaller number) of temperature compensations may be applied across groups of memory cells within a zone, in some examples avoiding (or reducing) individual temperature compensations within a zone.

[0023] The memory system may include a temperature sensor, or multiple temperature sensors associated with different zones (or portions thereof) of a memory controller or one or more memory devices. Data from the one or more temperature sensors may be recorded in one or more locations, such as accessible by the memory controller. The memory controller or one or more device controllers or controller circuitry of the one or more memory devices may apply thermal management controls on a device basis or sub-device basis (plane, superblock, etc.). The temperature information itself may be stored, such as in a table, and may be analyzed by the controller to generate one or more statistical measures of the temperature information, which may then be stored in a readily available location for use in controlling device (or sub-device) operations, as described herein.

[0024] For example, a group of memory cells with uniform range of temperature information (e.g., within the same range, or with variations within a threshold) may be assigned or grouped to have a pre-selected or specific read process (e.g., using one or more specific read thresholds, etc.). When an idle block is urgently needed, the storage system (e.g., the FW of the memory device) may select a source block for a folding operation based on a lower validity block count, a lower temperature variation, or a combination thereof. In an example, the storage system may avoid folding blocks or performing other memory device or storage system maintenance when the current operating temperature is different from the write temperature (e.g., opposite temperature range, etc.), or may select a block with a matching or closer write temperature (close to the current temperature, etc.). If the temperature can be visualized on a horizontal line, the opposite temperature or temperature range may be separated by a horizontal difference above a threshold, or have several intervening ranges, etc. The storage system (e.g., a memory controller or one or more device controllers or controller circuitry of one or more memory devices) may perform maintenance on a group of memory cells with large temperature information variations during idle time or other times or periods that do not adversely affect system performance or user experience.

[0025] In an example, a storage system (e.g., a FW of a storage system) may collect, determine, and store statistical measures of temperature information in a memory (e.g., static random access memory (SRAM), etc.) for each group (e.g., block, superblock, superpage, etc.) of memory cells, such as in a table (e.g., similar to a physical to logical (P2L) table, etc.). If the temperature information is uniform across a particular region or group of memory cells, then the data for that region may be integrated into one or more measures and the table may be omitted, saving space, time, and system resources. In some examples, the defined regions (groups of memory cells) may be dynamic, changing to accommodate variations across the device. To improve performance, for example, the stored statistical measures of temperature information (e.g., a table, etc.) may be loaded prior to memory device or storage system maintenance (e.g., a folding operation, etc.) or during normal read operations. The stored statistical measures may be loaded and combined with current temperature information for determining one or more parameters of a data operation (e.g., a read operation, a write operation, a folding operation, etc.).

[0026] Even when detailed statistical measures of temperature information are not stored in the memory device or storage system, such as when an over-provisioned design does not allow for such storage, statistical measures of temperature information (e.g., a table) can be dynamically generated during memory operations such as folding operations, during extended read operations (e.g., detected sequential read operations or patterns), etc.

[0027] During the garbage collection process, some storage systems process blocks in a logical order, such as the first to valid blocks in the L2P table stored in static memory. In the worst case, such order is not sequential and includes random reads scattered throughout the block. Temperature information can be measured and recorded in the metadata (or flag) of the stored data. The storage system (e.g., the FW of the storage system) can retrieve the recorded temperature information at each read and store it in a dedicated data structure, such as in static memory, etc. When falling on the super page that has been touched again, the previously retrieved temperature information can be used to determine the parameters of the read operation (e.g., adjusting one or more read thresholds based on the retrieved temperature information and the current temperature information, etc.). When falling on a fresh page-line, the storage system can try and predict the write temperature information by inserting values ​​from the closest known point. In some instances, such interpolation can be particularly effective for qualification testing, where preprocessing can be performed during a controlled temperature ramp, etc. In addition, the storage system can track failed predictions and can stop predicting after a threshold number of failed predictions (e.g., read failures using predicted write temperature information, etc.).

[0028] Figure 1An example system (e.g., a host system) 100 is described, which includes a host device 105 and a storage system 110 configured to communicate through a communication interface (I / F) 115 (e.g., a bidirectional parallel or serial communication interface). In an example, the communication interface 115 may be referred to as a host interface. The host 105 may include a host processor 106 (e.g., a host central processing unit (CPU) or other processor or processing device) or other host circuitry (e.g., a memory management unit (MMU), interface circuitry, etc.). In some examples, the host device 105 may include a main memory (MAIN MEM) 108 (e.g., DRAM, etc.) and optionally a static memory (STATIC MEM) 109 to support the operation of the host processor (HOST PROC) 106.

[0029] The storage system 110 may include a universal flash storage (UFS) device, an embedded MMC (eMMC TM ) device, or one or more other memory devices. For example, if the storage system 110 includes a UFS device, the communication interface 115 may include a serial bidirectional interface, such as defined in one or more Joint Electronic Device Engineering Council (JEDEC) standards (e.g., JEDEC Standard D223D (JESD223D), commonly referred to as JEDEC UFS Host Controller Interface (UFSHCI) 3.0, etc.). In another example, if the storage system 110 includes an eMMC device, the communication interface 115 may include a plurality of parallel bidirectional data lines (e.g., DAT[7:0]) and one or more command lines, such as defined in one or more JEDEC standards (e.g., JEDEC Standard D84-B51 (JESD84-A51), commonly referred to as JEDEC eMMC Standard 5.1, etc.). In other examples, storage system 110 may include one or more other memory devices, or communication interface 115 may include one or more other interfaces, depending on host device 105 and storage system 110 .

[0030] The memory system 110 may include a memory controller (MEM CTRL) 111 and a non-volatile memory device 112. The memory controller 111 may optionally include a limited amount of static memory 119 to support the operation of the memory controller 111. In an example, the non-volatile memory device 112 may include a plurality of non-volatile memory devices (e.g., dies or LUNs), such as one or more stacked flash memory devices (e.g., as illustrated by the stacked dashed lines below the non-volatile memory device 112), etc., each of which includes a non-volatile memory (NVM) 113 (e.g., one or more groups of non-volatile memory cells) and a device controller (CTRL) 114 or other peripheral circuitry thereon (e.g., device logic, etc.), and is controlled by the memory controller 111 through an internal storage device-system communication interface (e.g., an Open NAND Flash Interface (ONFI) bus, etc.) separate from the communication interface 115.

[0031] Flash memory devices typically include one or more groups of single transistor, floating gate (FG) or replacement gate (RG) memory cells. Two common types of flash memory array architectures include NAND and NOR architectures. The memory cells of a memory array are typically arranged in a matrix. The gate of each memory cell in a row of the array is coupled to an access line (e.g., a word line). In a NOR architecture, the drain of each memory cell in a column of the array is coupled to a data line (e.g., a bit line). In a NAND architecture, the drain of each memory cell in a column of the array is coupled together in series in a source-to-drain manner between a source line and a bit line.

[0032] Each memory cell in a NOR, NAND, 3D crosspoint, HRAM, MRAM, or one or more other architecture semiconductor memory array can be programmed individually or collectively to one or more programmed states. A single-level cell (SLC) can represent one bit of data per cell in one of two programmed states (e.g., 1 or 0). A multi-level cell (MLC) can represent one bit of data per cell in several programmed states (e.g., 2 n , where n is the number of bits of data) to represent two or more bits of data per cell. In some instances, MLC may refer to a memory cell that can store two bits of data in one of four programmed states. A triple-level cell (TLC) may represent three bits of data per cell in one of eight programmed states. A quad-level cell (QLC) may represent four bits of data per cell in one of 16 programmed states. In other instances, MLC may refer to any memory cell that can store more than one bit of data per cell, including TLC and QLC, among others.

[0033] The storage system 110 may include a multimedia card (MMC) solid-state storage device (e.g., a micro secure digital (SD) card, etc.). The MMC device includes several parallel interfaces (e.g., an 8-bit parallel interface) with the host device 105, and is typically a component that is removable and separable from the host device. In contrast, an embedded MMC (eMMC) device is attached to a circuit board and is considered a component of the host device, with a read speed comparable to a Serial ATA (SATA)-based SSD device. As the demand for mobile device performance continues to increase, in order to fully enable virtual or augmented reality devices, take advantage of increased network speeds, etc., storage systems have transitioned from parallel communication interfaces to serial communication interfaces between storage systems and host devices. The UFS device, which includes a controller and firmware, communicates with the host device using a low voltage differential signaling (LVDS) serial interface with a dedicated read / write path, further improving the read / write speed between the host device and the storage system.

[0034] In three-dimensional (3D) architecture semiconductor memory device technology, vertical floating gate (FG) or replacement gate (RG) (or charge trapping) storage structures can be stacked to increase the number of levels in the memory device, the physical pages, and the density of the corresponding memory cells. Data is usually stored arbitrarily on the storage system as small units. Even if accessed as a single unit, the data can be received in small, random 4k to 16k single file reads (for example, 60% to 80% of operations are less than 16k). It is difficult for users and even kernel applications to indicate that data should be stored as a sequential cohesive unit. File systems are usually designed to optimize space usage rather than sequentially retrieve space.

[0035] The memory controller 111 may receive instructions from the host device 105 and may communicate with the non-volatile memory device 112 to transfer (e.g., write or erase) data to or from one or more of the memory cells of the non-volatile memory device 112. The memory controller 111 may include, among other things, circuitry or firmware, such as a number of components or integrated circuits. For example, the memory controller 111 may include one or more memory control units, circuits, or components configured to control access across a memory array and provide a translation layer between the host device 105 and the memory system 100, such as a memory manager, one or more memory management tables, and the like.

[0036] The memory manager may include, among other things, circuitry or firmware, such as a number of components or integrated circuits associated with various memory management functions, including, among other functions, wear leveling (e.g., garbage collection or reclamation), error detection or correction, block deregistration, or one or more other memory management functions. The memory manager 125 may parse or format host commands (e.g., commands received from the host device 105) into device commands (e.g., commands associated with operation of a memory array, etc.), or generate device commands for the device controller 114 or one or more other components of the storage system 110 (e.g., to implement various memory management functions).

[0037] The memory manager may include a set of management tables configured to maintain various information associated with one or more components of the storage system 110 (e.g., various information associated with a memory array or one or more memory cells coupled to the memory controller 111). For example, the management table may include information about a block age, a block erase count, an error history, or one or more error counts (e.g., a write operation error count, a read bit error count, a read operation error count, an erase error count, etc.) of one or more blocks of memory cells coupled to the memory controller 111. In some instances, if the number of errors detected for one or more of the error counts is above a threshold, the bit error may be referred to as an uncorrectable bit error. Among other things, the management table may maintain a count of correctable or uncorrectable bit errors. In an example, the management table may include a translation table or an L2P map.

[0038] In operations involving searching for valid pages in the L2P table (e.g., garbage collection), the memory manager may implement and use a data structure to reduce storage system 110 latency. To this end, the memory manager is arranged to maintain a data structure of physical blocks (e.g., a table region data structure, a tracking data structure, etc.). The data structure includes an indication of an L2P mapping table region of the L2P table. In some examples, the data structure is a bitmap (e.g., a binary array). In an example, the bitmap includes a bit for each of a plurality of mutually exclusive regions across the L2P table.

[0039] The nonvolatile memory device 112 or nonvolatile memory 113 (e.g., one or more 3D NAND architecture semiconductor memory arrays) may include a number of memory cells arranged in, for example, a number of devices, planes, blocks, physical pages, super blocks, or super pages. As an example, a TLC memory device may include 18,592 bytes (B) of data per page, 1536 pages per block, 548 blocks per plane, and 4 planes per device. As another example, an MLC memory device may include 18,592 bytes (B) of data per page, 1024 pages per block, 548 blocks per plane, and 4 planes per device, but has half the required write time and twice the program / erase (P / E) cycles compared to a corresponding TLC memory device. Other examples may include other numbers or arrangements. A SuperBlock may contain a combination of multiple blocks, e.g. from different planes, etc., and a Window may refer to a stripe of a SuperBlock, typically matching the portion covered by a Physical to Logical (P2L) table information block, etc., and a SuperPage may contain a combination of multiple Pages.

[0040] The term "super" may refer to a combination or multiple of one or more items. For example, a superblock may include a combination of blocks. If a memory device includes 4 planes, a superblock may refer to the same block on each plane, or a pattern of blocks across a pane (e.g., a combination of block 0 on plane 0, block 1 on plane 1, block 2 on plane 2, and block 3 on plane 3, etc.). In an example, if a storage system includes multiple memory devices, the combination or pattern of blocks may extend across multiple memory devices. The term "stripe" may refer to a combination or pattern of one or more items. For example, a stripe of a superblock may refer to a combination or pattern of pages from each block in a superblock.

[0041] In operation, data is typically written to or read from the storage system 110 in pages and erased in blocks. However, one or more memory operations (e.g., read, write, erase, etc.) may be performed on larger or smaller groups of memory cells as desired. For example, partial updates of tag data from unloaded cells may be collected during data migration or garbage collection to ensure that they are effectively rewritten. The data transfer size of a memory device is typically referred to as a page, while the data transfer size of a host device is typically referred to as a sector. Although a data page may include several bytes of user data (e.g., a data payload including several sectors of data) and its corresponding metadata, the size of a page typically refers only to the number of bytes used to store the user data. As an example, a data page with a page size of 4KB may include 4KB of user data (e.g., assuming 8 sectors with a sector size of 512B) and several bytes (e.g., 32B, 54B, 224B, etc.) corresponding to the user data, such as integrity data (e.g., error detection or correction code data), address data (e.g., logical address data, etc.), or other metadata associated with the user data.

[0042] Different types of memory cells or memory arrays may implement different page sizes, or may require different amounts of metadata associated therewith. For example, different memory device types may have different bit error rates, which may cause different amounts of metadata to be necessary to ensure the integrity of a page of data (e.g., a memory device with a higher bit error rate may require more bytes of error correction code (ECC) data than a memory device with a lower bit error rate). As an example, an MLC NAND flash device may have a higher bit error rate than a corresponding SLC NAND flash device. Thus, an MLC device may require more bytes of metadata for error data than a corresponding SLC device.

[0043] In examples, data in a block or unit of data may be handled in a particular manner throughout its use on a storage system. For example, data may be managed as a unit during data migration (e.g., garbage collection, etc.) so that efficient read / write properties are preserved when the data is moved to its new physical location on the storage system. In some examples, the only limit to the number of blocks of information, units of data, or chunks that may be configured for storage, labeling, etc., is the capacity of the system.

[0044] In an example, one or more of the host device 105 or the storage system 110 may include a temperature sensor 118 (or one or more temperature sensors) configured to sense temperature information of one or more of the host device 105, the storage system 110, or the environment in which the host device 105 or the storage system 110 operates. In an example, the host device 105 may be configured to provide data to the storage system 110 including user and auxiliary data. In certain examples, the auxiliary data may include temperature information, such as from the host device 105 (e.g., from a temperature circuit or temperature sensor at the host device 105, etc.). In other examples, the host device 105 may provide data to the storage system 110 without temperature information, and the storage system 110 may be configured to augment the data received from the host device 105 with temperature information, such as when the data is stored in the storage system 110, such as in one or more memory devices of the non-volatile memory device 112.

[0045] The storage system 110 may include a temperature circuit 117 configured to determine a statistical measure of temperature information for one or more groups of memory cells, for example, using temperature information received from the host device 105, the storage system 110, or one or more other sensors or components configured to provide temperature information, such as when the storage system 110 writes the received information to the one or more groups of memory cells. In an example, the temperature circuit 117 may be a component of the memory controller 111. In other examples, the temperature circuit 117 may be a component of the storage system 110 that is separate from the memory controller 111. In an example, the temperature circuit 117 may be configured to receive information from a temperature sensor 118. In an example, the storage system 110 may include a single temperature sensor 118. In other examples, the storage system 110 may include multiple temperature sensors, including temperature sensors associated with one or more of the non-volatile memory devices 112, the memory controller 111, or one or more other groups or combinations of regions, zones, components, sectors, etc.

[0046] Figure 2An example storage configuration of user data (e.g., D0-D3) and auxiliary data (A0-A3) for a block or other group (or in some instances, subgroup) of memory cells is illustrated. A first block 201 stores user data (e.g., D0) and auxiliary data (e.g., A0) non-uniformly throughout the block, such as in separate pages (e.g., a first page 203 includes D1 and A0), as received from a memory controller, etc. A second block 202 stores user data separate from auxiliary data. Data structures for table region tracking, etc., ("information") may be stored on the block, in the first block 201 separate from user and auxiliary data, and in the second block 202 with auxiliary data. The auxiliary data may include metadata and flags, as well as other information, such as ECC information, CRC information, etc. The auxiliary data may include temperature information, such as measured by or received from a host device 105 or storage system 110, for each page or block of information stored or written in the storage system, such as in the auxiliary data.

[0047] However, the inventors have recognized that the storage temperature information is intermixed with the data to which it refers, such that it is available only after a read operation has completed and is therefore unavailable for error prevention. Accordingly, an abbreviated table of statistical measures of temperature information may be generated and stored, such as in a static memory of a memory controller, for groups of memory cells (e.g., blocks, superblocks, windows, superwindows, etc.) so that the system can determine one or more parameters for memory operations in an initial read operation.

[0048] The statistical measure of temperature information can be determined using a temperature circuit (e.g., temperature circuit 117) or a memory controller and stored in, for example, a static memory of a storage system. The hierarchy of the statistical information can be changed. In an example, a single measure of temperature information can be determined and stored for each block, in which the temperature information is summarized across each write page by a single measure, such as an average temperature. The average temperature can be determined for each write page in a block in a separate measure, such as during one or more specified cycles of idle time, startup, initialization, or operation, or during normal operation when each page is touched individually, such as between a hard reset and a storage system power cycle. In other examples, the specified distribution of temperature information can be based on, for example, the number of pages written in a block or a specific page written in a block. Sampled from write data across blocks, random distribution across blocks, or pseudo-random or pseudo-specified distribution. In other examples, other single measures, such as maximum temperature or minimum temperature, can be stored. In other examples, multiple measures, such as two or more of average temperature, maximum temperature, minimum temperature, standard deviation, coefficient of variation, median, etc., can be stored. In other examples, indications of write temperatures within ranges of temperatures (different zones) may be stored (e.g., a first range below 0°C, a second range between 0°C and 30°C, a third range between 30°C and 60°C, and a fourth range greater than 60°C, etc.). In other examples, other temperature ranges or numbers of temperature ranges may be used. The number of pages (or specific pages) assigned to each zone or range may be stored. Although described above with respect to (or other groups of memory cells greater than a block, such as a super block, window, super window, etc. in specific examples).

[0049] Although described above with respect to blocks, in other examples, groups of memory cells may include groups larger than blocks, such as superblocks, windows, superwindows, or one or more other groups larger than blocks. For each step in the organization (e.g., from page to block, from block to superblock, from superblock to window, from window to superwindow, etc.), the amount of information stored and the required overhead decreases, however, in the example of changes among groups of memory cells, the positive impact can decrease as individual groups of memory cells fall outside the stored statistical measure, and errors occur. In such examples, for those groups of memory cells that fall outside the stored statistical measure, a traditional temperature compensation mechanism specific to the specific data read will be triggered. In yet other examples, groups of memory cells smaller than blocks may be used, such as groups of pages, etc. However, in such examples, the amount of overhead increases, which can be burdensome.

[0050] Figure 3Example write (program) distributions 300 are illustrated at different levels and write temperatures. A first distribution 301 illustrates the first, second, and third levels (level 2 (L2), level 3 (L3), and level 4 (L4)) at a first write temperature, and a second distribution 302 illustrates the first, second, and third levels at a second write temperature lower than the first write temperature (e.g., the first write temperature may be 70° C. and the second write temperature may be 0° C., etc.). Such levels, number of levels, distributions, temperatures, and temperature variations are illustrative and may vary in other examples. In other examples, just as the write temperature affects the distribution, the read temperature may also affect the distribution.

[0051] When selecting, adjusting, optimizing, or calibrating one or more read thresholds, it may be beneficial to use at least one of the write temperature and the read temperature, but typically both, as well as other information, such as read / write counts, etc., as disclosed in U.S. application Ser. No. 14 / 644,365, entitled “Temperature Related Error Management,” commonly assigned to Muchherla et al., which is incorporated herein by reference in its entirety.

[0052] Figure 4 An example method 400 is described to improve one or more operations. A storage system may include multiple groups of non-volatile memory cells, and each of the multiple groups of non-volatile memory cells may include multiple sub-groups. Groups may include combinations and sub-combinations of memory devices, planes, windows, super blocks, blocks, super pages, pages, or memory cells. Sub-groups may include divisions of groups. With respect to temperature information, the smallest sub-group is typically a page. The storage system may include control circuitry. The control circuitry may include a memory controller, a temperature circuit, one or more device controllers, or a combination thereof.

[0053] At 401, subgroup temperature information may be received, such as by control circuitry of a storage system. The subgroup temperature information may include temperature information corresponding to a write temperature of at least one page (e.g., two or more pages, a threshold number of pages, etc.) of a first group of non-volatile memory cells. In other instances, the subgroup temperature information may include one or more other groups of memory cells at or below a block, superblock, window, plane, device, etc. at an organizational level. In an example, the temperature information may be read from auxiliary data of a page of memory cells or one or more other subgroups. In other instances, the temperature information may be received as a page of memory cells or one or more other subgroups that are written, moved, updated, etc.

[0054] At 402, the received subgroup temperature information (e.g., temperature information for individual pages) can be stored in a data structure (e.g., one or more arrays, tables, etc.) of a storage device, such as in a non-volatile memory of a storage system, for loading in response to one or more trigger conditions (e.g., garbage collection, folding operations, extended read operations, etc.).

[0055] At 403, group statistical temperature information may be determined using the received sub-group temperature information to represent the group of non-volatile memory cells. The difference between using the stored temperature information and using the determined group statistical information is significant and may improve the success of operations involving read operations at first read (e.g., no failed reads and recovery, in some instances, including recovery of stored temperature information), or time to a successful first read, etc.

[0056] In an example, the control circuitry may determine one or more statistical measures of temperature information for the first group of non-volatile memory cells using the received temperature information. The statistical measures may include at least one of an average temperature, a maximum temperature, a minimum temperature, a variance, a standard deviation, a distribution of temperature information for the first group of non-volatile memory cells (e.g., within one or more previously or dynamically defined ranges), or a combination thereof using the received temperature information for at least one page of the first group of memory cells.

[0057] In an example, a statistical measure of temperature information for a particular group of memory cells, such as a first group, may be determined using temperature information from a single page or subgroup. In other examples, the statistical information may be determined using temperature information from two or more pages or subgroups, providing a better representation across the group. In one example, if a memory operation is requested on a single page or a single subgroup of a group of memory cells for which the control circuit system has not yet received temperature information, or if such information is stale, or a trigger condition (e.g., a hard reset, restart, etc.) is received after a threshold time (several hours, days, etc.) or a number of operations (e.g., 1,000, etc.), then the control circuit system may repeat the memory operation for another sequential, random, or opposite page or subgroup (a relatively large distance from the single page or subgroup) to receive first and second temperature information to determine a statistical measure of temperature information for a group having two or more measured values.

[0058] In an example, the statistical measure may be determined or updated for each group as each group is used by the storage system. In other examples, a memory operation may be performed to determine the statistical measure specifically for each of the plurality of groups of the storage system. The plurality of groups may consist of each of the plurality of groups of the storage system, or in other examples, the number is less than the whole, such as each of the plurality of groups being configured to store user or auxiliary data (e.g., excluding FW, etc.), a group containing frequently used or accessed data, a random or representative sampling of the groups of the storage system, etc.

[0059] In an example, when writing data, the storage device may store a statistical measure of temperature information, such as an average temperature, a maximum temperature, a minimum temperature, a number of write temperatures outside an upper or lower threshold, or one or more specified ranges, or a combination thereof. In an example, a statistical measure need not be determined for any individual group of memory cells until a single individual write temperature (or a threshold number or rate of individual write temperatures) of the storage system falls outside one or more predefined boundaries or conditions (e.g., above an upper threshold, below a lower threshold, outside one or more ranges, etc.). Until such a time, each group or subgroup may be assigned to a single measure, such as an average temperature, etc., or no temperature information may be assigned at all, and a single measure may be an assumed default measure. After such a time, a specific statistical measure of temperature information may be determined and stored for each group, or only for each group that falls outside one or more predefined boundaries or conditions.

[0060] At 404, the determined group statistical temperature information can be stored, e.g., for a subgroup, a group containing a subgroup, etc. In an example, the control circuitry can store the determined statistical measure of temperature information for a first group of non-volatile memory cells, e.g., for use in optimizing or improving memory system operations, e.g., adjusting a read process, a threshold voltage, a group on which a memory operation is performed, etc.

[0061] In an example, a data structure containing one or more of the determined statistical measures for each group of memory cells (or for a specified set of groups) can be stored in a volatile memory of the storage system (e.g., static memory supporting a memory controller, etc.) so as to be available for use without read operations of non-volatile memory cells. In other examples, abbreviated tables can be backed up or stored in non-volatile memory and loaded in response to one or more trigger conditions (e.g., garbage collection, number of heavy uses, random data reads, etc.).

[0062] The group or subgroup statistical measure or temperature information can be determined or stored as one or more bits in a table or data structure defining each group or subgroup, or otherwise indicate one or more bits associated with a particular group or subgroup. For example, a single bit can indicate whether the temperature information or the statistical measure of the temperature information is inside or outside a specified range. Multiple bits can be used to indicate several ranges or several different statistical measures (e.g., average temperature, maximum temperature, minimum temperature, the number of measurements within a group, the number of measurements within a specific range, etc.). In an example, several temperature curves can be determined as having an acceptable number of measurements within or outside one or more specified ranges, etc., and each group can be assigned to the most suitable one of the several temperature curves. For example, a first temperature curve can include a first threshold number of measurements within a range (e.g., >80%, etc.), with less than a second threshold number of measurements falling above or below a range (e.g., below <10% and above <10%, etc.). The example range can be between 0°C and 60°C, etc. The second temperature profile can include a first threshold number of measurements within a range (e.g., >80%, etc.), none falling below the range and less than a third threshold number of measurements above the range (e.g., <20%, etc.). Other example ranges and thresholds can be defined, and groups of memory cells can be assigned to a matching or closest matching profile, such as by control circuitry.

[0063] Figure 5 An example method 500 is described to optimize or improve one or more storage system operations. At 501, a read command for data associated with a group or subgroup can be received. At 502, read parameters for the group, such as one or more voltage thresholds, can be determined using stored group statistics and, in some instances, an indication of a current temperature, or one or more other parameters, such as described above. At 503, data associated with the read command can be read using the determined read parameters. In certain embodiments and circumstances, at 504, the statistics can be optionally updated, optimized, or integrated using write temperature information retrieved during the read operation.

[0064] For example, during a sequential write operation, the temperature may rise, such as due to self-heating caused by the write or the operation that caused the write, etc. During a sequential write operation, or if a sequential write operation is detected, the rise in temperature information for the sequential write may be recorded. Sequentially written data is typically read in the same order in which it was written. The read hierarchy may be adapted to accommodate the changing temperature information during the sequential read of such data.

[0065] In other examples, indications of one or more other memory operations may be received or determined, and stored group statistics, such as candidate blocks for folding operations, etc., may be used to select or determine parameters for one or more of the operations.

[0066] Figure 6 An example method 600 is described to optimize or improve one or more memory system operations.At 601, an extended memory operation associated with a subgroup of non-volatile memory cells can be received or detected.

[0067] At 602, initial read parameters may be determined using stored group statistics. At 603, stored subgroup temperature information may be loaded. In some instances, while the stored subgroup temperature information is loaded, such as from a non-volatile memory of a storage system, the extended memory operation may continue to use the first estimated initial read parameters. Once loaded (e.g., into a volatile memory, etc.), the read parameters may be adapted to the specific page or subgroup of the extended memory operation. In other instances, in addition to loading the stored subgroup temperature information, the stored information may be updated, optimized, or integrated using write temperature information retrieved during each read operation.

[0068] Figure 7 An example schematic diagram illustrating a 3D NAND architecture semiconductor memory array 700 includes an array of memory cells organized into blocks (e.g., block A 701A, block B 701B, etc.) and sub-blocks (e.g., sub-block A 701A, block B 701B, etc.). 0 701A 0 , sub-block A n 701A n , sub-block B 0 701B 0 , sub-block B n 701B n etc.) of a plurality of memory cell strings (eg, a first A 0 Memory string 705A 0 To the third A 0 Memory string 707A 0 、First A n Memory string 705A n To the third A n Memory string 707A n 、First B 0 Memory string 705B 0 To the third B 0 Memory string 707B 0 、First B n Memory string 705B n To the third B n Memory string 707B nMemory array 700 represents a portion of a larger number of similar structures that would typically be found in a block, device, or other unit of a memory device.

[0069] Each memory cell string includes a source line (SRC) 735 or a source side select gate (SGS) (eg, a first A 0 SGS 731A 0 To the third A 0 SGS 733A 0 、First A n SGS 731A n To the third A n SGS 733A n 、First B 0 SGS 731B 0 To the third B 0 SGS 733B 0 、First B n SGS 731B n To the third B n SGS 733B n etc.) and the drain side select gate (SGD) (eg, the first A 0 SGD 726A 0 To the third A 0 SGD 728A 0 、First A n SGD 726A n To the third A n SGD 728A n 、First B 0 SGD 726B 0 To the third B 0 SGD 728B 0 、First B n SGD 726B n To the third B n SGD 728B n In the 3D memory array, several levels of memory transistors (e.g., floating gate, replacement gate, charge trapping structure, etc.) are stacked in a source-to-drain manner in the Z direction. Each memory cell string in the 3D memory array can be arranged as a data line (e.g., bit lines (BL) BL0 720 to BL3 722) along the X direction and arranged as a physical page along the Y direction.

[0070] Within a physical page, each level represents a row of memory cells, and each string of memory cells represents a column. A sub-block may include one or more physical pages. A block may include several sub-blocks (or physical pages) (e.g., 128, 256, 384, etc.). Although described herein as having two blocks, each block having two sub-blocks, each sub-block having a single physical page, each physical page having three strings of memory cells, and each string having 8 levels of memory cells, in other examples, the memory array 700 may include more or fewer blocks, sub-blocks, physical pages, strings of memory cells, memory cells, or levels. For example, each string of memory cells may include more or fewer levels (e.g., 16, 32, 64, 128, etc.) as desired, as well as one or more additional levels of semiconductor material above or below the storage transistors (e.g., select gates, data lines, etc.). As an example, a 48GB TLC NAND memory device may contain 18,592 bytes (B) of data per page (16,384 + 2208 bytes), 1536 pages per block, 548 blocks per plane, and 4 or more planes per device.

[0071] Each memory cell in the memory array 700 includes a memory cell coupled to (eg, electrically connected to or otherwise operably connected to) an access line (eg, a word line (WL) WL0). 0 710A to WL7 0 717A、WL0 1 710B to WL7 1 717B, etc.), the access lines commonly couple the control gates (CG) across a particular level or portion of a level as needed. A particular level, and thus a particular memory cell in a string, in a 3D memory array may be accessed or controlled using a respective access line. Various select lines may be used to access groups of select gates. For example, A 0 SGD LineSGDA 0 725A 0 Access First A 0 SGD 726A 0 To the third A 0 SGD 728A 0 , you can use A n SGD LineSGDA n 725A n Access First A n SGD 726A n To the third A n SGD 728A n , you can use B 0 SGD LineSGDB 0 725B 0Access First B 0 SGD 726B 0 To the third B 0 SGD 728B 0 , and can use B n SGD LineSGDB n 725B n Access First B n SGD 726B n To the third B n SGD 728B n . The gate selection line SGS can be used 0 730A Access First A 0 SGS 731A 0 To the third A 0 SGS 733A 0 and the first A n SGS731A n To the third A n SGS 733A n , and the gate selection line SGS can be used 1 730B access first B 0 SGS 731B 0 To the third B 0 SGS 733B 0 and the first B n SGS 731B n To the third B n SGS 733B n .

[0072] In an example, the memory array 700 may include several levels of semiconductor material (e.g., polysilicon, etc.) configured to couple a control gate (CG) or select gate (or a portion of a CG or select gate) of each memory cell of a corresponding level of the array. A combination of bit lines (BLs) and select gates, etc., may be used to access, select, or control a particular string of memory cells in the array, and one or more access lines (e.g., word lines) may be used to access, select, or control a particular memory cell at one or more levels in a particular string.

[0073] In a NAND architecture semiconductor memory array, the state of a selected memory cell can be accessed by sensing a current or voltage change associated with a particular data line containing the selected memory cell. The memory array 700 can be accessed using one or more drivers (e.g., by a control circuit, one or more processors, digital logic, etc.). In an example, the one or more drivers can activate a particular memory cell or a set of memory cells by driving a particular potential to one or more data lines (e.g., bit lines BL0 to BL2), access lines (e.g., word lines WL0 to WL7), or select gates depending on the type of desired operation to be performed on the particular memory cell or set of memory cells.

[0074] To program or write data to a memory cell, a programming voltage (Vpgm) (eg, one or more programming pulses, etc.) may be applied to a selected word line (eg, WL4). 0 ), and thus applied to the control gate of each memory cell coupled to the selected word line. The programming pulse may start, for example, at or near 15V, and in some instances may increase in amplitude during each programming pulse application. When the programming voltage is applied to the selected word line, a potential, such as a ground potential (e.g., Vss), may be applied to the data line (e.g., bit line) and substrate (and thus the channel between the source and drain) of the memory cell targeted for programming, thereby causing charge transfer (e.g., direct injection or Fowler-Nordheim (FN) tunneling, etc.) from the channel to the floating gate of the target memory cell.

[0075] In contrast, a pass voltage (Vpass) may be applied to one or more word lines having memory cells that are not targeted for programming, or an inhibit voltage (e.g., Vcc) may be applied to data lines (e.g., bit lines) having memory cells that are not targeted for programming, for example, to inhibit charge from being transferred from the channel to the floating gates of such non-target memory cells. The pass voltage may be variable depending on, for example, the proximity of the applied pass voltage to the word lines targeted for programming. The inhibit voltage may include a power supply voltage (Vcc), such as a voltage from an external source or power supply (e.g., a battery, an AC to DC converter, etc.) relative to a ground potential (e.g., Vss).

[0076] As an example, if a programming voltage (eg, 15V or higher) is applied to a particular word line, such as WL4 0 , then a pass voltage of 10V may be applied to one or more other word lines, such as WL3 0 、WL5 0etc. to inhibit programming of non-target memory cells or to preserve the values ​​stored in such memory cells that are not targeted for programming. As the distance between the applied programming voltage and the non-target memory cells increases, the pass voltage required to prevent programming of the non-target memory cells can be reduced. For example, when WL4 is applied 0 When a programming voltage of 15V is applied, WL3 0 and WL5 0 Applying a 10V pass voltage to WL2 0 and WL6 0 Applying a pass voltage of 8V can supply power to WL1 0 and WL7 0 A pass voltage of 7V is applied, etc. In other examples, the pass voltage may be higher or lower, or the number of word lines may be more or less, etc.

[0077] The sense amplifier may be coupled to one or more of the data lines (eg, first, second, or third bit lines (BL0-BL2) 720-722) and may detect the state of each memory cell in the corresponding data line by sensing the voltage or current on the particular data line.

[0078] Between the application of one or more programming pulses (e.g., Vpgm), a verify operation may be performed to determine whether the selected memory cell has reached its intended programmed state. If the selected memory cell has reached its intended programmed state, it may be inhibited from further programming. If the selected memory cell has not yet reached its intended programmed state, additional programming pulses may be applied. If the selected memory cell has not reached its intended programmed state after a certain number of programming pulses (e.g., a maximum number), the selected memory cell or a string, block, or page associated with such selected memory cell may be marked as defective.

[0079] To erase a memory cell or group of memory cells (e.g., erasure is typically performed in blocks or sub-blocks), an erase voltage (Vers) (e.g., typically Vpgm) may be applied (e.g., using one or more bit lines, select gates, etc.) to the substrate (and thus the channel between the source and drain) of the memory cell targeted for erasure while the word line of the target memory cell is maintained at a potential such as ground potential (e.g., Vss), thereby causing charge transfer (e.g., direct injection or Fowler-Nordheim (FN) tunneling, etc.) from the floating gate of the target memory cell to the channel.

[0080] Figure 8An example block diagram of a memory device 800 is illustrated, the memory device including a memory array 802 having a plurality of memory cells 804, and one or more circuits or components that provide communication with the memory array 802 or perform one or more memory operations on the memory array 802. Although shown as having a single memory array 802, in other examples, one or more additional memory arrays, dies, or LUNs may be included herein. In some examples, in a storage system having several dies or LUNs, the memory device 800 may represent a block diagram of circuits and components for each die or LUN. The memory device 800 may include a row decoder 812, a column decoder 814, a sense amplifier 820, a page buffer 822, a selector 824, an input / output (I / O) circuit 826, and a memory control unit 830.

[0081] The memory cells 804 of the memory array 802 may be arranged in blocks, such as a first block 802A and a second block 802B. Each block may include sub-blocks. For example, the first block 802A may include a first sub-block 802A. 0 and the second sub-block 802A n , and the second block 802B may include the first sub-block 802B 0 and the second sub-block 802B n Each sub-block may include a number of physical pages, each page including a number of memory cells 804. Although illustrated herein as having two blocks, each block having two sub-blocks, and each sub-block having a number of memory cells 804, in other examples, the memory array 802 may include more or fewer blocks, sub-blocks, memory cells, etc. In other examples, the memory cells 804 may be arranged in a number of rows, columns, pages, sub-blocks, blocks, etc., and accessed using, for example, an access line 806, a first data line 810, or one or more select gates, source lines, etc.

[0082] The memory control unit 830 may control the memory operation of the memory device 800 according to one or more signals or instructions received on the control line 832, including, for example, one or more clock signals or control signals indicating the desired operation (e.g., write, read, erase, etc.), or address signals (A0-AX) received on one or more address lines 816. One or more devices external to the memory device 800 may control the value of the control signal on the control line 832 or the address signal on the address line 816. Examples of devices external to the memory device 800 may include, but are not limited to, a host, a memory controller, a processor, or Figure 8 One or more circuits or components not described in the specification.

[0083] The memory device 800 can transfer (e.g., write or erase) data to or from (e.g., read) one or more of the memory cells 804 using the access lines 806 and the first data lines 810. The row decoder 812 and the column decoder 814 can receive and decode address signals (A0-AX) from the address lines 816, can determine which memory cells 804 are to be accessed, and can provide signals to one or more of the access lines 806 (e.g., one or more of a plurality of word lines (WL0-WLm)) or the first data lines 810 (e.g., one or more of a plurality of bit lines (BL0-BLn)), such as described above.

[0084] The memory device 800 may include sensing circuitry, such as sense amplifiers 820, configured to determine (e.g., read) the value of data on the memory cell 804, or to determine the value of data to be written to the memory cell, using the first data line 810. For example, in a selected string of memory cells 804, in response to a read current flowing through the selected string in the memory array 802 to the data line 810, one or more of the sense amplifiers 820 may read the logic level in the selected memory cell 804.

[0085] One or more devices external to the memory device 800 may communicate with the memory device 800 using the I / O lines (DQ0-DQN) 808, the address lines 816 (A0-AX), or the control lines 832. The input / output (I / O) circuits 826 may use the I / O lines 808 to transfer values ​​of data to or from the memory device 800, such as to or from the page buffers 822 or the memory array 802, based on, for example, the control lines 832 and the address lines 816. The page buffers 822 may store data received from one or more devices external to the memory device 800 before the data is programmed into the associated portion of the memory array 802, or may store data read from the memory array 802 before the data is transmitted to one or more devices external to the memory device 800.

[0086] The column decoder 814 can receive the address signals (A0-AX) and decode them into one or more column select signals (CSEL1-CSELn). The selector 824 (e.g., a selection circuit) can receive the column select signals (CSEL1-CSELn) and select the data in the page buffer 822 representing the data value to be read from or programmed into the memory cell 804. The selected data can be transmitted between the page buffer 822 and the I / O circuit 826 using the second data line 818.

[0087] The memory control unit 830 may receive positive and negative power supply signals, such as a power supply voltage (Vcc) 834 and a negative power supply (Vss) 836 (e.g., ground potential) from an external source or power supply (e.g., an internal or external battery, an AC to DC converter, etc.). In some examples, the memory control unit 830 may include a regulator 828 to provide the positive or negative power supply signals internally.

[0088] Fig. 9 Block diagram illustrating an example machine (eg, host system) 900 on which any one or more of the techniques (eg, methods) discussed herein may be executed (eg, Figure 1 , etc.). In alternative embodiments, the machine 900 may operate as a standalone device or may be connected (e.g., networked) to other machines. In a networked deployment, the machine 900 may operate as a server machine, a client machine, or both in a server-client network environment. In an example, the machine 900 may act as a peer machine in a peer-to-peer (P2P) (or other distributed) network environment. The machine 900 may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a network appliance, an IoT device, an automotive system, or any machine capable of executing (sequentially or otherwise) instructions specifying actions to be taken by the machine. In addition, although only a single machine is described, the term "machine" will also be deemed to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methods discussed herein, such as cloud computing, software as a service (SaaS), and other computer cluster configurations.

[0089] As described herein, an example may include logic, components, devices, packages, or mechanisms, or may be operated by logic, components, devices, packages, or mechanisms. A circuit system is a collection (e.g., a set) of circuits implemented in a tangible entity including hardware (e.g., simple circuits, gates, logic, etc.). The members of the circuit system may be flexible over time and as the underlying hardware changes. The circuit system includes components that can perform specific tasks individually or in combination when in operation. In an example, the hardware of the circuit system may be designed in an unchangeable manner to perform specific operations (e.g., hard wiring). In an example, the hardware of the circuit system may include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.), which include computer-readable media that are physically modified (e.g., magnetic, electrically movable placement of fixed centralized particles, etc.) to encode instructions for specific operations. When the physical components are connected, the basic electrical properties of the hardware composition are changed, for example, from an insulator to a conductor or vice versa. The instructions enable the participating hardware (e.g., execution units or loading mechanisms) to generate components of the circuit system in the hardware via variable connections to perform parts of specific tasks when in operation. Thus, the computer-readable medium is communicatively coupled to other components of the circuit system when the device is operating. In an example, any of the physical components may be used in more than one component in more than one circuit system. For example, under operation, an execution unit may be used in a first circuit of a first circuit system at one point in time and reused by a second circuit in the first circuit system, or reused by a third circuit in the second circuit system at a different time.

[0090] The machine (e.g., a computer system, a host system, etc.) 900 may include a processing device 902 (e.g., a hardware processor, a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof, etc.), a main memory 904 (e.g., a read-only memory (ROM), a dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 906 (e.g., a static random access memory (SRAM)), etc.), and a storage system 918, some or all of which may communicate with each other via a communication interface (e.g., a bus) 930.

[0091] The processing device 902 may represent one or more general processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. The processing device 902 may also be one or more special processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 902 may be configured to execute instructions 926 for performing the operations and steps discussed herein. The computer system 900 may further include a network interface device 908 to communicate on a network 920.

[0092] The storage system 918 may include a machine-readable storage medium (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 926 or software embodying any one or more of the methodologies or functions described herein. The instructions 926 may also reside, completely or at least partially, within the main memory 904 and / or within the processing device 902 during execution by the computer system 900, the main memory 904 and the processing device 902 also constituting machine-readable storage media.

[0093] The term "machine-readable storage medium" should be taken to include a single medium or multiple media storing one or more sets of instructions, or any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present invention. Thus, the term "machine-readable storage medium" should be taken to include, but not be limited to, solid-state memory, optical media, and magnetic media. In an example, a centralized machine-readable medium includes a machine-readable medium having a plurality of particles, the particles having a constant (e.g., stationary) mass. Thus, a centralized machine-readable medium is not a transient propagating signal. Specific examples of centralized machine-readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0094] The machine 900 may further include a display unit, an alphanumeric input device (e.g., a keyboard), and a user interface (UI) navigation device (e.g., a mouse). In an example, one or more of the display unit, input device, or UI navigation device may be a touch screen display. A machine signal generating device (e.g., a speaker), or one or more sensors, such as a global positioning system (GPS) sensor, a compass, an accelerometer, or one or more other sensors. The machine 900 may include an output controller, such as a serial (e.g., universal serial bus (USB), parallel or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection to communicate with or control one or more peripheral devices (e.g., printer, card reader, etc.).

[0095] Instructions 926 (e.g., software, programs, operating system (OS), etc.) or other data stored on storage system 918 may be accessed by main memory 904 for use by processing device 902. Main memory 904 (e.g., DRAM) is typically fast but volatile, and therefore a different type of storage device than storage system 918 (e.g., SSD), which is suitable for long-term storage, including long-term storage when in an "off" condition. Instructions 926 or data for use by a user or machine 900 are typically loaded in main memory 904 for use by processing device 902. When main memory 904 is full, virtual space from storage system 918 may be allocated to supplement main memory 904; however, because storage system 918 is typically slower than main memory 904, and write speeds are typically at least twice slower than read speeds, the use of virtual memory can greatly reduce the user experience due to storage system latency (compared to main memory 904, e.g., DRAM). Furthermore, using storage system 918 for virtual storage may significantly shorten the usable life of storage system 918 .

[0096] The instructions 924 may further be transmitted or received over the communication network 920 using a transmission medium via the network interface device 908 using any of a number of transmission protocols (e.g., frame relay, Internet Protocol (IP), transmission control protocol (TCP), user datagram protocol (UDP), hypertext transfer protocol (HTTP), etc.). Example communication networks may include a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), a mobile telephone network (e.g., a cellular network), a plain old telephone (POTS) network, and a wireless data network (e.g., a wireless network called a cellular network), among others. The Institute of Electrical and Electronics Engineers (IEEE) 802.11 series of standards, known as ), IEEE 802.16 family of standards, IEEE 802.15.4 family of standards, peer-to-peer (P2P) networks. In an example, network interface device 908 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas to connect to network 920. In an example, network interface device 908 may include multiple antennas to communicate wirelessly using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) technology. The term "transmission media" should be taken to include any intangible media capable of storing, encoding, or carrying instructions for execution by machine 900, and includes digital or analog communication signals or other intangible media for facilitating communication of such software.

[0097] The above detailed description includes reference to the accompanying drawings, which form part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the present invention can be practiced. These embodiments are also referred to herein as "examples". Such examples may include elements other than those shown or described. However, the inventors also contemplate examples in which only those elements shown or described are provided. In addition, the inventors also contemplate examples (or one or more aspects thereof) of any combination or arrangement of those elements shown or described with respect to a specific example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0098] All publications, patents, and patent documents referenced in this document are incorporated herein by reference in their entirety, as if individually incorporated by reference. In the event of an inconsistency in usage between this document and those documents incorporated by reference, the usage in the incorporated reference documents should be considered supplementary to that of this document; for irreconcilable inconsistencies, the usage in this document controls.

[0099] In this document, as is common in patent documents, the term "one" is used to include one or more than one, independent of any other examples or uses of "at least one" or "one or more". In this document, unless otherwise indicated, the term "or" is used to refer to non-exclusive or so that "A or B" includes "A but not including B", "B but not including A" and "A and B". In the appended claims, the terms "including" and "in which" are used as colloquial equivalents of the corresponding terms "including" and "wherein". Moreover, in the appended claims, the terms "including" and "including" are open-ended, that is, systems, devices, objects or processes containing elements other than those listed after such terms in the claims are still considered to be within the scope of the claims. In addition, in the appended claims, the terms "first", "second" and "third" etc. are used only as markers and are not intended to impose numerical requirements on their objects.

[0100] In various examples, the components, controllers, processors, units, engines, or tables described herein may include, among other things, physical circuitry or firmware stored on a physical device. As used herein, "processor" means any type of computing circuit, such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor (DSP), or any other type of processor or processing circuit, including groups of processors or multi-core devices.

[0101] The term "horizontal" as used in this document is defined as a plane parallel to a conventional plane or surface of a substrate, such as a conventional plane or surface underlying a wafer or die, regardless of the actual orientation of the substrate at any point in time. The term "vertical" refers to a direction perpendicular to the horizontal as defined above. Prepositions such as "on", "above", and "below" are defined relative to a conventional plane or surface on the top or exposed surface of a substrate, regardless of the orientation of the substrate; and while "on" is intended to indicate direct contact of one structure relative to another structure that is "on" it (in the absence of an expression indicating the contrary); the terms "above" and "below" are expressly intended to identify the relative placement of structures (or layers, features, etc.), which expressly include but are not limited to direct contact between the identified structures unless specifically identified as such. Similarly, the terms "above" and "below" are not limited to horizontal orientations, because if a structure is the outermost part of the construction being discussed at a certain point in time, then such structure can be "above" a reference structure even if such structure extends vertically rather than in a horizontal orientation relative to the reference structure.

[0102] The terms "wafer" and "substrate" are used herein to refer generally to any structure on which an integrated circuit is formed, and also to such structures during the various stages of integrated circuit fabrication. The following detailed description, therefore, should not be taken in a limiting sense, and the scope of the various embodiments is defined solely by the appended claims, along with the full scope of equivalents to which such claims are entitled.

[0103] Various embodiments according to the present invention and described herein include memories utilizing a vertical structure of memory cells (e.g., a NAND string of memory cells). As used herein, directional adjectives will be employed relative to the surface of a substrate on which the memory cells are formed (i.e., a vertical structure will be considered to extend away from the substrate surface, a bottom end of a vertical structure will be considered to be the end closest to the substrate surface, and a top end of a vertical structure will be considered to be the end farthest from the substrate surface).

[0104] As used herein, directional adjectives, such as horizontal, vertical, orthogonal, parallel, perpendicular, etc., may refer to relative orientations, and unless otherwise indicated, are not intended to require strict adherence to specific geometric properties. For example, as used herein, a vertical structure need not be strictly perpendicular to the surface of a substrate, but may instead be substantially perpendicular to the surface of a substrate, and may form an acute angle (e.g., between 60 and 120 degrees, etc.) with the surface of the substrate.

[0105] In some embodiments described herein, different doping configurations may be applied to a select gate source (SGS), a control gate (CG), and a select gate drain (SGD), each of which in this instance may be formed of or at least include polysilicon, such that these layers (e.g., polysilicon, etc.) may have different etch rates when exposed to an etching solution. For example, during the formation of a monomer pillar in a 3D semiconductor device, the SGS and CG may form a recess, while the SGD may remain less recessed or even not recessed. These doping configurations may thus enable selective etching into different layers (e.g., SGS, CG, and SGD) in a 3D semiconductor device using an etching solution (e.g., tetramethylammonium hydroxide (TMCH)).

[0106] As used herein, operating a memory cell includes reading from the memory cell, writing to the memory cell, or erasing the memory cell. The operation of placing a memory cell in a desired state is referred to herein as "programming," and may include both writing to the memory cell or erasing from the memory cell (i.e., a memory cell may be programmed to an erased state).

[0107] According to one or more embodiments of the present invention, a memory controller (e.g., a processor, controller, firmware, etc.) located inside or outside a memory device is capable of determining (e.g., selecting, setting, adjusting, calculating, changing, clearing, transferring, adapting, deriving, defining, utilizing, modifying, applying, etc.) a certain number of wear cycles or wear states (e.g., recording wear cycles, counting operations of the memory device when they occur, tracking operations of the memory device from which they originate, evaluating memory device characteristics corresponding to wear states, etc.).

[0108] According to one or more embodiments of the present invention, a memory access device may be configured to provide wear cycle information to a memory device with each memory operation. The memory device control circuitry (e.g., control logic) may be programmed to compensate for memory device performance changes corresponding to the wear cycle information. The memory device may receive the wear cycle information and determine one or more operating parameters (e.g., values, characteristics) in response to the wear cycle information.

[0109] It will be understood that when an element is referred to as being "on," "connected to," or "coupled to" another element, it may be directly on, directly connected or coupled to another element, or there may be intervening elements. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element, there are no intervening elements or layers. If two elements are shown in a drawing as being connected by a line, the two elements may be coupled or directly coupled unless otherwise indicated.

[0110] The method examples described herein may be implemented at least in part by a machine or computer. Some examples may include a computer-readable medium or machine-readable medium encoded with instructions, which are operable to configure an electronic device to perform a method as described in the above examples. The implementation of such methods may include code, such as microcode, assembly language code, high-level language code, or the like. Such code may include computer-readable instructions for executing various methods. The code may form part of a computer program product. In addition, the code may be tangibly stored on one or more volatile or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media may include, but are not limited to, hard disks, removable disks, removable optical disks (e.g., optical disks and digital video disks), cassettes, memory cards or sticks, random access memories (RAM), read-only memories (ROM), and the like.

[0111] In Example 1, a subject matter (e.g., a storage system) may include: a first group of nonvolatile memory cells, the first group including multiple pages of memory cells; a control circuit system configured to: receive temperature information corresponding to a write temperature of at least one page of the first group of nonvolatile memory cells; determine a statistical measure of the temperature information for the first group of nonvolatile memory cells using the received temperature information; and store the determined statistical measure of the temperature information for the first group of nonvolatile memory cells.

[0112] In Example 2, the subject matter described in Example 1 may optionally be configured such that to determine a statistical measure of temperature information for a first group of nonvolatile memory cells, the control circuit system is configured to determine at least one metric using received temperature information of at least one page of the first group of memory cells, the at least one metric including at least one of an average temperature, a maximum temperature, a minimum temperature, a variance, a standard deviation, or a distribution of the temperature information for the first group of nonvolatile memory cells, the first group of nonvolatile memory cells comprising a super block or a window, and to receive the temperature information, the control circuit system is configured to receive temperature information corresponding to write temperatures of two or more pages of the first group of nonvolatile memory cells.

[0113] In Example 3, the subject matter described according to any one or more of Examples 1 to 2 may optionally be configured such that the control circuit system includes a memory controller, the memory controller being configured to: receive a read command for data associated with at least a portion of a first group of nonvolatile memory cells, and the control circuit system being configured to: determine read parameters for the first group of nonvolatile memory cells using stored statistical measures of temperature information for the first group of nonvolatile memory cells; and read data from the first group of nonvolatile memory cells in response to the read command using the determined read parameters.

[0114] In Example 4, the subject matter described according to any one or more of Examples 1 to 3 may optionally include a temperature sensor configured to detect a temperature indication, wherein the control circuit system includes a memory controller configured to: receive a write command and user data associated with the write command from a host device; receive temperature information from the temperature sensor; use the temperature information to amplify auxiliary data associated with the user data; and write the user data associated with the write command and the auxiliary data to at least one page of the first group of memory cells.

[0115] In Example 5, the subject matter described according to any one or more of Examples 1 to 4 may optionally be configured such that pages of memory cells are organized into multiple blocks, and the control circuit system is configured to: receive current temperature information of the storage system; and determine one of the multiple blocks on which to perform a folding operation using the stored statistical measure of temperature information for the first group of non-volatile memory cells and the current temperature information of the storage system.

[0116] In Example 6, the subject matter described according to any one or more of Examples 1 to 5 may optionally be configured such that the multiple groups of nonvolatile memory cells include a first group of nonvolatile memory cells, wherein the control circuit system is configured to: receive temperature information corresponding to the write temperature of at least one page of each of the multiple groups of nonvolatile memory cells; determine a statistical measure of the temperature information for each of the multiple groups of nonvolatile memory cells using the received temperature information; and store the determined statistical measure of the temperature information for each of the multiple groups of nonvolatile memory cells, and wherein the control circuit system is configured to: before performing a first memory operation on a selected one of the multiple groups of nonvolatile memory cells, use the stored statistical measure of the temperature information to determine one of the multiple groups of nonvolatile memory cells on which to perform the first memory operation.

[0117] In Example 7, the subject matter described according to any one or more of Examples 1 to 6 may optionally be configured such that the control circuit system is configured to: perform a first memory operation on a first subgroup of a first group of nonvolatile memory cells; receive temperature information from the first subgroup of the first group of nonvolatile memory cells during the first memory operation; determine a statistical measure of the temperature information for the first group of nonvolatile memory cells using the received temperature information from the first subgroup of the first group of nonvolatile memory cells; and store the received temperature information from the first subgroup of the first group of nonvolatile memory cells in a first data structure on a storage system.

[0118] In Example 8, the subject matter described according to any one or more of Examples 1 to 7 may optionally be configured such that the control circuit system includes a memory controller, the memory controller being configured to: receive a second memory operation associated with a second subgroup of the first group of non-volatile memory cells, and the control circuit system being configured to: determine a read parameter for the second subgroup of the first group of non-volatile memory cells using a stored statistical measure of temperature information for the first group of non-volatile memory cells before reading data associated with the second subgroup of the first group of non-volatile memory cells in response to the second memory operation.

[0119] In Example 9, the subject matter described according to any one or more of Examples 1 to 8 may optionally be configured such that the control circuit system includes: a memory controller configured to: receive or detect an extended memory operation associated with a first subgroup of a first group of non-volatile memory cells, the extended memory operation comprising a folding operation or a sequential read operation; and a control circuit system configured to: determine initial read parameters using stored statistical measures of temperature information for the first group of non-volatile memory cells before reading data associated with the extended memory operation; and load the stored temperature information of the first subgroup of the first group of non-volatile memory cells from a dedicated first data structure.

[0120] In Example 10, the subject matter described according to any one or more of Examples 1 to 9 may optionally be configured such that the first memory operation includes a read operation or a garbage collection operation, the first group of nonvolatile memory cells includes a first superpage of nonvolatile memory cells, the first subgroup of the first group of nonvolatile memory cells includes a first page of nonvolatile memory cells, and the control circuit system is configured to: update the first data structure after receiving additional temperature information from the first group of nonvolatile memory cells.

[0121] In Example 11, the subject matter described according to any one or more of Examples 1 to 10 may optionally include: a memory controller comprising a group of volatile memory cells, the memory controller being configured to receive memory operations from a host device separate from the memory system; and a memory device comprising a device controller and a first group of non-volatile memory cells, wherein the control circuit system comprises the group of volatile memory cells and at least one of the memory controller or the device controller and is configured to store the determined statistical measure of temperature information in a table in a static memory.

[0122] In Example 12, the subject matter described according to any one or more of Examples 1 to 11 may optionally be configured such that in order to receive temperature information corresponding to the write temperature of at least one page of the first group of nonvolatile memory cells, the control circuit system is configured to: receive temperature information corresponding to the write temperature of at least one page of nonvolatile memory cells selected in response to a memory operation to determine a statistical measure of the temperature information for the first group of nonvolatile memory cells; or receive temperature information corresponding to the write temperature of at least one page of nonvolatile memory cells associated with a memory operation in which auxiliary data of at least one page is read.

[0123] In Example 13, the subject matter described according to any one or more of Examples 1 to 12 may optionally be configured such that the control circuit system is configured to: update a determined statistical measure of temperature information for a first group of nonvolatile memory cells, and store the updated determined statistical measure in response to receiving additional temperature information corresponding to a write temperature of at least one of a plurality of pages of the first group of nonvolatile memory cells.

[0124] In Example 14, subject matter (e.g., a method) may include: receiving, using a control circuit system of a storage system, temperature information corresponding to a write temperature of at least one of a plurality of pages of nonvolatile memory cells for each of a plurality of groups of nonvolatile memory cells; determining, using the control circuit system, a statistical measure of the temperature information for each of the plurality of groups of nonvolatile memory cells using the received temperature information; and storing, using the control circuit system, the determined statistical measure of the temperature information for each of the plurality of groups of nonvolatile memory cells.

[0125] In Example 15, the subject matter described in Example 14 may optionally include: receiving a read command for data associated with at least a portion of a first group of nonvolatile memory cells; determining read parameters for the first group of nonvolatile memory cells using stored statistical measures of temperature information for the first group of nonvolatile memory cells before performing a read operation in response to the read command; and reading data from the first group of nonvolatile memory cells in response to the read command using the determined read parameters.

[0126] In Example 16, the subject matter described according to any one or more of Examples 14 to 15 may optionally be configured such that pages of memory cells are organized into multiple blocks, the method further comprising: receiving current temperature information of the storage system; and determining one of the multiple blocks on which to perform a folding operation using stored statistical measures of temperature information for each of multiple groups of non-volatile memory cells and the current temperature information of the storage system.

[0127] In Example 17, the subject matter described according to any one or more of Examples 14 to 16 may optionally be configured to include: before performing the first memory operation on a selected one of the plurality of groups of non-volatile memory cells, determining one of the plurality of groups of non-volatile memory cells on which to perform the first memory operation using a stored statistical measure of temperature information.

[0128] In Example 18, the subject matter described according to any one or more of Examples 14 to 17 may optionally be configured to include: performing a first memory operation on a first subgroup of a first group of multiple groups of nonvolatile memory cells; receiving temperature information from the first subgroup of the first group of nonvolatile memory cells during the first memory operation; determining a statistical measure of the temperature information for the first group of nonvolatile memory cells using the received temperature information from the first subgroup of the first group of nonvolatile memory cells; and storing the received temperature information from the first subgroup of the first group of nonvolatile memory cells in a first data structure on a storage system.

[0129] In Example 19, the subject matter described according to any one or more of Examples 14 to 18 may optionally be configured to receive a second memory operation associated with a second subgroup of the first group of nonvolatile memory cells; and before reading data associated with the second subgroup of the first group of nonvolatile memory cells in response to the second memory operation, determine a read parameter for the second subgroup of the first group of nonvolatile memory cells using a stored statistical measure of temperature information for the first group of nonvolatile memory cells.

[0130] In Example 20, the subject matter described according to any one or more of Examples 14 to 19 may optionally be configured to receive or detect an extended memory operation associated with a first subgroup of a first group of non-volatile memory cells, the extended memory operation comprising a folding operation or a sequential read operation; determine initial read parameters using stored statistical measures of temperature information for the first group of non-volatile memory cells before reading data associated with the extended memory operation; and load the stored temperature information of the first subgroup of the first group of non-volatile memory cells from a dedicated first data structure.

[0131] In Example 21, the subject matter described according to any one or more of Examples 14 to 20 may optionally be configured such that receiving temperature information corresponding to a write temperature of at least one of a plurality of pages includes: receiving temperature information from at least one of a plurality of pages of each of a plurality of groups of nonvolatile memory cells in response to a memory operation to determine a statistical measure of temperature information for the plurality of groups of nonvolatile memory cells; or receiving temperature information from at least one of a plurality of pages of each of a plurality of groups of nonvolatile memory cells in response to a separate memory operation for each of the plurality of groups.

[0132] In Example 22, the subject matter described according to any one or more of Examples 14 to 21 may optionally be configured to update the determined statistical measure of the temperature information in response to receiving additional temperature information corresponding to the write temperature of at least one of the multiple pages of the multiple groups of non-volatile memory cells, and store the updated determined statistical measure.

[0133] In Example 23, subject matter (e.g., a non-transitory device readable storage medium) may include instructions that, when executed by a control circuit system of the storage system, cause the storage system to perform operations including: receiving temperature information corresponding to a write temperature of at least one of a plurality of pages of nonvolatile memory cells for each of a plurality of groups of nonvolatile memory cells; determining a statistical measure of the temperature information for each of the plurality of groups of nonvolatile memory cells using the received temperature information; and storing the determined statistical measure of the temperature information for each of the plurality of groups of nonvolatile memory cells.

[0134] In Example 24, the subject matter of Example 23 may optionally be configured such that operation includes, before performing the first memory operation on a selected one of the plurality of groups of nonvolatile memory cells, determining, using a stored statistical measure of temperature information, one of the plurality of groups of nonvolatile memory cells on which to perform the first memory operation.

[0135] In Example 25, the subject matter described according to any one or more of Examples 23 to 24 may optionally be configured such that operation includes updating a determined statistical measure of temperature information in response to receiving additional temperature information corresponding to a write temperature of at least one of a plurality of pages of a plurality of groups of non-volatile memory cells, and storing the updated determined statistical measure.

[0136] In Example 26, the subject matter (e.g., a method) may include: monitoring temperatures in multiple regions of a memory device during selected operations in such regions; determining at least one measure of the monitored temperatures in the regions, the measure selected from a group consisting essentially of a maximum value, a minimum value, a mean value, a variance, a standard deviation, a coefficient of variation, and a distribution of the monitored temperatures; for at least one determined measure relative to the monitored regions, storing one or more bits representing the determined measure; and reading the one or more stored bits for at least one monitored region to determine the region of the memory device in which the memory operation is to be performed.

[0137] In Example 27, the subject matter (e.g., a system or apparatus) may optionally combine any portion or combination of any portion of any one or more of Examples 1 to 26 to include "a device for performing any portion of any one or more of the functions or methods described in Examples 1 to 26," or at least one "non-transitory machine-readable medium" containing instructions that, when executed by a machine, cause the machine to perform any portion of any one or more of the functions or methods described in Examples 1 to 26.

[0138] The above description is intended to be illustrative rather than restrictive. For example, the examples described above (or one or more aspects thereof) can be used in combination with each other. For example, a person of ordinary skill in the art can use other embodiments after consulting the above description. An abstract is provided to comply with 37C.FR§1.72(b), thereby allowing the reader to quickly confirm the essence of the technical disclosure. It should be understood that the abstract will not be used to interpret or limit the scope or meaning of the claims. Moreover, in the above specific embodiments, various features can be grouped together to simplify the present invention. This situation should not be interpreted as intending that the disclosed features that are not claimed for protection are necessary for any claim. In fact, the subject matter of the present invention may be less than all the features of a specific disclosed embodiment. Therefore, the attached claims are hereby incorporated into the specific embodiments, wherein each claim exists independently as a separate embodiment, and it is expected that such embodiments can be combined with each other in various combinations or arrangements. The scope of the present invention should be determined by reference to the attached claims and the full scope of equivalents granted by such claims.

Claims

1. A storage system, comprising: a memory array comprising a plurality of groups of nonvolatile memory cells, each group comprising a plurality of pages of memory cells; as well as A control circuit system configured to: receiving temperature information corresponding to a write temperature of at least one page of memory cells; determining a group statistical measure of temperature information for a plurality of groups of the non-volatile memory cells using the received temperature information; determining a variation in temperature information across the memory array; grouping the plurality of groups of nonvolatile memory cells into different zones associated with a range of temperature information using the determined group statistics, wherein the sizes of the different zones are dynamic relative to determined variations in temperature information across the memory array; as well as An integrated region and a group of non-volatile memory cells associated with the region are stored.

2. The storage system according to claim 1, in, In order to store the integrated regions and the groups of non-volatile memory cells associated with the regions, the control circuit system is configured to store the integrated regions and the groups of non-volatile memory cells associated with the regions in a volatile memory that supports the control circuit system to be available for use without a read operation of the non-volatile memory cells.

3. The storage system according to claim 1, in, To determine the group statistical measure of temperature information for the plurality of groups of the nonvolatile memory cells, the control circuit system is configured to determine at least one metric using the received temperature information of the at least one page of a respective group of nonvolatile memory cells, the at least one metric comprising at least one of an average temperature, a maximum temperature, a minimum temperature, a variance, a standard deviation, or a distribution of temperature information for the respective group of nonvolatile memory cells.

4. The storage system according to claim 3, wherein the group of non-volatile memory cells comprises a superblock or a stripe of superblocks, and in, To receive temperature information, the control circuitry is configured to receive temperature information corresponding to write temperatures of two or more pages of the respective group of non-volatile memory cells.

5. The storage system according to claim 1, wherein the control circuitry includes a memory controller configured to: receiving a read command for data associated with at least a portion of a first group of non-volatile memory cells, and wherein the control circuit system is configured to: determining read parameters for a first group of nonvolatile memory cells using the stored integrated region for the first group of nonvolatile memory cells; and Data is read from a first group of the non-volatile memory cells in response to the read command using the determined read parameters.

6. The storage system according to claim 1, comprising: a temperature sensor configured to detect an indication of a temperature, wherein the control circuitry includes a memory controller configured to: receiving a write command and user data associated with the write command from a host device; receiving temperature information from the temperature sensor; augmenting auxiliary data associated with the user data using the temperature information; as well as The user data associated with the write command and the auxiliary data are written to at least one page of a plurality of groups of the memory cells.

7. The storage system according to claim 1, wherein the pages of memory cells are organized into a plurality of blocks, and wherein the control circuit system is configured to: receiving current temperature information of the storage system; and One of the plurality of blocks on which to perform a fold operation is determined using the stored consolidated region and the group of non-volatile memory cells associated with the region and the current temperature information of the memory system.

8. The storage system according to claim 1, wherein the control circuit system is configured to: Prior to performing a first memory operation on a selected one of a plurality of groups of nonvolatile memory cells, one of the plurality of groups of nonvolatile memory cells on which to perform the first memory operation is determined using the stored integrated region and the group of nonvolatile memory cells associated with the region.

9. The storage system according to claim 1, wherein the control circuitry includes a memory controller configured to: receiving a memory operation associated with the at least one subgroup of the plurality of groups of the non-volatile memory cells, and wherein the control circuit system is configured to: Prior to reading data associated with the subgroup of the at least one of the multiple groups of the nonvolatile memory cells in response to the memory operation, read parameters for the subgroup of the at least one of the multiple groups of the nonvolatile memory cells are determined using the stored integrated region for the at least one of the multiple groups of the nonvolatile memory cells.

10. The storage system according to claim 1, wherein storing the integrated region and the group of non-volatile memory cells associated with the region in a volatile memory comprises storing in a dedicated first data structure on the storage system, and wherein the control circuitry includes a memory controller configured to: receiving or detecting an extended memory operation associated with a first subgroup of the at least one of the plurality of groups of the non-volatile memory cells, the extended memory operation comprising a folding operation or a sequential read operation, and wherein the control circuit system is configured to: Prior to reading data associated with the extended memory operation, determining initial read parameters using the determined variation in temperature information across the memory array; and The stored consolidated region and the group of non-volatile memory cells associated with the region are loaded from the dedicated first data structure.

11. The storage system according to claim 1, comprising: a memory controller comprising a group of volatile memory cells, the memory controller being configured to receive memory operations from a host device separate from the memory system; as well as A memory device comprising a device controller and a first group of said non-volatile memory cells, Wherein the control circuitry includes groups of volatile memory cells and at least one of the memory controller or the device controller and is configured to store in a table in static memory the integrated regions and the groups of non-volatile memory cells associated with the regions.

12. The storage system according to claim 1, in, To receive temperature information corresponding to the write temperature of at least one page of memory cells, the control circuitry is configured to: receiving temperature information corresponding to the write temperature of at least one page of nonvolatile memory cells selected in response to a memory operation to determine a group statistical measure of the temperature information for a first group of the nonvolatile memory cells; or Temperature information corresponding to the write temperature of at least one page of nonvolatile memory cells associated with a memory operation in which auxiliary data of the at least one page is read is received.

13. The storage system according to claim 1, wherein the control circuit system is configured to: A determined group statistical metric of temperature information for a corresponding group of nonvolatile memory cells is updated, and the updated determined group statistical metric is stored in response to receiving additional temperature information corresponding to a write temperature of at least one of a plurality of pages of the corresponding group of nonvolatile memory cells.

14. The storage system according to claim 1, wherein the different zones across the memory array include at least three zones, each zone including a portion of the determined variation in temperature information across the memory array, the at least three zones including a low zone for temperature information below a first threshold temperature, a high zone for temperature information above a second threshold temperature, and at least one intermediate zone for temperature information between the first threshold temperature and the second threshold temperature.

15. A method comprising: receiving, using control circuitry of a memory system, temperature information corresponding to a write temperature of at least one of a plurality of pages of nonvolatile memory cells of each of a plurality of groups of nonvolatile memory cells of a memory array of the memory system; determining, using the control circuitry, a group statistical measure of temperature information for each of a plurality of groups of the nonvolatile memory cells using the received temperature information; determining, using the control circuitry, a variation in temperature information across the memory array; using the control circuitry to aggregate a plurality of groups of the nonvolatile memory cells into distinct zones associated with ranges of temperature information utilizing the determined group statistics, wherein sizes of the distinct zones are dynamic relative to determined variations in temperature information across the memory array; as well as The control circuitry is used to store integrated regions and groups of non-volatile memory cells associated with the regions.

16. The method according to claim 15, Wherein storing the integrated region and the group of non-volatile memory cells associated with the region includes storing the integrated region and the group of non-volatile memory cells associated with the region in a volatile memory that supports the control circuit system to be available for use without a read operation of the non-volatile memory cells.

17. The method according to claim 15, wherein the different zones across the memory array include at least three zones, each zone including a portion of the determined variation in temperature information across the memory array, the at least three zones including a low zone for temperature information below a first threshold temperature, a high zone for temperature information above a second threshold temperature, and at least one intermediate zone for temperature information between the first threshold temperature and the second threshold temperature.

18. At least one non-transitory device readable storage medium comprising instructions that, when executed by control circuitry of a storage system, cause the storage system to perform operations comprising: receiving temperature information corresponding to a write temperature of at least one of a plurality of pages of nonvolatile memory cells of each of a plurality of groups of nonvolatile memory cells of a memory array of the memory system; determining a group statistical measure of temperature information for each of a plurality of groups of said non-volatile memory cells using the received temperature information; determining a variation in temperature information across the memory array; grouping the plurality of groups of nonvolatile memory cells into distinct zones associated with ranges of temperature information using the determined group statistics, wherein sizes of the distinct zones are dynamic relative to determined variations in temperature information across the memory array; as well as An integrated region and a group of non-volatile memory cells associated with the region are stored.

19. The device-readable storage medium according to claim 18, Wherein storing the integrated region and the group of non-volatile memory cells associated with the region includes storing the integrated region and the group of non-volatile memory cells associated with the region in a volatile memory that supports the control circuit system to be available for use without a read operation of the non-volatile memory cells.

20. The device-readable storage medium of claim 18, wherein the different zones across the memory array include at least three zones, each zone including a portion of the determined variation in temperature information across the memory array, the at least three zones including a low zone for temperature information below a first threshold temperature, a high zone for temperature information above a second threshold temperature, and at least one intermediate zone for temperature information between the first threshold temperature and the second threshold temperature.

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