Chip management network configuration method, chip management network system and related equipment

Abstract

The embodiment of the invention provides a chip management network configuration method, a chip management network system and related equipment, which are applied to a target chip, the target chip comprises a plurality of different types of core particles, each core particle comprises one or more modules, and each core particle is configured with a management network configuration sequence number. The management network configuration serial number is obtained based on the type of the core particle and the packaging position configuration of the core particle in the target chip; the method comprises the following steps: acquiring architecture information of a target chip, wherein the architecture information at least comprises a management network configuration serial number configured by a chip particle; according to the architecture information of the target chip, dividing a preset address space into a plurality of sub-configuration spaces; according to the management network configuration sequence number, corresponding sub-configuration spaces are distributed to the target chip and all core particles in the target chip in multiple sub-configuration spaces, and the sub-configuration spaces distributed to modules contained in all the core particles are different. According to the embodiment of the invention, the adaptability requirement on software is reduced.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of chip technology, and specifically to a chip management network configuration method, a chip management network system, and related equipment. Background Art

[0002] A chiplet is a unit chip that can realize certain functions and contains interconnection interfaces. Multiple chiplets can be packaged into a chiplet group (chiplet) through 2D, 2.5D, 3D and other packaging technologies, and different chiplets can be interconnected based on the interconnection interface to form a chip with the expected functions, such as a SOC (System On Chip) chip.

[0003] When designing a chip, by adjusting the number of corelets in the corelet group, chips with different specifications can be obtained. Moreover, in addition to determining the corelet group information that makes up the chip, management network configuration is also required. Among them, the management network connects the modules in the corelets that need to be configured and managed for address space. The chip manages each module in the corelet through the management network, and each module can also report interrupts and error information through the management network. It can be seen that the management network configuration of the chip is of great significance to realize the network connection and dynamic interaction between each corelet and achieve the expected functions of the chip.

[0004] However, the chips configured by the existing chip management network configuration method have high requirements on software adaptability. Summary of the invention

[0005] In view of this, the embodiments of the present application provide a chip management network configuration method, a chip management network system and related equipment to reduce the adaptability requirements for software.

[0006] In a first aspect, an embodiment of the present application provides a chip management network configuration method, which is applied to a target chip, wherein the target chip includes a plurality of core particles of different types, the core particles include one or more modules, and the core particles are configured with a management network configuration sequence number, and the management network configuration sequence number is configured based on the type of the core particle and its packaging position in the target chip, including:

[0007] Acquire architecture information of the target chip, wherein the architecture information at least includes a management network configuration sequence number of the chiplet configuration;

[0008] According to the architecture information of the target chip, the preset address space is divided into a plurality of sub-configuration spaces;

[0009] According to the management network configuration sequence number, in a plurality of sub-configuration spaces, corresponding sub-configuration spaces are allocated to the target chip and each coregrain in the target chip, wherein the modules included in each coregrain are allocated different sub-configuration spaces.

[0010] Optionally, the preset address space is divided into multiple sub-configuration spaces according to the architecture information of the target chip, specifically: according to the architecture information of the target chip, the preset address space is divided into multiple sub-configuration spaces that meet predetermined rules; wherein the predetermined rules are associated with the address space of each core particle in the target chip.

[0011] Optionally, the predetermined rule includes:

[0012] Different types of core particles correspond to different address spaces, and the modules contained in the core particles correspond to different address spaces.

[0013] Optionally, the architecture information of the target chip also includes the type of the target chip;

[0014] The step of dividing the preset address space into a plurality of sub-configuration spaces satisfying a predetermined rule according to the architecture information of the target chip comprises:

[0015] According to the type of the target chip, the preset address space is divided into a plurality of configuration spaces, and different configuration spaces correspond to different functional implementations of the target chip;

[0016] According to the number of cores of the target chip, the types and numbers of corelets constituting the target chip, and the number and functions of modules contained in each corelet in the target chip, the corresponding configuration space is divided into a plurality of sub-configuration spaces.

[0017] Optionally, the multiple configuration spaces include at least a core configuration space, a system management configuration space, and an IO management configuration space;

[0018] Among them, the core configuration space corresponds to the core task execution of the target chip; the system management configuration space corresponds to the state control of the target chip; and the IO management configuration space corresponds to the information interaction of the target chip.

[0019] Optionally, the sub-configuration space includes: a sub-core configuration space, a sub-system configuration space and a sub-IO configuration space;

[0020] According to the number of cores of the target chip, the types and numbers of corelets constituting the target chip, and the types and numbers of modules contained in each corelet, the corresponding configuration space is divided into a plurality of sub-configuration spaces, including:

[0021] According to the number of cores of the target chip, the core configuration space is divided into a corresponding plurality of sub-core configuration spaces, wherein the number of the divided sub-core configuration spaces is greater than or equal to the number of cores of the target chip;

[0022] According to the type and quantity of the corelets constituting the target chip, the system management configuration space is divided into a corresponding plurality of subsystem configuration spaces, wherein the number of the divided subsystem configuration spaces is greater than or equal to the number of the corelets included in the target chip;

[0023] According to the number of modules and module functions contained in each core particle in the target chip, the IO management configuration space is divided into a corresponding plurality of sub-IO configuration spaces, wherein the number of the divided sub-IO configuration spaces is greater than or equal to the sum of the number of modules contained in each core particle in the target chip.

[0024] Optionally, allocating corresponding sub-configuration spaces to the target chip and each chiplet in the target chip in a plurality of sub-configuration spaces according to the management network configuration sequence number includes:

[0025] According to the management network configuration sequence number, in a plurality of sub-core configuration spaces, based on the number of cores of the target chip, a sub-core configuration space is allocated to the target chip;

[0026] In the plurality of subsystem configuration spaces, based on the type and quantity of the corelets of the target chip, a subsystem management configuration space is allocated to the corelets of the target chip;

[0027] In the plurality of sub-IO configuration spaces, sub-IO configuration spaces are allocated to modules included in each coregrain based on the number of modules and module functions included in each coregrain in the target chip.

[0028] Optionally, the configuration space further includes a reserved address space, and the reserved address space is used to adapt to address expansion requirements of target chips of different specifications, or to meet different address expansion requirements of target chips.

[0029] Optionally, the architecture information of the target chip further includes a routing table corresponding to the target chip, the routing table being used to indicate routing information of a routing unit in the target chip, the routing information being used to formulate a data transmission path corresponding to a module included in a core particle in the target chip;

[0030] The method further includes allocating a corresponding sub-configuration space to each chiplet in the target chip in a plurality of sub-configuration spaces according to the management network configuration sequence number, and further includes:

[0031] According to the management network configuration sequence number, in the routing table, corresponding routing units are allocated to the modules included in each core particle in the target chip.

[0032] Optionally, the target chip further comprises an interface unit corresponding to the modules included in each core particle, and the interface unit is used for communication maintenance of the corresponding module;

[0033] The method of allocating corresponding routing units to the modules included in each core particle in the target chip in the routing table according to the management network configuration serial number also includes: allocating corresponding interface units to the modules included in each core particle in the target chip.

[0034] Optionally, the target chip further comprises a relay unit provided for each coreparticle in the target chip, and the relay unit is used for signal transmission between the coreparticle and the opposite coreparticle;

[0035] The method further includes allocating corresponding relay units to the modules included in each core particle in the target chip in the routing table according to the management network configuration serial number.

[0036] In a second aspect, an embodiment of the present application provides a chip management network system, which is applied to a target chip, wherein the target chip includes a plurality of core particles of different types, the core particles include one or more modules, and the core particles are configured with a management network configuration number, and the management network configuration number is configured based on the type of the core particle and its packaging position in the target chip; the chip management network system includes:

[0037] An acquisition module, used for acquiring architecture information of the target chip, wherein the architecture information at least includes a management network configuration sequence number of a core chip configuration;

[0038] A configuration module is used to divide a preset address space into a plurality of sub-configuration spaces according to the architecture information of the target chip; and, according to the management network configuration sequence number, allocate corresponding sub-configuration spaces to the target chip and each core particle in the target chip in the plurality of sub-configuration spaces, wherein the modules contained in each core particle are allocated different sub-configuration spaces.

[0039] In a third aspect, an embodiment of the present application provides a computing device, comprising a chip management network system as described in the third aspect above.

[0040] In a fourth aspect, an embodiment of the present application provides a storage medium, which stores one or more computer-executable instructions. When the one or more computer-executable instructions are executed, the chip management network configuration method described in the first aspect above is implemented.

[0041] In a fifth aspect, an embodiment of the present application provides a computer program product, characterized in that it includes one or more computer executable instructions, and when the one or more computer executable instructions are executed, the chip management network configuration method described in the first aspect above is implemented.

[0042] In the chip management network configuration method, chip management network system and related equipment provided in the embodiments of the present application, the chip management network configuration method obtains the architecture information of the target chip, and the architecture information of the target chip at least includes the management network configuration serial number of the core grain configuration; then, according to the architecture information of the target chip, the preset address space is divided into multiple sub-configuration spaces, and according to the management network configuration serial number, in the multiple sub-configuration spaces, corresponding sub-configuration spaces are allocated to the target chip and each core grain in the target chip, wherein the modules contained in each core grain are allocated different sub-configuration spaces.

[0043] It can be seen that the embodiment of the present application allocates corresponding sub-configuration spaces to the core particles in the multiple sub-configuration spaces divided by the preset address space, so that multiple core particles in the target chip share the preset address space, and then the preset address space can be applied to core particle groups with different types of core particles. At the same time, based on the different sub-configuration spaces allocated to the modules contained in each core particle, the preset address space of the present application is also applicable to core particle groups with core particles of different specifications, such as a core particle group constituting a 32-core CPU, or a core particle group constituting a 64-core CPU. Therefore, the preset address space of the embodiment of the present application can be understood as a shared address space with a uniform configuration provided by the software system for each core particle in the core particle group, so that there is no need to match the core particles in the core particle group with a specific software based on the address space, so that the applicability of the present application is improved and the adaptability requirements of the target chip to the software are reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0045] Figure 1 This is a schematic diagram of an optional structure of a chip.

[0046] Figures 2 to 3 Schematic diagram of an optional architecture of a CPU chip composed of multiple cores.

[0047] Figure 4 It is a schematic diagram of the module address space configuration of a core particle containing 16 groups of modules.

[0048] Figure 5 It is a schematic diagram of the module routing configuration of a core particle containing 16 groups of modules.

[0049] Figure 6 Schematic diagram of the internal structure of CPU chip 1.

[0050] Figure 7 It is a schematic diagram of the internal structure of CPU chip 2.

[0051] Figure 8 It is an optional flow chart of the chip management network configuration method provided in the embodiment of the present application.

[0052] Fig. 9 It is another optional flow chart of the chip management network configuration method provided in the embodiment of the present application.

[0053] Fig.10 It is a schematic diagram of the internal structure of a core particle provided in an embodiment of the present application.

[0054] Fig.11 It is a schematic diagram of the interconnection structure of different core particles provided in the embodiments of the present application.

[0055] Fig.12 It is a schematic diagram of the optional internal structure of the 32-core CPU chip provided in an embodiment of the present application.

[0056] Fig.13 This is a schematic diagram of the optional internal structure of the 64-core CPU chip provided in an embodiment of the present application.

[0057] Fig.14 This is a schematic diagram of the division of the 64MB preset address space provided in an embodiment of the present application.

[0058] Fig.15 It is an optional structural diagram of the chip management network system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0059] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0060] To understand the chip structure, Figure 1 The optional structural diagram of a chip is shown as an example. Figure 1 As shown, the chip may include multiple core particles (core particles 1, 2, 3 and 4 are shown as examples in the figure). Among them, core particles 1, 2, 3 and 4 can be the same kind of core particles with the same functions, or different kinds of core particles with different functions. Core particles 1, 2, 3 and 4 are packaged and integrated through a substrate to obtain Figure 1 The chip shown.

[0061] It should be noted that, in the chip design stage, the overall architecture of the chip can be decomposed according to the different computing units or functional units required for the chip to realize the expected functions, and one or more core particles corresponding to different computing units or functional units can be designed according to the chip architecture decomposition scheme, and the core particles are interconnected and packaged together to realize the expected functions of the chip as a whole. Among them, since the core particle is a unit chip that can realize certain functions and contains an interconnection interface, the multiple core particles constituting the same computing unit or functional unit can be called a core particle group (Chiplet), and the multiple core particles in the core particle group can be the same or different. In addition, based on the interconnection communication between different modules, the core particles in the same core particle group can also be used to constitute different core particle groups. Moreover, with the continuous development of semiconductor technology, a single core particle can contain various functional blocks to achieve effects such as calculation, so in some specific scenarios, the single core particle can be regarded as a special core particle group.

[0062] In an optional example, taking a CPU chip as an example, Figure 2 and Figure 3 shows a schematic diagram of an alternative architecture of a different CPU chip consisting of multiple core particles, Figure 2 A CPU chip 1 with 32 cores, Figure 3 It is a CPU chip 2 having 64 cores.

[0063] like Figure 2 As shown, the 32-core CPU chip 1 may include 2 IO cores (respectively IO core m1 and IO core m2) and 2 CPU cores (respectively CPU core n1 and CPU core n2). Among them, the 2 IO cores and the 2 CPU cores can be regarded as a chipset, such as chipset A, the 2 IO cores are responsible for input and output (I / O) tasks; the 2 CPU cores are used to implement the 32-core channels of the CPU.

[0064] like Figure 3 As shown, the 64-core CPU chip 2 may include 2 IO cores (IO core M1 and IO core M2) and 4 CPU cores (CPU core N1, CPU core N2, CPU core N3 and CPU core N4). The 2 IO cores and 4 CPU cores may be considered as a chipset, such as chipset B, where the 2 IO cores are responsible for input and output (I / O) tasks; and the 4 CPU cores are used to implement the 64-core channels of the CPU.

[0065] When determining the chiplet group information (such as Figure 2 or Figure 3After the chip types and the number of each type of chip included in the CPU chip shown in the figure are completed, the management network configuration is required. The management network connects the modules in the chip that need to configure and manage the address space. The chip manages each module in the chip through the management network. Each module can also report interrupts and error information to the CPU through the management network, so as to realize the network connection and dynamic interaction between each chip, so as to achieve the expected function of the chip.

[0066] It should be further explained that, since each chip in the chip group can be used as a unit chip, the configuration space of each chip can be designed independently. Therefore, in order to realize the complete chip function of the chip group, the management network (i.e., control bus) of each chip in the chip group can be interconnected between the chips through inter-chip interconnection technology. Among them, the interconnected management networks in the chip group can be regarded as a complete chip management network. The content of the chip management network configuration includes management address space configuration, data routing configuration, permission and priority configuration, etc.

[0067] As an optional implementation, when configuring the management network, based on the independent design of the configuration space of the core particles, fixed address space allocation and fixed routing can be used for the core particles, that is, the address space allocation and routing in each core particle are pre-designed by the manufacturer based on the hardware specifications and are fixed. The management network configuration is explained using a core particle containing 16 groups of modules as an example, see Figure 4 and Figure 5 As shown, Figure 4 This is a schematic diagram of the module address space configuration of the core particle. Figure 5 The schematic diagram of the module routing configuration of the core particle. The management network configuration space corresponding to the core particle containing 16 groups of modules is a 16-bit address space. Modules 1 to 16 are configured to occupy 4KB of address space respectively, and the address space of each module does not overlap. In addition, while configuring the address space of the 16 groups of module configurations of the core particle, the routing in the management network must also be configured accordingly. Each module is configured with a corresponding routing to formulate the information transmission path of the module. Among them, the configured routing constitutes a routing table. The configured routing can adopt static routing or dynamic routing according to the design requirements. The way to configure the routing can adopt, for example, source routing, distributed routing, etc.

[0068] Therefore, when configuring the chip management network with a single chip as a unit, for chips of different specifications obtained by packaging a chip group with different numbers of chips, even if the internal configuration of the chip (such as the controller) is the same, it will be designed to have different configuration spaces, thereby reducing the flexibility of the chip's later use and development. In other words, different chips are configured with configuration spaces that are unique to the chip and adapted to the type and specification of the chip, so that the chip constructed based on this method needs to be configured with software that is adapted to its internal chip configuration space, that is, different software systems are required to match chips of different specifications, and the software adaptability is required to be high.

[0069] by Figure 2 and Figure 3 The CPU chip 1 and the CPU chip 2 are used as examples to illustrate the corresponding Figure 2 and Figure 3 As shown, Figure 6 and Figure 7 Schematic diagrams of the internal structures of CPU chip 1 and CPU chip 2 are shown respectively. Figure 6 As shown, in a CPU chip 1 with 32 cores, CPU core n1 and CPU core n2 are both configured with two sets of DDR (Double Data Rate) controllers, that is, a total of four sets of DDR controllers are configured in the CPU chip 1. Figure 7 As shown, in the CPU chip 2 with 64 cores, the CPU cores N1, N2, N3 and N4 are each configured with one set of DDR controllers, that is, a total of four sets of DDR controllers are also configured in the CPU chip 2.

[0070] It can be seen that CPU chip 1 and CPU chip 2 with different product specifications are both configured with 4 groups of DDR controllers. However, since the number of CPU chiplets packaged in CPU chip 1 and CPU chip 2 is different, and the DDR controllers configured in the packaged CPU chiplets are also different, when the manufacturer pre-designs the address space allocation and routing in the chiplets based on the hardware specifications, the address spaces configured for the 4 groups of DDR controllers in CPU chip 1 and CPU chip 2 are different. When CPU chip 1 and CPU chip 2 are later used and developed, different software systems are required to match them, which increases the adaptability requirements for the software.

[0071] In view of this, the embodiment of the present application proposes an improved scheme, so that the chip and each chiplet in the chip are allocated a corresponding sub-configuration space based on a preset address space, so that multiple chiplets in the chip can share the preset address space, and then the preset address space can be applicable to a chiplet group with different types of chiplets, and at the same time, it is applicable to a chiplet group with chiplets of different specifications, thereby eliminating the need to match the chiplets in the chiplet group with a specific software based address space, thereby effectively improving the applicability of the scheme and reducing the adaptability requirements of the target chip to the software.

[0072] Based on the above ideas, as an optional implementation, the embodiment of the present application provides a chip management network configuration method, by allocating corresponding sub-configuration spaces to the core particles in the multiple sub-configuration spaces divided by the preset address space, so that multiple core particles in the target chip share the preset address space, and then the preset address space can be applied to the core particle group with different types of core particles, and at the same time, based on the different sub-configuration spaces allocated to the modules contained in each core particle, the preset address space of the present application is also applicable to the core particle group with different specifications of core particles, such as the core particle group constituting a 32-core CPU, or the core particle group constituting a 64-core CPU. Therefore, the preset address space of the embodiment of the present application can be understood as a shared address space with a uniform configuration provided by the software system for each core particle in the core particle group, so that there is no need to match the core particles in the core particle group with a specific software based on the address space, so that the applicability of the present application is improved, and the adaptability requirements of the target chip to the software are reduced.

[0073] in, Figure 8 The following is an exemplary diagram of an optional flow chart of the chip management network configuration method according to an embodiment of the present application. Figure 8 As shown, the following steps may be included:

[0074] Step S100: Acquire architecture information of a target chip.

[0075] Wherein, the target chip refers to any chip pre-designed to realize the expected function, the target chip includes a plurality of core particles of different types, the core particles include one or more modules, and the core particles are configured with a management network configuration number, and the management network configuration number is obtained based on the type of the core particles and the packaging position configuration in the target chip;

[0076] The architecture information of the target chip at least includes the management network configuration serial number of the core particle configuration, wherein the management network configuration serial number can be obtained based on the type of the core particle and its packaging position in the target chip, and is used to coordinate and identify the routing rules and interconnection relationships in the data packet or connection process between different core particles.

[0077] Step S200 , dividing the preset address space into a plurality of sub-configuration spaces according to the architecture information of the target chip.

[0078] The preset address space can be understood as a pre-set address range that can meet the address space configuration requirements of target chips of different specifications. By obtaining the architecture information of the target chip, the preset address space can be divided into multiple sub-configuration spaces according to the architecture information of the target chip, so as to allocate corresponding addresses to the target chip and each chiplet in the target chip.

[0079] Step S300 , allocating corresponding sub-configuration spaces to the target chip and each chiplet in the target chip in a plurality of sub-configuration spaces according to the management network configuration sequence number.

[0080] The modules contained in each core particle are allocated to different sub-configuration spaces.

[0081] It can be understood that the management network configuration serial number of the embodiment of the present application is obtained based on the type of core particles and their packaging position configuration in the target chip, so that corresponding to different core particles, when different packaging positions are set in the target chip, the management configuration network serial numbers of different core particles are different. Furthermore, when the corresponding sub-configuration space is allocated to the target chip and each core particle in the target chip in the multiple sub-configuration spaces according to the management network configuration serial number, the multiple core particles in the target chip can share the preset address space, so that the preset address space can be applicable to a core particle group with different types of core particles. At the same time, based on the different sub-configuration spaces allocated to the modules contained in each core particle, the sub-configuration space obtained by the present application based on the division of the preset address space can also be applied to a core particle group with core particles of different specifications, such as a core particle group constituting a 32-core CPU, or a core particle group constituting a 64-core CPU. Therefore, the preset address space in the embodiment of the present application can be understood as a shared address space with a uniform configuration provided by the software system for each chip in the chip group, thereby eliminating the need to match the address space of the chip in the chip group based on specific software, thereby improving the applicability of the chip management network configuration and reducing the adaptability requirements of the target chip for the software.

[0082] In some embodiments, in order to organize and manage the effective use of memory and I / O resources, the configuration space allocation of the target chip can meet certain rule requirements, so that when different target chips correspond to corresponding architecture information, a predetermined rule associated with the address space of each core in the target chip can be set based on the architecture information. As an optional implementation, when the preset address space is divided into multiple sub-configuration spaces according to the architecture information of the target chip, the preset address space can be specifically divided into multiple sub-configuration spaces that meet the predetermined rules according to the architecture information of the target chip.

[0083] In an optional example, the architecture information content of the target chip corresponding to the target chip, based on the architecture information of the target chip, the predetermined rules associated with the address space of each chiplet in the target chip may include that different types of chiplets correspond to different address spaces, and modules included in the chiplets correspond to different address spaces. That is, when the target chip is configured for a management network, it is required to satisfy that the address space configured for any module of any chiplet does not have an intersection.

[0084] In some embodiments, to ensure that the designed system fully utilizes resources while meeting functional requirements and expected performance, the target chip's architecture information may also include the type of the target chip, for example, the target chip is a 32-core CPU chip or a 64-core CPU chip.

[0085] Therefore, based on the content of the architecture information of the target chip, when the preset address space is divided into a plurality of sub-configuration spaces that meet a predetermined rule according to the architecture information of the target chip, the preset address space may be first divided into a plurality of configuration spaces according to the type of the target chip, and different configuration spaces correspond to different functional implementations of the target chip. Then, according to the number of cores of the target chip, the type and number of corelets constituting the target chip, and the number of modules and module functions contained in each corelet in the target chip, the corresponding configuration space is divided into a plurality of sub-configuration spaces.

[0086] It should be noted that the target chip contains multiple functional units. In order to enable the software system to customize the hardware behavior according to the environment of the target chip, and the preset address space meets the configuration requirements of different types of target chips, and provides higher performance and adaptability, the preset address space can be divided into multiple configuration spaces based on the type of the target chip, so as to achieve the purpose of managing and optimizing the target chip. In addition, each core of the target chip can be configured with a corresponding module, so as to dynamically determine the enabled part of the core, and complete the collaborative work of different modules and different cores. Therefore, in order to prevent mutual interference between the functional units of the target chip, meet the configuration requirements of target chips of different specifications, improve the resource management efficiency of the chip, and ensure the flexibility and reliability of the chip management network configuration, the configuration space divided corresponding to the functional implementation of the target chip can be further divided into multiple sub-configuration spaces.

[0087] In an optional example, corresponding to different functional implementations of the target chip, the multiple configuration spaces divided by the preset address space may include at least a core configuration space, a system management configuration space, and an IO management configuration space.

[0088] The core configuration space corresponds to the core task execution of the target chip, the system management configuration space corresponds to the state control of the target chip, and the IO management configuration space corresponds to the information interaction of the target chip.

[0089] In another optional example, in addition to the core configuration space, system management configuration space and IO management configuration space divided by the preset address space, address space can also be reserved in the multiple configuration spaces divided by the preset address space. The reserved address space is used to adapt to the address expansion requirements of target chips of different specifications, or to meet the different address expansion requirements of the target chips.

[0090] It should be noted that the preset address space of the present application can meet the address space configuration requirements of chips of different specifications. Therefore, the address range of the preset address space is larger than the address range requirement of the target chip. Therefore, when the preset address space is divided into multiple configuration spaces, a reserved address space can be correspondingly divided to adapt to the address expansion requirements of target chips of different specifications.

[0091] In some embodiments, based on the type of configuration space partitioning, the sub-configuration space may include a sub-core configuration space, a sub-system configuration space, and a sub-IO configuration space.

[0092] Thus, when the corresponding configuration space is divided into a plurality of sub-configuration spaces according to the number of cores of the target chip, the types and number of corelets constituting the target chip, and the types and number of modules contained in each corelet, the core configuration space can be specifically divided into a plurality of corresponding sub-core configuration spaces according to the number of cores of the target chip, wherein the number of divided sub-core configuration spaces can be greater than or equal to the number of cores of the target chip; the system management configuration space can be divided into a plurality of corresponding sub-system configuration spaces according to the types and number of corelets constituting the target chip, wherein the number of divided sub-system configuration spaces can be greater than or equal to the number of corelets contained in the target chip; and, the IO management configuration space can be divided into a plurality of corresponding sub-IO configuration spaces according to the number of modules contained in each corelet in the target chip and the module functions, wherein the number of divided sub-IO configuration spaces can be greater than or equal to the sum of the numbers of modules contained in each corelet in the target chip.

[0093] It should be noted that the preset address space of the present application can meet the address space configuration requirements of chips of different specifications. Therefore, when the corresponding configuration space is divided into multiple sub-configuration spaces, the number of configuration spaces and the number of sub-configuration spaces obtained can be greater than or equal to the number of corresponding division conditions to meet the different address expansion requirements of the target chip. In addition, after allocating the sub-configuration space to the core of the corresponding target chip, the core particles contained in the target chip, and the modules contained in each core particle in the target chip based on the corresponding conditions, the remaining sub-configuration space can be used as a reserved address space.

[0094] In some embodiments, based on the classification and division of sub-configuration spaces, when allocating corresponding sub-configuration spaces to the target chip and each core grain in the target chip in multiple sub-configuration spaces according to the management network configuration serial number, it can be specifically allocated sub-core configuration space to the target chip based on the number of cores of the target chip in multiple sub-core configuration spaces according to the management network configuration serial number; in multiple subsystem configuration spaces, based on the type and number of core grains of the target chip, allocate subsystem management configuration space to the core grains of the target chip; and in multiple sub-IO configuration spaces, based on the number of modules and module functions contained in each core grain in the target chip, allocate sub-IO configuration space to the modules contained in each core grain.

[0095] In some embodiments, in order to perform data transmission in the target chip and realize the expected functions of the target chip, the architecture information of the target chip may also include a routing table, wherein the routing table contains routing information for indicating the routing unit in the target chip, and the routing information is used to formulate the data transmission path corresponding to the module contained in the core particle in the target chip.

[0096] Therefore, when managing the network configuration of the target chip, the corresponding routing configuration also needs to be performed. Fig. 9 Another optional flow chart of the chip management network configuration method of the embodiment of the present application is shown. While executing step S300, step S400 can also be executed. According to the management network configuration sequence number, corresponding routing units are allocated in the routing table to the modules contained in each core particle in the target chip.

[0097] It should be noted that the routing unit can be a static route (that is, when a data packet is sent, the routing unit will directly forward it according to the preset path) or a dynamic route (that is, a route dynamically calculated according to changes in network status). The routing selection method of the corresponding routing table can be source routing, distributed routing, etc., and the embodiments of the present application do not limit this.

[0098] In some embodiments, based on the communication and cooperation between the modules included in each core particle in the target chip, the target chip may further include an interface unit corresponding to the module included in each core particle, and the interface unit is used for communication maintenance of the corresponding module. Fig.10 The schematic diagram of the internal structure of a core particle is shown, and the core particle contains 8 modules from module 01 to module 08, and each module is provided with an interface unit, namely interface unit 01, interface unit 02, interface unit 03, and so on, to interface unit 08. Moreover, based on the function of the interface unit, the interface unit of each module can be connected to its corresponding routing unit, and transmit the corresponding communication information through the information transmission path formulated by the routing unit. Among them, the communication information can be the address space information configured by the module.

[0099] Correspondingly, according to the management network configuration serial number, in the routing table, while corresponding routing units are allocated to the modules included in each core particle in the target chip, corresponding interface units can also be allocated to the modules included in each core particle in the target chip at the same time.

[0100] In some embodiments, based on the communication and cooperation between different chiplets in the target chip, the target chip may further include a relay unit provided for each chiplet in the target chip, and the relay unit is used for signal transmission between the chiplet and the opposite chiplet. Fig.11 In the schematic diagram of the interconnection structure of different core particles shown, core particle A and core particle B are both provided with relay units (relay unit Aa and relay unit Bb, respectively), and core particle A establishes transmission with relay unit Bb of core particle B through its relay unit Aa, and communicates with each other. Among them, corresponding to the setting of the relay unit, taking core particle A as an example, relay unit Aa can be connected to the routing unit of core particle A, and then correspondingly connected to the interface unit, so as to send the corresponding communication information transmitted by core particle B to the corresponding module of core particle A. Among them, the communication information is, for example, a data signal transmitted between core particle A and core particle B.

[0101] Correspondingly, according to the management network configuration serial number, in the routing table, while corresponding routing units are allocated to the modules included in each core particle in the target chip, corresponding relay units can also be allocated to the modules included in each core particle in the target chip at the same time.

[0102] It should be noted that the interface unit and relay unit in the target chip can be set according to actual design requirements. When the communication protocol of the module is relatively simple, each module may not have a corresponding interface unit. When the data transmission between core particles is relatively simple, each core particle may not have a corresponding relay unit. The embodiments of the present application do not limit this.

[0103] To facilitate understanding of the chip management network configuration method of the embodiment of the present application, the chip management network configuration method of the embodiment of the present application is explained by taking a 32-core CPU chip and a 64-core CPU chip as target chips. Among them, the preset address space of the CPU chip can be pre-set to 64MB to allocate corresponding address spaces to the 32-core CPU chip and the 64-core CPU chip.

[0104] Fig.12 The following is an exemplary diagram showing the optional internal structure of a 32-core CPU chip. Fig.12 As shown, the 32-core CPU chip includes IO core 1, IO core 2, CPU core 1 and CPU core 2. In addition, IO core 1 and IO core 2 each contain 2 PCLe modules ( Fig.12In the figure, the CPU core 1 and the CPU core 2 both contain two DDR modules ( Fig.12 DDR21, DDR22, DDR23 and DDR24).

[0105] Fig.13 The following is an exemplary diagram showing the optional internal structure of a 64-core CPU chip. Fig.13 As shown, the 64-core CPU chip includes IO core 1', IO core 2', CPU core 1', CPU core 2', CPU core 3' and CPU core 4'. In addition, IO core 1' and IO core 2' each contain 2 PCLe modules ( Fig.13 11', PCLe12', PCLe13' and PCLe14'), CPU chip 1 to CPU chip 4 each contain a DDR module ( Fig.13 DDR21', DDR22', DDR23' and DDR24').

[0106] Fig.14 The diagram of dividing the 64MB preset address space is shown as an example.

[0107] If the target chip is Fig.13 The 64-core CPU chip shown in the figure can first divide the 64MB preset address space into 16MB CPU core configuration space, 16MB IO management configuration space and 16MB system management configuration space according to the type of the 64-core CPU chip. Among them, the 64MB preset address space still has 16MB of address space unallocated, which can be used as a reserved address space for use when needed.

[0108] Secondly, based on the 64 cores of a 64-core CPU chip, the 16MB CPU core configuration space can be divided into 64 256KB sub-core configuration spaces ( Fig.14 256KB CPU1 configuration space, 256KB CPU2 configuration space, ..., 256KB CPU64 configuration space).

[0109] Based on the types and number of cores that make up the 64-core CPU chip, the 16MB system management configuration space can be divided into 4 CPU core system management configuration spaces ( Fig.14 2MB CPU core 1 system management configuration space to 2MB CPU core 4 system management configuration space) and 2 IO core system management configuration space ( Fig.142MB IO core 1 system management configuration space and 2MB IO core 2 system management configuration space are shown in FIG. 1 ). Among them, 4MB of address space remains unallocated in the 16MB system management configuration space, which can be used as a reserved address space for use when needed.

[0110] Based on the 64-core CPU chip, each CPU core contains a DDR module, and each IO core contains two PCL modules, the 16MB IO management configuration space can be divided into 4MB DDR configuration space and 4MB PCLe configuration space. The 4MB DDR configuration space can be specifically 4 IMB DDR configuration space ( Fig.14 1MB DDR1 configuration space to 1MB DDR4 configuration space), the 4MB PCLe configuration space may be specifically a PCLe configuration space of 4 IMBs ( Fig.14 Shown in the figure is 1MB PCLe1 configuration space to 1MB PCLe4 configuration space).

[0111] It should be noted that since the CPU chip inevitably needs to use low-speed IO, in order to realize the use of low-speed IO by the 64-core CPU chip, when dividing the 16MB IO management configuration space, it is necessary to divide out the low-speed IO configuration space, and the capacity of the low-speed IO configuration space can be 4MB.

[0112] There is 4MB of address space left unallocated in the 16MB IO management configuration space, which can be used as a reserved address space for use when needed.

[0113] Similarly, if the target chip is Fig.12 The 32-core CPU chip shown in the figure has a 64MB preset address space. Fig.14 As shown. Based on the fact that the number of cores of a 32-core CPU chip is 32, the 16MB CPU core configuration space can be divided into 32 256KB sub-core configuration spaces (i.e., 256KB CPU1 configuration space to 256KB CPU32 configuration space). At this time, there is still 8MB of address space unallocated for the 16MB preset address space, which can be used as a reserved address space for use when needed, such as when allocating CPU core configuration space for a 64-core CPU.

[0114] based on Fig.14 As shown in the partition diagram, when the corresponding sub-configuration space is allocated to the target chip and each chiplet in the target chip according to the management network configuration sequence number, if the target chip is Fig.13The 64-core CPU chip shown in the figure, in which the management network configuration serial number of the CPU chip 1' is set to 1 through the substrate connection, wherein the number of cores provided by 1 CPU chip is 16, and the core configuration space configured for the CPU chip 1' is 256KB CPU1 configuration space to 256KB CPU16 configuration space, and the system management configuration space is 2MBCPU chip 1 system management configuration space; the corresponding CPU chip 1' contains a DDR21' module, and the IO management configuration space configured for the DDR21' module in the CPU chip 1' is 1MB DDR1 configuration space.

[0115] In the 64-core CPU, the management network configuration number of the CPU chip 2' is set to 2 through the substrate connection, and the core configuration space configured for the CPU chip 2' is 256KB CPU17 configuration space to 256KB CPU32 configuration space, and the system management configuration space is 2MBCPU chip 2 system management configuration space; the corresponding CPU chip 2' contains a DDR21' module, and the IO management configuration space configured for the DDR22' module in the CPU chip 2' is 1MB DDR2 configuration space.

[0116] In the 64-core CPU, the management network configuration number of the CPU chip 3' is set to 3 through the substrate connection, and the core configuration space configured for the CPU chip 3' is 256KB CPU33 configuration space to 256KB CPU48 configuration space, and the system management configuration space is 2MBCPU chip 3 system management configuration space; the corresponding CPU chip 3' contains a DDR23' module, and the IO management configuration space configured for the DDR23' module in the CPU chip 3' is 1MB DDR3 configuration space.

[0117] In the 64-core CPU, the management network configuration number of the CPU chip 4' is set to 4 through the substrate connection, and the core configuration space configured for the CPU chip 4' is 256KB CPU49 configuration space to 256KB CPU64 configuration space, and the system management configuration space is 2MBCPU chip 4 system management configuration space; the corresponding CPU chip 4' contains a DDR24' module, and the IO management configuration space configured for the DDR24' module in the CPU chip 4' is 1MB DDR4 configuration space.

[0118] It should be noted that, since the 64-core CPU chip needs to use low-speed IO, in order to realize the use of low-speed IO by the 64-core CPU chip, when configuring the IO management configuration space for the CPU chip, the 4MB low-speed IO configuration space can be allocated to any CPU chip in the 64-core CPU chip, such as CPU chip 1'.

[0119] Similarly, if the target chip is Fig.12 The 32-core CPU chip shown in the figure, in which the management network configuration serial number of CPU chip 1 is set to 11 through the baseboard connection, wherein the number of cores provided by 1CPU chip is 16, and the core configuration space configured for CPU chip 1 is 256KB CPU1 configuration space to 256KB CPU16 configuration space, and the system management configuration space is 2MBCPU chip 1 system management configuration space; corresponding to the DDR21 module and DDR22 module contained in the CPU chip 1, the IO management configuration space configured for the DDR21 module and DDR22 module in the CPU chip 1 is 1MB DDR1 configuration space and 1MBDDR2 configuration space respectively.

[0120] In this 32-core CPU, the management network configuration number of CPU chip 2 is set to 22 through the baseboard connection, and the core configuration space configured for CPU chip 2 is 256KB CPU17 configuration space to 256KB CPU32 configuration space, and the system management configuration space is 2MBCPU chip 2 system management configuration space; corresponding to the DDR23 module and DDR24 module contained in CPU chip 2, the IO management configuration space configured for the DDR23 module and DDR24 module in CPU chip 2 is 1MB DDR3 configuration space and 1MB DDR4 configuration space respectively.

[0121] It should be noted that since the 32-core CPU chip needs to use low-speed IO, in order to realize the use of low-speed IO by the 32-core CPU chip, when configuring the IO management configuration space for the CPU chip, the 4MB low-speed IO configuration space can be allocated to any CPU chip in the 32-core CPU chip, such as CPU chip 1.

[0122] Moreover, when the management network configuration is executed on the CPU chip based on the management network configuration serial number, each interface module contained in each core particle in the CPU chip can obtain the management network configuration serial number accordingly, so that the interface module selects the configuration space and routing table of the routing according to the management network configuration serial number, wherein the routing method can be source routing or distributed routing.

[0123] It can be seen that the chip management network configuration method of the embodiment of the present application allocates corresponding sub-configuration spaces to the core particles in the multiple sub-configuration spaces divided by the preset address space, so that multiple core particles in the target chip share the preset address space, so that the preset address space can be applicable to core particle groups with different types of core particles, and at the same time, based on the different sub-configuration spaces allocated to the modules contained in each core particle, the configuration space can be simultaneously applicable to core particle groups with core particles of different specifications, such as a core particle group constituting a 32-core CPU, or a core particle group constituting a 64-core CPU. Therefore, the preset address space provided for the software system can be understood as a space shared by the core particles in the core particle group and having a unified configuration, without the need to configure specific software to match it, thereby improving its applicability and reducing the adaptability requirements of the target chip to the software.

[0124] The embodiment of the present application also provides a chip management network system, which can be applied to a target chip, wherein the target chip may include a plurality of core particles of different types, the core particles include one or more modules, and the core particles are configured with a management network configuration number, and the management network configuration number is obtained based on the type of the core particle and its packaging position in the target chip. In an optional implementation, in combination with the above description, Fig.15 The optional structural diagram of the chip management network system of the embodiment of the present application is exemplarily shown, and the chip management network system may include: an acquisition module 151 and a configuration module 152. The functions and detailed structures of the acquisition module and the configuration module may refer to the description of the corresponding parts above.

[0125] The acquisition module 151 is used to acquire the architecture information of the target chip, wherein the architecture information at least includes the management network configuration sequence number of the chiplet configuration;

[0126] The configuration module 152 is used to divide the preset address space into multiple sub-configuration spaces according to the architecture information of the target chip; and, according to the management network configuration sequence number, allocate corresponding sub-configuration spaces to the target chip and each core in the target chip in the multiple sub-configuration spaces, wherein the modules contained in each core are allocated different sub-configuration spaces.

[0127] Optionally, the configuration module 152 is used to divide the preset address space into multiple sub-configuration spaces according to the architecture information of the target chip, specifically: according to the architecture information of the target chip, the preset address space is divided into multiple sub-configuration spaces that meet predetermined rules; wherein the predetermined rules are associated with the address space of each core particle in the target chip.

[0128] Optionally, the predetermined rule includes:

[0129] Different types of core particles correspond to different address spaces, and the modules contained in the core particles correspond to different address spaces.

[0130] Optionally, the architecture information of the target chip acquired by the acquisition module 151 also includes the type of the target chip;

[0131] The configuration module 152 is used to divide the preset address space into a plurality of sub-configuration spaces satisfying a predetermined rule according to the architecture information of the target chip, including:

[0132] According to the type of the target chip, the preset address space is divided into a plurality of configuration spaces, and different configuration spaces correspond to different functional implementations of the target chip;

[0133] According to the number of cores of the target chip, the types and numbers of corelets constituting the target chip, and the number and functions of modules contained in each corelet in the target chip, the corresponding configuration space is divided into a plurality of sub-configuration spaces.

[0134] Optionally, the multiple configuration spaces include at least a core configuration space, a system management configuration space, and an IO management configuration space;

[0135] Among them, the core configuration space corresponds to the core task execution of the target chip; the system management configuration space corresponds to the state control of the target chip; and the IO management configuration space corresponds to the information interaction of the target chip.

[0136] Optionally, the sub-configuration space includes: a sub-core configuration space, a sub-system configuration space and a sub-IO configuration space;

[0137] The configuration module 152 is used to divide the corresponding configuration space into multiple sub-configuration spaces according to the number of cores of the target chip, the types and numbers of corelets constituting the target chip, and the types and numbers of modules contained in each corelet, including:

[0138] According to the number of cores of the target chip, the core configuration space is divided into a corresponding plurality of sub-core configuration spaces, wherein the number of the divided sub-core configuration spaces is greater than or equal to the number of cores of the target chip;

[0139] According to the type and quantity of the corelets constituting the target chip, the system management configuration space is divided into a corresponding plurality of subsystem configuration spaces, wherein the number of the divided subsystem configuration spaces is greater than or equal to the number of the corelets included in the target chip;

[0140] According to the number of modules and module functions contained in each core particle in the target chip, the IO management configuration space is divided into a corresponding plurality of sub-IO configuration spaces, wherein the number of the divided sub-IO configuration spaces is greater than or equal to the sum of the number of modules contained in each core particle in the target chip.

[0141] Optionally, the configuration module 152 is used to allocate corresponding sub-configuration spaces to the target chip and each chiplet in the target chip in a plurality of sub-configuration spaces according to the management network configuration sequence number, including:

[0142] According to the management network configuration sequence number, in a plurality of sub-core configuration spaces, based on the number of cores of the target chip, a sub-core configuration space is allocated to the target chip;

[0143] In the plurality of subsystem configuration spaces, based on the type and quantity of the corelets of the target chip, a subsystem management configuration space is allocated to the corelets of the target chip;

[0144] In the plurality of sub-IO configuration spaces, sub-IO configuration spaces are allocated to modules included in each coregrain based on the number of modules and module functions included in each coregrain in the target chip.

[0145] Optionally, the configuration space obtained by dividing the configuration module 152 also includes a reserved address space, and the reserved address space is used to adapt to address expansion requirements of target chips of different specifications, or to meet different address expansion requirements of the target chips.

[0146] Optionally, the architecture information of the target chip acquired by the acquisition unit 151 further includes a routing table corresponding to the target chip, the routing table includes a plurality of routing units, and the routing units are used to formulate data transmission paths corresponding to modules included in the core particles in the target chip;

[0147] The configuration module 152 is used to allocate a corresponding sub-configuration space to each chiplet in the target chip in a plurality of sub-configuration spaces according to the management network configuration sequence number, and is also used to:

[0148] According to the management network configuration sequence number, in the routing table, corresponding routing units are allocated to the modules included in each core particle in the target chip.

[0149] Optionally, the target chip further comprises an interface unit corresponding to the modules included in each core particle, and the interface unit is used for communication maintenance of the corresponding module;

[0150] The configuration module 152 is used to allocate corresponding routing units to the modules included in each core particle in the target chip in the routing table according to the management network configuration serial number, and also includes: allocating corresponding interface units to the modules included in each core particle in the target chip.

[0151] Optionally, the target chip further comprises a relay unit provided for each chiplet in the target chip, and the relay unit is used for signal transmission between the chiplet and the opposite chiplet.

[0152] The configuration module 152 is used to allocate corresponding routing units to the modules included in each core particle in the target chip in the routing table according to the management network configuration sequence number, and also includes: allocating corresponding relay units to the modules included in each core particle in the target chip.

[0153] It can be seen that the chip management network configuration device of the embodiment of the present application can be a space with a unified configuration shared by the core particles in the core particle group, without the need to configure specific software to match it, thereby improving its applicability and reducing the adaptability requirements of the target chip to the software.

[0154] An embodiment of the present application also provides a computing device, such as a server device or a terminal device, which may include a chip management network system as provided in an embodiment of the present application.

[0155] An embodiment of the present application also provides a storage medium, which stores one or more computer-executable instructions. When the one or more computer-executable instructions are executed, the chip management network configuration method provided in the embodiment of the present application is implemented.

[0156] An embodiment of the present application also provides a computer program product, which includes one or more computer executable instructions. When the one or more computer executable instructions are executed, the chip management network configuration method provided in the embodiment of the present application is implemented.

[0157] The above describes multiple implementation schemes provided by the embodiments of the present application. The various optional methods introduced in each implementation scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible implementation schemes, which can all be considered as implementation schemes disclosed and open in the embodiments of the present application.

[0158] Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined by the claims.

Claims

1. A chip management network configuration method, characterized in that: Applied to a target chip, the target chip includes a plurality of core particles of different types, the core particles include one or more modules, and the core particles are configured with a management network configuration number, the management network configuration number is configured based on the type of the core particle and its packaging position in the target chip, including: Acquire architecture information of the target chip, wherein the architecture information at least includes a management network configuration sequence number of the chiplet configuration; According to the architecture information of the target chip, the preset address space is divided into a plurality of sub-configuration spaces; According to the management network configuration sequence number, in a plurality of sub-configuration spaces, corresponding sub-configuration spaces are allocated to the target chip and each coregrain in the target chip, wherein the modules included in each coregrain are allocated different sub-configuration spaces.

2. The method according to claim 1, characterized in that: The method of dividing the preset address space into a plurality of sub-configuration spaces according to the architecture information of the target chip is specifically as follows: dividing the preset address space into a plurality of sub-configuration spaces satisfying a predetermined rule according to the architecture information of the target chip; wherein the predetermined rule is associated with the address space of each core particle in the target chip.

3. The method according to claim 2, characterized in that The predetermined rules include: Different types of core particles correspond to different address spaces, and the modules contained in the core particles correspond to different address spaces.

4. The method according to claim 3, characterized in that The architecture information of the target chip also includes the type of the target chip; The step of dividing the preset address space into a plurality of sub-configuration spaces satisfying a predetermined rule according to the architecture information of the target chip comprises: According to the type of the target chip, the preset address space is divided into a plurality of configuration spaces, and different configuration spaces correspond to different functional implementations of the target chip; According to the number of cores of the target chip, the types and numbers of corelets constituting the target chip, and the number and functions of modules contained in each corelet in the target chip, the corresponding configuration space is divided into a plurality of sub-configuration spaces.

5. The method according to claim 4, characterized in that The multiple configuration spaces include at least a core configuration space, a system management configuration space, and an IO management configuration space; Among them, the core configuration space corresponds to the core task execution of the target chip; the system management configuration space corresponds to the state control of the target chip; and the IO management configuration space corresponds to the information interaction of the target chip.

6. The method according to claim 5, characterized in that The sub-configuration space includes: a sub-core configuration space, a sub-system configuration space and a sub-IO configuration space; According to the number of cores of the target chip, the types and numbers of corelets constituting the target chip, and the types and numbers of modules contained in each corelet, the corresponding configuration space is divided into a plurality of sub-configuration spaces, including: According to the number of cores of the target chip, the core configuration space is divided into a corresponding plurality of sub-core configuration spaces, wherein the number of the divided sub-core configuration spaces is greater than or equal to the number of cores of the target chip; According to the type and quantity of the corelets constituting the target chip, the system management configuration space is divided into a corresponding plurality of subsystem configuration spaces, wherein the number of the divided subsystem configuration spaces is greater than or equal to the number of the corelets included in the target chip; According to the number of modules and module functions contained in each core particle in the target chip, the IO management configuration space is divided into a corresponding plurality of sub-IO configuration spaces, wherein the number of the divided sub-IO configuration spaces is greater than or equal to the sum of the number of modules contained in each core particle in the target chip.

7. The method according to claim 6, characterized in that The method of allocating corresponding sub-configuration spaces to the target chip and each chiplet in the target chip in a plurality of sub-configuration spaces according to the management network configuration sequence number includes: According to the management network configuration sequence number, in a plurality of sub-core configuration spaces, based on the number of cores of the target chip, a sub-core configuration space is allocated to the target chip; In the plurality of subsystem configuration spaces, based on the type and quantity of the corelets of the target chip, a subsystem management configuration space is allocated to the corelets of the target chip; In the plurality of sub-IO configuration spaces, sub-IO configuration spaces are allocated to modules included in each coregrain based on the number of modules and module functions included in each coregrain in the target chip.

8. The method according to claim 5, characterized in that The configuration space also includes a reserved address space, and the reserved address space is used to adapt to address expansion requirements of target chips of different specifications, or to meet different address expansion requirements of target chips.

9. The method according to claim 1, characterized in that: The architecture information of the target chip also includes a routing table corresponding to the target chip, wherein the routing table is used to indicate routing information of a routing unit in the target chip, and the routing information is used to formulate a data transmission path corresponding to a module included in a core particle in the target chip; The method further includes allocating a corresponding sub-configuration space to each chiplet in the target chip in a plurality of sub-configuration spaces according to the management network configuration sequence number, and: According to the management network configuration sequence number, in the routing table, corresponding routing units are allocated to the modules included in each core particle in the target chip.

10. The method according to claim 1, characterized in that The target chip also includes an interface unit corresponding to the modules included in each core particle, and the interface unit is used for communication maintenance of the corresponding module; The method of allocating corresponding routing units to the modules included in each core particle in the target chip in the routing table according to the management network configuration serial number also includes: allocating corresponding interface units to the modules included in each core particle in the target chip.

11. The method according to claim 1, characterized in that: The target chip further comprises a relay unit provided for each coreparticle in the target chip, wherein the relay unit is used for signal transmission between the coreparticle and the opposite coreparticle; The method further includes allocating corresponding relay units to the modules included in each core particle in the target chip in the routing table according to the management network configuration serial number.

12. A chip management network system, characterized in that: Applied to a target chip, the target chip includes a plurality of core particles of different types, the core particles include one or more modules, and the core particles are configured with a management network configuration number, the management network configuration number is configured based on the type of the core particle and its packaging position in the target chip; the chip management network system includes: An acquisition module, used for acquiring architecture information of the target chip, wherein the architecture information at least includes a management network configuration sequence number of a core chip configuration; A configuration module is used to divide a preset address space into a plurality of sub-configuration spaces according to the architecture information of the target chip; and, according to the management network configuration sequence number, allocate corresponding sub-configuration spaces to the target chip and each core particle in the target chip in the plurality of sub-configuration spaces, wherein the modules contained in each core particle are allocated different sub-configuration spaces.

13. A computing device, characterized in that: Comprising the chip management network system as claimed in claim 12.

14. A storage medium, characterized in that: The storage medium stores one or more computer executable instructions, and when the one or more computer executable instructions are executed, the chip management network configuration method as described in any one of claims 1 to 11 is implemented.

15. A computer program product, characterized in that It comprises one or more computer executable instructions, and when the one or more computer executable instructions are executed, the chip management network configuration method according to any one of claims 1 to 11 is implemented.

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