Reconfigurable computing module and coarseness reconfigurable computing device

Abstract

The invention relates to a reconfigurable computing module and a coarseness reconfigurable computing device.The reconfigurable computing module comprises a plurality of parallel channels, each channel comprises a reconfigurable register set and a function unit, and the output of the function unit of each channel is connected with a pipeline crossbar switch; the reconfigurable register group is used for storing input data and calculation results of the functional units; the function unit is used for acquiring data from the reconfigurable register groups for calculation, and transmitting a calculation result to the reconfigurable register group of any channel or the reconfigurable register group of any channel in other reconfigurable calculation modules connected to the rear end of the reconfigurable calculation module through the pipeline crossbar switch; and the pipeline crossbar switch is used for providing a mapping relation of the functional units between a pulsation mode and an SIMD calculation mode. According to the invention, the flexibility, the field universality and the hardware resource utilization rate of a hardware architecture can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of reconfigurable processors, and in particular to a reconfigurable computing module and a coarse-grained reconfigurable computing device. Background Art

[0002] At present, there are massive amounts of data that need to be searched and analyzed in various computing scenarios, which greatly increases the demand for computing and storage. However, most of the operations are simple basic operations, which are not suitable for software programming of CPUs (central processing units) with a small number of computing units. Therefore, in order to improve the cost-effectiveness of information processing, customized chips ASIC (application-specific integrated circuits) came into being. It has great advantages in power consumption and performance. However, with the continuous iteration of artificial intelligence algorithms, dedicated ASICs cannot implement different network structures, so there is a greater demand for chip flexibility. Reconfigurable computing is a computing method that combines the functional flexibility of instruction stream-driven processors with the high energy efficiency of data stream-driven processors, and has a good balance between key chip indicators such as performance, power consumption and functional flexibility.

[0003] The coarse-grained reconfigurable processor improves computing efficiency by building modules internally and reducing interconnections, and maximizes the resource utilization of computing units. The data path is composed of a processing element array PEA (Processing Element Array), which includes many basic computing units (such as adders, multipliers, etc.) and logic computing units (such as AND, OR, NOT logic gates). The control unit selects these computing units through configuration information to implement specific functions.

[0004] During the design process, PEA is composed of multiple reconfigurable computing units (PEs), each of which is usually composed of an arithmetic logic unit (ALU), multiple multiplexers (Mux), and input and output registers. In order to realize the functional reconstruction of PEA, it is necessary to consider the design parameters of each PE, such as the homogeneous and heterogeneous modes of PEA, the granularity of PE, and the computing model of PEA. Whether to select homogeneous PE in PEA will directly affect the complexity of control logic and data routing; the granularity of PE will affect the communication cost and computing performance of reconstruction. The most important factor affecting the performance of PEA is the computing model supported by PEA. With the growing demand for high-performance computing in today's computer architecture, how to process large amounts of data more efficiently is an important consideration in determining the performance of the architecture.

[0005] Single Instruction Single Data (SIMD) has emerged as an important parallel processing technology. It performs the same computing operations on multiple processing elements that perform the same operations at the same time. By utilizing data-level parallelism, the data processing speed can be significantly improved, especially in scenarios where the same operations are performed on a large amount of data, such as image processing, matrix calculation, etc. In order to support the SIMD computing mode, a wider number of computing units ALU and control logic are often required in hardware. The processing units in the reconfigurable processing array have simple functions and naturally support the SIMD parallel computing mode. The compiler is configured once and data is sent down for calculation, which reduces the overhead of issuing, switching and decoding between instructions and maximizes the computing efficiency of the hardware.

[0006] In the traditional computing model, the speed of data access is often much lower than the speed of data processing. Therefore, the processing power of the overall system is largely limited by the ability to access memory, which leads to a pulsating computing mode, that is, letting the data flow in the processing unit for a while longer. In order to support the pulsating computing mode, the hardware usually has several basic features. It is composed of multiple isomorphic PEs, and the PE functions are relatively simple. Only a large number of PEs are needed in parallel to improve the efficiency of calculations. PE can only send data to adjacent PEs. Data flows "downstream" in a "pipeline" manner until it flows out of the last PE. This pulsating architecture is consistent with the basic characteristics of the reconfigurable processing array. Therefore, considering the computing efficiency, most reconfigurable processing arrays support the pulsating computing mode.

[0007] The existing coarse-grained reconfigurable processors are not well developed and are still limited to small domains. They also have low computational efficiency and hardware resources are still used in the layout and routing process, resulting in low utilization. In the process of task switching, existing processors mostly use instruction scheduling methods, which will cause a lot of instruction overhead. Summary of the invention

[0008] The technical problem to be solved by the present invention is to provide a reconfigurable computing module and a coarse-grained reconfigurable computing device, which can improve the flexibility, field versatility and hardware resource utilization of the hardware architecture.

[0009] The technical solution adopted by the present invention to solve the technical problem is: providing a reconfigurable computing module, including multiple parallel channels, each channel including a reconfigurable register group and a functional unit, and the output of the functional unit of each channel is connected to a pipeline cross switch;

[0010] The reconfigurable register group is used to store input data and calculation results of the functional unit;

[0011] The functional unit is used to obtain data from the reconfigurable register group for calculation, and transmit the calculation result to the reconfigurable register group of any channel or the reconfigurable register group of any channel in other reconfigurable computing modules connected to the back end of the reconfigurable computing module through the pipeline cross switch;

[0012] The pipeline crossbar switch is used to provide a mapping relationship between the functional units between the systolic mode and the SIMD computing mode.

[0013] The technical solution adopted by the present invention to solve the technical problem is: a coarse-grained reconfigurable computing device is also provided, comprising:

[0014] Multiple input ports for inputting data;

[0015] A data packet decoding module, used to decode the data passing through the input port into data usable by the computing array and task configuration information;

[0016] A data packet encoding module, used for encoding the calculation results of the calculation array into a specified data format;

[0017] Multiple output ports for outputting encoded data;

[0018] An input port crossbar switch for transferring decoded data to a computing array;

[0019] An output port cross switch, used for transmitting the calculation result of the calculation array to the data packet encoding module;

[0020] A configuration storage area, connected to the data packet decoding module, for storing configuration information of the reconfigurable computing device each time a task is issued;

[0021] An array controller, connected to the configuration storage area, for performing state management and task configuration on the computing array;

[0022] The computing array comprises a plurality of the above-mentioned reconfigurable computing modules connected in sequence and is used for performing computing tasks under the control of the array controller.

[0023] The configuration information includes the specific computing task index number executed by the reconfigurable computing module in the computing array, the input-output mapping relationship of the reconfigurable register groups at each level in the reconfigurable computing module, the data pipeline delay, the computing mode configuration and the number of state machine cycles.

[0024] The configuration storage area includes a plurality of configuration registers for storing task configuration information.

[0025] The array controller loads the hardware configuration information according to the task index number in the configuration information, and controls the computing array to start the computing task after the loading is completed.

[0026] When it is necessary to switch computing tasks, the computing array first completes the calculation of the previous task, waits for the data retained in the pipeline of the computing array to be drained, and then reports the state of the computing array to the array controller. The array controller directly calls the configuration information corresponding to the task index number according to the task index number to switch the state of the computing array.

[0027] The coarse-grained reconfigurable computing device further includes: a plurality of data buffers FIFOs corresponding to the plurality of input ports, located between the input port cross switch and the computing array, and used to transmit the decoded data to the computing array according to the computing mode configured by the array;

[0028] The input port cross switch and the output port cross switch each include a plurality of switch input terminals, a plurality of switch output terminals and a switch matrix; data enters from the plurality of switch input terminals and is sent to the appropriately configured switch output terminals; the switch matrix implements data routing between the switch input terminals and the switch output terminals.

[0029] Beneficial Effects

[0030] Due to the adoption of the above technical solution, the present invention has the following advantages and positive effects compared with the prior art: the present invention provides a small amount of pipeline cross-switch logic in the hardware architecture to provide reconfigurable interconnection for hardware computing resources, is compatible with SIMD and pulsating computing modes, and can be used to switch between different tasks in real time through configuration registers, thereby increasing the reconfigurability of computing and improving computing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a schematic diagram of the structure of a coarse-grained reconfigurable computing device according to an embodiment of the present invention;

[0032] Figure 2 is a schematic diagram of configuring a storage area in an embodiment of the present invention;

[0033] Figure 3 is a schematic diagram of the structure of a computing array in an embodiment of the present invention;

[0034] Figure 4 is a simplified structural diagram of a computing array in an embodiment of the present invention;

[0035] Figure 5-Figure 8 Schematic diagram of a calculation array when performing matrix multiplication in an embodiment of the present invention. DETAILED DESCRIPTION

[0036] The present invention will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall within the scope limited by the appended claims of the application equally.

[0037] The embodiment of the present invention relates to a coarse-grained reconfigurable computing device, which adds a pipeline cross-switch hard connection form in the reconfigurable computing module, provides a hardware architecture for flexible switching of multiple computing modes, increases the reconfigurability of computing, and improves computing efficiency. Figure 1 As shown, the coarse-grained reconfigurable computing device of this embodiment includes multiple input ports, a data packet decoding module, a data packet encoding module, multiple output ports, multiple data buffer FIFOs, an input port cross switch, an output port cross switch, a configuration storage area, an array controller, and a computing array composed of multiple reconfigurable computing modules connected in sequence.

[0038] Among them, multiple input ports are used to input data, the number of input ports corresponds to the number of data buffer FIFO, data is sent from the bus to the coarse-grained reconfigurable computing device, and flows to the data packet decoding module through the input ports. Multiple output ports are used to output data, and the multiple output ports are connected to the data packet encoding module to output the encoded data.

[0039] The data packet decoding module in this embodiment is used to decode the data passing through the input port into data and configuration information available to the computing array. The data packet encoding module in this embodiment is used to encode the calculation results of the computing array into a user-specified data format and transmit it to the output port with the task index number.

[0040] The input port cross switch is used to transfer the decoded data to the configured data buffer FIFO; multiple data buffer FIFOs, corresponding to the multiple input ports, are used to transfer the decoded data to the calculation array according to the calculation mode configured by the array; the output port cross switch is used to transfer the calculation result of the calculation array to the data packet encoding module. The input port cross switch and the output port cross switch in this embodiment both include multiple switch input terminals, multiple switch output terminals and a switch matrix; data enters from the multiple switch input terminals and is sent to the configured appropriate switch output terminals; the switch matrix realizes the routing of data between the switch input terminals and the switch output terminals.

[0041] A configuration storage area is connected to the data packet decoding module and is used to store configuration information of the reconfigurable computing device each time a task is issued; wherein the configuration information includes the index number of the specific computing task executed by the reconfigurable computing module in the computing array, the input-output mapping relationship of the reconfigurable register groups at each level in the reconfigurable computing module, the data pipeline delay, the computing mode configuration, and the number of state machine cycles, etc.

[0042] The array controller is connected to the configuration storage area and is used to perform state management and task configuration on the computing array. It determines the specific tasks of the computing array, the specific configuration of data, the call of the reconfigurable computing module, and reconfigures tasks and switches between tasks.

[0043] The computing array comprises a plurality of the above-mentioned reconfigurable computing modules connected in sequence, and is used to perform computing tasks under the control of the array controller.

[0044] like Figure 2 As shown, the configuration storage area in this embodiment includes a plurality of configuration registers for storing task configuration information. The data packet decoding module transmits the decoded data to the computing array for data calculation. At the same time, the configuration information is transmitted to the configuration storage area, and the array controller loads the hardware configuration information according to the task index number in the configuration information. After loading, it takes effect immediately and starts the computing task. When the subsequent task is switched, the configuration information corresponding to the task index number is directly called according to the task index number carried by the data packet to switch the state of the computing array.

[0045] In this embodiment, multiple sets of configuration information are pre-stored in the configuration register. When it is necessary to switch the computing task, the computing array will first complete the calculation of the previous task, wait for the data retained in the pipeline in the computing array to be drained, and then report the state of the computing array to the array controller. The array controller switches the corresponding configuration information according to the task index number, thereby completing the switching of the computing task. It can be seen that the collaborative design of the data packet and the multi-configuration scheduling logic in this embodiment realizes the real-time task switching of the reconfigurable computing module, which greatly improves the computing efficiency.

[0046] like Figure 3 As shown, the reconfigurable computing module includes multiple parallel channels, each channel includes a reconfigurable register group R and a functional unit PE, and the output of the functional unit PE of each channel is connected to the pipeline cross switch.

[0047] The input data is received from the input port cross switch via the main line and sent to the reconfigurable register group in each reconfigurable computing module. The reconfigurable register group R receives the input data as the register in the computing array and transmits it to the functional unit PE in the array for calculation. The result of the calculation is then transmitted to the reconfigurable register group R for storage.

[0048] As the most important component of the reconfigurable computing module, the functional unit PE plays the main computing function. The functional unit PE obtains data from the reconfigurable register group R, performs calculations, and transmits the data results obtained through the pipeline cross switch to any reconfigurable register group in the same level reconfigurable computing module or the reconfigurable register group in the next level reconfigurable computing module.

[0049] The pipeline cross switch is at the back end of the functional unit of each level of the reconfigurable computing module. Through the pipeline cross switch, the data of the functional unit PE of a certain level is transmitted to the functional unit PE of the same level or the next level during the data transmission process. Through the pipeline cross switch, the computing mode of the reconfigurable computing array in this embodiment supports the pulsation mode and the SIMD computing mode. The pipeline technology realizes data parallelism in time, and SIMD realizes data parallelism in space, supporting data flow in different scenarios. Through the pipeline cross switch on the hardware, different mapping relationships between functional units PE in different computing modes are provided, and the hard connection method is adopted to completely isolate the wiring resources from the functional unit PE, thereby improving the resource utilization of the functional unit PE.

[0050] The computing array of this embodiment provides two computing modes: SIMD and pipeline. For different application scenarios, the computing array can reconfigure the computing mode. The hybrid computing mode of the pipeline crossbar switch is described below through an example in a matrix multiplication scenario.

[0051] Take a 4*4 (4 represents the number of functional units PE in the reconfigurable computing module) computing array as an example. Figure 4 As shown, it is assumed that each reconfigurable register group R includes three basic registers for receiving data, namely Reg0, Reg1, and Reg2.

[0052] Define matrix A as a matrix of size m*n, expressed as Matrix B is a matrix of size n*k, expressed as The result of the multiplication of matrices AB is an m*k matrix C. After the operation, each operation in matrix C undergoes element multiplication and addition. Therefore, in this scenario, the algorithm mapping process of matrix multiplication is as follows:

[0053] The first-level functional unit PE obtains input data from the FIFO in the computing core via the bus into the computing array. Figure 5As shown, Reg0 of the functional unit PE receives the elements of matrix A and reads them by row. Reg1 receives the elements of matrix B and reads them by column. When the input data enters the first-level functional unit PE for multiplication at the same time, the intermediate result after the operation is stored in Reg2 of the corresponding functional unit PE, and is sent to the functional unit PE of the corresponding level of the configured corresponding channel through the pipeline cross switch.

[0054] The result of the calculation of the first-level functional unit PE is passed to the second-level functional unit, which is as follows: Figure 6 shown. Figure 6 The pipeline crossbar is omitted, and only the mapping relationship between the input and output of the pipeline crossbar is retained. For example, the multiplication result r 11 =a 11 *b 11 The multiplication result r is passed to the Reg0 of the functional unit PE of the first channel of the second stage through the pipeline crossbar switch. 12 =a 12 *b 21 The multiplication result r is transmitted to Reg1 of the same functional unit PE through the crossbar switch. 13 and the multiplication result r 14 The Reg0 and Reg1 are respectively transmitted to the functional unit PE of the third channel of the second stage. After the operation of the corresponding functional unit PE, the result is stored in the Reg2 of the corresponding functional unit PE.

[0055] Multiplication result r 11 and the multiplication result r 12 The result after addition is r 1112 Multiplication result r 13 and the multiplication result r 14 The result after addition is r 1314 It is transmitted to Reg0 and Reg1 of the second channel of the second stage through the pipeline cross switch for addition calculation. Figure 7 shown.

[0056] like Figure 8 As shown, the result of the addition operation of the functional unit PE of the second channel of the second level is transmitted to the Reg0 of the functional unit PE at the bottom, and another operation is transmitted by the data bus. The data transmitted by Reg1 here is 0, and the intermediate result is output. It is used as the input data of Reg1 of the functional unit PE in the subsequent matrix multiplication operation.

[0057] It can be seen from this embodiment that the computing mode of the first-level functional unit PE is SIMD, and the computing mode of the second-level functional unit PE is pipeline parallel. Compared with the traditional pipeline operation that will waste hardware resources, this embodiment increases the hard connection of the pipeline cross switch so that the computing array supports mixed configuration SIMD and pipeline parallel computing modes, while fully utilizing hardware resources, and maximizes the versatility and reconfigurability of the computing array.

[0058] The present invention also supports a multi-level computing mode mix and a pulsating pipeline computing mode. On the basis of the above embodiment, when the functional units PE of the first two levels are used for matrix multiplication, it is hoped that the functional units PE of the last two levels also perform computing tasks at the same time. For example, the third-level functional unit PE maintains the SIMD computing mode, and the data is input from the input cross switch. The fourth-level functional unit PE is configured with a pipeline computing mode, and the data is provided after the third-level functional unit PE calculates. The pulsating mode receives part of the input data and computing results of the previous-level functional PE. The configuration method of the computing task is the same as the above embodiment, and will not be repeated here.

[0059] It is not difficult to find that the present invention provides a small amount of pipeline cross-switch logic in the hardware architecture to provide reconfigurable interconnection for hardware computing resources, is compatible with SIMD and pulsating computing modes, and can be used to switch between different tasks in real time through configuration registers, thereby increasing the reconfigurability of computing and improving computing efficiency.

Claims

1. A reconfigurable computing module, characterized in that: It includes multiple parallel channels, each of which includes a reconfigurable register group and a functional unit. The output of the functional unit of each channel is connected to the pipeline cross switch: The reconfigurable register group is used to store input data and calculation results of the functional unit; The functional unit is used to obtain data from the reconfigurable register group for calculation, and transmit the calculation result to the reconfigurable register group of any channel or the reconfigurable register group of any channel in other reconfigurable computing modules connected to the back end of the reconfigurable computing module through the pipeline cross switch; The pipeline crossbar switch is used to provide a mapping relationship between the functional units between the systolic mode and the SIMD computing mode.

2. A coarse-grained reconfigurable computing device, characterized in that: include: Multiple input ports for inputting data; A data packet decoding module, used to decode the data passing through the input port into data usable by the computing array and task configuration information; A data packet encoding module, used for encoding the calculation results of the calculation array into a specified data format; Multiple output ports for outputting encoded data; An input port crossbar switch for transferring decoded data to a computing array; An output port cross switch, used for transmitting the calculation result of the calculation array to the data packet encoding module; A configuration storage area, connected to the data packet decoding module, for storing configuration information of the reconfigurable computing device each time a task is issued; An array controller, connected to the configuration storage area, for performing state management and task configuration on the computing array; A computing array comprises a plurality of reconfigurable computing modules as claimed in claim 1 connected in sequence and used for performing computing tasks under the control of the array controller.

3. The coarse-grained reconfigurable computing device according to claim 2, characterized in that: The configuration information includes the specific computing task index number executed by the reconfigurable computing module in the computing array, the input-output mapping relationship of the reconfigurable register groups at each level in the reconfigurable computing module, the data pipeline delay, the computing mode configuration and the number of state machine cycles.

4. The coarse-grained reconfigurable computing device according to claim 2, characterized in that: The configuration storage area includes a plurality of configuration registers for storing task configuration information.

5. The coarse-grained reconfigurable computing device according to claim 4, characterized in that: The array controller loads the hardware configuration information according to the task index number in the configuration information, and controls the computing array to start the computing task after the loading is completed.

6. The coarse-grained reconfigurable computing device according to claim 4, characterized in that: When it is necessary to switch computing tasks, the computing array first completes the calculation of the previous task, waits for the data retained in the pipeline of the computing array to be drained, and then reports the state of the computing array to the array controller. The array controller directly calls the configuration information corresponding to the task index number according to the task index number to switch the state of the computing array.

7. The coarse-grained reconfigurable computing device according to claim 2, characterized in that: Also includes: A plurality of data buffer FIFOs, corresponding to the plurality of input ports, are located between the input port cross switch and the computing array, and are used to transmit the decoded data to the computing array according to the computing mode configured by the array.

8. The coarse-grained reconfigurable computing device according to claim 2, characterized in that: The input port cross switch and the output port cross switch each include a plurality of switch input terminals, a plurality of switch output terminals and a switch matrix; data enters from the plurality of switch input terminals and is sent to the appropriately configured switch output terminals; the switch matrix implements data routing between the switch input terminals and the switch output terminals.

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