Access control method and device, chip system, readable storage medium and program product

Abstract

The invention relates to an access control method and device, a chip system, a computer readable storage medium and a computer program product. The method is applied to an access control assembly electrically connected with a bus, a first master device and a second master device access a slave device through the bus, and the method comprises the steps of obtaining an access request sent by the second master device based on the bus; determining an address window corresponding to the second master device and an attribute of the address window based on a value in a configurable register of the access control component; the value in the configurable register is obtained by mapping the first array information in the programmed disposable fuse; the attribute of the address window comprises access limitation or access permission; and under the condition that the address of the slave device in the access request is covered by the access-restricted address window corresponding to the second master device, sending an instruction of intercepting the access request to a request processing component electrically connected with the first master device. By adopting the method, the security of the data in the chip can be improved.

Description

Technical Field

[0001] The present application relates to the field of information security technology, and in particular to an access control method, device, chip system, computer-readable storage medium and computer program product. Background Art

[0002] In the field of information security technology, it is crucial to ensure that key data is not illegally obtained. With the advancement of technology, in the security chip system, ensuring that the data of the slave device is not obtained by the unauthorized master device faces multiple challenges.

[0003] At present, the related technology mainly limits the access rights of the master device to the bus, or limits the access rights of the slave device to the bus by embedding software programs in the chip. However, the stability of the software program is poor. When the chip is reset or the software is tampered with, the security restrictions are easily bypassed, resulting in the leakage of key data and posing a threat to the overall system security. Therefore, there is an urgent need for an access control method that can improve the security of data in the chip. Summary of the invention

[0004] Based on this, it is necessary to provide an access control method, device, chip system, computer-readable storage medium and computer program product that can improve the security of data in the chip in response to the above technical problems.

[0005] In a first aspect, the present application provides an access control method, which is applied to an access control component, wherein the access control component is electrically connected to a bus, and a first master device and a second master device access a slave device through the bus, and the method includes:

[0006] Based on the bus, obtaining an access request sent by a second master device;

[0007] Determine an address window corresponding to the second master device and an attribute of the address window based on a value in a configurable register of the access control component; the value in the configurable register is obtained by mapping the first array information in the programmed one-time fuse; the attribute of the address window includes restricting access or allowing access;

[0008] When the address of the slave device in the access request is covered by the access-restricted address window corresponding to the second master device, an instruction to intercept the access request is sent to a request processing component electrically connected to the first master device.

[0009] In one embodiment, the sending an instruction to intercept the access request to a request processing component electrically connected to the first host device includes:

[0010] Sending an instruction to intercept the access request to a request processing component electrically connected to the first host device, so that the request processing component instructs the first host device to start a software program to intercept the access request;

[0011] Alternatively, an instruction to intercept the access request is sent to a request processing component electrically connected to the first master device, so that the request processing component triggers an operation of hardware resetting the chip.

[0012] In one embodiment, the sending an instruction to intercept the access request to a request processing component electrically connected to the first master device so that the request processing component triggers an operation of hardware resetting the chip includes:

[0013] An instruction to intercept the access request is sent to a request processing component electrically connected to the first master device, so that the request processing component triggers a hardware reset operation on the chip when the value of the first target bit in the programmed one-time fuse is a valid value.

[0014] In one of the embodiments, the first array information in the programmed one-time fuse is obtained by programming the value in the configurable register configured by the first master device.

[0015] In one embodiment, the configuration method of the configurable register includes:

[0016] In response to the value of the second target bit in the programmed one-time fuse being a valid value, disabling write permission of the configurable register.

[0017] In one of the embodiments, the request processing component is obtained based on mapping the second array information in the programmed one-time fuse, and the second array information in the programmed one-time fuse is obtained based on burning the software program configured by the first master device.

[0018] In a second aspect, the present application also provides an access control device, including:

[0019] An access request acquisition module, used for acquiring an access request sent by a second master device based on the bus;

[0020] an address window acquisition module, configured to determine an address window corresponding to the second master device and an attribute of the address window based on a value in a configurable register of the access control component; the value in the configurable register is obtained by mapping the first array information in the programmed one-time fuse; the attribute of the address window includes restricting access or allowing access;

[0021] The access request processing module sends an instruction to intercept the access request to a request processing component electrically connected to the first master device when the address of the slave device in the access request is covered by the restricted access address window corresponding to the second master device.

[0022] In a third aspect, the present application further provides a chip system, including: a first master device, a second master device, a slave device, and a bus, wherein the first master device and the second master device access the slave device through the bus, and the system further includes:

[0023] The access control component electrically connected to the bus is used to implement the steps of any of the above methods when executing a computer program.

[0024] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the steps of any of the methods described above when executed by a processor.

[0025] In a fifth aspect, the present application also provides a computer program product, including a computer program, which implements the steps of any of the methods described above when executed by a processor.

[0026] The access control method, device, chip system, computer-readable storage medium and computer program product can effectively monitor and manage the master device's authority over the slave device and reduce the risk of illegal access by adding an access control component connected to the bus in the chip system, configuring an address window with restricted access for each master device based on the access control component, and executing the control logic of the access request. And the configuration of the address window is obtained by mapping the array information in the one-time fuse, which can ensure the persistence and consistency of the access control policy, for example, avoiding the loss of configuration when the chip is reset or restarted. Since hardware is involved in the process of running the control logic, it is not easy to be tampered with, and the configuration of the address window is obtained by mapping the array information in the one-time fuse, which can ensure that the configuration of the address window will not be lost, thereby enhancing the operation stability of the control logic and improving the security of the data in the chip. Further, by flexibly configuring software interception / hardware reset, it is possible to flexibly improve the overall security of the system. Further, by means of hardware solidification, the execution of software interception / hardware reset and the control of whether the address access rules can be changed can be controlled, so that multiple protection levels can be flexibly configured. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0028] FIG1 is a diagram of an application environment of an access control method according to an embodiment;

[0029] FIG2 is a schematic diagram of a flow chart of an access control method in an embodiment;

[0030] FIG3 is a schematic diagram of a flow chart of an access control method in another embodiment;

[0031] FIG4 is a schematic diagram of a flow chart of an access control method in yet another embodiment;

[0032] FIG. 5 is a structural block diagram of an access control device in an embodiment. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0034] The access control method provided in the embodiment of the present application can be applied to the application environment shown in FIG. 1. The first master device 101 and the second master device 102 access the slave device 103 through the bus 104, and the access control unit (Access Control Unit, ACU) 105 is electrically connected to the bus 104. The number of the second master device 102 and the slave device 103 can be one or more. Specifically, the first master device 101 and the second master device 102 have control over the bus 104. The bus 104 connects the first master device 101, the second master device 102 and the slave device 103, receives the access request sent by the first master device 101 and the second master device 102, and provides a data transmission channel through arbitration, priority arbitration and other logics. The access control component 105 performs access control on the access request sent by the second master device 102, and instructs the request processing component (not shown in FIG. 1) to selectively limit the slave device 103 from responding to the access request sent by the second master device 102. The first master device 101 can be implemented based on the CPU. The second master device 102 can be implemented based on, but not limited to, multiple module controllers such as PCIE (Peripheral Component Interconnect Express), DMA (Direct Memory Access), GMAC (Gigabit Media Access Controller), SEC (Security Controller), USB, SD, etc. The slave device 103 can be implemented based on, but not limited to, SRAM (Static Random-Access Memory), DDR (Double Data Rate SDRAM), ROM (Read-Only Memory), EMMC (Embedded MultiMedia Card) particles, SD cards, USB flash drives, Flash, and other memories. In one possible implementation, key data such as user sensitive information and startup execution code of the chip can be stored in non-volatile memories such as ROM and Flash. Temporary data and system information generated during the operation of the chip can be stored in volatile memories such as SRAM and DDR.

[0035] In an exemplary embodiment, as shown in FIG2 , an access control method is provided, which is described by taking the method applied to the access control component 105 in FIG1 as an example, and includes the following steps S202 to S206 . Among them:

[0036] Step S202: Based on the bus, obtain an access request sent by the second master device.

[0037] Exemplarily, the second master device may be any one of the other master devices connected to the AXI bus except the CPU. The access control component 105 may monitor the access request from the second master device to any slave device by configuring the control logic.

[0038] Step S204, based on the value in the configurable register of the access control component, determine the address window and the attributes of the address window corresponding to the second master device; the value in the configurable register is obtained based on mapping the first array information in the programmed one-time fuse; the attributes of the address window include restricting access or allowing access.

[0039] Exemplarily, the value in the configurable register may be obtained by mapping the first array information in the programmed one-time fuse when the chip is reset or restarted. The one-time fuse is a non-volatile memory device with one-time programmable capability, and its programming process is irreversible. For example, the one-time fuse may be an electronic fuse (eFUSE). The configuration method of the configurable register may include: according to the eFUSE burning process, the address access rules (including the address window and the attributes of the address window) corresponding to each second master device are burned into the eFUSE array mapped by the configurable register to obtain the first array information. When the chip is reset or the chip is restarted, since the eFUSE array is a logic circuit based on hardware control, the chip will first load the eFUSE array and map the first array information to the configurable register, so that the address access rules corresponding to each second master device can be determined based on the value in the configurable register. The address access rules corresponding to each second master device can be predetermined according to the storage of data in the chip. Optionally, the value in the configurable register may also be obtained during the operation of the chip based on mapping the first array information in the programmed one-time fuse.

[0040] Specifically, the access control component 105 can allocate one or more address windows to each second master device, and allocate two configurable registers to each address window, including: the address register can be used to configure the starting position and the end position of the address window (for example, the initial size of each address window can be 4KB), and the attribute register can be used to configure the size of the address window, whether to restrict access, and the direction of the master device access (for example, read operation or write operation). Among them, the address window can be obtained by dividing the storage space of the slave device. The address windows and their attributes corresponding to each second master device can be different.

[0041] Step S206: When the address of the slave device in the access request is covered by the access-restricted address window corresponding to the second master device, an instruction to intercept the access request is sent to a request processing component electrically connected to the first master device.

[0042] Exemplarily, the address of the slave device in the access request is covered by the restricted access address window corresponding to the second master device, which can be used to characterize that the target address of the access request meets the restricted access rule corresponding to the second master device that issues the access request. At this time, the access control component 105 can send an instruction to intercept the access request to the request processing component electrically connected to the first master device, so that the request processing component intercepts the access request based on a software program or hardware. Whether to perform a hardware reset can be controlled by a software program. The request processing component can be implemented in whole or in part by software, hardware, and a combination thereof.

[0043] Optionally, the access control component 105 may also modify the target address of the access request to the default address of the AXI bus in response to the address of the slave device in the access request being covered by the restricted access address window corresponding to the second master device to prevent the AXI bus from being locked.

[0044] In the above access control method, by adding an access control component connected to the bus in the chip system, configuring an address window with restricted access for each master device based on the access control component, and executing the control logic of the access request, it is possible to effectively monitor and manage the master device's authority over the slave device and reduce the risk of illegal access. The configuration of the address window is obtained by mapping the array information in the one-time fuse, which can ensure the persistence and consistency of the access control policy, for example, avoiding the loss of configuration when the chip is reset or restarted. Since hardware is involved in the process of running the control logic, it is not easy to be tampered with, and the configuration of the address window is obtained by mapping the array information in the one-time fuse, which can ensure that the configuration of the address window will not be lost, thereby enhancing the operational stability of the control logic and improving the security of the data in the chip.

[0045] In an exemplary embodiment, as shown in FIG3 , the step of sending an instruction to intercept the access request to a request processing component electrically connected to the first host device may include:

[0046] Step A1: Send an instruction for intercepting an access request to a request processing component electrically connected to a first host device, so that the request processing component instructs the first host device to start a software program to intercept the access request.

[0047] Step A2: sending an instruction to intercept the access request to a request processing component electrically connected to the first master device, so that the request processing component triggers a hardware reset operation on the chip.

[0048] Exemplarily, the request processing component can be implemented based on a security monitor (SECMON). The request processing component can monitor and collect all security information of the chip in real time, and determine the current security status of the chip based on the security information. The request processing component can monitor the address window restricted by the access control component 105, and in response to the occurrence of illegal access by the second master device, notify the first master device by interruption, instruct the first master device to start the software program to trigger the chip to immediately enter the security violation state, so as to close the access channel of the key data inside the chip and automatically destroy the user's sensitive information. Since the access request is intercepted by software, users who obtain the software modification permission can avoid interception by modifying the execution operation of the interception behavior, which poses a certain risk. For data with higher security requirements, the request processing component can also trigger the entire chip system to perform a hardware reset, and then re-enter the startup loading process of the chip.

[0049] In this embodiment, by providing two options of software interception and hardware reset in the event of unexpected access, different interception schemes can be configured based on different security requirements of data, and the overall security of the system can be flexibly improved.

[0050] In an exemplary embodiment, as shown in FIG4 , the above step A2 may include:

[0051] Step A21, sending an instruction to intercept access requests to a request processing component electrically connected to the first master device, so that the request processing component triggers a hardware reset operation on the chip when the value of the first target bit in the programmed one-time fuse is a valid value.

[0052] Among them, the first target bit may correspond to the exception handling hardware reset control bit of the control register. Exemplarily, the programming method of the one-time fuse includes: burning the first target bit in the one-time fuse to make it a valid value. Furthermore, when the chip is reset or restarted, if the value of the first target bit in the one-time fuse is not a valid value, the request processing component may instruct the first master device to start a software program to intercept the access request; if the value of the first target bit in the one-time fuse is a valid value, the request processing component may trigger the operation of hardware resetting the chip.

[0053] The first target bit corresponding to the control register is protected by a one-time fuse. Once it is set to hardware reset, it cannot be tampered with unless the main chip is replaced. Therefore, it can effectively prevent the hardware reset function from being turned off, further improving the security of the data in the chip.

[0054] In an exemplary embodiment, the first array information in the programmed one-time fuse may be obtained by programming a value in a configurable register configured by the first master device.

[0055] Exemplarily, the configuration method of the configurable register may include: when the chip is running, the user who obtains the configuration permission of the access control component 105 can dynamically configure the value in the configurable register (for example, add or delete the configuration entry of the access control component 105), so as to realize the dynamic configuration of the address access rule. The programming method of the one-time fuse includes: burning the dynamically configured address access rule to the eFUSE array corresponding to the configurable register of the access control component 105, so as to realize the static configuration of the address access rule. Therefore, the flexible configuration of the address access rule can be realized.

[0056] In an exemplary embodiment, the configuration method of the configurable register may include: in response to the value of the second target bit in the programmed one-time fuse being a valid value, disabling the write permission of the configurable register.

[0057] Exemplarily, the programming method of the one-time fuse includes: burning the second target bit (write protection control bit of the address window) in the one-time fuse to make it a valid value. Furthermore, when the chip is reset or restarted, the eFUSE array is loaded, and the address windows and their attributes corresponding to each second master device are automatically enabled through the mapping relationship between the eFUSE array and the configurable register of the access control component 105, and at the same time, the hardware automatically loads the valid value of the second target bit. For the enabled address window, the user's dynamic configuration permission for the address window is closed by hardware. Therefore, it is possible to prevent the effective statically configured address access rules from being tampered with, further improving the security of the data in the chip. It is understandable that the value of the second target bit corresponding to each address window can be different, so that the configuration of the address window can be diversified.

[0058] In an exemplary embodiment, the request processing component may be obtained based on mapping the second array information in the programmed one-time fuse, and the second array information in the programmed one-time fuse may be obtained based on burning the software program configured on the first master device.

[0059] Exemplarily, the programming method of the one-time fuse may include: configuring the monitoring function of the request processing component through a software program, enabling the alarm and processing method of the request processing component for the restricted access address window, hardware fusing the control column corresponding to the one-time fuse, and obtaining the second array information. It can be understood that the second array information can be used to restore the monitoring function of the request processing component.

[0060] Optionally, the programming method of the one-time fuse may include: burning a third target bit (a write protection control bit of the monitoring function) in the one-time fuse to make it a valid value to prevent the enabled monitoring function from being turned off.

[0061] In one possible implementation, a one-time fuse may include an eFUSE array (for example, the size of the eFUSE array may be 1KB) and a read-write control logic. Each bit value in the eFUSE array has a corresponding programmable register. The programming method of the one-time fuse may include: entering the burning process of the one-time fuse; software configuration of address access rules; enabling write protection for address access rules; fusing the array corresponding to the address access rules; software configuration of monitoring functions; enabling write protection for monitoring functions; fusing the array corresponding to the monitoring function; exiting the burning process of the one-time fuse. Furthermore, after the chip is started, the hardware can automatically load the array information in the one-time fuse, the write protection control bit of the address window, the enable control bit of the monitoring function, the write protection control bit of the monitoring function, and the value of the exception handling hardware reset control bit, and map the address access rules in the array information to the corresponding configurable register group. After the hardware is loaded, different access control schemes are executed according to the values ​​of each control bit.

[0062] In summary, in the above access control method, by adding an access control component connected to the bus in the chip system, configuring an address window with restricted access for each master device based on the access control component, and executing the control logic of the access request, the master device can effectively monitor and manage the permissions of the slave device and reduce the risk of illegal access. And the configuration of the address window is obtained by mapping the array information in the one-time fuse, which can ensure the persistence and consistency of the access control policy, for example, avoiding the loss of configuration when the chip is reset or restarted. Since the hardware is involved in the process of running the control logic, it is not easy to be tampered with, and the configuration of the address window is obtained by mapping the array information in the one-time fuse, which can ensure that the configuration of the address window will not be lost, thereby enhancing the operation stability of the control logic and improving the security of the data in the chip. Further, by flexibly configuring software interception / hardware reset, it is possible to flexibly improve the overall security of the system. Further, by means of hardware solidification, the execution of software interception / hardware reset and the control of whether the address access rules can be changed can be controlled, so that multiple protection levels can be flexibly configured.

[0063] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0064] Based on the same inventive concept, the embodiment of the present application also provides an access control device for implementing the access control method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in one or more access control device embodiments provided below can refer to the limitations on the access control method above, and will not be repeated here.

[0065] In an exemplary embodiment, as shown in FIG5 , an access control device 300 is provided, comprising: an access request acquisition module 301, an address window acquisition module 302 and an access request processing module 303, wherein:

[0066] The access request acquisition module 301 is used to acquire the access request sent by the second master device based on the bus.

[0067] The address window acquisition module 302 is used to determine the address window and the attributes of the address window corresponding to the second master device based on the value in the configurable register of the access control component; the value in the configurable register is obtained based on mapping the first array information in the programmed one-time fuse; the attributes of the address window include restricting access or allowing access.

[0068] The access request processing module 302 sends an instruction to intercept the access request to a request processing component electrically connected to the first master device when the address of the slave device in the access request is covered by the restricted access address window corresponding to the second master device.

[0069] In an exemplary embodiment, the access request processing module 302 is further configured to:

[0070] Sending an instruction to intercept the access request to a request processing component electrically connected to the first host device, so that the request processing component instructs the first host device to start a software program to intercept the access request;

[0071] Alternatively, an instruction to intercept the access request is sent to a request processing component electrically connected to the first master device, so that the request processing component triggers an operation of hardware resetting the chip.

[0072] In an exemplary embodiment, the access request processing module 302 is further configured to:

[0073] An instruction to intercept the access request is sent to a request processing component electrically connected to the first master device, so that the request processing component triggers a hardware reset operation on the chip when the value of the first target bit in the programmed one-time fuse is a valid value.

[0074] In an exemplary embodiment, the first array information in the programmed one-time fuse is obtained by programming a value in a configurable register configured by the first master device.

[0075] In an exemplary embodiment, the configuration of the configurable registers includes:

[0076] In response to the value of the second target bit in the programmed one-time fuse being a valid value, the write permission of the configurable register is turned off.

[0077] In an exemplary embodiment, the request processing component is obtained based on mapping the second array information in the programmed one-time fuse, and the second array information in the programmed one-time fuse is obtained based on burning the software program configured by the first master device.

[0078] Each module in the above access control device can be implemented in whole or in part by software, hardware or a combination thereof.

[0079] In an exemplary embodiment, a chip system is provided, comprising: a first master device, a second master device, a slave device, and a bus, wherein the first master device and the second master device access the slave device through the bus, and the system further comprises:

[0080] The access control component electrically connected to the bus is used to implement the steps of the above methods when executing the computer program.

[0081] Those skilled in the art will understand that the structure shown in FIG. 1 is merely a block diagram of a partial structure related to the scheme of the present application, and does not constitute a limitation on the chip system to which the scheme of the present application is applied. The specific chip system may include more or fewer components than shown in the figure, or combine certain components, or have a different arrangement of components.

[0082] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above method embodiments are implemented.

[0083] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0084] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0085] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.

[0086] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0087] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. An access control method, characterized in that: Applied to an access control component, the access control component is electrically connected to a bus, a first master device and a second master device access a slave device through the bus, and the method includes: Based on the bus, obtaining an access request sent by a second master device; Determine an address window corresponding to the second master device and an attribute of the address window based on a value in a configurable register of the access control component; the value in the configurable register is obtained by mapping the first array information in the programmed one-time fuse; the attribute of the address window includes restricting access or allowing access; When the address of the slave device in the access request is covered by the access-restricted address window corresponding to the second master device, an instruction to intercept the access request is sent to a request processing component electrically connected to the first master device.

2. The method according to claim 1, characterized in that The sending an instruction to intercept the access request to a request processing component electrically connected to the first master device includes: Sending an instruction to intercept the access request to a request processing component electrically connected to the first host device, so that the request processing component instructs the first host device to start a software program to intercept the access request; Alternatively, an instruction to intercept the access request is sent to a request processing component electrically connected to the first master device, so that the request processing component triggers an operation of hardware resetting the chip.

3. The method according to claim 2, characterized in that The step of sending an instruction to intercept the access request to a request processing component electrically connected to the first master device, so that the request processing component triggers an operation of hardware resetting the chip, includes: An instruction to intercept the access request is sent to a request processing component electrically connected to the first master device, so that the request processing component triggers a hardware reset operation on the chip when the value of the first target bit in the programmed one-time fuse is a valid value.

4. The method according to claim 1, characterized in that: The first array information in the programmed one-time fuse is obtained by programming the value in the configurable register configured by the first master device.

5. The method according to claim 4, characterized in that The configuration method of the configurable register includes: In response to the value of the second target bit in the programmed one-time fuse being a valid value, disabling write permission of the configurable register.

6. The method according to claim 1, characterized in that The request processing component is obtained based on mapping the second array information in the programmed one-time fuse, and the second array information in the programmed one-time fuse is obtained based on burning the software program configured by the first master device.

7. An access control device, characterized in that: Applied to an access control component, the access control component is electrically connected to a bus, a first master device and a second master device access a slave device through the bus, and the device comprises: An access request acquisition module, used for acquiring an access request sent by a second master device based on the bus; an address window acquisition module, configured to determine an address window corresponding to the second master device and an attribute of the address window based on a value in a configurable register of the access control component; the value in the configurable register is obtained by mapping the first array information in the programmed one-time fuse; the attribute of the address window includes restricting access or allowing access; The access request processing module sends an instruction to intercept the access request to a request processing component electrically connected to the first master device when the address of the slave device in the access request is covered by the restricted access address window corresponding to the second master device.

8. A chip system, comprising: A first master device, a second master device, a slave device, and a bus, wherein the first master device and the second master device access the slave device through the bus, wherein the system further comprises: An access control component electrically connected to the bus is used to implement the steps of the method according to any one of claims 1 to 6 when executing a computer program.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed, the steps of the method according to any one of claims 1 to 6 are implemented.

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