Wiring-driven FPGA (Field Programmable Gate Array) layout division method and system and storage medium

Abstract

The invention discloses a wiring-driven FPGA (Field Programmable Gate Array) layout division method and system. The method comprises the following steps: generating a coarse-grained netlist through node clustering; performing initial division according to the netlist to obtain an initial division result; and based on an initial division result, node movement is performed layer by layer, and division optimization is performed by taking the minimum wiring cost of division as an optimization target. According to the scheme, occupation of interconnection resources can be reduced, and then the overall performance of a chip system is improved.

Description

Technical Field

[0001] The present invention relates to the field of wiring technology, and in particular to a wiring-driven FPGA layout partitioning method and system, and a storage medium. Background Art

[0002] FPGA (Field Programmable Gate Array) is a programmable logic chip that is widely used in communications, industrial control, and intelligent computing. Domestic and domestic high-end FPGA chips all use 2.5D packaging technology to increase the chip logic scale. 2.5D FPGA uses stacked silicon interconnect technology (Stacked Silicon Interconnect, SSI) to package multiple FPGA chips (die) on a substrate to achieve ultra-large-scale design.

[0003] A 2.5D FPGA consists of multiple FPGA dies, each of which is also called a SuperLogic Region (SLRs), which are arranged linearly on a silicon interposer. FPGA dies are connected by super-long lines (SLLs). Due to physical characteristics and cost factors, the number of SLL interconnects is much smaller than the on-chip interconnect resources, and its latency is also relatively large.

[0004] As the logic scale of 2.5D FPGA increases, traditional layout and routing is difficult to handle. Therefore, multiple FPGA dies are usually divided in advance, and then on-chip layout and routing are performed to improve the efficiency and optimization results of layout and routing. An existing partitioning algorithm is the multi-level partitioning algorithm hMetis with the minimum cut as the optimization goal. After the partitioning is completed, each FPGA die is then placed and routed. Since each FPGA die is only 1 / 3 or 1 / 4 of the entire design, the on-chip layout and routing will be greatly simplified, thereby improving the efficiency and optimization effect of layout and routing.

[0005] hMetis is an efficient circuit diagram segmentation tool commonly used in the industry. It is a multi-level partitioning algorithm and a hierarchical partitioning algorithm based on clustering. The algorithm can perform fast and efficient partitioning for ultra-large-scale graphs. The traditional partitioning algorithm hMetis cannot consider the hardware configuration connection and can only optimize the minimum cut. Due to the limitation of wiring cost and the number of SLLs on 2.5D FPGA, it is impossible to obtain good partitioning results using the hMetis algorithm. Summary of the invention

[0006] The embodiment of the present invention provides a wiring-driven FPGA layout partitioning method and system to reduce the occupation of interconnection resources and thus improve the overall performance of the chip system.

[0007] On the one hand, an embodiment of the present invention provides a wiring-driven FPGA layout partitioning method, the method comprising:

[0008] Generate a coarse-grained netlist through node clustering;

[0009] Performing initial partitioning according to the netlist to obtain an initial partitioning result;

[0010] Based on the initial partitioning results, the nodes are moved layer by layer, and the partitioning optimization is performed with the minimum routing cost of the partitioning as the optimization goal.

[0011] Optionally, generating a coarse-grained netlist by node clustering includes:

[0012] Calculate clustering weights between node pairs;

[0013] Select the node pair with the largest clustering weight for clustering;

[0014] Generate a coarse-grained netlist based on the clustering results.

[0015] Optionally, performing initial partitioning according to the netlist to obtain an initial partitioning result includes: randomly and evenly distributing nodes to each partition according to the netlist to obtain an initial partitioning result.

[0016] Optionally, performing partition optimization by moving nodes and taking the minimum wiring cost of partition as the optimization target includes:

[0017] Calculate the movement gain of each node, and insert the node into the priority queue according to the gain from large to small;

[0018] Select the free nodes in the priority queue to move in order from large to small according to the gain, update the gain of the adjacent nodes of the free nodes in the priority queue, adjust the position of the adjacent nodes in the priority queue according to the gain of the adjacent nodes, and calculate the routing cost after the move;

[0019] Select the partition optimization result corresponding to the minimum wiring cost.

[0020] Optionally, calculating the movement gain of each node includes:

[0021] Calculating the wiring cost before and after the node is moved respectively;

[0022] The movement gain of the node is determined according to the wiring cost before the node is moved and the wiring cost after the node is moved.

[0023] Optionally, respectively calculating the wiring cost before and after the node is moved includes:

[0024] Calculate the sum of the wiring distances of the connection lines where the node is located before moving, and obtain the wiring cost of the node before moving;

[0025] The sum of the wiring distances of the lines where the node is moved is calculated to obtain the wiring cost of the node after it is moved.

[0026] On the other hand, an embodiment of the present invention further provides a wiring-driven FPGA layout partitioning system, characterized in that the system comprises:

[0027] Clustering and coarsening module, used to generate a coarse-grained netlist by node clustering;

[0028] An initial partitioning module, used to perform initial partitioning according to the netlist to obtain an initial partitioning result;

[0029] The optimization module is used to move through nodes layer by layer based on the initial partitioning result and optimize the partitioning with the minimum wiring cost of the partitioning as the optimization target.

[0030] Optionally, the clustering coarsening module includes:

[0031] A weight calculation unit, used to calculate the clustering weights between node pairs;

[0032] The clustering unit is used to cluster and select the node pairs with the largest clustering weight for clustering;

[0033] The netlist generation unit is used to generate a coarse-grained netlist according to the clustering result.

[0034] Optionally, the initial partitioning module is specifically configured to randomly and evenly distribute the nodes to each partition according to the netlist to obtain an initial partitioning result.

[0035] Optionally, the optimization module includes:

[0036] A priority queue generation unit, used to calculate the mobility gain of each node, and insert the node into the priority queue according to the gain from large to small;

[0037] A mobile cost calculation unit, used to select free nodes in the priority queue to move in order from large to small according to the gain, and update the gain of the adjacent nodes of the free node in the priority queue, adjust the position of the adjacent node in the priority queue according to the gain of the adjacent node, and calculate the wiring cost after the move;

[0038] The selection unit is used to select the partition optimization result corresponding to the minimum wiring cost.

[0039] Optionally, the priority queue generation unit is used to respectively calculate the routing cost before and after the node moves; and determine the movement gain of the node according to the routing cost before and after the node moves.

[0040] Optionally, the movement cost calculation unit calculates the sum of the wiring distances of the connection line where the node is located before movement to obtain the wiring cost of the node before movement; calculates the sum of the wiring distances of the connection line where the node is located after movement to obtain the wiring cost of the node after movement.

[0041] On the other hand, an embodiment of the present invention further provides a computer-readable storage medium, which is a non-volatile storage medium or a non-transient storage medium, on which a computer program is stored, and when the computer program is run by a processor, the steps of the above-mentioned wiring-driven FPGA layout partitioning optimization method are executed.

[0042] The wiring-driven FPGA layout partitioning method and system provided by the embodiment of the present invention generates a coarse-grained netlist by node clustering; performs initial partitioning according to the netlist to obtain an initial partitioning result; then, based on the initial partitioning result, moves through the nodes layer by layer, and performs partitioning optimization with the minimum wiring cost of the partitioning as the optimization target to obtain the final partitioning result. The scheme of the present invention can effectively reduce the occupation of interconnection resources and improve the quality of FPGA layout partitioning.

[0043] Furthermore, the wiring distance generated by the division result is calculated according to the minimum Steiner tree principle, that is, the number of wire mesh cuts generated by the division in actual applications, so as to optimize the wiring cost of the overall division and reduce the wiring difficulty. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 It is a wiring schematic diagram obtained by using two different partitioning algorithms in the prior art;

[0045] Figure 2 It is a flow chart of a wiring-driven FPGA layout partitioning method provided by an embodiment of the present invention;

[0046] Figure 3 It is a flowchart of each layer partition optimization in the wiring-driven FPGA layout partition method provided by an embodiment of the present invention;

[0047] Figure 4 It is a structural schematic diagram of a wiring-driven FPGA layout partitioning system provided in an embodiment of the present invention;

[0048] Figure 5 It is a structural schematic diagram of an optimization module in a wiring-driven FPGA layout partitioning system provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0049] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0050] It should be noted that the terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments and are not intended to limit this specification. The singular forms of "a", "the" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings. In addition, the "plurality" appearing in the embodiments of the present invention refers to two or more.

[0051] The following first briefly describes the existing partitioning algorithm hMetis.

[0052] The partitioning algorithm hMetis divides the entire partitioning process into three steps: coarsening, initial partitioning, and refinement. The first step is coarsening: generating a coarse-grained netlist through node clustering to reduce the partitioning solution space; the second step is initial partitioning: randomly generating initial partitions in the top-level netlist; the third step is refinement: optimizing the partitioning by moving nodes at each level. As the top-down process progresses, the clustering of each level gradually decreases, and the partitioning optimization of each level continues to be refined until a more optimized partitioning result is finally generated.

[0053] For example, an FPGA has four dies. One partitioning method is to perform iterative two-way partitioning, that is, first divide it into two modules with equal areas, and then perform two-way partitioning on each module to form four balanced area partitions. Another partitioning method is to directly perform multi-way partitioning, that is, directly divide it into four modules with equal areas. The advantage of multi-way partitioning is better area balance optimization, but the cutting optimization effect is lower than iterative two-way partitioning. In specific applications, both solutions are used.

[0054] The hMetis algorithm is an optimization algorithm for the minimum cut algorithm. Figure 1 As shown in the figure, assuming that an FPGA has 4 dies, the minimum cut partitioning algorithm is used, where: (a) aims to minimize the cut size, and (b) aims to minimize the wiring distance; the cut number (cut size) of (a) and (b) is 1, and the cost of the two methods is the same.

[0055] However, on a 2.5D FPGA, the two nodes of a connection (net) in (a) are on die1 and die4 respectively. The net from die1 to die4 requires three SLL interconnections and two buffers (the function of the buffer is to provide buffering for the interconnection inside the FPGA to meet the timing requirements), and the wiring distance of the net is 3; while the two nodes of a net in (b) are on die1 and die2, and the net connecting die1 and die2 only needs one SLL interconnection, and the wiring distance of the net is 1. Its cost is obviously much smaller than the previous case. However, the partitioning algorithm with the minimum cut as the goal cannot handle this situation, which seriously affects the results of layout and routing.

[0056] In view of the influence of the calculation error of the existing minimum cut partitioning algorithm that can reduce the occupation of interconnection resources on layout and routing, an embodiment of the present invention provides a routing-driven FPGA layout and partitioning method and system. For the layout and routing partitioning of 2.5D FPGA, before executing the partitioning, the connection relationship between the partitions to be divided, that is, the internal connection structure of the FPGA is obtained, and then the minimum routing cost of the partition is used as the optimization goal to complete the path optimization and obtain the final partitioning result.

[0057] like Figure 2 FIG. 1 is a flow chart of a wiring-driven FPGA layout partitioning method provided in an embodiment of the present invention, comprising the following steps:

[0058] Step 201 : Generate a coarse-grained netlist by node clustering.

[0059] In the embodiment of the present invention, the scale of the graph is first reduced by clustering the nodes, that is, the nodes with the same clustering result are merged into one node, thereby reducing the number of nodes and the scale of the graph. Specifically, the clustering weights between node pairs are calculated; then the node pairs with the largest clustering weights are selected for clustering. The larger the clustering weights of the node pairs, the closer their connections are, so they can be clustered to reduce the number of cuts during division; finally, a coarse-grained netlist is generated according to the clustering results.

[0060] The sum of the weights of the shared links between the node pairs (ie, adjacent nodes) can be used as the clustering weight between the node pairs. It should be noted that the fewer the nodes on the shared links, the greater the weight.

[0061] Assuming that nodes P1 and P2 are connected and there are several links between P1 and P2, the clustering weight of the node pair P1 and P2 is the sum of the weights of the links between nodes P1 and P2; the weight of the links is determined by the number of nodes on each link, and the fewer the number of nodes, the greater the weight.

[0062] It should be noted that each cluster coarsening will control the number and size of cluster nodes, and the coarsening will be performed step by step to generate a series of graphs with gradually decreasing scales and gradually increasing node granularity. Finally, a coarse-grained netlist with only a small number of nodes is generated.

[0063] Step 202, performing initial partitioning according to the netlist to obtain an initial partitioning result.

[0064] In a non-limiting embodiment, the nodes may be randomly and evenly distributed to each partition according to the netlist to obtain an initial partition result. Of course, other initial partitioning methods may also be used, which are not limited in the embodiment of the present invention.

[0065] Step 203 , based on the initial partitioning result, the nodes are moved layer by layer, and the partitioning optimization is performed with the minimum routing cost of the partitioning as the optimization target.

[0066] In the embodiment of the present invention, for each net across dies, RSMT (Rectilinear Steiner Minimum Tree) based routing is performed to evaluate the optimization effect of partitioning and moving.

[0067] It should be noted that considering that the partition optimization is performed based on different initial partition results, the final partition optimization results will be different. Therefore, in specific applications, in order to avoid the initial solution of random partitioning from falling into the local optimal solution, random partitioning can be performed multiple times and partition optimization can be performed to a certain depth, that is, the partition optimization process is repeated multiple times, and then the optimal solution after partition optimization is selected as the initial partition result. This can effectively avoid falling into the local optimal solution and improve the quality of initial partitioning.

[0068] Accordingly, the process of optimizing the division of each layer in the embodiment of the present invention is as follows: Figure 3 As shown, the following steps are included:

[0069] Step 231, calculate the mobility gain of each node, and insert the node into the priority queue according to the gain from large to small.

[0070] Specifically, the wiring cost before the node moves and the wiring cost after the node moves are calculated respectively; then, the movement gain of the node is determined according to the wiring cost before the node moves and the wiring cost after the node moves.

[0071] For each node, the sum of the wiring costs of the net where the node is located can be defined as the wiring cost of the node; the movement gain of each node can also be called the node's movement cost function, which is the difference between the wiring costs before and after the node moves. Based on this, the gains of all nodes moving to different partitions can be calculated, and the nodes can be inserted into the priority queue according to the gain size.

[0072] In the embodiment of the present invention, RSMT can be used to calculate the wiring cost of each net, thereby calculating the overall wiring cost, that is, the overall optimization target of the partition.

[0073] The definition of RSMT is: select a specified number of nodes in the graph, connect all the specified nodes through the lines in the graph and make the path of the lines as short as possible. The path tree thus formed is the minimum Steiner tree.

[0074] The Steiner tree problem in partitioning can be summarized as the shortest path cost connecting specified nodes in a given graph. In an embodiment of the present invention, dynamic planning (DP) can be used to determine the minimum cost.

[0075] Let dp(i,T) represent the minimum cost of the Steiner tree from the root node i to all nodes in the point set T. The calculation can be divided into two cases:

[0076] (1) If the point set T contains only two nodes, i and j, then dp(i, T) is equal to the cost (i, j) from i to j, that is:

[0077] dp(i,T)=cost(i,j)

[0078] (2) If the point set T contains multiple nodes, then:

[0079] dp(i,T)=dp(i,Z)+dp(i,TZ),

[0080] Among them, dp(i,Z) represents the Steiner tree cost of the nodes in the subset Z that has been calculated, and dp(i,TZ) represents the Steiner tree cost of the nodes in the point set T that have not been calculated except the subset Z.

[0081] The cost calculation during state transition can be implemented by the Dijkstra shortest path algorithm. For example, when calculating the wiring distance of a net, you only need to know its span vector (i.e. the partition connected by the net) to get its corresponding Steiner tree cost, i.e. the wiring cost.

[0082] Step 232, select the free nodes in the priority queue to move in order from large to small according to the gain, update the gain of the adjacent nodes of the free nodes in the priority queue, adjust the position of the adjacent nodes in the priority queue according to the gain of the adjacent nodes, and calculate the routing cost after the move.

[0083] The free node refers to a node that meets the partition area constraint and has not been moved before, and it needs to meet the following conditions:

[0084] (1) The movement of a free node must meet the area constraint of the partition to which it moves. If the area of ​​the target partition of a node has reached the area constraint of the die, it cannot be moved;

[0085] (2) A free node is a node that has not been moved. If a node has been moved before, it cannot be moved again during this round of optimization, that is, the node is a non-free node.

[0086] Step 233, selecting the partition optimization result corresponding to the minimum wiring cost.

[0087] It should be noted that after each layer of partition optimization is completed, the partition results of the cluster nodes need to be mapped to the next layer, and then the partition optimization of the next layer is continued until the partition optimization of all layers is completed to obtain the final partition optimization result.

[0088] The wiring-driven FPGA layout partitioning method provided by the embodiment of the present invention obtains the connection relationship between the partitions to be divided, that is, the internal connection structure of the FPGA, before executing the partitioning, and then takes the minimum wiring cost of the partitioning as the optimization target to complete the path optimization and obtain the final partitioning result. The solution of the present invention can effectively reduce the occupation of interconnection resources and improve the quality of FPGA layout partitioning.

[0089] Accordingly, an embodiment of the present invention further provides a wiring-driven FPGA layout partitioning system, such as Figure 4 The figure shows a structural diagram of the system.

[0090] The routing-driven FPGA placement and partitioning system 400 includes the following modules:

[0091] A clustering and coarsening module 401 is used to generate a coarse-grained netlist by node clustering;

[0092] An initial partitioning module 402 is used to perform initial partitioning according to the netlist to obtain an initial partitioning result;

[0093] The optimization module 403 is used to perform partition optimization by moving nodes layer by layer based on the initial partition result.

[0094] A specific structure of the clustering coarsening module 401 may include the following units:

[0095] A weight calculation unit, used to calculate the clustering weights between node pairs;

[0096] The clustering unit is used to cluster and select the node pairs with the largest clustering weight for clustering;

[0097] The netlist generation unit is used to generate a coarse-grained netlist according to the clustering result.

[0098] The initial partitioning module 402 may randomly and evenly distribute the nodes to each partition according to the netlist to obtain an initial partitioning result.

[0099] Among them, a specific structure of the optimization module 403 is as follows Figure 5 As shown, it includes the following units:

[0100] The priority queue generating unit 431 is used to calculate the mobility gain of each node and insert the node into the priority queue according to the gain from large to small;

[0101] A moving cost calculation unit 432 is used to select free nodes in the priority queue to move in order from large to small according to the gains, and update the gains of the adjacent nodes of the free nodes in the priority queue, adjust the positions of the adjacent nodes in the priority queue according to the gains of the adjacent nodes, and calculate the routing cost after the move;

[0102] The selection unit 433 is used to select the partition optimization result corresponding to the minimum wiring cost.

[0103] The priority queue generating unit 431 may respectively calculate the routing cost before the node moves and the routing cost after the node moves; and determine the movement gain of the node according to the routing cost before the node moves and the routing cost after the node moves.

[0104] The calculation of the routing cost by the movement cost calculation unit 432 may be performed in the following manner:

[0105] Calculate the sum of the wiring distances of the connection lines where the node is located before moving, and obtain the wiring cost of the node before moving;

[0106] The sum of the wiring distances of the lines where the node is moved is calculated to obtain the wiring cost of the node after it is moved.

[0107] Accordingly, the difference between the routing cost before the node moves and the routing cost after the node moves is calculated to obtain the movement gain of the node.

[0108] The wiring-driven FPGA layout partitioning system provided by the embodiment of the present invention obtains the connection relationship between the partitions to be divided, that is, the internal connection structure of the FPGA, before executing the partitioning, and then takes the minimum wiring cost of the partitioning as the optimization target to complete the path optimization and obtain the final partitioning result. The solution of the present invention can effectively reduce the occupation of interconnection resources and improve the quality of FPGA layout partitioning.

[0109] For other related descriptions of the above-mentioned wiring-driven FPGA layout partitioning system 400, please refer to Figure 2 and Figure 3 The relevant description in will not be repeated here.

[0110] The traditional partitioning algorithm hMetis cannot consider the hardware configuration connection situation and can only partition for the minimum cut. Due to the limitation of wiring cost and the number of SLLs on 2.5D FPGA, it is impossible to obtain a good partitioning result using the hMetis algorithm. The present invention is directed to the layout and routing partitioning of 2.5D FPGA, and the wiring distance generated by the partitioning result is calculated according to the minimum Steiner tree principle, that is, the number of wire net cuts generated by the partitioning in practical applications, thereby optimizing the wiring cost of the overall partitioning. The partitioning optimized for wiring can reduce the occupation of wiring resources by the partitioning, reduce the difficulty of wiring, and thus improve the overall performance of the system. Moreover, it is fully proved by comparative tests that better optimization effects can be obtained by using the present invention.

[0111] For example, Table 1 below is the comparative test data of a test set.

[0112] Table 1

[0113]

[0114] Seven test cases are given in this test set, such as the test data in Table 1, a total of seven test cases, comparing three indicators: line length, number of interconnections, and running time. Among them, based on the partitioning algorithm table of hMetis, there is one example in which the subsequent layout and routing cannot be completed, and the partitioning algorithm of the present invention is adopted to successfully complete the layout and routing task. Referring to the numerical value shown in the last row in Table 1, in the example in which all six partitioning algorithms are completed, the existing results of layout partitioning using hMetis are used as the benchmark, and under three different indicators, the results of layout partitioning using the scheme of the present invention are compared with the existing results of hMetis.

[0115] By comparison, it can be seen that the solution of the present invention has 14%, 40% and 31% improvements in system line length, number of interconnections between modules and running time of layout and routing after layout and routing are completed.

[0116] The experimental data in Table 1 above fully demonstrates that the layout optimization partitioning algorithm of the solution of the present invention can effectively reduce the difficulty of layout and routing.

[0117] Regarding the various modules / units included in the various systems and products described in the above embodiments, they can be software modules / units, or hardware modules / units, or they can be partially software modules / units and partially hardware modules / units. For example, for various devices and products applied to or integrated in a chip, the various modules / units included therein can all be implemented in the form of hardware such as circuits, or at least some of the modules / units can be implemented in the form of software programs, which run on a processor integrated inside the chip, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits; for various devices and products applied to or integrated in a chip module, the various modules / units included therein can all be implemented in the form of hardware such as circuits, and different modules / units can be located in the same component of the chip module (such as a chip, circuit module, etc.) or in different components, or at least some of the modules / units can be implemented in the form of software programs. It is implemented in the form of a software program, which runs on a processor integrated inside the chip module, and the remaining (if any) modules / units can be implemented in hardware such as circuits; for various devices and products applied to or integrated in the terminal equipment, the various modules / units contained therein can be implemented in hardware such as circuits, and different modules / units can be located in the same component (for example, chip, circuit module, etc.) or in different components in the terminal equipment, or, at least some modules / units can be implemented in the form of a software program, which runs on a processor integrated inside the terminal equipment, and the remaining (if any) modules / units can be implemented in hardware such as circuits.

[0118] The present application also discloses a storage medium, which is a computer-readable storage medium and stores a computer program, which can be executed when the computer program is run. Figure 2 or Figure 3 All or part of the steps of the method shown in . The storage medium may include a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc. The storage medium may also include a non-volatile memory (non-volatile) or a non-transitory memory, etc.

[0119] The first, second, etc. descriptions appearing in the embodiments of the present application are only used for illustration and distinction of the description objects. There is no order, nor do they indicate any special limitation on the number of devices in the embodiments of the present application, and cannot constitute any limitation on the embodiments of the present application.

[0120] The above embodiments may be implemented in whole or in part by software, hardware, firmware or any other combination thereof. When implemented using software, the above embodiments may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired or wireless means.

[0121] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0122] In the several embodiments provided in the present application, it should be understood that the disclosed methods, devices and systems can be implemented in other ways. For example, the device embodiments described above are merely schematic; for example, the division of the units is only a logical function division, and there may be other division methods in actual implementation; for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0123] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0124] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may be physically included separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0125] The above-mentioned integrated unit implemented in the form of a software functional unit can be stored in a computer-readable storage medium. The above-mentioned software functional unit is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to perform some steps of the method described in each embodiment of the present application.

[0126] Although the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application shall be subject to the scope defined by the claims.

Claims

1. A wiring-driven FPGA layout partitioning method, characterized in that: The method comprises: Generate a coarse-grained netlist through node clustering; Performing initial partitioning according to the netlist to obtain an initial partitioning result; Based on the initial partitioning results, the nodes are moved layer by layer, and the partitioning optimization is performed with the minimum routing cost of the partitioning as the optimization goal.

2. The method according to claim 1, characterized in that The generating of a coarse-grained netlist by node clustering includes: Calculate clustering weights between node pairs; Select the node pair with the largest clustering weight for clustering; Generate a coarse-grained netlist based on the clustering results.

3. The method according to claim 1, characterized in that The performing initial partitioning according to the netlist to obtain the initial partitioning result comprises: According to the netlist, the nodes are randomly and evenly distributed to each partition to obtain an initial partition result.

4. The method according to any one of claims 1 to 3, characterized in that: The partition optimization by moving nodes and taking the minimum wiring cost of the partition as the optimization target includes: Calculate the movement gain of each node, and insert the node into the priority queue according to the gain from large to small; Select the free nodes in the priority queue to move in order from large to small according to the gain, update the gain of the adjacent nodes of the free nodes in the priority queue, adjust the position of the adjacent nodes in the priority queue according to the gain of the adjacent nodes, and calculate the routing cost after the move; Select the partition optimization result corresponding to the minimum wiring cost.

5. The method according to claim 4, characterized in that The calculation of the movement gain of each node includes: Calculating the wiring cost before and after the node is moved respectively; The movement gain of the node is determined according to the wiring cost before the node is moved and the wiring cost after the node is moved.

6. The method according to claim 5, characterized in that The calculating of the wiring cost before and after the node is moved comprises: Calculate the sum of the wiring distances of the connection lines where the node is located before moving, and obtain the wiring cost of the node before moving; The sum of the wiring distances of the lines where the node is moved is calculated to obtain the wiring cost of the node after it is moved.

7. A wiring-driven FPGA placement partitioning system, characterized in that: The system comprises: Clustering and coarsening module, used to generate a coarse-grained netlist by node clustering; An initial partitioning module, used to perform initial partitioning according to the netlist to obtain an initial partitioning result; The optimization module is used to move through nodes layer by layer based on the initial partitioning result and optimize the partitioning with the minimum wiring cost of the partitioning as the optimization target.

8. The system according to claim 7, characterized in that The clustering coarsening module includes: A weight calculation unit, used to calculate the clustering weights between node pairs; The clustering unit is used to cluster and select the node pairs with the largest clustering weight for clustering; The netlist generation unit is used to generate a coarse-grained netlist according to the clustering result.

9. The system according to claim 7, characterized in that The initial partitioning module is specifically used to randomly and evenly distribute the nodes to each partition according to the netlist to obtain an initial partitioning result.

10. The system according to any one of claims 7 to 9, characterized in that: The optimization module includes: A priority queue generation unit, used to calculate the mobility gain of each node, and insert the node into the priority queue according to the gain from large to small; A mobile cost calculation unit, used to select free nodes in the priority queue to move in order from large to small according to the gain, and update the gain of the adjacent nodes of the free node in the priority queue, adjust the position of the adjacent node in the priority queue according to the gain of the adjacent node, and calculate the wiring cost after the move; The selection unit is used to select the partition optimization result corresponding to the minimum wiring cost.

11. The system according to claim 10, characterized in that The priority queue generation unit is used to respectively calculate the routing cost before and after the node moves; and determine the movement gain of the node according to the routing cost before and after the node moves.

12. The system according to claim 11, characterized in that The movement cost calculation unit calculates the sum of the wiring distances of the connection line where the node is located before movement to obtain the wiring cost of the node before movement; calculates the sum of the wiring distances of the connection line where the node is located after movement to obtain the wiring cost of the node after movement.

13. A computer-readable storage medium, wherein the computer-readable storage medium is a non-volatile storage medium or a non-transient storage medium, and a computer program is stored thereon, wherein: When the computer program is executed by a processor, the steps of the wiring-driven FPGA layout partitioning optimization method according to any one of claims 1 to 6 are executed.

Images